Semiconductor module and method of manufacturing semiconductor module

Abstract

To provide a semiconductor module that can reduce thermal stress applied to an electrode and also reduce strain of the electrode to improve reliability, and a method of manufacturing the semiconductor module.SOLUTION: A semiconductor module comprises a multilayer substrate 5 mounted with a semiconductor element 1, a lead frame 10 electrically connected to the semiconductor element 1, and sealing resin 8 sealing a sealed member including the semiconductor element 1, lead frame 10, and multilayer substrate 5. The lead frame 10 is provided with a plurality of recessed parts 23 on a top surface of a joint part 31 joined to the semiconductor element 1.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This disclosure relates to a semiconductor module and a method of manufacturing the semiconductor module.

Background Art

[0002] Conventionally, before joining a wire to a lead portion, a roughened region is formed in the lead portion by laser irradiation, and a semiconductor device is known in which a joint portion of the wire is surrounded by a region having high adhesion to a mold resin, suppressing disconnection of the wire due to stress (see Patent Document 1 below).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor module, there are problems such that the lead frame and the encapsulating resin are peeled off due to thermal stress, cracks occur in the electrodes of the semiconductor element, or peeling occurs between the electrodes and a bonding material such as solder.

[0005] An object of this disclosure is to provide a semiconductor module and a method of manufacturing the semiconductor module that can reduce the thermal stress applied to the electrodes, reduce the distortion of the electrodes, and improve the reliability in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0006] In order to solve the above-described problems and achieve the object of the present disclosure, the semiconductor module according to this disclosure has the following features. The semiconductor module includes a laminated substrate on which semiconductor elements are mounted, a lead frame electrically connected to the semiconductor elements, and a sealing resin that seals a sealing member including the semiconductor elements, the lead frame, and the laminated substrate. A plurality of recesses are provided on the upper surface of the joint portion of the lead frame that joins with the semiconductor element.

[0007] According to the above-described disclosure, by providing a plurality of recesses on the joint portion of the lead frame, the thermal stress applied to the upper surface electrode can be reduced, the distortion of the upper surface electrode can be reduced, and the reliability of the semiconductor module can be improved.

Effect of the Invention

[0008] According to the semiconductor module and the method for manufacturing the semiconductor module according to the present disclosure, it is possible to reduce the thermal stress applied to the electrode, reduce the distortion of the electrode, and improve the reliability.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0010] <Outline of Embodiments of the Present Disclosure> In order to solve the above-described problems and achieve the object of the present disclosure, the semiconductor module according to this disclosure has the following features. The semiconductor module includes a laminated substrate on which a semiconductor element (also referred to as a semiconductor chip) is mounted, a lead frame electrically connected to the semiconductor element, and a sealing resin that seals a sealing member including the semiconductor element, the lead frame, and the laminated substrate. A plurality of recesses are provided on the upper surface of the joint portion of the lead frame that joins with the semiconductor element.

[0011] According to the above-described disclosure, by providing a plurality of recesses on the upper surface of the joint portion of the lead frame, the thermal stress applied to the upper surface electrode can be reduced, the strain of the upper surface electrode can be reduced, and the reliability of the semiconductor module can be improved.

[0012] Also, in the semiconductor module according to this disclosure, in the above-described disclosure, the concave portion has a pore diameter of 0.05 mm or more and 0.4 mm or less, and a depth of 0.1 mm or more and 0.45 mm or less.

[0013] Also, in the semiconductor module according to this disclosure, in the above-described disclosure, the ratio of the volume of the concave portion to the volume of the joint portion is 5% or more.

[0014] According to the above-described disclosure, the maximum strain of the upper surface electrode can be reduced by 4%.

[0015] Also, in the semiconductor module according to this disclosure, in the above-described disclosure, when the length of the joint portion is L and the length from the root of the lead frame to the center of the concave portion is D, the concave portion is provided in a row in the depth direction of the lead frame, and the position of the concave portion is provided at a position where the ratio D / L is 60% or less. Note that, as shown in FIG. 2, the root is the boundary portion between the bent portion 32 and the joint portion 31 of the lead frame.

[0016] According to the above-described disclosure, the strain of the upper surface electrode can be reduced by 3% or more, and the reliability can be improved by 30% or more.

[0017] Also, in the semiconductor module according to this disclosure, in the above-described disclosure, the position of the concave portion is provided at a position where the ratio D / L is 10% or more and 40% or less.

[0018] According to the above-described disclosure, the strain of the upper surface electrode is reduced by 3.5% or more, and the reliability is improved by 40% or more.

[0019] Also, in the semiconductor module according to this disclosure, in the above-described disclosure, when the length of the joint portion is L and the length from the root of the lead frame to the center of the concave portion farthest from the root is D, the concave portion is provided in a plurality of rows at a position up to the ratio D / L in the depth direction of the lead frame, and the ratio D / L is 5% or more and 20% or less.

[0020] According to the above disclosure, the strain of the top electrode can be reduced by 3% or more, and the reliability can be improved by 40% or more.

[0021] Also, in the semiconductor module according to this disclosure, in the above disclosure, the ratio D / L is characterized in that it is 20% or more and 60% or less.

[0022] According to the above disclosure, the strain of the top electrode can be reduced by 4% or more, and the reliability can be improved by 50% or more.

[0023] In order to solve the above problems and achieve the object of the present disclosure, the manufacturing method of the semiconductor module according to this disclosure has the following features. A first step of bonding a semiconductor element to a laminated substrate, a second step of mounting the laminated substrate in a case, a third step of bonding the semiconductor element and a lead frame having a plurality of recesses, a fourth step of injecting resin into the case, and a fifth step of curing the resin. The step of forming the plurality of recesses at a joint portion that joins the semiconductor element to the lead frame is included before the third step.

[0024] <The knowledge on which the present disclosure is based> First, the problems of conventional semiconductor modules will be described. A conventional semiconductor module includes a semiconductor chip, a laminated substrate, a case, a heat dissipation base, and a lead frame. The semiconductor chip is a power semiconductor chip such as a MOSFET, IGBT, or diode, and is joined to the laminated substrate with a joining layer such as solder. A laminated substrate refers to a substrate having a first conductive plate such as copper provided on the front surface of an insulating substrate such as a ceramic substrate and a second conductive plate such as copper provided on the back surface. The laminated substrate is joined to the heat dissipation base with a joining layer such as solder. Also, on the surface of the semiconductor chip, in the case of a MOSFET, a source electrode pad is formed as a power terminal electrode pad (current supply terminal). Then, a conductive connection member such as a lead frame or a metal wire is arranged as a take-out terminal from the power terminal electrode pad. Note that the power terminal electrode pad (upper surface electrode) of the semiconductor chip and the lead frame are joined with a joining layer such as solder. A case is adhered to the semiconductor module, and a lid through which a metal terminal penetrates and protrudes to the outside is attached. A sealing resin for insulating and protecting the laminated substrate and the semiconductor chip on the substrate is filled in the case.

[0025] FIG. 12 is a graph showing the distortion of the upper surface electrode due to thermal stress in a conventional semiconductor module. In FIG. 12, the horizontal axis represents the distance from the end of the joining layer 27 on the surface of the semiconductor chip, and the unit is mm. The vertical axis represents the distortion of the power terminal electrode pad (upper surface electrode) of the semiconductor chip, and the unit is %. FIG. 12 is the result of performing thermal stress analysis by the finite element method (FEM). In FIG. 12, L11 is the portion (joint portion) where the lead frame and the upper surface electrode are joined, and the length is about 3.0 mm. Also, L12 is the location corresponding to the root portion (bending portion side) of the joint portion of the lead frame. As shown in FIG. 12, the maximum distortion (A11) occurs in the electrode at the root portion of the joint portion.

[0026] As described above, in the conventional semiconductor module, due to the thermal stress applied to the lead frame, tensile stress also acts in the horizontal direction of the upper surface electrode, resulting in distortion of the upper surface electrode, cracking of the upper surface electrode, or peeling between the upper surface electrode and the bonding material such as solder. In addition, there is a problem that the lead frame and the encapsulating resin are peeled off due to thermal stress caused by power cycling, heat cycling, or the like.

[0027] With reference to the accompanying drawings below, preferred embodiments of the semiconductor module and the method for manufacturing the semiconductor module according to this disclosure will be described in detail. However, this disclosure is not limited to the embodiments described below.

[0028] (Embodiment) A semiconductor module according to an embodiment for solving the above problems will be described below. FIG. 1 is a cross-sectional view showing the configuration of a semiconductor module 50 according to the embodiment. In the semiconductor module 50, a first conductive plate 3 made of copper is disposed on the front surface, which is one surface of the insulating substrate 2, and a second conductive plate 4 such as copper is disposed on the back surface, which is the other surface, to form a laminated substrate 5. A plurality of semiconductor chips 1 are mounted on the front surface of the first conductive plate 3 of the laminated substrate 5 via a bonding layer 25 made of solder or a sintered material. The first conductive plate 3 is formed on the front surface (first main surface) of the insulating substrate 2 with a predetermined circuit pattern. The second conductive plate 4 on the back surface of the laminated substrate 5 is joined to the front surface of the heat dissipation base 26 by a bonding layer 25 such as solder or a sintered material. The second conductive plate 4 may be a metal foil formed over the entire back surface of the insulating substrate 2.

[0029] A metal terminal (not shown) for extracting a signal to the outside is joined inside the case 7. Further, a lead frame 10, which is a conductive connection part, is attached to the front surface (for example, a source electrode pad) of the semiconductor chip 1 via solder 24. In addition, the inside of the case 7 is filled with an encapsulating resin 8. Note that the configuration of the illustrated semiconductor module 50 is an example, and this disclosure is not limited to such a configuration. For example, a module structure without the case 7 is also possible.

[0030] (Semiconductor chip 1) The semiconductor chip 1 is a power chip such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or an SBD (Schottky Barrier Diode). As the semiconductor substrate, a device using Si, SiC, or GaN can be used. In particular, the present disclosure is effective for SiC chips and GaN chips with high power and high Young's modulus. The number of semiconductor chips 1 mounted may be one, or a plurality of them can be mounted. On the upper surface of the semiconductor chip 1, an upper surface electrode 22 such as a source electrode pad made of an aluminum alloy or the like is formed.

[0031] (Stacked substrate 5) The stacked substrate 5 can be composed of an insulating substrate 2, a first conductive plate 3 formed in a predetermined shape on one main surface thereof, and a second conductive plate 4 formed on the other main surface. The surface of the first conductive plate 3 and the back surface of the semiconductor chip 1 are joined via a joining layer 24. As the insulating substrate 2, a material excellent in electrical insulation and thermal conductivity can be used. Examples of the material of the insulating substrate 2 include Al 2 O 3, such as AlN and SiN. Particularly for high breakdown voltage applications, a material that combines electrical insulation and thermal conductivity is preferred. AlN and SiN can be used, but are not limited to these. As the first conductive plate 3 and the second conductive plate 4, Cu (copper) or a Cu alloy with excellent workability can be used. Note that a Cu alloy is an alloy containing 80% or more of Cu. Among such conductive plates made of Cu or a Cu alloy, the conductive plate not in contact with the semiconductor chip 1 may also be referred to as a back copper foil or a back conductive plate. As a method of disposing the conductive plate on the insulating substrate 2, a direct bonding method (Direct Copper Bonding method) or a brazing method (Active Metal Brazing method) can be mentioned. Also, Ni (nickel) plating or the like may be applied to the surface of the conductive substrate to form a Ni or Ni alloy layer.

[0032] (Heat dissipation base 26) The heat dissipation base 26 is, for example, a heat dissipation plate having a substantially rectangular planar shape formed of a metal such as Cu or Al with excellent thermal conductivity, and is also referred to as a metal substrate. The surface of the heat dissipation base 26 may be covered with a Ni film or a Ni alloy film having a corrosion prevention effect. The back surface of the heat dissipation base 26 may be joined to a cooling base portion (not shown). The heat dissipation base 26 can be joined to the second conductive plate 4 of the multilayer substrate 5 via the joining layer 25, and conducts the heat generated by the semiconductor chip 1 and transmitted through the multilayer substrate 5 to the heat dissipation fin portion. The heat dissipation fin portion has a plurality of heat dissipation fins and dissipates the heat conducted from the heat dissipation base 26. Note that the heat dissipation base 26 itself may be a cooling device such as a heat dissipation fin portion.

[0033] (Joining layer 27, joining layer 24, joining layer 25) The joining layer 27, the joining layer 24, and the joining layer 25 can be formed using lead-free solder. For example, Sn-Sb based, Sn-Cu based, Sn-Ag based, Sn-Sb-Ag based, etc. can be used, but are not limited to these. Also, it can be formed using a connecting material containing fine metal particles such as a sintered body of nano silver particles.

[0034] (Lead frame 10) The lead frame 10 is a conductive wiring that is electrically connected to the first conductive plate 3 of the laminated substrate 5, an external extraction terminal (not shown), etc. from the upper surface electrode 22 of the semiconductor chip 1 via a bonding material such as the bonding layer 27. FIG. 2 is a cross-sectional view showing the structure of the joint portion between the semiconductor chip and the lead frame of the semiconductor module according to the embodiment. FIG. 3 is a plan view showing the structure of the lead frame of the semiconductor module according to the embodiment.

[0035] As shown in FIG. 2, the lead frame 10 includes a joint portion 31 that joins with the solder 24 on the upper surface electrode 22 of the semiconductor chip 1, a bent portion 32 that connects the joint portion 31 and the rising portion 33, a rising portion 33 that is provided substantially perpendicular to the upper surface of the semiconductor chip 1 and away from the upper surface electrode 22, a bent portion that connects the rising portion 33 and the connecting portion 34, and a connecting portion 34 that is substantially parallel to the upper surface of the semiconductor chip 1 and connects to other joint portions (such as the first conductive plate 3 and the external extraction terminal). The joint portion 31 of the lead frame 10 is joined to the upper surface electrode 22 of the semiconductor chip 1 via the solder 24 provided in the opening of the insulating protective film 21. Note that the root portion of the lead frame is in the vicinity of the bent portion side of the joint portion 31.

[0036] FIG. 4 is a top view showing the structure of the lead frame of the semiconductor module according to the embodiment. FIG. 5 is a perspective view showing the structure of the lead frame of the semiconductor module according to the embodiment. For example, in the lead frame 10, the length L1 in the longitudinal direction (x direction) is 3.5 mm, and the length L2 (L) of the joint portion 31 is the length from the end (tip) E of the lead frame 10 to the bent portion 32, which is 2.8 mm. The length L3 from the end (tip) E of the lead frame 10 to the rising portion 33 is 3.1 mm. Also, the width W1 in the depth direction (y direction) of the lead frame 10 (the width of the joint portion 31) is 2.7 mm, and the width W2 of the connecting portion 34 is 2.0 mm. The structures in FIGS. 4 and 5 are examples, and other structures, for example, a structure in which the width of the joint portion 31 and the width of the connecting portion 34 are the same may be used. As shown in FIGS. 4 and 5, in the rising portion 33, the width on the joint portion 31 side may be longer than the width on the connecting portion 34 side. This is because the width of the rising portion 33 on the connecting portion 34 side is short, so that the thermal stress applied to the upper surface electrode 22 (the base portion of the lead frame 10) can be reduced. The thickness of the lead frame 10 is 0.5 mm, it is made of copper, and Ni plating (NiP) may be performed after forming the recess 23 described later.

[0037] In the embodiment, as shown in FIGS. 2 and 3, the joint portion 31 has a plurality of recesses 23. The upper surface of the joint portion 31 refers to the surface on the side opposite to the semiconductor chip 1 side and in contact with the sealing resin 8 layer. The recesses 23 are circular in top view and are evenly arranged in a dot pattern on the entire surface of the joint portion 31. Note that the shape of the recesses 23 in top view may be, in addition to circular, elliptical, square, rectangular, or rhombic. Also, the cross-sectional shape of the recesses 23 may be a shape with a bulging middle, a hemispherical shape, a rectangular shape, or a trapezoidal shape, a triangular shape, or a wedge shape with the tip of the recess 23 narrowed. The recesses 23 have, for example, a hole diameter of 0.05 mm or more and 0.4 mm or less, and a depth of 0.1 mm or more and 0.45 mm or less. For example, as shown in FIG. 3, the plurality of recesses 23 are formed by press molding in 6 rows (0.5 mm pitch P1) in the longitudinal direction and 5 locations (0.46 mm pitch P2) in a row in the depth direction. The plurality of recesses 23 can also be formed by laser processing or the like. Also, the row R1 closest to the rising portion 33 among the plurality of recesses 23 is separated from the end of the joint portion 31 by a distance E1 (for example, 0.15 mm), and the row R6 farthest from the rising portion 33 among the plurality of recesses 23 is separated from the end of the joint portion 31 by a distance E2 (for example, 0.15 mm).

[0038] FIG. 6 is a graph showing the relationship between the recess volume ratio of the semiconductor module according to the embodiment and the strain of the upper electrode. The recesses 23 are provided uniformly over the entire upper surface of the bonding layer 27 as shown in FIGS. 2 and 3. The upper surface is the surface in contact with the sealing resin 8. In FIG. 6, the horizontal axis represents the ratio of the volume of the recesses 23 to the volume of the joint portion 31 of the lead frame 10 (volume ratio: volume of recesses 23 / volume of joint portion 31), and the unit is %. The vertical axis represents the normalized maximum strain of the upper electrode 22 of the semiconductor chip 1, and the unit is %. FIG. 6 is the result of performing a thermal stress analysis by FEM. Also in the embodiment, as in the conventional example, the maximum strain occurs in the electrode at the root portion of the joint portion 31, and the maximum strain is the strain of the upper electrode 22 at the root portion of the joint portion 31. In FIG. 6, the conventional example without the recesses 23 is set to 100%.

[0039] The volume of the recess 23 is changed by varying the depth of the recess 23 from 0.1 mm to 0.45 mm and the hole diameter from 0.05 mm to 0.4 mm. The volume of the joint portion 31 of the lead frame 10 is 3.1 mm × 2.7 mm × 0.5 mm.

[0040] As shown in FIG. 6, regardless of the volume ratio, it can be seen that by providing the recess 23, the maximum strain of the upper surface electrode 22 is reduced, and the effect is achieved at all volume ratios. Also, as shown by A1 in FIG. 6, when the volume ratio is 5% or more, the maximum strain of the upper surface electrode can be reduced by 4%. For example, a volume ratio of 5.4% can be realized by making the recess 23 have a hole diameter of 0.2 mm and a depth of 0.4 mm. Thus, in the embodiment, by providing a plurality of recesses 23 on the lead frame 10, particularly on the joint portion 31, the thermal stress applied to the upper surface electrode 22 can be reduced, the strain of the upper surface electrode 22 can be reduced, and the reliability of the semiconductor module 50 can be improved.

[0041] (Case 7) The lower end of the case 7 made of resin or the like is adhered to the periphery of the heat dissipation base 26. The case 7 has a substantially rectangular cylindrical shape and surrounds the periphery of the front surface of the heat dissipation base 26. A box-shaped recess is formed with the front surface of the heat dissipation base 26 as the bottom surface and the inner wall of the case 7 orthogonal to the front surface of the heat dissipation base 26 as the side wall. Inside this recess, the semiconductor chip 1, the laminated substrate 5, and the wiring member components wired by the wiring member of the lead frame 10 are housed. The material of the case 7 may be a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT), or a thermosetting resin such as phenol resin. Note that the semiconductor chip 1, the laminated substrate 5, etc. may be molded with a sealing resin 8 without including the case 7 to form the semiconductor module 50.

[0042] (Sealing Resin 8) The encapsulating resin 8 is used for an encapsulating resin layer that encapsulates an element to be encapsulated, is provided in contact with the element to be encapsulated, and mainly covers the periphery of the semiconductor chip 1, the multilayer substrate 5, the lead frame 10, and the like. The encapsulating resin 8 can be composed of a thermosetting resin composition, and particularly preferably, it is composed of a thermosetting resin composition having high heat resistance. The thermosetting resin composition contains a thermosetting resin base, and optionally may contain an inorganic filler, a curing agent, a curing accelerator, and necessary additives. The thermosetting resin composition constituting the encapsulating resin 8 may or may not contain a fluorine-based silane coupling agent, but it is preferably not contained. This is because it may lower the glass transition temperature (Tg) of the encapsulating resin 8.

[0043] The thermosetting resin base is not particularly limited, and examples thereof include epoxy resins, phenol resins, maleimide resins, and the like. Among them, an epoxy resin having at least two or more epoxy groups in one molecule is particularly preferable because of its high dimensional stability, water resistance, chemical resistance, and electrical insulation. Specifically, it is preferable to use an aliphatic epoxy resin, an alicyclic epoxy resin, or a mixture thereof.

[0044] The thermosetting resin composition according to this embodiment may contain an inorganic filler (filler) as an optional component. The inorganic filler may be a metal oxide or a metal nitride. For example, it may be fused silica (fused silicon oxide), silica (silicon oxide), alumina (aluminum oxide), aluminum hydroxide, titania (titanium oxide), zirconia (zirconium oxide), aluminum nitride, talc, clay, mica, glass fiber, etc., but is not limited thereto. By using these inorganic fillers, the thermal conductivity of the cured product can be increased and the thermal expansion coefficient can be reduced. Further, these inorganic fillers may be used alone or in combination of two or more. Also, these inorganic fillers may be microfillers or nanofillers, and two or more inorganic fillers having different particle sizes and / or types may be mixed and used. Note that it is preferable from the viewpoint of adhesion that the inorganic filler at least partially enters the recess 23, and it is preferable to contain more inorganic fillers having a smaller particle size than inorganic fillers having a particle size larger than the diameter (hole diameter) of the recess 23 in a top view. Specifically, the particle size (average particle size) of the inorganic filler is preferably from 5 μm to 100 μm, more preferably from 20 μm to 60 μm. Further, it is preferable to contain 10% to 20% of an inorganic filler having a particle size of 5 μm to 10 μm, which is smaller than the diameter of the recess 23 in a top view. Note that the particle size of the inorganic filler can be measured using a particle size distribution measuring instrument utilizing laser scattering or the like.

[0045] The thermosetting resin composition may contain, as an optional component, a curing agent in addition to the thermosetting resin base, or in addition to the thermosetting resin base and the inorganic filler. The curing agent is not particularly limited as long as it can react with the thermosetting resin base, preferably an epoxy resin base, and cure, but it is preferable to use an acid anhydride-based curing agent. Examples of the acid anhydride-based curing agent include aromatic acid anhydrides, specifically phthalic anhydride, pyromellitic anhydride, trimellitic anhydride, etc. Alternatively, cycloaliphatic acid anhydrides, specifically tetrahydrophthalic anhydride, methyltetrahydrophthalic anhydride, hexahydrophthalic anhydride, methylhexahydrophthalic anhydride, methylnadic anhydride, etc., or aliphatic acid anhydrides, specifically succinic anhydride, polyadipic anhydride, polysebacic anhydride, polyazelainic anhydride, etc. can be mentioned. When using bisphenol A type epoxy resin alone or a mixture of bisphenol A type epoxy resin and the high heat-resistant epoxy resin exemplified above as the thermosetting resin base, it may be preferable not to use a curing agent in order to improve heat resistance.

[0046] A curing accelerator can be further added to the thermosetting resin composition as an optional component. As the curing accelerator, imidazole or its derivative, tertiary amine, boric acid ester, Lewis acid, organometallic compound, organic acid metal salt, etc. can be appropriately blended.

[0047] The thermosetting resin composition may also contain optional additives as long as its properties are not impaired. Examples of the additives include, but are not limited to, flame retardants, pigments for coloring the resin, plasticizers and silicone elastomers for improving crack resistance. These optional components and their addition amounts can be appropriately determined by those skilled in the art according to the specifications required for the semiconductor device and / or the encapsulant.

[0048] (Method for manufacturing a semiconductor module according to an embodiment) Next, a method for manufacturing a semiconductor module according to an embodiment will be described. First, the semiconductor chip 1 is bonded to the heat dissipation base 26 and the laminated substrate 5 with the bonding layer 25. A plurality of recesses 23 are formed in the lead frame 10, for example, at the bonding portion 31, by press molding, laser processing, or the like, before bonding the lead frame 10.

[0049] After that, after attaching the case 7 to the heat dissipation base 26, the lead frame 10 having a plurality of recesses 23 is bonded to the semiconductor chip 1. Next, a thermosetting resin composition constituting the encapsulation resin 8 is injected into the case 7 and heat-cured. Specifically, the encapsulation resin 8 is filled in the case 7, and is temporarily cured at 100 to 120 °C for 10 to 120 minutes as the encapsulation resin 8, and is finally cured at about 175 to 185 °C for 1 to 2 hours.

[0050] As described above, according to the semiconductor module of the embodiment, by providing a plurality of recesses on the bonding portion of the lead frame, the thermal stress applied to the upper surface electrode can be reduced, the distortion of the upper surface electrode can be reduced, and the reliability of the semiconductor module can be improved.

[0051] (Example) Hereinafter, the present disclosure will be described in more detail with reference to examples of the present disclosure. However, the present disclosure is not limited to the scope of the following examples. Table 1 shows an example in which only a single row of recesses 23 is provided in the depth direction (y direction), and the dependence of the position (longitudinal direction) of the recesses 23 is confirmed. Table 2 shows an example in which the number of rows of recesses 23 is increased in the longitudinal direction (x direction) from the root, and the dependence of the number of recesses 23 is confirmed. Comparative Example 1 has a shape in which no recess 23 is provided in the lead frame 10. The adhesion was evaluated by a peel test, and the module reliability was evaluated by a power cycle test. The ratio with Comparative Example 1 set to 1 is shown together with the evaluation value.

[0052]

Table 1

[0053] In Table 1, Examples 1 to 6 are examples in which the total length of the lead frame 10 is 3.8 mm, the length L of the joint portion 31 is 3 mm, the length from the base of the lead frame 10 to the center of the recess 23 is D (see FIG. 2), and the position from the base of the recess 23 is changed. The hole diameter of the recess 23 is 0.2 mm, the depth is 0.4 mm, and the pitch in the depth direction is 0.5 mm, and a row of recesses 23 is formed. In Example 1, five recesses 23 are provided in row R1, and no recesses 23 are provided in rows R2 to R6. In Example 2, five recesses 23 are provided in row R2, and no recesses 23 are provided in rows R1, R3 to R6. The same applies to Examples 3 to 6. The base of the lead frame 10 is the boundary between the joint portion 31 and the bent portion 32. The position of the recess in Table 1 (position from the base (mm), ratio) indicates the length D and the ratio D / L (%). The strain reduction rate (%) indicates the reduction rate of the maximum strain of the upper electrode 22 from Comparative Example 1, and is the result of performing thermal stress analysis by FEM. Specifically, based on the maximum strain of Comparative Example 1, the ratio of the reduced strain was defined as the reduction rate.

[0054] FIG. 7 is a graph showing the relationship between the longitudinal position of the recess of the semiconductor module according to the embodiment and the strain of the upper electrode. It is the result of converting Table 1 into a graph. In FIG. 7, the horizontal axis indicates the position from the base of the recess 23 in terms of the ratio D / L, and the unit is %. The vertical axis indicates the maximum strain of the upper electrode 22 of the semiconductor chip 1, and the unit is %. The dotted line in FIG. 7 indicates the strain value of Comparative Example 1 where no recess is provided.

[0055] As shown in Table 1 and FIG. 7, when a row of recesses 23 is provided at a position 60% or less from the base of the lead frame 10, the strain of the upper electrode 22 can be reduced by 3% or more, and the reliability can be improved by 30% or more (A3 in FIG. 7). In particular, when the recess 23 is provided at a position of 10% or more and 40% from the base of the lead frame 10 (A2 in FIG. 7), the strain of the upper electrode 22 is reduced by 3.5% or more, and the reliability is improved by 40% or more. On the other hand, when provided at a position closer to the tip than 60%, the strain increases, the strain reduction rate decreases, and the reliability does not improve much.

[0056] That is, it is understood that even when the volume ratio of the recessed portion 23 is the same, the rate of reduction of strain differs depending on the position of the recessed portion 23, and it is understood that providing the recessed portion 23 closer to the base near the rising portion 33 (bent portion 32) of the joint portion 31 is more effective.

[0057]

Table 2

[0058] In Table 2, Examples 7 to 12 are examples in which the total length of the lead frame 10 is 3.8 mm, the length L of the joint portion 31 is 3 mm, the length from the base of the lead frame 10 to the center of the recessed portion 23 is D, and the number of rows of the recessed portion 23 is increased from the base. When there are a plurality of rows of the recessed portion 23 as in Examples 8 to 12, the length D is the length from the base of the lead frame 10 to the center of the recessed portion 23 that is farthest from the base of the lead frame 10. The hole diameter of the recessed portion 23 is 0.2 mm, the depth is 0.4 mm, and the pitch in the depth direction is 0.5 mm, and a single row of recessed portions 23 is formed. The recessed volume ratio of a single row of recessed portions 23 is 0.9% (5.4 / 6%). Example 7 is an example in which five recessed portions 23 are provided in a single row in the depth direction (y direction) in row R1, and no recessed portion 23 is provided in rows R2 to R6. Example 8 is an example in which five recessed portions 23 are provided in a single row in the depth direction (y direction) in rows R1 and R2, and no recessed portion 23 is provided in rows R3 to R6. The same applies to Examples 9 to 12. The position of the recessed portion in Table 2 (position from the base (mm), ratio) indicates the length D and the ratio D / L (%). The strain reduction rate (%) indicates the reduction rate of the maximum strain of the upper electrode 22 from Comparative Example 1 and is the result of performing thermal stress analysis by FEM. The adhesion indicates the adhesion strength when the recessed portions 23 of 5×6 rows in Example 12, 5×5 rows in Example 11, 5×4 rows in Example 10, 5×3 rows in Example 9, 5×2 rows in Example 8, and 5×1 row in Example 7 are provided at the center of the cup (measurement region).

[0059] FIG. 8 and FIG. 9 are graphs showing the relationship between the longitudinal position where the recess of the semiconductor module according to the embodiment is provided and the distortion of the upper surface electrode. They are respectively the results of converting Table 2 into graphs. In FIG. 8, the horizontal axis represents the position from the base of the recess 23 in terms of the ratio D / L, and the unit is %. The vertical axis represents the maximum distortion of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. The dotted line in FIG. 8 indicates the distortion value of Comparative Example 1 without the recess. In FIG. 9, the horizontal axis represents the position from the base of the recess 23 in terms of the ratio D / L, and the unit is %. The vertical axis represents the normalized maximum distortion of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. In FIG. 9, the comparative example without the recess 23 is set to 100%.

[0060] As shown in Table 2, FIG. 8, and FIG. 9, when the recess 23 is provided by increasing the number of columns from the base to the tip of the lead frame 10, the distortion of the upper surface electrode 22 is reduced compared to the case where only one row of the recess 23 is provided. Furthermore, when the recess 23 is provided from the base to a position of 5% or more and 60% or less, the distortion of the upper surface electrode 22 can be reduced by 3% or more (A4 in FIG. 9), and the reliability can be improved by 40% or more. In particular, when the recess 23 is provided from the base to a position of 20% or more and 60% or less, the distortion of the upper surface electrode 22 can be reduced by 4% or more (A5 in FIG. 9), and the reliability can be improved by 50% or more.

[0061] Therefore, it is preferable to provide the recess 23 at least up to a position of 20% or less from the base. That is, when increasing the number of columns of the recess 23 from the base, the distortion can be further reduced by providing the recess 23 from the base close to the rising portion 33 (bending portion 32) of the joint portion 31.

[0062] Figures 10 and 11 are graphs showing the relationship between the longitudinal position of the recess in the semiconductor module according to the embodiment and the strain of the upper surface electrode. Figures 10 and 11 summarize the results of Tables 1 and 2. In Figure 10, the horizontal axis represents the position from the root as a ratio D / L, and the unit is %. The vertical axis represents the maximum strain of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. The dotted line in Figure 10 indicates the strain value of Comparative Example 1 without a recess, the thick line with △ in Figure 10 indicates the case where only one row of recesses 23 is provided, and the thin line with ○ indicates the case where the number of rows of recesses 23 is increased. Also, in Figure 11, the horizontal axis represents the position from the root as a ratio D / L, and the unit is %. The vertical axis represents the normalized maximum strain of the upper surface electrode 22 of the semiconductor chip 1, and the unit is %. The thick line with △ in Figure 11 indicates the case where only one row of recesses 23 is provided, and the thin line with ○ indicates the case where the number of rows of recesses 23 is increased. In Figure 11, the comparative example without the recess 23 is set to 100%.

[0063] From these results, by providing the recess 23 in the lead frame 10, the strain of the upper surface electrode 22 can be reduced. When the number of rows of the recess 23 is increased from the root to the tip of the lead frame 10, the strain of the upper surface electrode 22 is reduced compared to the case where only one row of the recess 23 is provided.

[0064] As a mechanism for reducing the strain of the upper surface electrode 22, it is presumed that by forming the recess 23 near the root portion of the lead frame 10 where stress concentration occurs, the stress due to the reduction in the rigidity of the lead frame 10 is relaxed. Also, the sealing resin 8 enters the recess 23, and since the sealing resin 8 has lower rigidity than the lead frame 10, the overall rigidity is reduced and it is considered to be more easily deformed. Therefore, it is presumed that the sealing resin 8 in the recess 23 contributes to stress relaxation. It was also found that the same effects as in the examples can be obtained even if the size of the joint portion 31 of the lead frame 10, the depth of the recess 23, the hole diameter, etc. are changed.

[0065] The details of the printing test and power cycle test conducted in the examples are described below. The lead frame 10 used in the power cycle test had a trapezoidal cross-sectional shape of the recess 23 formed by pressing (laser processing) with a wide opening and a narrow hole tip. The recess 23 was formed with a hole diameter of 0.2 mm and a depth of 0.4 mm. An epoxy resin commonly used for encapsulation was used (the same applies to the filler).

[0066] In the power cycle test, with ΔT = 135 °C and Tjmax = 175 °C, one cycle was defined as 1 second of energized operation and 9 seconds of rest. The number of cycles when the thermal resistance increased by 20% or the electrical resistance of the main current part increased by 5% was taken as the power cycle tolerance.

[0067] In the printing test, on the surface of a 5 mm × 5 mm copper plate imitating the joint part 31 of the lead frame 10, recesses 23 with a predetermined shape (0.2 mm Φ / depth 0.4 mm) were provided in a predetermined range (pitch in the longitudinal direction: 0.5 mm, pitch in the depth direction: 0.46 mm), and this copper plate was used as the substrate for the printing cup test. On this copper plate, an epoxy resin composition that can be used as a sealing material was molded into a shape with a bottom diameter of 3.6 mm, a top diameter of 3.0 mm, and a height of 3.0 mm, and a thermosetting reaction was carried out at 100 to 180 °C for 3 hours to obtain a test piece of the epoxy resin cured product molded on the copper plate.

[0068] For the measurement of the shear strength, a force gauge (load measuring instrument: ZTA - 1000N manufactured by IMADA) was used. The measurement conditions were to push the epoxy resin cured product part parallel to the adhesive surface at a speed (strain rate) of 0.2 mm / s, and the strength at the time when the interface between the epoxy resin cured product / resin composite substrate peeled and broke was taken as the adhesion strength.

[0069] In the above, the present disclosure can be variously modified without departing from the spirit of the present disclosure. In each of the above-described embodiments, for example, the dimensions and impurity concentrations of each part are variously set according to the required specifications and the like. Also, in each of the above-described embodiments, in addition to silicon, it is also applicable to wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) as the semiconductor.

Industrial Applicability

[0070] As described above, the semiconductor module and the method for manufacturing the semiconductor module according to the present disclosure are useful for power semiconductor modules used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters for automobiles.

Explanation of Reference Numerals

[0071] 1 Semiconductor chip 2 Insulating substrate 3 First conductive plate 4 Second conductive plate 5 Stacked substrate 7 Case 8 Encapsulating resin 10 Lead frame 21 Insulating protective film 22 Upper surface electrode 23 Concave portion 24 Bonding layer 25 Bonding layer 26 Heat dissipation base (cooler) 27 Bonding layer 31 Joint portion 32 Bent portion 33 Upright portion 34 Connecting portion 50 Semiconductor module

Claims

1. A laminated substrate having a semiconductor element mounted thereon; a lead frame electrically connected to the semiconductor element; a sealing resin that seals a member to be sealed, the member including the semiconductor element, the lead frame, and the laminated substrate; Equipped with The lead frame has a plurality of recesses on an upper surface of a joint portion that is joined to the semiconductor element.

2. 2. The semiconductor module according to claim 1, wherein the recess has a hole diameter of 0.05 mm or more and 0.4 mm or less, and a depth of 0.1 mm or more and 0.45 mm or less.

3. 2. The semiconductor module according to claim 1, wherein a ratio of a volume of the recess to a volume of the joint is 5% or more.

4. If the length of the joint is L and the length from the base of the lead frame to the center of the recess is D, then The recesses are provided in a row in a depth direction of the lead frame, 2. The semiconductor module according to claim 1, wherein the recess is provided at a position where the ratio D / L is 60% or less.

5. 5. The semiconductor module according to claim 4, wherein the recess is provided at a position where the ratio D / L is 10% or more and 40% or less.

6. If the length of the joint is L and the length from the base of the lead frame to the center of the recess that is the farthest from the base is D, then The recesses are provided in a plurality of rows at positions up to a ratio D / L in a depth direction of the lead frame, 2. The semiconductor module according to claim 1, wherein the ratio D / L is 5% or more and 60% or less.

7. 7. The semiconductor module according to claim 6, wherein the ratio D / L is equal to or greater than 20% and equal to or less than 60%.

8. A first step of bonding a semiconductor element to a laminate substrate; a second step of mounting the laminated substrate in a case; a third step of bonding the semiconductor element to a lead frame having a plurality of recesses; a fourth step of injecting resin into the case; A fifth step of curing the resin; Including, A method for manufacturing a semiconductor module, comprising the step of forming the plurality of recesses in a joint portion of the lead frame that is to be joined to the semiconductor element, prior to the third step.

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