Test device, operating method of test device, and semiconductor device test system

Abstract

To provide a test device, an operating method of the test device and a semiconductor device test system.SOLUTION: A test device according to a technical idea of the present disclosure includes an input / output unit including a plurality of input / output terminals configured to be electrically connected to devices formed on a wafer, a comparative circuit configured to receive a plurality of test signals from a device under test formed on the wafer, and generate a plurality of test result signals, based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store bad cell information and repair information related to the device under test, which are indicated by the plurality of test result signals, wherein the number of the plurality of test signals received from the device under test may correspond to an integer.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device test apparatus, a test apparatus operating method, and a semiconductor device test system, and more particularly to a semiconductor device test apparatus having an integer number of input / output resources. [Background technology]

[0002] Automatic test equipment (ATE) can be used to test a number of semiconductor devices formed on a wafer. The ATE can provide test patterns to a device under test (DUT) or receive test signals from the device under test (DUT) through input / output resources of the ATE, and analyze the received signals to test for defects in the semiconductor devices.

[0003] The number of input / output resources of the automatic test equipment may be physically limited. As a result, the burst length of the test signal received from the device under test may become longer depending on the number of semiconductor devices formed on the wafer. As the burst length becomes longer, the test time required to test the semiconductor devices formed on the wafer for defects becomes longer, which results in an increase in the cost of manufacturing the semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to reduce the test time required to test a device under test by receiving an integer number of test signals from the device under test included on a wafer through a test apparatus having an integer number of input / output resources.

[0005] The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A test apparatus according to one aspect of the technical idea of ​​the present disclosure includes an input / output unit including a plurality of input / output terminals electrically connected to elements formed on a wafer, a comparison circuit that receives a plurality of test signals from an element under test included in the wafer and generates a plurality of test result signals based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store defective cell information and repair information related to the element under test indicated by the plurality of test result signals, wherein the number of the plurality of test signals received from the element under test may correspond to an integer.

[0007] A method of operating a test apparatus according to one aspect of the technical idea of ​​the present disclosure includes the steps of receiving a plurality of test signals from a device under test included in a wafer, generating a plurality of test result signals based on a result of comparing each of the received plurality of test signals with a test reference voltage, storing defective cell information related to the device under test in a memory of the test apparatus based on the plurality of test result signals, and generating repair information corresponding to the defective cell information, wherein the number of the plurality of test signals received from the device under test may correspond to an integer.

[0008] A test system according to one aspect of the technical idea of ​​the present disclosure includes a probe card including a plurality of input / output pins electrically connected to an element formed on a wafer, and a test device configured to test an element under test included in the wafer, wherein the probe card receives a plurality of test signals from the element under test via the plurality of input / output pins and provides the received plurality of test signals to the test device, and the test device includes an input / output unit including a plurality of input / output terminals configured to receive the plurality of test signals from the probe card, a comparison circuit that generates a plurality of test result signals based on the plurality of test signals, and a memory configured to receive the plurality of test result signals and store defective cell information and repair information related to the element under test indicated by the plurality of test result signals, and the number of input / output pins electrically connected to the element under test among the plurality of input / output pins may correspond to an integer. Effect of the Invention

[0009] According to the technical idea of ​​the present disclosure, the burst length of the test signal can be shortened by the test apparatus receiving an integer number of test signals from the device under test, and the test time required for the test apparatus to test the device under test can be shortened by shortening the burst length of the test signal.

[0010] The effects obtained from the exemplary embodiments of the present disclosure are not limited to the effects described above, and other effects not mentioned will be clearly derived and understood by a person having ordinary skill in the art to which the exemplary embodiments of the present disclosure belong from the following description. In other words, unintended effects by implementing the exemplary embodiments of the present disclosure will also be derived from the exemplary embodiments of the present disclosure by a person having ordinary skill in the art. [Brief description of the drawings]

[0011] [Figure 1] 1 illustrates a semiconductor device test system according to an exemplary embodiment of the present disclosure. [Figure 2A] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Figure 2B] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Diagram 3] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Figure 4] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Diagram 5] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Figure 6] 1 is a diagram illustrating a semiconductor device test system according to an exemplary embodiment of the present disclosure; [Figure 7A] 4 is a table illustrating a burst length of a test signal when a test is performed on a device under test by a semiconductor device test system according to an exemplary embodiment of the present disclosure. [Figure 7B] 4 is a table illustrating a burst length of a test signal when a test is performed on a device under test by a semiconductor device test system according to an exemplary embodiment of the present disclosure. [Figure 8] 4 is a flow chart illustrating a method of operation of a test apparatus according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or corresponding elements are designated by the same reference numerals, and redundant description thereof will be omitted.

[0013] FIG. 1 is a diagram illustrating a semiconductor device test system 10 according to an exemplary embodiment of the present disclosure.

[0014] 1, a semiconductor device test system 10 according to an exemplary embodiment of the present disclosure is also a system for testing semiconductor devices formed on a wafer WF. In this specification, the semiconductor device test system 10 is also simply referred to as a test system. The wafer WF may include a plurality of semiconductor devices. In this specification, the plurality of semiconductor devices are tested by a test apparatus 100, and the semiconductor devices to be tested at this time are also referred to as devices under test (DUTs).

[0015] In an exemplary embodiment, each of the semiconductor elements formed on the wafer WF may be any one of devices such as a dynamic random-access memory (DRAM), a static random-access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), a phase-change random-access memory (PRAM), and a magnetoresistive random-access memory (MRAM). However, this is merely an example, and the technical idea of ​​the present disclosure is not limited thereto. Each of the semiconductor elements formed on the wafer WF may be any one of devices such as a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), a system large-scale integration (LSI), and a flash memory.

[0016] The semiconductor device test system 10 may include a test apparatus 100 , a probe card 200 , a tester head 300 , and a test chamber 400 .

[0017] The wafer WF may be loaded into the test chamber 400 and then tested by the semiconductor device test system 10. The wafer WF may include silicon (Si). The wafer WF may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0018] In an exemplary embodiment, the wafer WF may be loaded onto the chuck 430 such that connection terminals of the device under test face the probe card 200. In an exemplary embodiment, an Electric Die Sorting (EDS) test may be performed in the test chamber 400. Here, the EDS test refers to a process of applying an electrical signal to the device under test and determining whether the semiconductor device is defective or not based on a signal output by the device under test based on the electrical signal.

[0019] In an exemplary embodiment, the EDS test may include a DC (Direct Current) test and an AC (Alternating Current) test. Here, the DC test is a test that applies a predetermined potential to an input terminal of the device under test and measures DC characteristics such as open / short, input current, output potential, and power supply current to determine whether the device under test is defective. Meanwhile, the AC test is a test that applies a pulse signal to the input terminal of the device under test and measures operational characteristics such as input / output transport delay time and start / end time of the output signal to determine whether the device under test is defective.

[0020] A chuck 430 and a chuck driver 440 may be disposed in the test chamber 400. A plurality of pins 210 may be mounted on the probe card 200. A connection region 110 of the probe card 200 and a connection terminal of an element under test may be electrically connected through the plurality of pins 210. The plurality of pins 210 may include a plurality of pins 210 for connecting a connection terminal on the connection region 110 of the probe card 200 and a connection terminal of the element under test. The plurality of pins 210 may be, for example, but is not limited to, pogo pins.

[0021] The chuck 430 may be disposed on the chuck driving device 440. The chuck 430 may fix the wafer WF by electrostatic adsorption, vacuum adsorption, or the like. The chuck driving device 440 may be disposed under the chuck 430 and connected to the chuck 430. The chuck driving device 440 may translate the chuck 430 in the X direction, the Y direction, and the Z direction. The chuck driving device 440 may also rotate the chuck 430. Here, the X direction and the Y direction are parallel to the first surface 200S of the probe card 200, i.e., the surface facing the wafer WF in the test chamber 400, and are also two directions substantially perpendicular to each other. The Z direction refers to a direction substantially perpendicular to the first surface 200S of the probe card 200. Unless otherwise specified, the definitions of the directions are the same for all the following drawings. For example, even if only a portion of the semiconductor device test system 10 (e.g., the probe card 200) is illustrated, the definitions of the X direction, Y direction, and Z direction based on the first surface 200S of the probe card 200 are the same as those described above.

[0022] In an exemplary embodiment, the chuck driving device 440 may rotate the chuck 430 about an axis parallel to the Z direction so that the connection terminals of the device under test formed on the wafer WF are aligned with the connection region 110 of the probe card 200. In an exemplary embodiment, the chuck driving device 440 may move the chuck 430 in the X direction and the Y direction so that the connection terminals of the device under test formed on the wafer WF are aligned vertically with the connection region 110 of the probe card 200. In an exemplary embodiment, the chuck driving device 440 may move the chuck 430 in the Z direction so that the connection terminals of the device under test formed on the wafer WF are electrically or physically connected to the connection region 110 of the probe card 200.

[0023] In an exemplary embodiment, the probe card 200 may be connected to the test apparatus 100 via the tester head 300. Thus, an electrical signal generated in the test apparatus 100 may be transmitted to the probe card 200. However, the present invention is not limited thereto, and the test apparatus 100 may directly transmit a signal to the probe card 200.

[0024] In an exemplary embodiment, the test apparatus 100 may output electrical signals required for testing electrical characteristics of the device under test formed on the wafer WF. In an exemplary embodiment, the electrical signals output by the test apparatus 100 may be applied to the device under test formed on the wafer WF via the tester head 300 and the probe card 200. The device under test may perform an operation according to the applied electrical signals and generate a plurality of test signals. The plurality of test signals generated by the device under test may be transmitted to the test apparatus 100 via the probe card 200 and the tester head 300. In this case, the number of the plurality of test signals generated by the device under test may correspond to an integer. For example, the number of the plurality of test signals generated by the device under test may correspond to an integer number other than a power-of-two.

[0025] The test apparatus 100 includes input / output resources and may provide a test pattern to a device under test or receive a test signal from the device under test through the input / output resources. In this specification, the test apparatus 100 may refer to automated test equipment (ATE). The input / output resources may refer to, for example, input / output terminals of the test apparatus 100. A specific configuration of the test apparatus 100 will be described later with reference to FIGS. 2A, 3, and 6.

[0026] In an exemplary embodiment, the number of I / O resources (i.e., the number of I / O terminals included in the I / O resources) of the test apparatus 100 may correspond to an integer. For example, the number of I / O resources of the test apparatus 100 may correspond to an integer excluding a power of 2.

[0027] In an exemplary embodiment, the number of I / O terminals of the test apparatus 100 allocated to each DUT may vary based on the number of semiconductor devices formed on the wafer WF. The semiconductor device test system 10 allocates the I / O resources of the test apparatus 100 to each DUT in integer units based on the number of semiconductor devices formed on the wafer WF, and by allocating the I / O resources in integer units in this manner, the burst length of the test signal received from the DUT is reduced. The effect of reducing the burst length depending on the number of semiconductor devices formed on the wafer WF will be described later with reference to Figures 7A and 7B.

[0028] 2A and 2B are diagrams for explaining a semiconductor device test system 10 according to an exemplary embodiment of the present disclosure. Specifically, FIG. 2A is a diagram for explaining a specific configuration of a test apparatus 100. FIG. 2B is a diagram for explaining a wafer WF and a device under test DUT. FIG. 2A and FIG. 2B are described with reference to FIG. 1, and repeated description may be omitted.

[0029] 2A and 2B, a semiconductor device test system 10 may include a test apparatus 100, a probe card 200, and a wafer WF.

[0030] The test apparatus 100 may include a Fail Analysis Memory (FAM) 110 , a comparison circuit 120 , an input / output resource 130 , a control circuit 140 , a pattern generator 150 , and a driver 160 .

[0031] The test apparatus 100 may be electrically connected to the wafer WF via the probe card 200. The wafer WF may include a plurality of semiconductor devices, and the test apparatus 100 may perform an electrical test operation (e.g., an EDS test) on each of the semiconductor devices on the wafer WF. The semiconductor devices included in the wafer WF may also be called devices under test (DUTs) since they are also test targets by the test apparatus 100.

[0032] The test apparatus 100 can detect defective cells present in the device under test DUT by performing electrical tests on the device under test DUT included in the wafer WF, and can allow the device under test DUT to function normally by replacing the detected defective cells with redundancy cells.

[0033] 2B is a diagram for explaining a device under test (DUT). Referring to FIG. 2B, each device under test (DUT) may include a memory cell array (MCA) including a plurality of memory cells configured to store data, and an external connection pad (PADS) used for connection with an external device (e.g., the test device 100). The external connection pad (PADS) may be divided into a first pad (PAD_1) and a second pad (PAD_2).

[0034] In an exemplary embodiment, the first pad PAD_1 is also configured to transmit and receive data signals between the test apparatus 100 and the device under test DUT. In some embodiments, the first pad PAD_1 is also referred to as a data input / output pad. In some embodiments, the data signals between the test apparatus 100 and the device under test DUT may be referred to as DQ signals. An example of a data signal transmitted and received between the test apparatus 100 and the device under test DUT is a test signal provided from the device under test DUT to the test apparatus 100.

[0035] In the exemplary embodiment, the second pad PAD_2 is also configured to transmit and receive a clock signal CLK, a command signal CMD, and an address signal ADDR between the test apparatus 100 and the device under test DUT.

[0036] In an exemplary embodiment, electrical tests on multiple semiconductor devices included in a wafer WF may be performed in parallel at the same time by the test apparatus 100. For example, an electrical test operation by the test apparatus 100 is performed simultaneously on all semiconductor devices present on the wafer WF, and such a test method is also called a one-shot test.

[0037] 2A , FAM 110 is any hardware that stores information and is accessible by control circuitry 140. FAM 110 may include, for example, read only memory (ROM), random-access memory (RAM), dynamic random access memory (DRAM), double-data-rate dynamic random access memory (DDR-DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, polymer memory, phase change memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic cards / disks, optical cards / disks, or a combination of two or more thereof.

[0038] The information stored in the FAM 110 may include redundancy cell information 111 , bad cell information 112 , and repair information 113 .

[0039] The redundancy cell information 111 may include information related to an address of a redundancy cell present in the device under test DUT. The redundancy cell may refer to a cell designed as an extra cell to replace a defective cell in the case where a defective cell exists in the semiconductor device. In some embodiments, the FAM 110 further includes a buffer memory, and the redundancy cell information 111 may be stored in the buffer memory. The defective cell information 112 may include information related to an address of a defective cell present in the device under test DUT. The repair information 113 may include information for repairing a defective cell present in the device under test DUT. The information for repairing a defective cell may also be information obtained by mapping an address of a defective cell and an address of a redundancy cell. For example, if a first memory cell of a first device under test is a defective cell, the repair information 113 may include information in which an address of the first memory cell and an address of a redundancy cell corresponding to the first memory cell are mapped.

[0040] In an exemplary embodiment, the test apparatus 100 may perform an electrical test on the wafer WF and output the generated repair information 113 to the outside.

[0041] The comparison circuit 120 may generate a plurality of test result signals trs based on a result of comparing the plurality of test signals ts received from the device under test DUT with a test reference voltage. The number of the plurality of test signals ts received by the comparison circuit 120 may correspond to an integer. For example, the number of the plurality of test signals ts received by the comparison circuit 120 may correspond to an integer excluding a power of two.

[0042] In an exemplary embodiment, the test apparatus 100 receiving the test signals ts through the comparison circuit 120 also means that the test apparatus 100 reads data stored in memory cells of the device under test. In this case, the time it takes for the test apparatus 100 to read each test signal is also referred to as a burst length. The burst length of a test signal may be divided into a plurality of burst sections. In this case, each burst section may correspond to a read time of two or more memory cells among memory cells included in a memory cell array of the device under test. In some embodiments, the two or more memory cells corresponding to each burst section may be adjacent memory cells among memory cells present in the memory cell array of the device under test, and such adjacent two or more memory cells may be referred to as compressed memory cells. Examples of burst lengths and burst sections will be described below with reference to FIG. 4 and FIG. 6.

[0043] In an exemplary embodiment, the comparison circuit 120 may include a plurality of comparators. The number of comparators included in the comparison circuit 120 may correspond to an integer. For example, the number of comparators included in the comparison circuit 120 may correspond to an integer excluding a power of 2. A detailed description of the comparators will be provided below with reference to FIGS. 3 and 6.

[0044] The comparison circuit 120 may provide a plurality of test result signals trs to the FAM 110. The number of the plurality of test result signals trs provided to the FAM 110 may correspond to an integer. For example, the number of the plurality of test result signals trs provided to the FAM 110 may correspond to an integer excluding a power of 2. The plurality of test result signals trs may include information related to whether the device under test DUT passed the test or not.

[0045] The test apparatus 100 may provide test patterns to the device under test DUT via the input / output resources 130 or may receive test signals from the device under test DUT via the input / output resources 130 .

[0046] The I / O resource 130 may include a plurality of I / O terminals. For example, the I / O resource 130 may include first through N-th I / O terminals 130_1 through 130_N. In this case, the number of I / O terminals included in the I / O resource 130 may correspond to an integer, for example, an integer excluding a power of 2.

[0047] The control circuit 140 may generate repair information 113 based on the redundancy cell information 111 and the defective cell information 112 stored in the FAM 110. The control circuit 140 may control the pattern generator 150 to provide a clock signal CLK, a command signal CMD, an address signal ADDR, etc. to the device under test DUT. At this time, the signals generated by the pattern generator 150 may be provided to the device under test DUT via the driver 160. In an exemplary embodiment, the control circuit 140 may generate a test reference voltage and provide the test reference voltage to the comparison circuit 120. However, this is merely an example, and the test reference voltage may be generated by a separate voltage generation circuit present in the test apparatus 100.

[0048] The probe card 200 may electrically connect the device under test (DUT) and the test apparatus 100. A plurality of test signals (ts) generated in the device under test (DUT) may be provided to the test apparatus 100 through the probe card 200. The probe card 200 may include a plurality of pins. The plurality of pins may include a plurality of input / output pins electrically connected to a first pad (PAD_1) of the device under test (DUT), and the number of the plurality of input / output pins may correspond to an integer. For example, the number of the plurality of input / output pins of the probe card 200 may correspond to an integer that is not a power of 2. In this specification, among the plurality of pins included in the probe card 200, a pin electrically connected to a first pad (PAD_1) that is a data input / output pad of the device under test (DUT) is also referred to as an input / output pin. In the semiconductor device test system 10 according to an exemplary embodiment of the present disclosure, the test apparatus 100 may be configured to receive a plurality of test signals (ts) from the device under test (DUT) through the probe card 200. In this case, the number of the plurality of test signals (ts) may correspond to an integer. For example, the number of the multiple test signals ts may correspond to an integer that is not a power of 2. In this manner, by the test apparatus 100 receiving from the device under test DUT a number of test signals that correspond to an integer that is not a power of 2, the burst length of the test signals may be reduced compared to when receiving a number of test signals that correspond to a power of 2. By reducing the burst length of the test signals, the time required to test the device under test DUT may be reduced.

[0049] 3 and 4 are diagrams for explaining a semiconductor device test system 10a according to an exemplary embodiment of the present disclosure. Specifically, the diagrams are for explaining that a test apparatus 100 tests a device under test using two data I / O pads among data I / O pads included in the device under test. FIGS. 3 and 4 are described with reference to FIGS. 1 to 2B, and repeated description may be omitted.

[0050] 3, a semiconductor device test system 10a may correspond to the semiconductor device test system 10 of FIG. 2A. In the following, FIG. 3 will be described focusing on the differences from FIG. 2A. The semiconductor device test system 10a may include a test apparatus 100, a probe card 200, a first device under test 510a, and a second device under test 520a. The test apparatus 100 may include a FAM 110, a comparison circuit 120a, an input / output resource 130a, a control circuit 140, and a pattern generator 150.

[0051] 3, the test apparatus 100 is illustrated testing two elements, a first element under test 510a and a second element under test 520a, but this is merely an example and it is possible to test a larger number of elements. When the test apparatus 100 tests the first element under test 510a and the second element under test 520a, the first element under test 510a and the second element under test 520a may be operated in a burst mode.

[0052] The first device under test 510a may include a first pad 511a as an external connection pad. The first pad 511a may include a first data input / output pad 511_1a and a second data input / output pad 511_2a. The first device under test 510a may output a first test signal ts1 through the first data input / output pad 511_1a and output a second test signal ts2 through the second data input / output pad 511_2a. The first test signal ts1 and the second test signal ts2 are also signals obtained by reading values ​​(e.g., test patterns already input by the test apparatus 100) stored in a plurality of memory cells included in the first device under test 510a.

[0053] The second device under test 520a may include a first pad 521a as an external connection pad. The first pad 521a may include a first data input / output pad 521_1a and a second data input / output pad 521_2a. The second device under test 520a may output a third test signal ts3 through the first data input / output pad 521_1a and a fourth test signal ts4 through the second data input / output pad 521_2a. The third test signal ts3 and the fourth test signal ts4 are also signals obtained by reading values ​​(e.g., test patterns already input by the test apparatus 100) stored in a plurality of memory cells included in the second device under test 520a.

[0054] In an exemplary embodiment, the first element under test 510a and the second element under test 520a may operate based on a clock signal, a command signal, and an address signal generated by the pattern generator 150. Although not shown, the first element under test 510a and the second element under test 520a may receive the clock signal, the command signal, and the address signal through pins other than the data input / output pins among a plurality of pins included in the probe card 200.

[0055] The input / output resource 130a includes first to fourth input / output terminals 130_1a to 130_4a, and the test apparatus 100 may receive two test signals from each of the elements under test 510a, 520a through the input / output resource 130a. For example, the test apparatus 100 may receive two test signals, i.e., a first test signal ts1 and a second test signal ts2, from the first element under test 510a. Similarly, the test apparatus 100 may receive two test signals, i.e., a third test signal ts3 and a fourth test signal ts4, from the second element under test 520a.

[0056] The probe card 200 may receive a first test signal ts1 from the first device under test 510a via a first input / output pin 211_1a, and may provide the first test signal ts1 to the test apparatus 100 via a first input / output terminal 130_1a.

[0057] The probe card 200 may receive a second test signal ts2 from the first device under test 510a via the second input / output pin 211_2a, and may provide the second test signal ts2 to the test apparatus 100 via the second input / output terminal 130_2a.

[0058] The probe card 200 may receive a third test signal ts3 from the second device under test 520a via the third input / output pin 211_3a, and may provide the third test signal ts3 to the test apparatus 100 via the third input / output terminal 130_3a.

[0059] The probe card 200 may receive a fourth test signal ts4 from the second device under test 520a via the fourth input / output pin 211_4a, and may provide the fourth test signal ts4 to the test apparatus 100 via the fourth input / output terminal 130_4a.

[0060] The comparison circuit 120a may include first to fourth comparators C1 to C4. The first comparator C1 may receive a first test signal ts1 via a first input / output terminal 130_1a and compare the first test signal ts1 with a test reference voltage VOH. The first comparator C1 may generate a first test result signal trs1 based on a result of comparing the first test signal ts1 with the test reference voltage VOH.

[0061] In an exemplary embodiment, the test reference voltage VOH is generated by the control circuit 140, but this is merely exemplary and may be generated through a separate voltage generating circuit present in the test apparatus 100.

[0062] The second comparator C2 may receive the second test signal ts2 via the second input / output terminal 130_2a, compare the second test signal ts2 with the test reference voltage VOH, and generate a second test result signal trs2 based on a result of comparing the first test signal ts2 with the test reference voltage VOH.

[0063] The third comparator C3 may receive the third test signal ts3 via the third input / output terminal 130_3a, and compare the third test signal ts3 with the test reference voltage VOH. The third comparator C3 may generate a third test result signal trs3 based on a result of comparing the third test signal ts3 with the test reference voltage VOH.

[0064] The fourth comparator C4 may receive a fourth test signal ts4 via the fourth input / output terminal 130_4a, compare the fourth test signal ts4 with a test reference voltage VOH, and generate a fourth test result signal trs4 based on a result of comparing the fourth test signal ts4 with the test reference voltage VOH.

[0065] The test result signal generated by the comparison circuit 120a may include information on memory cells that have failed the test among the memory cells of the device under test (e.g., addresses of memory cells that have failed the test). In an exemplary embodiment, if the value indicated by the first test signal ts1 is greater than the test reference voltage VOH, the first comparator C1 may generate a first test result signal trs1 indicating that the test result for the memory cells of the first device under test 510a is pass. If the value indicated by the first test signal ts1 is less than the test reference voltage VOH, the first comparator C1 may generate a first test result signal trs1 including information on memory cells that have failed the test result among the memory cells of the first device under test 510a corresponding to the first test signal ts1. The second test result signal trs2 through the fourth test result signal trs4 are also generated in the same manner as the first test result signal trs1, and a duplicated description will be omitted.

[0066] 4, FIG. 4 is a diagram showing the test apparatus 100 reading the first test signal ts1 and the second test signal ts2 from the first device under test 510a in response to the clock signal CLK generated by the pattern generator 150.

[0067] In an exemplary embodiment, it is assumed that a total of 288 burst sections are required to read data (e.g., input test pattern data) stored in memory cells of the first device under test 510a of FIG. 3. The burst length of the first test signal ts1 and the second test signal ts2 is also the first burst length RT1, and since the first device under test 510a of FIG. 3 outputs test signals to the test apparatus 100 via two data I / O pads 511_1a and 511_2a, the first burst length RT1 is also 144. The first test signal ts1 and the second test signal ts2 may be composed of a total of 144 burst sections, i.e., the first burst section BL1 to the 144th burst section BL144. Each burst section may correspond to a data signal for reading a plurality of cells among a plurality of memory cell arrays included in the first device under test 510a. For example, the first burst section BL1 may correspond to a data signal that reads M (M is an integer equal to or greater than 1) adjacent memory cells in the memory cell array of the first device under test 510a. The second burst section BL2 through the 144th burst section BL144 may also correspond to data signals that read M (M is an integer equal to or greater than 1) adjacent memory cells in the memory cell array of the first device under test 510a, similar to the first burst section BL1.

[0068] 3, when electrically testing the DUTs, the test apparatus 100 may assign only two I / O terminals of the I / O resources 130a to each DUT, but if the number of terminals assigned to each DUT is increased, the burst length of the test signal may be reduced. In relation to this, an example of assigning three I / O terminals to each DUT will be described with reference to FIGS. 5 and 6.

[0069] 5 and 6 are diagrams for explaining a semiconductor device test system 10b according to an exemplary embodiment of the present disclosure. Specifically, the diagrams are for explaining that the test apparatus 100 tests the device under test using three data I / O pads among the data I / O pads included in the device under test. The following description will be given with reference to FIGS. 5, 6, and 1 to 4, and redundant description may be omitted.

[0070] 5, a semiconductor device test system 10b may correspond to the semiconductor device test system 10 of FIG. 2A. In the following description of FIG. 5, differences from FIG. 2A will be mainly described. The semiconductor device test system 10b may include a test apparatus 100, a probe card 200, a first device under test 510b, and a second device under test 520b. The test apparatus 100 may include a FAM 110, a comparison circuit 120B, an input / output resource 130b, a control circuit 140, and a pattern generator 150.

[0071] 5, the test apparatus 100 is illustrated testing two devices, a first device under test 510b and a second device under test 520b, however, this is merely an example and it is possible to test a larger number of devices. When the test apparatus 100 tests the first device under test 510b and the second device under test 520b, the first device under test 510b and the second device under test 520b may be operated in a burst mode.

[0072] The first device under test 510b may include a first pad 511b as an external connection pad. The first pad 511b may include a first data input / output pad 511_1b, a second data input / output pad 511_2b, and a third data input / output pad 511_3b. The first device under test 510b may output a first test signal ts1 through the first data input / output pad 511_1b, a second test signal ts2 through the second data input / output pad 511_2b, and a third test signal ts3 through the third data input / output pad 511_3b. The first test signal ts1, the second test signal ts2, and the third test signal ts3 are also signals obtained by reading values ​​(e.g., test patterns already input by the test apparatus 100) stored in memory cells of the first device under test 510b.

[0073] The second device under test 520b may include a first pad 521b as an external connection pad. The first pad 521b may include a first data input / output pad 521_1b, a second data input / output pad 521_2b, and a third data input / output pad 521_3b. The second device under test 520b may output a fourth test signal ts4 through the first data input / output pad 521_1b, a fifth test signal ts5 through the second data input / output pad 521_2b, and a sixth test signal ts6 through the third data input / output pad 521_3b. The fourth test signal ts4, the fifth test signal ts5, and the sixth test signal ts6 are also signals obtained by reading values ​​(e.g., test patterns already input by the test apparatus 100) stored in memory cells of the second device under test 520b.

[0074] In an exemplary embodiment, the first element under test 510b and the second element under test 520b may operate based on a clock signal, a command signal, and an address signal generated by the pattern generator 150. Although not shown, the first element under test 510b and the second element under test 520b may receive the clock signal, the command signal, and the address signal through pins other than the data input / output pins among a plurality of pins included in the probe card 200.

[0075] 5, the I / O resource 130b includes first to sixth I / O terminals 130_1b to 130_6b, and the test apparatus 100 may receive three test signals from each of the devices under test 510a and 520b through the I / O resource 130b. For example, the test apparatus 100 may receive three test signals, i.e., a first test signal ts1, a second test signal ts2, and a third test signal ts3, from the first device under test 510b. Similarly, the test apparatus 100 may receive three test signals, i.e., a fourth test signal ts4, a fifth test signal ts5, and a sixth test signal ts6, from the second device under test 520b.

[0076] The probe card 200 may receive a first test signal ts1 from the first device under test 510b via a first input / output pin 211_1b, and may provide the first test signal ts1 to the test apparatus 100 via a first input / output terminal 130_1b.

[0077] The probe card 200 may receive a second test signal ts2 from the first device under test 510b via the second input / output pin 211_2b, and may provide the second test signal ts2 to the test apparatus 100 via the second input / output terminal 130_2b.

[0078] The probe card 200 may receive a third test signal ts3 from the first device under test 510b via the third input / output pin 211_3b, and may provide the third test signal ts3 to the test apparatus 100 via the third input / output terminal 130_3b.

[0079] The probe card 200 may receive a fourth test signal ts4 from the second device under test 520b via the fourth input / output pin 211_4b, and may provide the fourth test signal ts4 to the test apparatus 100 via the fourth input / output terminal 130_4b.

[0080] The probe card 200 may receive a fifth test signal ts5 from the second device under test 520b via a fifth input / output pin 211_5b, and may provide the fifth test signal ts5 to the test apparatus 100 via a fifth input / output terminal 130_5b.

[0081] The probe card 200 may receive a sixth test signal ts6 from the second device under test 520b via a sixth input / output pin 211_6b, and may provide the sixth test signal ts6 to the test apparatus 100 via a sixth input / output terminal 130_6b.

[0082] The comparison circuit 120B may include first to sixth comparators C1 to C6. The first comparator C1 may receive a first test signal ts1 via the first input / output terminal 130_1b and compare the first test signal ts1 with a test reference voltage VOH. The first comparator C1 may generate a first test result signal trs1 based on a result of comparing the first test signal ts1 with the test reference voltage VOH.

[0083] The second comparator C2 may receive the second test signal ts2 via the second input / output terminal 130_2b, compare the second test signal ts2 with the test reference voltage VOH, and generate a second test result signal trs2 based on a result of comparing the first test signal ts2 with the test reference voltage VOH.

[0084] The third comparator C3 may receive the third test signal ts3 via the third input / output terminal 130_3b, and compare the third test signal ts3 with the test reference voltage VOH. The third comparator C3 may generate a third test result signal trs3 based on a result of comparing the third test signal ts3 with the test reference voltage VOH.

[0085] The fourth comparator C4 may receive the fourth test signal ts4 via the fourth input / output terminal 130_4b, compare the fourth test signal ts4 with the test reference voltage VOH, and generate a fourth test result signal trs4 based on a result of comparing the fourth test signal ts4 with the test reference voltage VOH.

[0086] The fifth comparator C5 may receive a fifth test signal ts5 via the fifth input / output terminal 130_5b, compare the fifth test signal ts5 with a test reference voltage VOH, and generate a fifth test result signal trs5 based on a result of comparing the fifth test signal ts5 with the test reference voltage VOH.

[0087] The sixth comparator C6 may receive a sixth test signal ts6 via the sixth input / output terminal 130_6b, and compare the sixth test signal ts6 with a test reference voltage VOH. The sixth comparator C6 may generate a sixth test result signal trs6 based on a result of comparing the sixth test signal ts6 with the test reference voltage VOH.

[0088] Referring to FIG. 6, FIG. 6 is a diagram showing the test apparatus 100 reading the first test signal ts1, the second test signal ts2 and the third test signal ts3 from the first element under test 510b according to the clock signal CLK generated by the pattern generator 150 of FIG. 5.

[0089] In an exemplary embodiment, assume that a total of 288 burst intervals are required to read data (e.g., input test pattern data) stored in the memory cells of the first device under test 510b of FIG. 5, as is the case for reading data stored in the memory cells of the first device under test 510a of FIG. 3.

[0090] 5, one more data I / O pad can be used to output a test signal to the test apparatus 100, as compared with the first device under test 510a of FIG 3. Therefore, the burst lengths of the first test signal ts1, the second test signal ts2, and the third test signal ts3 are also the second burst length RT2, and since the first device under test 510b of FIG 5 outputs test signals to the test apparatus 100 via three data I / O pads 511_1b, 511_2b, and 511_3b, the second burst length RT2 is also 96.

[0091] The first test signal ts1, the second test signal ts2, and the third test signal ts3 may be composed of a total of 96 burst sections, that is, a first burst section BL1 to a 96th burst section BL96.

[0092] As can be seen by comparing the graph of FIG. 6 with FIG. 4, if the number of I / O terminals of the test apparatus 100 assigned to each DUT increases, the burst length of the test signal read from the DUT decreases, and therefore the test time required to test the DUT may decrease. However, since the number of I / O terminals included in the test apparatus 100 is physically limited, it is necessary to adjust the number of I / O terminals of the test apparatus 100 assigned to the DUT based on the number of semiconductor devices included in the wafer (FIG. 2A) WF. In this regard, examples of adjusting the number of I / O terminals will be described later with reference to FIGS. 7 and 8.

[0093] 7A and 7B are tables for explaining burst lengths of test signals when a test is performed on a device under test by a semiconductor device test system according to an exemplary embodiment of the present disclosure. Specifically, FIG. 7A is a table showing burst lengths when an input / output terminal of the test apparatus 100 is assigned to each device under test DUT in units of a power of 2, and FIG. 7B is a table showing burst lengths when an input / output terminal of the test apparatus 100 is assigned to each device under test DUT in units of an integer excluding powers of 2. FIG. 7A and FIG. 7B are described with reference to FIG. 2A, and repeated description may be omitted.

[0094] For convenience of explanation, it is assumed that the number of input / output terminals 130_1 to 130_N included in the input / output resource 130 of the test system 10 is 6144. That is, it is assumed that N=6144. This assumption is merely exemplary, and it goes without saying that the value of N may be smaller or larger. It is also assumed that a total of 288 burst periods are required for the test apparatus 100 of FIG. 1 to read data (e.g., input test pattern data) stored in a memory cell of the device under test DUT.

[0095] Referring to FIG. 7A, if the number of input / output terminals of the test apparatus 100 assigned to each device under test DUT is adjusted in units of a power of two, the burst length is as follows.

[0096] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the first reference value ref1 and less than the second reference value ref2, four input / output terminals are assigned to each device under test DUT, and such assignment of four input / output terminals to each device under test DUT is also called PBT (Parallel Bit Test) x 4. In this case, the burst length of the test signal is 72. In this case, the first reference value ref1 is, for example, 768, and the second reference value ref2 is, for example, 877.

[0097] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the second reference value ref2 and less than the third reference value ref3, each device under test DUT can still be assigned four input / output terminals. In this case, the burst length of the test signal is 72. In this case, the third reference value ref3 is, for example, 1013.

[0098] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the third reference value ref3 and less than the fourth reference value ref4, each device under test DUT is still assigned four input / output terminals. In this case, the burst length of the test signal is also 72. In this case, the fourth reference value ref4 is also, for example, 1228.

[0099] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the fourth reference value ref4 and less than the fifth reference value ref5, each device under test DUT is still assigned four input / output terminals. In this case, the burst length of the test signal is also 72. In this case, the fifth reference value ref5 is also, for example, 1536.

[0100] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the fifth reference value ref5 and less than the sixth reference value ref6, two input / output terminals may be assigned to each device under test DUT. In this case, the burst length of the test signal may be 144. In this case, the sixth reference value ref6 may be, for example, 2048.

[0101] Referring to FIG. 7B, if the number of input / output terminals of the test apparatus 100 assigned to each device under test DUT is adjusted in integer units, the burst length is as follows.

[0102] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the first reference value ref1 and less than the second reference value ref2, seven input / output terminals are assigned to each device under test DUT, and the burst length of the test signal is also 42.

[0103] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the second reference value ref2 and less than the third reference value ref3, six input / output terminals are assigned to each device under test DUT, and the burst length of the test signal is 48.

[0104] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the third reference value ref3 and less than the fourth reference value ref4, five input / output terminals may be assigned to each device under test DUT. In this case, the burst length of the test signal is also 58.

[0105] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the fourth reference value ref4 and less than the fifth reference value ref5, each device under test DUT is assigned four input / output terminals, and the burst length of the test signal is also 72.

[0106] In an exemplary embodiment, when the number of devices under test DUT formed on the wafer WF is greater than the fifth reference value ref5 and less than the sixth reference value ref6, each device under test DUT is assigned three input / output terminals, and the burst length of the test signal is also 96.

[0107] As described above, if the number of input / output terminals of the test apparatus 100 assigned to each device under test DUT is adjusted in integer units rather than in power-of-two units, the burst length of the test signal can be reduced compared to when the number of input / output terminals of the test apparatus 100 assigned to each device under test DUT is adjusted in power-of-two units.

[0108] For example, the number of input / output terminals of the test apparatus 100 may be determined by dividing the total number of available input / output terminals of the test apparatus 100 by the total number of test apparatuses 100, and then rounding down to the nearest integer. For example, as shown in FIG. 7B, if the total number of input and output terminals of the test apparatus 100 is N=6144, and the number of devices of the DUT under test is greater than the first reference value ref1 (e.g., 768) and less than the second reference value ref2 (e.g., 877) (e.g., 800), the number of input and output terminals of the test apparatus 100 assigned to each DUT under test is 6144 / 800=7.

[0109] In an exemplary embodiment, the assignment of input and output terminals of test apparatus 100 to each device of the DUT under test may be performed by control circuitry 140 of test apparatus 100 .

[0110] In an exemplary embodiment, the allocation of input and output terminals of test apparatus 100 to each device of the DUT under test may be accomplished by varying attributes such as the shape of probe card 200 .

[0111] Fig. 8 is a flow chart for explaining an operation method of the test apparatus according to an exemplary embodiment of the present disclosure. The operation method will be explained with reference to Fig. 8, Fig. 2A, and Fig. 5. When the operation method is explained with reference to Fig. 5, the first element under test 510b is taken as an example for convenience of explanation, but it goes without saying that the second element under test 520b can be explained in the same manner as the first element under test 510b. Hereinafter, explanations that overlap with the above contents may be omitted.

[0112] 8, in step S110, the test apparatus 100 may receive a plurality of test signals ts from a device under test DUT included in a wafer (FIG. 2A) WF.

[0113] In an exemplary embodiment, the test apparatus 100 may receive a first test signal ts1 through a third test signal ts3 from the first device under test 510b.

[0114] In an exemplary embodiment, the number of the plurality of test signals ts corresponds to an integer, for example, the number of the plurality of test signals ts may correspond to an integer excluding a power of two.

[0115] In step S120, the test apparatus 100 may generate a plurality of test result signals trs based on the results of comparing each of the plurality of test signals ts with a test reference voltage VOH (FIG. 5).

[0116] In an exemplary embodiment, the number of the plurality of test result signals trs corresponds to an integer, for example, the number of the plurality of test signals trs may correspond to an integer other than a power of two.

[0117] In an exemplary embodiment, the test apparatus 100 may generate a first test result signal trs1 based on a result of comparing the first test signal ts1 with the test reference voltage VOH through a first comparator C1 of the comparison circuit 120B. Similarly, the test apparatus 100 may generate a second test result signal trs2 based on a result of comparing the second test signal ts2 with the test reference voltage VOH through a second comparator C2 of the comparison circuit 120B. Also, the test apparatus 100 may generate a third test result signal trs3 based on a result of comparing the third test signal ts3 with the test reference voltage VOH through a third comparator C3 of the comparison circuit 120B.

[0118] In step S130, the test apparatus 100 may store the failed cell information 112 related to the device under test DUT in the FAM 110 based on the plurality of test result signals trs.

[0119] In step S140, the test apparatus 100 may generate repair information 113 corresponding to the defective cell information 112.

[0120] In an exemplary embodiment, the test apparatus 100 may include repair information 113 for repairing the defective cells of the first device under test 510b based on the redundancy cell information 111 and the defective cell information 112 through the control circuit 140.

[0121] As described above, the drawings and the specification disclose exemplary embodiments. Although specific terms are used in the present specification to describe the embodiments, these terms are used only for the purpose of describing the technical ideas of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical ideas of the claims. [Explanation of symbols]

[0122] 10. Semiconductor device test system 100 Test Equipment 200 Probe Card 300 Tester Head 400 Test Chamber WF Wafer

Claims

1. 1. A test apparatus for performing electrical tests on devices formed on a wafer, comprising: an input / output unit including a plurality of input / output terminals electrically connected to the devices formed on the wafer; a comparison circuit that receives a plurality of test signals from devices under test included in the wafer and generates a plurality of test result signals based on the plurality of test signals; a memory configured to receive the plurality of test result signals and store defective cell information and repair information related to the device under test indicated by the plurality of test result signals; 2. A test apparatus comprising: a device under test, the device being configured to receive a plurality of test signals each corresponding to an integer number;

2. 2. The test apparatus according to claim 1, wherein the number of the plurality of test signals corresponds to an integer other than a power of two.

3. 2. The test apparatus according to claim 1, wherein the number of the plurality of test result signals corresponds to an integer excluding a power of two.

4. 2. The test device according to claim 1, wherein the plurality of test signals are input via independent input / output terminals.

5. 5. The test apparatus of claim 1, wherein the number of terminals electrically connected to the device under test among the plurality of input / output terminals corresponds to an integer excluding a power of two.

6. 5. The test apparatus of claim 1, wherein the plurality of input / output terminals are electrically connected to data input / output pads of devices formed on the wafer.

7. 1. A method of operating a test apparatus for performing electrical tests on devices formed on a wafer, comprising: receiving a plurality of test signals from devices under test included in the wafer; generating a plurality of test result signals based on a comparison of each of the received test signals with a test reference voltage; storing defective cell information related to the device under test in a memory of the test apparatus based on the plurality of test result signals; generating repair information corresponding to the defective cell information; 13. The method of claim 12, wherein a number of the plurality of test signals received from the device under test corresponds to an integer number.

8. 8. The method of claim 7, wherein the number of the plurality of test signals corresponds to an integer other than a power of two.

9. 1. A test system for performing electrical tests on devices formed on a wafer, comprising: a probe card including a plurality of input / output pins electrically connected to devices formed on the wafer; a test apparatus configured to test devices under test included on the wafer; The probe card comprises: receiving a plurality of test signals from the device under test via the plurality of input / output pins, and providing the received plurality of test signals to the test apparatus; The test device comprises: an input / output unit including a plurality of input / output terminals configured to receive the plurality of test signals from the probe card; a comparison circuit for generating a plurality of test result signals based on the plurality of test signals; a memory configured to receive the plurality of test result signals and store defective cell information and repair information related to the device under test indicated by the plurality of test result signals; 2. A test system comprising: a test pin circuit for testing a device under test including a plurality of input / output pins, the number of which corresponds to an integer;

10. The plurality of test signals are input via independent input / output pins, 10. The test system of claim 9, wherein the number of the I / O pins electrically connected to the device under test corresponds to an integer excluding a power of two.

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