Test fixture, testing method and manufacturing method of semiconductor element

Abstract

To provide a test fixture capable of preventing a wafer from being damaged.SOLUTION: The test fixture for testing each of a plurality of semiconductor elements formed on a wafer comprises: a substrate that, when a thickness direction of the wafer in the test is defined as vertical direction, a front face of the wafer defined as upper, a rear face of the wafer defined as lower, is located above the wafer in the test and includes an opening formed through the vertical direction; a chamber provided below the substrate and formed so as to surround the opening; a first probe for measuring the semiconductor element, connected to the substrate. The chamber incudes: a surrounding member surrounding the first probe and floating upward when air is injected through the opening in the test; a support part supporting the surrounding member before the test; and an inhibition member inhibiting the surrounding member from being lowered so that the surrounding member does not come into in contact with wafer when air injection is stopped into the opening in the test.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a test jig, a test method, and a method for manufacturing a semiconductor device.

Background Art

[0002] In semiconductor devices such as power MOSFETs (Metal-Oxide-Semiconductor-Field-Effect-Transistors) and IGBTs (Insulated Gate Bipolar Transistors), a test for applying a high voltage (high voltage test) is performed to screen defective products. As a jig for such a high voltage test, a small chamber is provided under a probe card, and air is injected into the chamber to pressurize it, thereby suppressing the discharge breakdown of adjacent chips (see, for example, Patent Document 1 and Non-Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, during the high-voltage test, there was a risk that the bottom (lower end) of the chamber would come into contact with the wafer and damage the wafer surface. Further, Patent Document 1 discloses providing a ring (movable part) around the chamber and floating the ring upward by injecting air into the chamber during the test. Even in the case of providing and floating the ring in this way, for example, if the injection of air stops due to an abnormality or the like, the ring may drop and come into contact with the wafer (risk of damaging the wafer surface).

[0006] The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a test jig capable of suppressing damage to a wafer.

Means for Solving the Problems

[0007] The main invention of the present invention for solving the above-described problems is a test jig for testing each of a plurality of semiconductor elements formed on a wafer, with the thickness direction of the wafer during the test being the vertical direction, the front side of the wafer being upward, and the back side of the wafer being downward. When the test is performed, a substrate located above the wafer and having an opening penetrating in the vertical direction is provided, a chamber provided below the substrate and formed so as to surround the opening is provided, and a first probe for measuring the semiconductor element connected to the substrate is provided. The chamber includes a surrounding member that surrounds the first probe and floats upward when air is injected from the opening during the test, a support portion that supports the surrounding member before the test, and a suppression member that suppresses the lowering of the surrounding member so that the surrounding member does not come into contact with the wafer when the injection of air into the opening stops during the test. It is a test jig including.

Effects of the Invention

[0008] According to the present invention, it is possible to provide a test jig capable of suppressing damage to a wafer.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13A

Figure 13B

Best Mode for Carrying Out the Invention

[0010] From the description in this specification and the attached drawings, at least the following matters become clear.

[0011] Note that hereinafter, the same or equivalent components, members, etc. shown in each drawing may be denoted by the same reference numerals, and repeated explanations may be omitted as appropriate.

[0012] In addition, in the present embodiment, "connection" means a state of being electrically connected unless otherwise specified. Therefore, "connection" includes cases where two components are connected not only by wiring but also, for example, via a resistor.

[0013] =====First Embodiment===== <<Regarding Wafer and Semiconductor Chip>> FIG. 1 is a diagram showing an example of the relationship between wafer 1 and semiconductor chip 10.

[0014] Wafer 1 is a substantially disk-shaped thin plate member, and an orientation flat (hereinafter, also simply referred to as "orifla" or "OF") formed by linearly cutting a part of the disk is formed. Note that it is not limited to orifla, and for example, a notch formed by cutting a part of the disk in a V shape may be formed. Further, wafer 1 of the present embodiment is a SiC (silicon carbide) wafer, but it is not limited to this, and those formed of other materials (for example, silicon) may also be used.

[0015] Hereinafter, three mutually intersecting directions are defined for wafer 1 (specifically, wafer 1 during testing). The direction along the horizontal direction of the paper surface of FIG. 1 (the direction parallel to OF) is defined as the X direction, and the direction along the vertical direction of the paper surface (the direction perpendicular to OF) is defined as the Y direction. Further, the direction intersecting the X direction and the Y direction (the thickness direction of wafer 1) is defined as the Z direction (also referred to as the vertical direction), the front surface side of wafer 1 is defined as "up", and the back surface side is defined as "down" (see FIGS. 2 and 3). The front surface (upper surface) of wafer 1 is shown in FIG. 1.

[0016] As shown in FIG. 1, a plurality of semiconductor chips 10 are formed side by side on wafer 1 in the X direction and the Y direction. Note that these plurality of semiconductor chips 10 each correspond to a "semiconductor element". Further, in the following description, semiconductor chip 10 may be simply referred to as "chip".

[0017] After measuring the electrical characteristics of the plurality of semiconductor chips 10 formed on the wafer 1, they are separated chip by chip by dicing and sorted into good products (normal products) and defective products (abnormal products) (details will be described later).

[0018] FIG. 2 is a plan view and a cross-sectional view of the semiconductor chip 10. The lower figure (cross-sectional view) in FIG. 2 shows the A-A cross-section in the plan view. Note that the relationship between the X direction and the Y direction in FIG. 2 may be reversed.

[0019] The semiconductor chip 10 of the present embodiment is a MOSFET and includes a gate electrode 11, a source electrode 12, and a drain electrode 13. Note that the semiconductor chip 10 is not limited to a MOSFET, and for example, an IGBT may be used.

[0020] The drain electrode 13 is formed of a metal film on the back surface (lower surface) of the semiconductor chip 10. Therefore, when the wafer 1 is placed on a metal stage 30 (described later), the drain electrode 13 is electrically connected to the stage 30.

[0021] The gate electrode 11 and the source electrode 12 are formed so as to be exposed on the front surface (upper surface) of the semiconductor chip 10. Also, as shown in FIG. 2 (plan view), the gate electrode 11 and the source electrode 12 are arranged side by side in the X direction, and the source electrode 12 is formed with a larger area than the gate electrode 11. During a high-voltage test, usually a plurality of contact probes are brought into contact with the source electrode 12. However, in the present embodiment, for simplification, one contact probe (contact probes 42 and 43 described later) is brought into contact with the gate electrode 11 and the source electrode 12, respectively.

[0022] In the semiconductor chip 10, the gate electrode 11 corresponds to a "control electrode", the source electrode 12 (emitter electrode in the case of an IGBT) corresponds to a "first main electrode" and a "predetermined electrode", and the drain electrode 13 (collector electrode in the case of an IGBT) corresponds to a "second main electrode".

[0023] <<Regarding the test system>> Figure 3 is a schematic diagram of a test system TS when performing a test (high voltage test) on the wafer 1.

[0024] The test system TS shown in Figure 3 is composed of a test apparatus 20, a stage 30, and a test jig 140. Note that the test jig 140 in Figure 3 is a comparative example of the present embodiment.

[0025] <Test apparatus 20> The test apparatus 20 is an apparatus for performing a test (here, a high voltage test), and includes a storage unit, a power supply unit, a processing unit, etc. not shown in the figure.

[0026] The storage unit stores information about the wafer 1 and the semiconductor chip 10 (the map in Figure 1, information such as the chip size in the X and Y directions), and programs for performing tests. In addition, the test results (measurement results) of each chip are also stored in the storage unit.

[0027] The power supply unit supplies the power supply voltage used for the high voltage test. Specifically, the power supply unit applies a high voltage between the stage 30 and the contact probes 42, 43 (described later).

[0028] The processing unit executes, for example, the programs stored in the storage unit, controls the test jig (here, the test jig 140), and sequentially performs tests for each semiconductor chip 10. That is, based on the map in Figure 1, the measurements of the semiconductor chips 10 are sequentially performed in a predetermined order.

[0029] <Stage 30> The stage 30 is a metal table on which the wafer 1 is placed during the test, and is connected to the test apparatus 20. The wafer 1 is placed on the stage 30 in a state where it is aligned in the X and Y directions (for example, alignment using an orifice). In addition, the stage 30 performs vacuum suction on the wafer 1. As a result, the wafer 1 is fixed on the stage 30, and the back surface of the wafer 1 (the drain electrode 13 of the semiconductor chip 10) is electrically connected to the stage 30.

[0030] <<Test Fixture>> Before describing the test fixture of the present embodiment, a comparative example will be described.

[0031] With the development of design / process, the outer peripheral structure of high breakdown voltage semiconductor elements (chips) has been shrunk. For example, for adjacent chips in a wafer state, the risk of dielectric breakdown during high voltage application is increasing.

[0032] When testing in the chip state, it is common to create a pressurized state in a sealed pressurized chamber that covers the entire chip to prevent discharge. However, when testing in the wafer state, if a chamber that covers the entire wafer is provided, there are problems such as an increase in volume, making it not easy.

[0033] Therefore, in the test fixture 140 of FIG. 3, a small (chip scale) chamber (chamber 150) is provided under the probe card 41.

[0034] <Comparative Example 1 (Test Fixture 140)> The test fixture 140 of FIG. 3 includes a probe card 41, contact probes 42 and 43, and a chamber 150.

[0035] The probe card 41 is an instrument used for electrical testing of semiconductor chips 10 formed on a wafer 1. It has a circular printed circuit board, and contact probes 42 and 43 are precisely assembled on this circuit board. Note that the probe card 41 corresponds to the "substrate". As shown in FIG. 3, the probe card 41 is disposed (located) above the wafer 1 during the test of the semiconductor chip 10.

[0036] Also, in the center of the probe card 41, an air injection opening 41a is formed to penetrate in the vertical direction. Air (compressed air) is supplied to this opening 41a from a gas supply unit (not shown).

[0037] The contact probes 42 and 43 are measurement members (probes) for performing a test by bringing their tips into contact with the electrodes on the front surface of the semiconductor chip 10, and correspond to the "first probes". During the test, the contact probes 42 and 43 are brought into contact with (connected to) the gate electrodes 11 and the source electrodes 12 of the semiconductor chip 10, respectively. Also, the contact probes 42 and 43 are connected to the probe card 41 and are connected to the test apparatus 20 via the probe card 41.

[0038] In this embodiment, the high voltage test is a static characteristic test such as leakage current measurement (for example, drain cutoff current (Idss)) or breakdown voltage measurement (for example, drain-source breakdown voltage (BVds)). In such a high voltage test, the gate voltage Vgs of the gate electrode 11 is basically 0 V (GND potential), and a high voltage is applied between the drain electrode 13 and the source electrode 12 to measure current and voltage. Generally, when applying a high voltage, the high voltage is applied to the drain electrode 13 (in other words, the stage 30) side.

[0039] The chamber 150 is provided below the probe card 41 and is formed so as to surround the opening 41a of the probe card 41 and the contact probes 42 and 43. Also, the chamber 150 is a small chamber and is provided so as to cover at least the semiconductor chip 10 to be tested on the wafer 1.

[0040] Then, during the test (measurement), air is injected into the chamber 150 through the opening 41a of the probe card 41 to pressurize the inside of the chamber 150. By pressurizing the inside of the chamber 150 in this way, it is possible to suppress the adjacent chips from being damaged by discharge when a high voltage is applied to the chip to be tested.

[0041] Note that an air gap (gap) of about 100 μm, for example, is provided between the chamber 150 and the front surface (upper surface) of the wafer 1. However, when the test is continuously performed, wear and deformation occur in the contact probes 42 and 43, making it difficult to maintain the air gap. For this reason, the bottom surface (lower part) of the chamber 150 may come into contact with the front surface of the wafer 1, and there is a risk of scratching the wafer surface (front surface).

[0042] <Comparative Example 2 (Test Fixture 240)> Figs. 4 to 7 are explanatory views of Comparative Example 2 (Test Fixture 240) of the test fixture. Fig. 4 is a perspective view of the test fixture 240 as viewed from below, and for convenience, the contact probes 42 and 43 are not shown. Fig. 5 is an explanatory view of the relationship between the floating ring support portion 54 and the floating ring 55. Fig. 6 is a cross-sectional view taken along line B-B of Fig. 4, and Fig. 7 is a cross-sectional view taken along line C-C of Fig. 4.

[0043] The test fixture 240 includes a probe card 41, contact probes 42 and 43, and a chamber 250.

[0044] The chamber 250 is provided below the probe card 41, similarly to the chamber 150 of Comparative Example 1, and is formed so as to surround the opening 41a of the probe card 41 and the contact probes 42 and 43. Further, as shown in Figs. 6 and 7, the chamber 250 includes a substrate connection portion 51, an insulating layer 52, a relay member 53, a floating ring support portion 54, a floating ring 55, and a rotation prevention member 56.

[0045] The substrate connection portion 51 is a connection portion between the chamber (here, the chamber 250) and the probe card 41, and is formed of metal or resin.

[0046] The insulating layer 52 is a layer formed of a resin such as an adhesive. Further, wirings 42a and 43a are fixed to the insulating layer 52. Note that the wiring 42a is a wiring that connects the probe card 41 and the contact probe 42, and the wiring 43a is a wiring that connects the probe card 41 and the contact probe 43.

[0047] The relay member 53 is a member for fixing the floating ring support portion 54 under the insulating layer 52. The relay member 53 is formed of metal or resin. Note that the relay member 53 and the floating ring support portion 54 may be integrally formed.

[0048] The floating ring support portion 54 has a portion that sandwiches the floating ring 55 (specifically, an extending portion 55a described later) with a space in the Z direction (vertical direction). Then, the floating ring support portion 54 supports the floating ring 55 so that it does not fall, for example, before the test of the semiconductor chip 10.

[0049] The floating ring 55 is a ring-shaped member formed of resin, is provided at the lower end portion of the chamber 250, and surrounds the contact probes 42 and 43. Further, the floating ring 55 has an extending portion 55a and a groove portion 55b as shown in FIG. 5.

[0050] The extending portion 55a is provided at the upper end of the floating ring 55 so as to extend outward. Further, the extending portion 55a is provided at three spaced locations around the floating ring 55. As described above, when the floating ring 55 is not floating, for example, before the test, this extending portion 55a (in other words, the floating ring 55) is supported by the floating ring support portion 54.

[0051] The groove portion 55b is a groove formed for circumferential alignment between the floating ring 55 and the floating ring support portion 54, and is formed so as to notch the extending portion 55a along the Z direction (vertical direction). Note that in the present embodiment, the groove portion 55b is formed in one of the three extending portions 55a.

[0052] The rotation prevention member 56 is a member for preventing the rotation of the floating ring 55 with respect to the floating ring support portion 54 (rotation around the axis along the Z direction), and is, for example, a screw or a pin. The rotation prevention member 56 is attached to the side wall of the floating ring support portion 54, and the tip thereof is inserted into a groove portion 55b formed in an extension portion 55a of the floating ring 55. Thereby, the floating ring 55 is prohibited from rotating with respect to the floating ring support portion 54 and is movable in the Z direction (vertical direction).

[0053] During the test, air is injected into the chamber 250 from the opening 41a of the probe card 41. As a result, the floating ring 55 rises (floats upward) from the state supported by the floating ring support portion 54, so that the distance from the wafer 1 can be maintained (see FIGS. 6 and 7).

[0054] However, in the case of this Comparative Example 2, it is necessary to control and monitor the flow rate of the gas air supplied into the chamber 250. If the injection of air stops (or the injection amount decreases) for some reason, the floating ring 55 may drop (descend) and contact the wafer 1 (scratches may be formed on the surface of the wafer 1).

[0055] Therefore, in the test jig 40 of the present embodiment, even if the injection of air stops (or the injection amount decreases), it is possible to prevent scratches on the wafer surface.

[0056] <Test jig 40 of the first embodiment> FIGS. 8 and 9 are schematic explanatory views of the test jig 40 of the first embodiment. Note that FIG. 8 is a cross-sectional view corresponding to FIG. 6, and FIG. 9 is a cross-sectional view corresponding to FIG. 7.

[0057] The test jig 40 of the present embodiment includes a probe card 41, contact probes 42 and 43, and a chamber 50. The chamber 50 includes a substrate connection portion 51, an insulating layer 52, a relay member 53, a floating ring support portion 54, a floating ring 55, a rotation prevention member 56, and a position holding probe 57.

[0058] The position-holding probe 57 is a member that suppresses the lowering of the floating ring 55 so that the floating ring 55 does not contact the wafer 1. The position-holding probe 57 is provided below the floating ring 55, and the tip of the position-holding probe 57 is located below the lower end of the floating ring 55. Also, during the test, the tip of the position-holding probe 57 is located at the position of the source electrode 12 of the semiconductor chip 10 in a plan view seen from above. Note that the material of the position-holding probe 57 is the same as that of the contact probes 42 and 43.

[0059] In the chamber 50 of the present embodiment, the floating-ring support portion 54 corresponds to the "support portion", the floating ring 55 corresponds to the "surrounding member", and the position-holding probe 57 corresponds to the "suppressing member" and the "second probe".

[0060] By providing the position-holding probe 57, even if the injection of air stops (or the injection amount decreases) during the test, the position-holding probe 57 contacts the semiconductor chip 10, so the distance between the floating ring 55 and the wafer 1 is maintained. Therefore, it is possible to prevent the surface of the wafer 1 from being scratched. Also, in this case, the position-holding probe 57 contacts the electrode (source electrode 12) of the semiconductor chip 10, and since the floating ring 55 can move up and down, the scratch caused by the position-holding probe 57 is smaller (less noticeable) than the scratch caused by the contact probes 42 and 43.

[0061] <<Regarding the manufacturing method of the semiconductor chip 10>> FIG. 10 is a flowchart for explaining the manufacturing method of the semiconductor chip 10. Note that the flow of FIG. 10 also includes the test method of the semiconductor chip 10.

[0062] First, a plurality of semiconductor chips 10 (MOSFETs) are formed on the wafer 1, and each electrode of the semiconductor chip 10 is formed (S01). Specifically, a drain electrode 13 is formed on the back surface of the wafer 1 (semiconductor chip 10), and a gate electrode 11 and a source electrode 12 are formed on the front surface.

[0063] Next, the wafer 1 on which a plurality of semiconductor chips 10 are formed is placed on the stage 30 (S02). As a result, the drain electrode 13 of each semiconductor chip 10 is connected to the test apparatus 20 via the stage 30.

[0064] The test apparatus 20 executes a program stored in the storage unit and moves the test jig 40 onto the semiconductor chip 10 to be tested (hereinafter also referred to as the chip under test) (S03).

[0065] Next, the test apparatus 20 lowers the test jig 40 toward the chip under test while injecting air (air) into the chamber 50 from the opening 41a of the probe card 41 (S04).

[0066] At this time, by injecting air into the chamber 50, the floating ring 55 floats upward. As a result, the distance between the floating ring 55 and the wafer 1 is maintained, so that the surface of the wafer can be prevented from being scratched. Further, even if the injection of air stops (or the injection amount decreases), the positioning probe 57 contacts the electrode (source electrode 12) of the chip under test, so that the distance between the floating ring 55 and the wafer 1 is maintained.

[0067] Also, by lowering the test jig 40, the contact probes 42 and 43 are brought into contact with the gate electrode 11 and the source electrode 12 of the chip under test, respectively (S05).

[0068] Then, the test apparatus 20 applies a high voltage between the stage 30 and the contact probes 42 and 43 to perform a high-voltage electrical test (S06). At this time, since the chamber 50 is pressurized with air, breakdown due to discharge can be prevented between adjacent chips.

[0069] Note that the timing at which the floating ring 55 floats may be after the position - holding probe 57 and the test chip come into contact. Even in this case, the damage occurs on the electrode (source electrode 12) of the test chip. Furthermore, since the floating ring 55 can move up and down, the damage caused by the position - holding probe 57 is much smaller than the damage caused by the contact probes 42 and 43.

[0070] When the test of the test chip is completed, the test apparatus 20 moves (raises) the test jig 40 upward to separate the contact probes 42 and 43 from the test chip (S07). At this time, the injection of air into the chamber 50 may be stopped, or it may remain injected. Note that the floating ring 55 is supported by the floating - ring support portion 54.

[0071] If the tests for all chips are not completed (NO in S08), the test apparatus 20 moves the test jig 40 onto the next test chip (S09). Then, the test of the next test chip is performed in the same manner. Note that the data of the chips that have been tested are stored in the storage unit of the test apparatus 20.

[0072] When the tests for all chips are completed (YES in S08), based on the test results stored in the test apparatus 20, for example, a dedicated marking device (not shown) is used to mark the semiconductor chips 10 determined to be defective (S10). The type of marking is not particularly limited. For example, it may be by ink or by using a laser.

[0073] Thereafter, the wafer 1 is diced to separate (individualize) each semiconductor chip 10 (S11). Then, based on the presence or absence of marking, good products (normal products) and defective products (abnormal products) are sorted (S12). The defective products are removed, and only the good products are advanced to the next process (for example, semiconductor module assembly, etc.).

[0074] As described above, the test jig 40 of the present embodiment includes a chamber 50 below the probe card 41. The chamber 50 includes a floating ring 55, a floating ring support portion 54, and a position holding probe 57. The position holding probe 57 is provided on the floating ring 55 and suppresses the lowering of the floating ring 55 when the injection of air into the opening 41a is stopped during the test.

[0075] Thereby, since the floating ring 55 does not contact the wafer 1, it is possible to suppress damage to the surface (front surface) of the wafer 1.

[0076] =====Second Embodiment===== FIGS. 11 and 12 are schematic explanatory views of the test jig 40A of the second embodiment. Note that FIG. 11 is a cross-sectional view corresponding to FIG. 6, and FIG. 12 is a cross-sectional view corresponding to FIG. 7.

[0077] The test jig 40A of the second embodiment includes a probe card 41, contact probes 42 and 43, and a chamber 50A. The chamber 50A includes a substrate connection portion 51, an insulating layer 52, a relay member 53, a floating ring support portion 54, a floating ring 55, and a ball plunger 58. In the second embodiment, the ball plunger 58 corresponds to a "suppressing member" and a "plunger".

[0078] The ball plunger 58 is a member for holding the vertical position of the floating ring 55 and is attached to the side portion of the floating ring support portion 54. The ball plunger 58 is provided in place of the rotation preventing member 56 of the first embodiment (inserted into the groove portion 55b) and also has a function of preventing the rotation of the floating ring 55 with respect to the floating ring support portion 54. In the first embodiment, the rotation preventing member 56 was provided on one of the three extending portions 55a of the floating ring 55, whereas in the second embodiment, ball plungers 58 are provided for each of the three extending portions 55a (three groove portions 55b) of the floating ring 55 (that is, three ball plungers 58 are provided).

[0079] FIG. 13A is an explanatory diagram showing an example of the ball plunger 58. FIG. 13B is a diagram showing a state in which the ball plunger 58 presses the floating ring 55 when the floating ring 55 floats.

[0080] As shown in FIG. 13A, the ball plunger 58 has a ball 58a and a spring 58b.

[0081] The ball 58a is a sphere made of metal or plastic and is provided at the tip of the ball plunger 58.

[0082] The spring 58b is an elastic member (spring) provided inside the ball plunger 58 and presses the ball 58a forward.

[0083] With the above configuration, when the floating ring 55 rises (floats) due to air injection into the opening 41a, the ball plunger 58 presses the ball 58a against the groove portion 55b of the floating ring 55 by the spring pressure (elastic force) of the spring 58b to maintain the height of the floating ring 55 (see FIG. 13B).

[0084] Therefore, when the injection of air into the opening 41a is stopped during the test, the ball plunger 58 suppresses the lowering of the floating ring 55, so that the floating ring 55 and the wafer 1 can be prevented from coming into contact (the wafer 1 can be prevented from being scratched).

[0085] In this embodiment, the ball plunger 58 is used, but it is not limited thereto. For example, a plunger (pin plunger) provided with a pin at the tip may be used.

[0086] =====Summary===== The test jig 40 and the like according to one embodiment of the present invention have been described above. The test jig 40 is a jig for testing each of the plurality of semiconductor chips 10 formed on the wafer 1, and includes a probe card 41 having an opening 41a, a chamber 50, and contact probes 42 and 43 for measuring the semiconductor chip 10. The chamber 50 includes a floating ring 55, a floating ring support portion 54, and a position holding probe 57. The floating ring 55 surrounds the contact probes 42 and 43 and floats upward when air is injected from the opening 41a during the test of the semiconductor chip 10. The floating ring support portion 54 supports the floating ring 55 before the test. The position holding probe 57 suppresses the lowering of the floating ring 55 so that the floating ring 55 does not contact the wafer when the injection of air into the opening 41a is stopped during the test.

[0087] Thereby, even when the injection of air into the opening 41a is stopped, since the floating ring 55 does not contact the wafer 1, it is possible to suppress the surface (front surface) of the wafer 1 from being scratched.

[0088] Further, the position holding probe 57 is provided on the floating ring 55. The tip of the position holding probe 57 is located below the lower end of the floating ring 55.

[0089] Thereby, it is possible to suppress the floating ring 55 from contacting the surface of the wafer 1 and to suppress the surface of the wafer 1 from being scratched.

[0090] Further, a source electrode 12 is formed on the front surface of the semiconductor chip 10. During the test, the tip of the position holding probe 57 is located at the position of the source electrode 12 in a plan view of the semiconductor chip 10 when viewed from above.

[0091] Thereby, it is possible to prevent the portions other than the electrode (source electrode 12) of the semiconductor chip 10 from being scratched.

[0092] Further, after the tip of the position holding probe 57 contacts the source electrode 12 of the semiconductor chip 10, the floating ring 55 floats upward.

[0093] Thereby, even when the position holding probe 57 contacts the source electrode 12 of the semiconductor chip 10, the source electrode 12 is less likely to be damaged (the damage is not obvious).

[0094] Further, the test jig 40A of the second embodiment includes a chamber 50A. A ball plunger 58 is attached to the floating ring support portion 54 of the chamber 50A.

[0095] Thereby, when the floating ring 55 floats, the vertical position is held by the ball plunger 58, so that the lowering of the floating ring 55 can be suppressed.

[0096] Further, the test method for the semiconductor chip 10 of the present embodiment is a test method for performing a test using the above test jig 40, and includes each step of steps S02 to S08 in FIG. 10.

[0097] Thereby, when testing the semiconductor chip 10, it is possible to suppress damage to the surface (front surface) of the wafer 1.

[0098] Further, the manufacturing method of the semiconductor chip 10 of the present embodiment includes each step of steps S01 to S12 in FIG. 10.

[0099] Thereby, it is possible to suppress damage to the surface of the wafer 1 (semiconductor chip 10).

[0100] =====Others===== The above embodiments are for facilitating the understanding of the present invention and are not for limiting and interpreting the present invention. Further, the present invention can be changed and improved without departing from its gist, and it goes without saying that the present invention includes equivalents thereof.

Explanation of Reference Numerals

[0101] 1 wafer 10 semiconductor chips 11 gate electrode 12 source electrode 13 drain electrode 20 test apparatus 30 stage 40 test jig 41 probe card 41a opening 42, 43 contact probe 50, 50A chamber 51 substrate connection part 52 insulating layer 53 relay member 54 floating ring support part 55 floating ring 55a extending part 55b groove part 56 rotation stop member 57 position holding probe 58 ball plunger 58a ball 58b spring 140 test jig 150 chamber 240 test jig 250 chamber TS test system

Claims

1. A test jig for testing each of a plurality of semiconductor elements formed on a wafer, when the thickness direction of the wafer during the test is the vertical direction, with the front side of the wafer being upward and the back side of the wafer being downward, a substrate located above the wafer during the test and having an opening formed therethrough in the vertical direction; a chamber provided below the substrate and formed to surround the opening; a first probe for measuring the semiconductor element, connected to the substrate; comprising: the chamber includes: a surrounding member that surrounds the first probe and floats upward when air is injected from the opening during the test; a support portion that supports the surrounding member before the test; a suppression member that suppresses the lowering of the surrounding member so that the surrounding member does not contact the wafer when the injection of air into the opening is stopped during the test; A test jig including the above.

2. The test jig according to claim 1, wherein the suppression member is a second probe provided on the surrounding member, and the tip of the second probe is located below the lower end of the surrounding member. A test jig.

3. The test jig according to claim 2, wherein a predetermined electrode is formed on the front surface of the semiconductor element, and during the test, the tip of the second probe is located at the position of the predetermined electrode in a plan view of the semiconductor element when viewed from above. A test jig.

4. The test jig according to claim 3, wherein the surrounding member floats upward after the tip of the second probe contacts the predetermined electrode. A test jig.

5. The test jig according to claim 1, wherein the suppression member is a plunger attached to the support portion. A test jig.

6. A test method for performing the test on the semiconductor element using the test jig according to any one of claims 1 to 5, wherein a plurality of the first probes are provided in the test jig, a control electrode and a first main electrode are formed on the front surface of the semiconductor element, and a second main electrode is formed on the back surface, a step of placing the wafer on a stage; a step of aligning the test jig with the semiconductor element to be tested; a step of bringing the test jig closer to the semiconductor element while injecting air into the opening of the test jig to float the surrounding member; A step of bringing the first probe into contact with the control electrode and the first main electrode of the semiconductor element, respectively; A step of measuring the characteristics of the semiconductor element by applying a voltage between the first probe and the stage; A step of moving the test jig upward to separate the first probe from the semiconductor element, and then moving the test jig onto the next semiconductor element to be tested; A test method including the above steps.

7. A step of forming a control electrode, a first main electrode, and a second main electrode of each of a plurality of semiconductor elements on a wafer; A step of performing the test on each semiconductor element by the test method according to claim 6; A step of marking a semiconductor element determined to be a defective product by the test; A step of dicing the wafer; A step of sorting good products and defective products based on the presence or absence of the marking; A method for manufacturing a semiconductor element including the above steps.

Images