Printed circuit board and method of manufacturing the same
By forming metal vias in glass substrates through electroplating without a seed layer, the challenges of void formation and increased costs in existing methods are addressed, resulting in improved substrate quality and reduced manufacturing time and expense.
Patent Information
- Application Number
- JP2024084861
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-20
- Filing Date
- 2024-05-24
- Publication Date
- 2025-05-30
AI Technical Summary
Current methods for manufacturing glass substrates face challenges in forming metal vias due to the smooth surface of glass and high aspect ratio of through-holes, leading to difficulties in seed layer formation, increased time and cost, and the risk of voids during electroplating.
The proposed solution involves forming a first through-hole on one side of the insulating layer, filling and sintering a conductive paste to create a first metal layer, and then forming second and third metal layers on both sides of the first metal layer through electroplating, thereby creating metal vias in the glass substrate without the need for a seed formation process.
This method minimizes voids and improves substrate quality by directly forming metal vias through electroplating, while also reducing time and cost by omitting the seed formation step.
Smart Images
Figure 2025083270000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a printed circuit board and a method for manufacturing the same.
Background Art
[0002] Package technology has been constantly evolving, and in particular, attempts have been continuously made to move away from conventional substrate manufacturing methods and use silicon or glass instead of organic materials. As is known, glass has better warpage characteristics and flatness than conventional organic materials and can be advantageous for reducing the line and space of traces. However, currently, when manufacturing a glass substrate, there is a problem that it is difficult to form metal vias in a thick glass substrate. For example, a seed layer is required for plating in a through-hole, but since the glass surface is smooth and the through-hole generally has a high aspect ratio, it may be difficult to form a seed. Also, when forming a seed in a sputtering process or the like, a lot of time and cost may be required to form a seed of a desired thickness. Further, there is a risk that significant voids may occur during the process of filling the through-hole with electroplating.
Summary of the Invention
Problems to be Solved by the Invention
[0003] One of several objects of the present invention is to provide a printed circuit board and a method for manufacturing the same that can minimize voids and improve the quality of the substrate even when performing filling electroplating on through-holes formed in a glass substrate or the like.
[0004] Another one of several objects of the present invention is to provide a printed circuit board and a method for manufacturing the same that can omit the seed formation process and minimize time and cost even when performing filling electroplating on through-holes formed in a glass substrate or the like.
Means for Solving the Problems
[0005] One of the solutions proposed through the present invention is to form a first through-hole on one side of the insulating layer, and then form a first metal layer by filling and sintering a conductive paste, etc., and after processing a second through-hole for exposing the first metal layer on the other side of the insulating layer, form a second metal layer and a third metal layer on both sides of the first metal layer by electroplating, and form metal vias in the insulating layer which can be a glass substrate or the like.
[0006] For example, a printed circuit board according to an example includes an insulating layer, a through-hole having a first region penetrating a part of the insulating layer from the upper surface of the insulating layer and a second region penetrating another part of the insulating layer from the lower surface of the insulating layer, a first metal layer filling a part of the first region, a second metal layer disposed above the first metal layer and filling another part of the first region, and a third metal layer disposed below the first metal layer and filling the second region, and the upper surface of the first metal layer may be located below the upper surface of the insulating layer.
[0007] For example, a method for manufacturing a printed circuit board according to an example may include the steps of preparing an insulating layer, forming a first through-hole penetrating a part of the insulating layer from the upper surface of the insulating layer in the insulating layer, forming a first metal layer filling a part of the first through-hole, forming a second through-hole penetrating another part of the insulating layer from the lower surface of the insulating layer in the insulating layer and exposing the lower side of the first metal layer, and forming a second metal layer and a third metal layer filling the first through-hole and the second through-hole on the upper side and the lower side of the first metal layer, respectively.
Advantages of the Invention
[0008] Among various advantages of the present invention, as one advantage, it is possible to provide a printed circuit board and a method for manufacturing the same which can minimize voids and improve the quality of the substrate even when electroplating is performed on through-holes formed in a glass substrate or the like.
[0009] Among the various effects of the present invention, as another effect, there can be provided a printed circuit board and a method for manufacturing the same, which can minimize time and cost by omitting a seed formation step even when filling plating is performed on through holes formed in a glass substrate or the like.
Brief Description of the Drawings
[0010]
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Embodiments for Carrying Out the Invention
[0011] Hereinafter, the present invention will be described with reference to the accompanying drawings. The shapes and sizes of the elements in the drawings can be exaggerated or reduced for clearer explanation.
[0012] Electronic device FIG. 1 is a block diagram schematically showing an example of an electronic device system.
[0013] Referring to the drawings, the electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040, etc. are physically and / or electrically connected to the main board 1010. These also combine with other electronic components described later to form various signal lines 1090.
[0014] Examples of the chip-related components 1020 include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; logic chips such as an analog-digital converter and an ASIC (application-specific IC). However, the present invention is not limited thereto, and it goes without saying that other different forms of chip-related electronic components may also be included. Also, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in a package form including the above-described chips and electronic components.
[0015] Examples of the network-related components 1030 include Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated for those and later generations. However, the present invention is not limited thereto, and any of other different numerous wireless or wired standards and protocols may also be included. Also, it goes without saying that the network-related components 1030 may be combined with the chip-related components 1020 and combined with each other.
[0016] Examples of other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (Low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condensers), etc. However, the present invention is not limited thereto, and passive elements in the form of chip components used for other different applications may also be included. Needless to say, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030 with each other.
[0017] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected or not connected to the main board 1010. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, a battery 1080, etc. However, the present invention is not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a CD (compact disk), a DVD (digital versatile disk), etc. Needless to say, other electronic components used for various applications depending on the type of the electronic device 1000 may also be included.
[0018] The electronic device 1000 may be, for example, a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is not limited to these, and needless to say, it may be any other electronic device that processes data other than these.
[0019] FIG. 2 is a perspective view schematically showing an example of an electronic device.
[0020] Referring to the drawings, the electronic device may be, for example, a smart phone 1100. Inside the smart phone 1100, a motherboard 1110 is housed, and various components 1120 are physically and / or electrically connected to such a motherboard 1110. Also, other components that are or are not physically and / or electrically connected to the motherboard 1110, such as a camera module 1130 and / or a speaker 1140, are housed inside. Some of the components 1120 may be the chip-related components described above, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with built-in active components and / or passive components. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and needless to say, it may be other electronic devices as described above.
[0021] Printed Circuit Board FIG. 3 is a cross-sectional view schematically showing an example of a printed circuit board.
[0022] Referring to the drawings, a printed circuit board 100A-1 according to an example can include an insulating layer 110, a first metal wiring 120 disposed on the upper surface of the insulating layer 110, a second metal wiring 130 disposed on the lower surface of the insulating layer 110, and a metal via 140 that penetrates the insulating layer 110 and connects the first metal wiring and the second metal wirings 120 and 130 to each other. The insulating layer 110 can have a through-hole H having a first region R1 that penetrates a part of the insulating layer 110 from the upper surface of the insulating layer 110 and a second region R2 that penetrates another part of the insulating layer 110 from the lower surface of the insulating layer 110. The metal via 140 can include a first metal layer M1 that fills a part of the first region R1, a second metal layer M2 that is disposed above the first metal layer M1 and fills another part of the first region R1, and a third metal layer M3 that is disposed below the first metal layer M1 and fills the second region R2. The upper surface of the first metal layer M1 can be located below the upper surface of the insulating layer 110. The first region and the second regions R1 and R2 of the through-hole H can respectively correspond to a first through-hole and a second through-hole h1 and h2 in the manufacturing method described later.
[0023] As described above, in the printed circuit board 100A-1 according to an example, in the insulating layer 110 having a substantial thickness such as a glass substrate, first, the first region R1 is formed, and then a first metal layer M1 that fills a part thereof by filling and sintering a conductive paste or the like is formed. Next, after the second region R2 is formed, a second metal layer and a third metal layer M2 and M3 that fill the remaining portions of the first region and the second regions R1 and R2 by electroplating or the like using the first metal layer M1 as a seed are formed, and a metal via 140 having a high aspect ratio that penetrates this can be formed. Therefore, it is possible to effectively suppress the occurrence of voids in the through-hole H. In addition, a seed formation process for fill plating, for example, a sputtering process, can be omitted.
[0024] On one hand, the first metal layer M1 can have boundaries with each of the second metal layer and the third metal layer M2, M3. For example, the first metal layer M1 may have a different metal crystal structure from each of the second metal layer and the third metal layer M2, M3. For example, the first metal layer M1 may be formed by filling and sintering a conductive paste, and the second metal layer and the third metal layer M2, M3 may be formed by electroplating. The interface between the first metal layer and the third metal layer M1, M3 may be substantially the same as the interface between the first region and the second region R1, R2. For example, at least a part of each of the first region and the second region R1, R2 may overlap each other on a plane and be arranged to be connected to each other with respect to the thickness direction. At this time, the first metal layer M1 fills the lower side of the first region R1, but the second region R2 may not be filled, and the third metal layer M3 can contact the first metal layer M1 exposed from the second region R2. Such a structural feature can be a structure that serves as a basis for having the above-described effects.
[0025] In addition, the first region R1 can have a tapered shape in which the width of the upper end portion is wider than the width of the lower end portion in a cross section. Also, the second region R2 can have a tapered shape in which the width of the lower end portion is wider than the width of the upper end portion in a cross section. For example, the through hole H can have an hourglass shape in a cross section. For example, the depths of the first region and the second region R1, R2 may be substantially the same as each other in a cross section. Also, the width of the lower end portion of the first region R1 in a cross section and the width of the upper end portion of the second region R2 in a cross section may be substantially the same. Also, the areas of the first region and the second region R1, R2 may be substantially the same as each other in a cross section. Such a structural feature can be a structure that serves as a basis for having the above-described effects.
[0026] On one hand, the upper surface of the insulating layer 110 can be substantially coplanar with the upper surface of the second metal layer M2. Also, the lower surface of the insulating layer 110 can be substantially coplanar with the lower surface of the third metal layer M3. For example, a planarization process such as a polishing process may be performed after electroplating for forming the second metal layer and the third metal layer M2, M3. Therefore, the first metal wiring and the second metal wirings 120, 130 can be easily formed by plating on such a planar surface. For example, the first metal wiring 120 can include a first seed metal layer s1 disposed on the upper surface of the insulating layer 110 and the upper surface of the second metal layer M2, and a first wiring metal layer m1 disposed on the upper surface of the first seed metal layer s1 and having a greater thickness than the first seed metal layer s1. Also, the second metal wiring 130 can include a second seed metal layer s2 disposed on the lower surface of the insulating layer 110 and the lower surface of the metal layer M3, and a second wiring metal layer m2 disposed on the lower surface of the second seed metal layer s2 and having a greater thickness than the second seed metal layer s2. In this case, it may be easier to perform a build-up process to manufacture a package substrate or the like.
[0027] Also, a printed circuit board 100A-1 according to an example can be applied as any one layer of a multilayer circuit board. For example, it can be applied as a core layer of a multilayer circuit board. In this case, a build-up process can be performed on one or both sides of the printed circuit board 100A-1. Such a multilayer circuit board can be used as an FCB (Flip-Chip Board), a BGA (Ball Gird Array), an interposer substrate, a package substrate, or the like. However, it is not limited thereto, and it can be applied to various other forms of substrates.
[0028] Hereinafter, with reference to the drawings, the components of a printed circuit board 100A-1 according to an example will be described in more detail.
[0029] The insulating layer 110 can include a glass substrate. The glass substrate can include glass which is an amorphous solid. The glass can be, for example, pure silicon dioxide (about 100% SiO 2) It can include soda lime glass, borosilicate glass, aluminosilicate glass, etc. However, it is not limited thereto, and alternative glass materials, for example, fluorine glass, phosphate glass, chalcogen glass, etc. can also be used as materials. Further, in order to form glass having specific physical properties, it can further include other additives. Such additives can include not only calcium carbonate (for example, lime) and sodium carbonate (for example, soda), but also magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of such elements and other elements. The glass substrate can be distinguished from organic insulating materials including glass fiber (Glass Fiber, Glass Cloth, Glass Fabric), for example, CCL (Copper Clad Laminate), PPG (Prepreg), etc. For example, it can include plate glass. However, the insulating layer 110 is not limited to a glass substrate, and in the conventional method, substrates of various materials that are difficult to perform filling plating in through holes due to voids, etc. can be applied as the insulating layer 111. For example, a silicon substrate, a ceramic substrate, etc. can also be applied as the insulating layer 110, and if necessary, an organic substrate can also be applied as the insulating layer 110.
[0030] The first metal wiring and the second metal wirings 120 and 130 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. For example, the first seed metal layer and the second seed metal layers s1 and s2 of the first metal wiring and the second metal wirings 120 and 130, and the first wiring metal layer and the second wiring metal layers m1 and m2 can each contain the above-mentioned metals, and preferably can contain copper (Cu), but are not limited thereto. The first metal wiring and the second metal wirings 120 and 130 can each perform various functions according to the design. For example, it can include a signal pattern, a power pattern, a ground pattern, etc. These patterns can each have various forms such as a line, a plane, a pad, etc. The first metal wiring and the second metal wirings 120 and 130 can each contain an electroless plating layer (or electroless copper) and an electroplating layer (or electroplated copper). Instead of the electroless plating layer (or electroless copper), a sputtering layer may be included, and both the electroless plating layer (or electroless copper) and the sputtering layer may be included as needed.
[0031] The metal via 140 can contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, etc. For example, the first metal layer to the third metal layers M1, M2, and M3 of the metal via 140 can each contain the above-mentioned metals. For example, the first metal layer M1 can contain copper (Cu) coated with silver (Ag), and the second metal layer and the third metal layers M2 and M3 can each contain copper (Cu), but are not limited thereto. The metal via 140 can perform various functions according to the design. For example, it can include a ground via, a power via, a signal via, etc. The metal via 140 can contain a sintered layer of conductive paste and an electroplating layer. The electroplating layer may be a fill plating layer.
[0032] FIG. 4 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 3.
[0033] Referring to the drawings, in the printed circuit board 100A-2 according to the modified example, in the printed circuit board 100A-1 according to the above-described example, the second metal layer M2 can be extended and disposed on the upper surface of the insulating layer 110, and the third metal layer M3 can be extended and disposed on the lower surface of the insulating layer 110. At this time, the first metal wiring 120 can include the second metal layer M2 extended and disposed, and the second metal wiring 130 can include the third metal layer M3 extended and disposed. For example, at least a part of each of the first metal wiring and the second metal wirings 120 and 130 can be integrated with the metal via 140. In this way, in the printed circuit board 100A-2 according to the modified example, the first seed metal layer and the second seed metal layers s1 and s2 and the first wiring metal layer and the second wiring metal layers m1 and m2 can be omitted, and in the polishing process of the second metal layer and the third metal layers M2 and M3, the first metal wiring and the second metal wirings 120 and 130 can be formed by a method of polishing them with a pattern having a thickness required for the design. Therefore, when applied together with the glass substrate, it can be easily applied to a package substrate having low-loss characteristics of high-frequency signals by utilizing the characteristics of the glass substrate.
[0034] Since other descriptions can be substantially the same as those described in the printed circuit board 100A-1 according to the above-described example, duplicate descriptions are omitted.
[0035] FIGS. 5A to 5F are process cross-sectional views schematically showing an example of the manufacture of the printed circuit board of FIG. 3 and the printed circuit board of FIG. 4.
[0036] Referring to FIG. 5a, an insulating layer 110 can be prepared. The insulating layer 110 may be a glass substrate such as plate glass as described above. Next, a first through hole h1 that penetrates a part of the insulating layer 110 from the upper surface of the insulating layer 110 can be formed. The first through hole h1 can be formed by a chemical method or a mechanical method according to the material of the insulating layer 110. For example, etching, blasting, laser, plasma, etc. can be used.
[0037] Referring to FIG. 5b, a first metal layer M1 that fills a part of the first through hole h1 can be formed. The first metal layer M1 can be formed by filling a part of the first through hole h1 with a conductive paste and then sintering it. The conductive paste can contain copper (Cu), and can also contain a binder resin, a solvent, etc. in addition. For example, the conductive paste may be a low-temperature sintering material such as ACCP (Ag Coated Copper Paste). The first metal layer M1 can be formed such that its upper surface is located below the upper surface of the insulating layer 110.
[0038] Referring to FIG. 5c, a second through hole h2 that penetrates another part of the insulating layer 110 from the lower surface of the insulating layer 110 and exposes the lower side of the first metal layer M1 can be formed. The second through hole h2 can also be formed by a chemical method or a mechanical method such as etching, blasting, laser, plasma, etc. according to the material of the insulating layer 110.
[0039] Referring to FIG. 5d, a second metal layer and a third metal layer M2, M3 that fill the first through hole and the second through holes h1, h2 above and below the first metal layer M1 can be formed respectively. The second metal layer and the third metal layer M2, M3 can be formed by electroplating, for example, electrocopper plating, using the first metal layer M1 as a seed layer. At this time, the electroplating conditions can be set so as to minimize voids, thereby minimizing the generation of voids in the process of filling electroplating by electroplating. Also, a separate sputtering process or the like can be omitted.
[0040] Referring to FIG. 5e, after electroplating, the upper and lower surfaces of the insulating layer 110 and the plating surfaces of the second and third metal layers M2 and M3 can be substantially flattened to the same level in a polishing process such as CMP (Chemical Mechanical Planarization). Thereby, the metal via 140 can be formed. Next, electroless plating and electroplating can be performed on the upper and lower surfaces of the insulating layer 110 and on the upper and lower surfaces of the second and third metal layers M2 and M3 respectively. Thereby, the first metal wiring and the second metal wiring 120 and 130 can be formed, each including the first seed metal layer and the second seed metal layer s1 and s2 and the first wiring metal layer and the second wiring metal layer m1 and m2, and being connected to each other via the metal via 140. Through a series of processes, a printed circuit board 100A-1 according to an example can be manufactured, and a build-up process can be further performed as necessary.
[0041] Referring to FIG. 5f, after electroplating, the second and third metal layers M2 and M3 can be polished in a pattern of the required thickness in the design by a polishing process such as CMP (Chemical Mechanical Planarization), and then patterned by chemical etching or the like. Thereby, the first metal wiring and the second metal wiring 120 and 130 can be formed, each including the second and third metal layers M2 and M3 and being connected to each other via the metal via 140. Through a series of processes, a printed circuit board 100A-2 according to a modified example can be manufactured, and a build-up process can be further performed as necessary.
[0042] Other descriptions may be substantially the same as those described for the printed circuit board 100A-1 according to the above example and the printed circuit board 100A-2 according to its modified example, so duplicate descriptions are omitted.
[0043] FIG. 6 is a cross-sectional view schematically showing another example of a printed circuit board, and FIG. 7 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 6.
[0044] Referring to the drawings, in the printed circuit board 100B-1 according to another example and the printed circuit board 100B-2 according to a modification thereof, in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modification thereof, the first region R1 may be deeper than the second region R2. For example, in a cross section, the area of the first region R1 may be larger than the area of the second region R2. In this case, the first metal layer M1 can be formed larger, and the generation of voids in the electroplating process for forming the second metal layer and the third metal layers M2, M3 can be more effectively improved.
[0045] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modification thereof, and thus redundant explanations are omitted.
[0046] Figs. 8a to 8f are process cross-sectional views schematically showing an example of the manufacture of the printed circuit board of Fig. 6 and the printed circuit board of Fig. 7.
[0047] Referring to the drawings, in an example of the manufacture of the printed circuit board 100B-1 according to another example and the printed circuit board 100B-2 according to a modification thereof, in an example of the manufacture of the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modification thereof, the first through hole h1 may be formed deeper than the second through hole h2. In this case, the first metal layer M1 can be formed larger, and the generation of voids in the electroplating process for forming the second metal layer and the third metal layers M2, M3 can be more effectively improved.
[0048] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above-described example, the printed circuit board 100A-2 according to a modification thereof, and an example of the manufacture thereof, and thus redundant explanations are omitted.
[0049] FIG. 9 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 10 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 9.
[0050] Referring to the drawings, in the printed circuit board 100C-1 according to still another example and the printed circuit board 100C-2 according to a modified example thereof, in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modified example thereof, the first region R1 can have a substantially rectangular shape with a substantially vertical wall surface in cross-section, and the second region R2 can have a substantially rectangular shape with a substantially vertical wall surface in cross-section. For example, the metal via 140 may have a columnar shape in cross-section. In this case, the area of the metal via 140 can be made wider, and it can be more excellent in electrical conductivity.
[0051] Since other descriptions can be substantially the same as those described in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modified example thereof, duplicate descriptions are omitted.
[0052] FIGS. 11a to 11f are process cross-sectional views schematically showing an example of the manufacture of the printed circuit board of FIG. 9 and the printed circuit board of FIG. 10.
[0053] Referring to the drawings, in an example of the manufacture of the printed circuit board 100C-1 according to still another example and the printed circuit board 100C-2 according to a modified example thereof, in an example of the manufacture of the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modified example thereof, the first through hole h1 and the second through hole h2 can each be formed in a substantially rectangular shape with a substantially vertical wall surface in cross-section. For example, the metal via 140 may be formed in a columnar shape in cross-section. In this case, the area of the metal via 140 can be made wider, and it can be more excellent in electrical conductivity.
[0054] Other explanations may be substantially the same as those described in the example of the printed circuit board 100A-1 and the modified example of the printed circuit board 100A-2, and the example of manufacturing thereof, so duplicate explanations are omitted.
[0055] FIG. 12 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 13 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 12.
[0056] Referring to the drawings, in the printed circuit board 100D-1 according to still another example and the printed circuit board 100D-2 according to a modified example thereof, in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modified example thereof, the width of the lower end portion on the cross section of the first region R1 and the width of the upper end portion on the cross section of the second region R2 may be different. For example, the width of the upper end portion on the cross section of the second region R2 may be wider than the width of the upper end portion on the cross section of the first region R1. In this way, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0057] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above-described example and the printed circuit board 100A-2 according to a modified example thereof, so duplicate explanations are omitted.
[0058] FIG. 14 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 15 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 14.
[0059] Referring to the drawings, for another example of the printed circuit board 100E-1 and its modified example of the printed circuit board 100E-2, in the printed circuit board 100B-1 according to another example described above and its modified example of the printed circuit board 100B-2, the width of the lower end portion in the cross-section of the first region R1 and the width of the upper end portion in the cross-section of the second region R2 may be different. For example, the width of the upper end portion in the cross-section of the second region R2 may be wider than the width of the upper end portion in the cross-section of the first region R1. Thus, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0060] Other explanations may be substantially the same as those described for the printed circuit board 100A-1 according to an example above and its modified example of the printed circuit board 100A-2, and the printed circuit board 100B-1 according to another example described above and its modified example of the printed circuit board 100B-2, so redundant explanations are omitted.
[0061] FIG. 16 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 17 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 16.
[0062] Referring to the drawings, for still another example of the printed circuit board 100F-1 and its modified example of the printed circuit board 100F-2, in the printed circuit board 100C-1 according to still another example described above and its modified example of the printed circuit board 100C-2, the width of the lower end portion in the cross-section of the first region R1 and the width of the upper end portion in the cross-section of the second region R2 may be different. For example, the width of the upper end portion in the cross-section of the second region R2 may be wider than the width of the upper end portion in the cross-section of the first region R1. Thus, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0063] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above example, the printed circuit board 100A-2 according to its modification example, and the printed circuit board 100C-1 according to still another example described above and the printed circuit board 100C-2 according to its modification example, so duplicate explanations are omitted.
[0064] FIG. 18 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 19 is a cross-sectional view schematically showing a modification example of the printed circuit board of FIG. 18.
[0065] Referring to the drawings, in the printed circuit board 100G-1 according to still another example and the printed circuit board 100G-2 according to its modification example, in the printed circuit board 100A-1 according to the above example and the printed circuit board 100A-2 according to its modification example, the width of the lower end portion in the cross-section of the first region R1 and the width of the upper end portion in the cross-section of the second region R2 may be different. For example, the width of the upper end portion in the cross-section of the second region R2 may be narrower than the width of the upper end portion in the cross-section of the first region R1. In this way, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0066] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above example and the printed circuit board 100A-2 according to its modification example, so duplicate explanations are omitted.
[0067] FIG. 20 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 21 is a cross-sectional view schematically showing a modification example of the printed circuit board of FIG. 20.
[0068] Referring to the drawings, in a printed circuit board 100H-1 according to still another example and a printed circuit board 100H-2 according to a modified example thereof, in the printed circuit board 100B-1 according to another example described above and the printed circuit board 100B-2 according to a modified example thereof, the width of the lower end portion in the cross section of the first region R1 and the width of the upper end portion in the cross section of the second region R2 may be different. For example, the width of the upper end portion in the cross section of the second region R2 may be narrower than the width of the upper end portion in the cross section of the first region R1. In this way, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0069] Other explanations may be substantially the same as those described for the printed circuit board 100A-1 according to an example described above and the printed circuit board 100A-2 according to a modified example thereof, and the printed circuit board 100B-1 according to another example described above and the printed circuit board 100B-2 according to a modified example thereof, and thus redundant explanations are omitted.
[0070] FIG. 22 is a cross-sectional view schematically showing still another example of a printed circuit board, and FIG. 23 is a cross-sectional view schematically showing a modified example of the printed circuit board of FIG. 22.
[0071] Referring to the drawings, in a printed circuit board 100I-1 according to still another example and a printed circuit board 100I-2 according to a modified example thereof, in the printed circuit board 100C-1 according to still another example described above and the printed circuit board 100C-2 according to a modified example thereof, the width of the lower end portion in the cross section of the first region R1 and the width of the upper end portion in the cross section of the second region R2 may be different. For example, the width of the upper end portion in the cross section of the second region R2 may be narrower than the width of the upper end portion in the cross section of the first region R1. In this way, the first region and the second regions R1 and R2 can be formed in more various forms, and the degree of freedom in design can be increased.
[0072] Other explanations may be substantially the same as those described in the printed circuit board 100A-1 according to the above example, the printed circuit board 100A-2 according to its modified example, the printed circuit board 100C-1 according to still another example described above, and the printed circuit board 100C-2 according to its modified example, so duplicate explanations are omitted.
[0073] In the present invention, the expression "cover" can include not only the case of covering entirely but also the case of covering at least a part, and further can include not only the case of directly covering but also the case of indirectly covering. Also, the expression "fill" can include not only the case of filling completely but also the case of filling at least a part, and further can include the case of generally filling. For example, it can include the case where there are some voids or voids. Also, the expression "surround" can include not only the case of being completely surrounded but also the case of surrounding a part and the case of generally surrounding. Note that the expression "adjacent" means the case of being arranged adjacent to each other in substantially the same layer, and is not limited to the case of being in contact with each other. Further, "exposing" can include not only the case of completely exposing but also the case of exposing a part, and "exposed" can mean exposing from embedding the said structure.
[0074] In the present invention, substantially, it can be judged including process errors, position deviations, errors at the time of measurement, etc. occurring in the manufacturing process. For example, "substantially coplanar" can include not only the case of existing on exactly the same plane but also the case of existing on substantially the same plane.
[0075] In the present invention, the meaning in the cross-section can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed in a side view. Also, the meaning on the plane can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed in a top view or a bottom view.
[0076] In the present invention, terms such as "lower side," "lower part," and "lower surface" are used, for the sake of convenience, to mean downward with reference to the cross-section of the drawing, and terms such as "upper side," "upper part," and "upper surface" are used to mean the opposite direction. However, this is only for the convenience of explanation and defines the direction. It goes without saying that the scope of rights in the claims is not particularly limited by the description of such a direction, and the concept of up / down can be changed at any time.
[0077] In the present invention, "being connected" includes not only being directly connected but also being indirectly connected via an adhesive layer or the like. Further, "being electrically connected" includes both the case of being physically connected and the case of not being connected. Furthermore, expressions such as "first" and "second" are used to distinguish one component from another component, and do not limit the order and / or importance of the component. In some cases, within the scope not departing from the scope of rights, the first component may be named the second component, and similarly, the second component may be named the first component.
[0078] In the present invention, "thickness," "width," "length," "depth," "line width," "interval," "pitch," etc. can be measured with a scanning microscope, an optical microscope, etc. based on the cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical cross-section or a horizontal cross-section, and each numerical value can be measured based on the required cut cross-section. For example, the width of the upper end and / or the lower end of the via can be measured on the cross-section obtained by cutting the central axis of the via. At this time, when the numerical value is not constant, the numerical value can be determined by the average value of the values measured at any five points. On the other hand, the minimum numerical value can be determined by the numerical value measured as the smallest value in the layer, the region, etc.
[0079] The expression "an example" used in the present invention does not mean the same embodiment, but is provided to emphasize and explain each unique feature that is different from each other. However, the above-mentioned examples do not exclude being combined with the features of other examples. For example, even if a matter described in a specific example is not described in another example, in another example, as long as there is no description contrary to or conflicting with that matter, it can be understood as a description related to another example.
[0080] The terms used in the present invention are merely used to explain an example and are not intended to limit the present invention. At this time, the singular expression includes plural expressions unless the context clearly indicates a different meaning.
Explanation of Reference Numerals
[0081] 1000: Electronic device 1010: Main board 1020: Chip-related components 1030: Network-related components 1040: Other components 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Components 1121: Component package 1130: Camera module 1140: Speaker 100A-1, 100A-2, 100B-1, 100B-2, 100C-1, 100C-2, 100D-1, 100D-2, 100E-1, 100E-2, 100F-1, 100F-2, 100G-1, 100G-2, 100H-1, 100H-2, 100I-1, 100I-2: Printed circuit board 110: Insulating layer 120, 130: Metal wiring 140: Metal via M1, M2, M3: Metal layers s1, s2: Seed metal layers m1, m2: Wiring metal layers H, h1, h2: Through-holes R1, R2: Regions
Claims
1. An insulating layer; a through hole having a first region penetrating a portion of the insulating layer from an upper surface of the insulating layer and a second region penetrating another portion of the insulating layer from a lower surface of the insulating layer; a metal via including a first metal layer filling a portion of the first region, a second metal layer disposed above the first metal layer and filling another portion of the first region, and a third metal layer disposed below the first metal layer and filling the second region; a top surface of the first metal layer below a top surface of the insulating layer;
2. The printed circuit board of claim 1 , wherein the insulating layer comprises a glass substrate.
3. The printed circuit board of claim 1 , wherein the first metal layer has a boundary with each of the second and third metal layers.
4. 4. The printed circuit board of claim 3, wherein an interface between the first metal layer and the third metal layer is substantially the same as an interface between the first region and the second region.
5. The printed circuit board according to claim 1 , wherein the first region and the second region are disposed so that at least a portion of each of the first region and the second region overlap each other on a plane and are connected to each other based on a thickness direction.
6. On the cross section, The first region has a tapered shape in which the width of an upper end portion is greater than the width of a lower end portion, The printed circuit board according to claim 1 , wherein the second region has a tapered shape in which the width at the bottom end is greater than the width at the top end.
7. The printed circuit board according to claim 6 , wherein a width of a bottom end of the first region is different from a width of an top end of the second region.
8. The printed circuit board of claim 6 , wherein the first region is deeper than the second region.
9. On the cross section, The first region has a rectangular shape with substantially vertical walls, The printed circuit board of claim 1 , wherein the second region has a rectangular shape with substantially vertical walls.
10. The printed circuit board of claim 9 , wherein a width of a bottom end of the first region is different from a width of an top end of the second region.
11. The printed circuit board of claim 9 , wherein the first region is deeper than the second region.
12. The printed circuit board of claim 1 , further comprising a first metal wiring and a second metal wiring disposed on the upper surface and the lower surface of the insulating layer, respectively, and connected to each other through the metal via.
13. an upper surface of the insulating layer substantially coplanar with an upper surface of the second metal layer; a lower surface of the insulating layer is substantially coplanar with a lower surface of the third metal layer; the first metal wiring includes a first seed metal layer disposed on an upper surface of the insulating layer and an upper surface of the second metal layer, and a first wiring metal layer disposed on the upper surface of the first seed metal layer and having a thickness greater than that of the first seed metal layer; 13. The printed circuit board of claim 12, wherein the second metal wiring includes a second seed metal layer disposed on the lower surface of the insulating layer and on the lower surface of the third metal layer, and a second wiring metal layer disposed on the lower surface of the second seed metal layer and having a thickness greater than that of the second seed metal layer.
14. the second metal layer is disposed extending over an upper surface of the insulating layer; the third metal layer is disposed extending over a lower surface of the insulating layer; the first metal wiring includes the second metal layer disposed in an extending manner; The printed circuit board of claim 12 , wherein the second metal wiring comprises the extending third metal layer.
15. Providing an insulating layer; forming a first through hole in the insulating layer, the first through hole penetrating a portion of the insulating layer from an upper surface of the insulating layer; forming a first metal layer filling a portion of the first via hole; forming a second through hole in the insulating layer, the second through hole passing through another portion of the insulating layer from a lower surface of the insulating layer to expose an underside of the first metal layer; forming a second metal layer and a third metal layer above and below the first metal layer, respectively, filling the first through hole and the second through hole.
16. The step of providing an insulating layer includes: The method for manufacturing a printed circuit board according to claim 15, further comprising the step of providing a glass substrate as the insulating layer.
17. The step of forming the first metal layer comprises: filling a portion of the first through hole with a conductive paste; and The method for manufacturing a printed circuit board according to claim 15, further comprising the step of sintering the conductive paste.
18. The forming of the second metal layer and the third metal layer comprises: electroplating using the first metal layer as a seed layer; and The method for manufacturing a printed circuit board according to claim 15, further comprising the step of polishing the plating layer formed by the electroplating.