Three-dimensional memory device and method for forming them

Abstract

To provide a three-dimensional (3D) memory device, and a manufacturing method of them.SOLUTION: The present invention discloses a three-dimensional (3D) memory device and a method for forming them. In a specific aspect, the 3D memory device contains: a stack structure body that contains a conductive layer and a dielectric layer that are alternately arranged; a channel structure that is extended through the stack structure; and a doped semiconductor layer. The channel structure contains: a memory film; and a semiconductor channel. The semiconductor channel contains a doped part, and a part where is not doped. One part of the part where is doped in the semiconductor channel is extended over the stack structure body to a first direction. One part of the semiconductor layer to be doped is contacted to a side wall part of the one part of the part of the semiconductor channel extended over the stack structure body, which is doped.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, when the feature size of the memory cells approaches the lower limit, planar processes and fabrication techniques become difficult and costly. As a result, the memory density for planar memory cells approaches the upper limit.

[0003] 3D memory architectures are capable of addressing the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, a 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with sidewall portions of a part of the doped portion of the semiconductor channel that extends beyond the stack structure.

[0005] In another aspect, a 3D memory device includes a stack structure including alternating conductive and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure to the doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The doped portion of the semiconductor channel is between the doped semiconductor layer and one of the conductive layers closest to the doped semiconductor layer.

[0006] In yet another aspect, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stack structure is formed over the fill layer. A channel structure is formed extending through the stack structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. The substrate and a portion of the memory film facing the fill layer are sequentially removed to expose a portion of the semiconductor channel facing the fill layer. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and a portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0007] In yet a further aspect, a system includes a 3D memory device configured to store data and a memory controller to control the 3D memory device. The 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A portion of the doped semiconductor layer is in contact with sidewalls of a portion of the doped portion of the semiconductor channel that extends beyond the stack structure.

[0008] The accompanying drawings are incorporated herein and form a part of the specification. The accompanying drawings illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and also enable those skilled in the art to make and use the present disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] The present disclosure will be described with reference to the accompanying drawings.

[0011] Although specific configurations and arrangements are being discussed, it should be understood that this is being done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can be used in a variety of other applications. The functional and structural features as described in the present disclosure can be combined, adjusted, and modified in ways that are not specifically shown in relation to each other and in the drawings, and these combinations, adjustments, and modifications are intended to be within the scope of the present disclosure.

[0012] Generally, specialized terms can be understood at least in part from their usage in context. For example, the term "one or more" as used herein can be used, at least in part depending on the context, to describe any feature, structure, or characteristic in the singular sense, or to describe a combination of features, structures, or characteristics in the plural sense. Similarly, terms such as "a", "an", or "the", although repeated, can be understood, at least in part depending on the context, to convey either the singular usage or the plural usage. Additionally, it can be understood that the term "based on" is not necessarily intended to convey an exclusive set of factors, and instead, although repeated, can, at least in part depending on the context, allow for the possibility of the existence of additional factors that are not necessarily explicitly described.

[0013] As used in this disclosure, the meanings of "on", "above", and "over" should be interpreted in the broadest manner. "On" not only means "directly on", but also includes "on" something with intermediate features or layers therebetween. "Above" or "over" not only means "above" or "over" something, but also can include that it is "above" or "over" something (i.e., directly on something) with no intermediate features or layers therebetween. This should be readily understood.

[0014] Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of explanation. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device can be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Moreover, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0016] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend across the entirety of a structure below or above it, or can have an extent smaller than the extent of the structure below or above it. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes (or at the top and bottom surfaces) between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductors and contact layers (interconnect lines and / or vertical interconnect access (via) contacts are formed therein) and one or more dielectric layers.

[0017] In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround sidewall portions of a channel structure (e.g., known as sidewall-selective epitaxial growth (SEG)). Compared to another type of semiconductor plug formed at a source end of the channel structure (e.g., bottom SEG), the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom surface of the channel hole (known as SONO punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices by advanced technologies (e.g., having 90 or more levels by a multi-deck architecture).

[0018] However, since an intrinsic (pure, undoped) semiconductor material (such as intrinsic polysilicon, etc.) is used to form the semiconductor channel, a relatively high potential barrier exists between the semiconductor channel and the sidewall portion SEG or between the semiconductor channel and the conductive layer in contact therewith, thereby introducing a high contact resistance therebetween. The electrical performance of the 3D memory device may be affected by the high contact resistance.

[0019] To address the above problems, the present disclosure introduces a solution in which the contact resistance between the semiconductor channel and the sidewall portion SEG or the conductive layer can be reduced. In some implementations, the semiconductor channel is partially doped, and a part of the semiconductor channel forming the source contact portion remains undoped or leaves another part of the semiconductor channel forming a lowly doped memory cell, and is highly doped to lower the potential barrier. In some implementations, one end of each channel structure is opened from the back side to expose the doped part of each semiconductor channel, and the 3D memory device further includes a doped semiconductor layer that electrically connects the exposed doped part of the semiconductor channel to further reduce the contact resistance and sheet resistance. As a result, it is possible to improve the electrical performance of the 3D memory device.

[0020] Consistent with the scope of the present disclosure, the doped portion of the semiconductor channel and the doped semiconductor layer can be locally activated (e.g., through local annealing) to activate the dopants therein without damaging other parts (such as bonding interfaces and copper interconnects, etc.) on the heat-sensitive device chip. For example, the heat for activating the dopants can be confined to an area that excludes the heat-sensitive components on the device chip. In some implementations, the local activation process also serves as an in-situ doping process for doping a portion of the intrinsic semiconductor channel in contact with the doped semiconductor layer.

[0021] FIG. 1 illustrates a side cross-sectional view of an exemplary 3D memory device 100 according to some aspects of the present disclosure. In some implementations, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. According to some implementations, the first and second semiconductor structures 102 and 104 are joined at a bonding interface 106 therebetween. As shown in FIG. 1, the first semiconductor structure 102 can include a substrate 101, and the substrate 101 can include silicon (e.g., single-crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0022] The first semiconductor structure 102 of the 3D memory device 100 can include a peripheral circuit 108 on the substrate 101. It is noted that the x-axis and y-axis are included in FIG. 1 to further illustrate the spatial relationship of the components in the 3D memory device 100 having the substrate 101. The substrate 101 includes two lateral surfaces (e.g., an upper surface and a bottom surface) that extend laterally in the x-direction (i.e., horizontally). As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of a semiconductor device is determined in the y-direction (i.e., the vertical direction) with respect to the substrate of the semiconductor device (e.g., the substrate 101) when the substrate is positioned in the lowest plane of the semiconductor device (e.g., the 3D memory device 100) in the y-direction. The same concept for explaining spatial relationships is applied throughout the present disclosure.

[0023] In some implementations, the peripheral circuit 108 is configured to control and sense the 3D memory device 100. The peripheral circuit 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate the operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 108 can include transistors formed on the substrate 101, where all or part of the transistors are formed in the substrate 101 (e.g., below the upper surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) can similarly be formed in the substrate 101. According to some implementations, the transistors are fast by advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm). It is understood that in some implementations, the peripheral circuit 108 can further include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)).

[0024] In some implementations, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuit 108 to transfer electrical signals to and from the peripheral circuit 108. The interconnect layer can include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as inter-metal dielectric (IMD) layers), and the interconnect lines and VIA contacts can be formed within the one or more ILD layers. That is, the interconnect layer can include interconnect lines and VIA contacts within a plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

[0025] As shown in FIG. 1, the first semiconductor structure 102 of the 3D memory device 100 can further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and the peripheral circuits 108. The bonding layer 110 can include a plurality of bonding contacts 111 and a dielectric that electrically isolates the bonding contacts 111. The bonding contacts 111 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 110 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric in the bonding layer 110 can be used for hybrid bonding.

[0026] Similarly, as shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 can include a plurality of bonding contacts 113 and a dielectric that electrically isolates the bonding contacts 113. The bonding contacts 113 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 112 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric in the bonding layer 112 can be used for hybrid bonding. According to some implementations, the bonding contacts 113 are in contact with the bonding contacts 111 at the bonding interface 106.

[0027] As described in detail below, the second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some implementations, the bonding interface 106 is disposed between the bonding layer 110 and the bonding layer 112 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (such as solder or adhesive)), and it is possible to simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some implementations, the bonding interface 106 is the location where the bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer having a specific thickness that includes the upper surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0028] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 for transferring electrical signals. The interconnect layer can include a plurality of interconnects (such as MEOL interconnects and BEOL interconnects). The interconnect layer can further include one or more ILD layers, and interconnect lines and VIA contacts can be formed within the one or more ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0029] In some implementations, the 3D memory device 100 is a NAND flash memory device, and the memory cells are provided in the form of an array of NAND memory strings within the NAND flash memory device. Each NAND memory string can include a respective channel structure 124. As shown in FIG. 1, each channel structure 124 can extend vertically through a plurality of pairs each including a stack conductive layer 116 and a stack dielectric layer 118. The stack conductive layers 116 and stack dielectric layers 118 arranged alternately are part of the memory stack 114. The number of pairs of stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 determines the number of memory cells in the 3D memory device 100. In some implementations, the memory stack 114 can have a multi-deck architecture (not shown), and it is understood that the multi-deck architecture includes a plurality of memory decks stacked on top of each other. The number of pairs of stack conductive layers 116 and stack dielectric layers 118 in each memory deck can be the same or different.

[0030] Memory stack 114 can include a plurality of stack conductive layers 116 and stack dielectric layers 118 arranged alternately. The stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 can be alternately arranged in the vertical direction. In other words, except for those at the top or bottom of the memory stack 114, each stack conductive layer 116 can be adjacent to two stack dielectric layers 118 on both sides, and each stack dielectric layer 118 can be adjacent to two stack conductive layers 116 on both sides. The stack conductive layer 116 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stack conductive layer 116 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stack conductive layer 116 can extend horizontally as a word line and end in one or more staircase structures of the memory stack 114. The stack dielectric layer 118 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0031] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can also include a fill layer 120 above the memory stack 114. The fill layer 120 can include polysilicon, a high-k dielectric, or a metal. For example, a high-k dielectric can include any dielectric material having a dielectric constant higher than that of silicon oxide (e.g., > 3.7). Different from some known solutions where the fill layer 120 acts as a sidewall portion SEG surrounding the channel structure 124 and / or a conductive layer (e.g., a doped polysilicon layer, etc.) electrically connecting the channel structure 124, the fill layer 120 of the second semiconductor structure 104 of the 3D memory device 100 may not act as a sidewall portion SEG and / or a conductive layer, and thus can include materials other than doped polysilicon, such as a dielectric (e.g., a high-k dielectric), a metal (e.g., W, Co, Cu, or Al), a metal silicide, or undoped polysilicon. It is understood that in some examples, the fill layer 120 can also include doped polysilicon.

[0032] In some implementations, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as semiconductor channel 128) and a composite dielectric layer (e.g., as memory film 126). In some implementations, semiconductor channel 128 includes silicon (e.g., amorphous silicon, polysilicon, or single crystal silicon, etc.). In some implementations, memory film 126 is a composite layer that includes a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole can be partially or fully filled by a capping layer that includes a dielectric material (e.g., silicon oxide, etc.) and / or an air gap. Channel structure 124 can have a cylindrical shape (e.g., pillar shape). According to some implementations, the capping layer, semiconductor channel 128, tunneling layer, storage layer, and blocking layer of memory film 126 are arranged in this order radially from the center towards the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, memory film 126 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0033] In some implementations, the channel structure 124 further includes a channel plug 129 at the bottom portion of the channel structure 124 (e.g., at the lower end). As used herein, when the substrate 101 is positioned at the lowest plane of the 3D memory device 100, the upper end of a component (e.g., the channel structure 124) is the end farther from the substrate 101 in the y direction, and the lower end of the component (e.g., the channel structure 124) is the end closer to the substrate 101 in the y direction. The channel plug 129 can include a semiconductor material (e.g., polysilicon). In some implementations, the channel plug 129 functions as the drain of the channel structure 124.

[0034] As shown in FIG. 1, each channel structure 124 can extend vertically into the fill layer 120 through the alternating stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114. According to some implementations, since a portion of the memory film 126 can be removed during the fabrication process as described in detail below, the upper end of the memory film 126 is not aligned with the upper end of the semiconductor channel 128 in the vertical direction. In some implementations, the upper end of the memory film 126 is below the upper end of the semiconductor channel 128 in the channel structure 124, as shown in FIG. 1. In some implementations, the upper end of the memory film 126 is coplanar with the interface between the fill layer 120 and the memory stack 114 (i.e., between the bottom surface of the fill layer 120 and the upper surface of the memory stack 114). Although not shown, it is understood that in some examples, the upper end of the memory film 126 can be between the upper and bottom surfaces of the fill layer 120. That is, the upper end of the memory film 126 can be coplanar with the upper surface of the memory stack 114 or extend beyond it. In some implementations, the upper end of the memory film 126 is not below the upper surface of the memory stack 114.

[0035] As shown in FIG. 1, the upper end of the semiconductor channel 128 is above the upper end of the memory film 126 according to some implementation forms. In other words, the semiconductor channel 128 can extend further into the filling layer 120 than the memory film 126. For example, as shown in FIG. 1, the memory film 126 can end at the upper surface of the memory stack 114, while the semiconductor channel 128 can extend above the upper surface of the memory stack 114 and face the filling layer 120. Also, referring to the enlarged side view of the channel structure 124 in FIG. 2, the semiconductor channel 128 can include a doped portion 128a and an undoped portion 128b. In some implementation forms, at least a part of the doped portion 128a of the semiconductor channel 128 extends beyond the memory stack 114 in a first direction (e.g., the positive y direction in FIG. 2). That is, the upper end of the doped portion 128a can be above the interface between the filling layer 120 and the memory stack 114 (i.e., between the bottom surface of the filling layer 120 and the upper surface of the memory stack 114). In some implementation forms, the doped portion 128a of the semiconductor channel 128 also extends beyond one of the stack conductive layers 116 in a second direction opposite to the first direction (e.g., the negative y direction in FIG. 2). One or more of the stack conductive layers 116 near the filling layer 120 can be the source selection gate line 201 (SSG line; sometimes referred to as the bottom selection gate (BSG) line), and it is understood that the remaining part of the stack conductive layer 116 can include the word line 203. Also, according to some implementation forms, the doped portion 128a of the semiconductor channel 128 extends beyond the source selection gate line 201 closest to the filling layer 120. When the second semiconductor structure 104 of the 3D memory device 100 includes two or more source selection gate lines 201, it is understood that the doped portion 128a can extend beyond all the source selection gate lines 201.On the other hand, the doped portion 128a may not extend further to face the word line 203. That is, the lower end of the doped portion 128a is, according to some implementations, vertically between the source select gate line 201 and the word line 203. For example, as shown in FIG. 2, a part of the doped portion 128a of the semiconductor channel 128 extending beyond the memory stack 114 can face the filling layer 120, while the remaining part of the doped portion 128a can face the source select gate line 201.

[0036] In some implementations, the doped portion 128a of the semiconductor channel 128 comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb), etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. In some implementations, the doping concentration of the doped portion 128a is about 10 19 cm -3 to about 10 21 cm -3 and, for example, between 10 19 cm -3 and 10 21 cm -3 (e.g., between 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×1020 cm -3 、 4 × 10 20 cm -3 、 5 × 10 20 cm -3 、 6 × 10 20 cm -3 、 7 × 10 20 cm -3 、 8 × 10 20 cm -3 、 9 × 10 20 cm -3 、 10 21 cm -3 、 Any range defined by the lower end by any of these values, or any range defined by any two of these values), etc. The doping concentration of the doped portion 128a disclosed in this specification can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122 as compared with the intrinsic semiconductor. In some examples, the diffusion of the dopant can be confined within the doped portion 128a of the semiconductor channel 128, and the remaining portion of the semiconductor channel 128 (i.e., the part facing the word line 203) is an undoped portion 128b that still contains an intrinsic semiconductor (such as intrinsic polysilicon, etc.) (i.e., the doping concentration is nominally zero). It is understood that the doping concentration profile described above can reduce the potential barrier, contact resistance, and sheet resistance in the doped portion 128a of the semiconductor channel 128, and it creates an electrical connection for the source of the corresponding NAND memory string without changing the inherent properties of the undoped portion 128b of the semiconductor channel 128 that forms the memory cell of the NAND memory string.

[0037] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 includes a doped semiconductor layer 122 that is capable of electrically connecting a plurality of channel structures 124. For example, the doped semiconductor layer 122 can provide an electrical connection between sources (i.e., array common sources (ACS)) of an array of NAND memory strings in the same block, regardless of the presence or absence of the fill layer 120 (depending on whether the fill layer 120 is conductive). In other words, the fill layer 120 may not need to include a conductive material (such as metal or doped polysilicon). This is because the doped semiconductor layer 122 alone can electrically connect the sources of a plurality of NAND memory strings. As a result, the material and dimensional constraints on the fill layer 120 may be relaxed.

[0038] As shown in FIGS. 1 and 2, in some implementations, the doped semiconductor layer 122 includes two portions (a first portion 121 that contacts at least a part of the sidewall of the doped portion 128a of the semiconductor channel 128 extending beyond the memory stack 114, and a second portion 123 that is above and in contact with the fill layer 120). That is, according to some implementations, a part of the doped semiconductor layer 122 (i.e., the second portion 123) is above the fill layer 120, and the remaining part of the doped semiconductor layer 122 (i.e., the first portion 121) surrounding the upper end of each channel structure 124 is in contact with the doped portion 128a of the semiconductor channel 128. The fill layer 120 can be formed vertically between the memory stack 114 and the second portion 123 of the doped semiconductor layer 122. In some implementations, it is understood that the first portion 121 of the doped semiconductor layer 122 can similarly be above and in contact with the upper surface of the doped portion 128a of the semiconductor channel 128. That is, the doped semiconductor layer 122 is in contact with both the upper surface and the sidewall of the doped portion 128a of the semiconductor channel 128 extending beyond the memory stack 114, and it is possible to increase the contact area.

[0039] As shown in FIG. 1, the channel structure 124 can extend through the memory stack 114 and the fill layer 120 to the doped semiconductor layer 122. In some implementations, at least a portion of the semiconductor channel 128 between the doped semiconductor layer 122 and the source select gate line 201 (e.g., one of the stack conductive layers 116 closest to the doped semiconductor layer 122) is doped. As a result, a portion of the doped semiconductor layer 122 (e.g., the first portion 121) can be in contact with the doped portion (e.g., the doped portion 128a) of the semiconductor channel 128, and the fill layer 120 can be formed vertically between the memory stack 114 and another portion (e.g., the second portion 123) of the doped semiconductor layer 122. As described in detail below, the formation of the memory stack 114, as well as the formation of the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122, occurs on the opposite side of the fill layer 120, thereby avoiding any deposition or etching processes through the openings extending through the memory stack 114, thereby reducing fabrication complexity and cost and improving yield and vertical scalability.

[0040] Similar to the doped portion 128a of the semiconductor channel 128, in some implementations, the doped semiconductor layer 122 also includes N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., P, Ar, or Sb, etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. Similar to the doped portion 128a of the semiconductor channel 128, in some implementations, the doping concentration of the doped semiconductor layer 122 is between about 10 19 cm -3 and about 10 21 cm -3 , for example, between 10 19 cm -3 and 10 21 cm -3 (e.g., between 10 19 cm -3, 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3in any range bounded by a lower end by any of these values, or any range defined by any two of these values). The doping concentration of the doped semiconductor layer 122 disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor channel 122, and the sheet resistance of the doped semiconductor layer 122, compared to the intrinsic semiconductor. As described in detail below, in some implementations, the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 have the same material (e.g., N-type doped polysilicon) with the same dopant, and also have a continuous doping profile due to the same local activation process implemented thereon. Therefore, the interface and boundary between the doped portion 128a of the semiconductor channel 128 and the first portion 121 of the doped semiconductor layer 122 may become indistinguishable, and thus it is understood that it cannot be discriminated within the 3D memory device 100.

[0041] By doping and contacting the semiconductor channel 128 and the doped semiconductor layer 122, it is possible to reduce the contact resistance between NAND memory strings (i.e., in the ACS of NAND memory strings in the same block), thereby improving the electrical performance of the 3D memory device 100. The N-type doped semiconductor layer 122 (which surrounds the doped portion 128a of the semiconductor channel 128) can enable gate-induced drain leakage (GIDL)-assisted body biasing for the erase operation of the 3D memory device 100. GIDL around the source select gate line 201 can generate a hole current (i.e., source leakage current) from the source of the corresponding NAND memory string into the semiconductor channel 128 and raise the body potential for the erase operation. That is, according to some implementations, the 3D memory device 100 is configured to generate GIDL-assisted body biasing when performing the erase operation. In some implementations, the GIDL effect can be further enhanced by doping a portion of the semiconductor channel 128 facing the source select gate line 201.

[0042] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can further include an insulating structure 130 that extends vertically through the alternately arranged stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114. Unlike the channel structure 124 that further extends into the filling layer 120, the insulating structure 130, according to some implementation forms, stops at the bottom surface of the filling layer 120, that is, it does not extend vertically into the filling layer 120. That is, the upper surface of the insulating structure 130 can be on the same plane as the bottom surface of the filling layer 120. Also, each insulating structure 130 can extend laterally to separate a plurality of blocks of the separate channel structure 124. That is, the memory stack 114 can be divided into a plurality of memory blocks by the insulating structures 130, such that an array of the channel structures 124 can be separated into respective memory blocks. Unlike the slit structures in existing 3D NAND memory devices (which include front-side ACS contacts), the insulating structure 130, according to some implementation forms, does not include any contacts therein (i.e., does not function as a source contact), and thus does not introduce parasitic capacitance and leakage current by the stack conductive layer 116. In some implementation forms, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide. In some examples, it is understood that the insulating structure 130 can be partially filled with a non-dielectric material (e.g., polysilicon, etc.) to adjust the mechanical properties (e.g., hardness and / or stress) of the insulating structure 130.

[0043] Moreover, as described in detail below, the openings for forming the insulating structure 130 are not used to form the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128. Therefore, as the number of the alternately arranged stack conductive layers 116 and stack dielectric layers 118 increases, the aspect ratio of the openings increases (e.g., greater than 50), which will not affect the formation of the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128.

[0044] Instead of the front side source contact, the 3D memory device 100 can include one or more back side source contacts 132 in contact with the doped semiconductor layer 122 above the doped semiconductor layer 122, as shown in FIG. 1. The source contact 132 and the memory stack 114 (and the insulating structure 130 therethrough) can be disposed on the opposite side of the filling layer 120, and thus can be regarded as the "back side" source contact. In some implementations, the source contact 132 is electrically connected to the semiconductor channel 128 of the channel structure 124 through the doped semiconductor layer 122. The source contact 132 can include any suitable type of contact. In some implementations, the source contact 132 includes a VIA contact. In some implementations, the source contact 132 includes a laterally extending wall-shaped contact. The source contact 132 can include one or more conductive layers such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0045] As shown in FIG. 1, 3D memory device 100 can further include a BEOL interconnect layer 133 that is electrically connected to source contact 132 above source contact 132 for pad out (e.g., to transfer electrical signals between 3D memory device 100 and an external circuit). In some implementations, interconnect layer 133 includes one or more ILD layers 134 on doped semiconductor layer 122 and a redistribution layer 136 on ILD layer 134. The upper end of source contact 132 is coplanar with the upper surface of ILD layer 134 and the bottom surface of redistribution layer 136, and source contact 132 extends vertically through ILD layer 134 to contact doped semiconductor layer 122 in some implementations. The ILD layer 134 in interconnect layer 133 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The redistribution layer 136 in interconnect layer 133 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of 3D memory device 100. A portion of redistribution layer 136 can be exposed from passivation layer 138 as contact pad 140. That is, interconnect layer 133 of 3D memory device 100 can also include contact pad 140 for wire bonding and / or bonding to an interposer. As described below with respect to the fabrication process, in some implementations, source contact 132 and redistribution layer 136 can be formed by the same process and can have the same material (e.g., Al). Thus, source contact 132 can, in some examples, also be viewed as part of BEOL interconnect layer 133.

[0046] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 that pass through the doped semiconductor layer 122 and the fill layer 120. Since the doped semiconductor layer 122 can include polysilicon, the contacts 142 and 144 are, according to some implementations, through silicon contacts (TSCs). In some implementations, the contact 142 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the redistribution layer 136, and the first portion 121 of the doped semiconductor layer 122 is electrically connected to the contact 142 through the source contact 132 of the interconnect layer 133 and the redistribution layer 136. In some implementations, the contact 144 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the contact pad 140. The contacts 142 and 144 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some implementations, at least the contact 144 further includes a spacer (e.g., a dielectric layer) for electrically isolating the contact 144 from the doped semiconductor layer 122 and the fill layer 120.

[0047] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148 that extend vertically outside the memory stack 114, respectively. Each peripheral contact 146 or 148 has a depth greater than the depth of the memory stack 114 and can extend vertically from the bonding layer 112 to the filling layer 120 in the peripheral region outside the memory stack 114. In some embodiments, the peripheral contact 146 is below the contact 142 and in contact with the contact 142, and the first portion 121 of the doped semiconductor layer 122 is electrically connected to the peripheral circuit 108 in the first semiconductor structure 102 through at least the source contact 132, the redistribution layer 136, the contact 142, and the peripheral contact 146. In some embodiments, the peripheral contact 148 is below the contact 144 and in contact with the contact 144, and the peripheral circuit 108 in the first semiconductor structure 102 is electrically connected to the contact pad 140 for pad out through at least the contact 144 and the peripheral contact 148. The peripheral contacts 146 and 148 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0048] As shown in FIG. 1, 3D memory device 100 also includes various local contacts (also known as "C1") as part of the interconnect structure, which are in direct contact with structures within memory stack 114. In some implementations, the local contacts include channel local contacts 150, each of which is below and in contact with the lower end of a respective channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fanout. In some implementations, the local contacts further include word line local contacts 152, each of which is below and in contact with a respective stack conductive layer 116 (including word lines) in the staircase structure of memory stack 114 for word line fanout. The local contacts (e.g., channel local contacts 150 and word line local contacts 152, etc.) can be electrically connected to the peripheral circuit 108 of the first semiconductor structure 102 through at least bonding layers 112 and 110. The local contacts (e.g., channel local contacts 150 and word line local contacts 152, etc.) can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., TiN).

[0049] Although an exemplary 3D memory device 100 is shown in FIG. 1, it is understood that any other suitable architecture of a 3D memory device may be applicable in the present disclosure without further detailed description by varying the relative positions of the first and second semiconductor structures 102 and 104, the use of backside source contacts 132 or known frontside source contacts (not shown), and / or the padout locations (e.g., through the first semiconductor structure 102 and / or the second semiconductor structure 104).

[0050] FIG. 5 illustrates a block diagram of an exemplary system 500 having a 3D memory device, according to some aspects of the present disclosure. System 500 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 5, system 500 can include a host 508 and a memory system 502, and memory system 502 has one or more 3D memory devices 504 and a memory controller 506. Host 508 can be a processor (e.g., a central processing unit (CPU), etc.) of the electronic device, or a system-on-chip (SoC) (e.g., an application processor (AP), etc.).

[0051] The 3D memory device 504 can be any 3D memory device disclosed herein (e.g., the 3D memory device 100 shown in FIGS. 1 and 2). In some implementations, each 3D memory device 504 includes a NAND flash memory. Consistent with the scope of the present disclosure, the semiconductor channel of the 3D memory device 504 can be partially doped, such that a portion of the semiconductor channel forming the source contact remains undoped or leaves another portion of the semiconductor channel forming a lightly doped memory cell, and is highly doped to reduce the potential barrier. One end of each channel structure of the 3D memory device 504 is open from the backside, capable of exposing the doped portion of each semiconductor channel. The 3D memory device 504 can further include a doped semiconductor layer that electrically connects the exposed doped portion of the semiconductor channel to further reduce contact resistance and sheet resistance. As a result, the electrical performance of the 3D memory device 504 can be improved, and it improves the performance of the memory system 502 and the system 500, for example, achieving a higher operating speed.

[0052] Memory controller 506 is connected to 3D memory device 504 and host 508, and in some implementations, is configured to control 3D memory device 504. Memory controller 506 can manage data stored in 3D memory device 504 and communicate with host 508. In some implementations, memory controller 506 is designed to operate in a low-duty-cycle environment, such as in a Secure Digital (SD) card, CompactFlash® (CF) card, Universal Serial Bus (USB) flash drive, or other media for use in an electronic device (e.g., personal computer, digital camera, mobile phone, etc.). In some implementations, memory controller 506 is designed to operate in a high-duty-cycle environment SSD or embedded multimedia card (eMMC) used as data storage for mobile devices (e.g., smartphones, tablets, laptop computers, etc.) and enterprise storage arrays. Memory controller 506 can be configured to control the operations of 3D memory device 504 (e.g., read operations, erase operations, and program operations, etc.). Also, memory controller 506 can be configured to manage various functions related to data stored or to be stored in 3D memory device 504 (including, but not limited to, bad block management, garbage collection, logical address-to-physical address translation, wear leveling, etc.). In some implementations, memory controller 506 is further configured to process error correction codes (ECC) for data read from or written to 3D memory device 504. Any other suitable functions can similarly be implemented by memory controller 506, such as forming 3D memory device 504. Memory controller 506 can communicate with external devices (e.g., host 508) according to a specific communication protocol.For example, the memory controller 506 can communicate with an external device through at least one of various interface protocols (e.g., USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.).

[0053] Memory controller 506 and one or more 3D memory devices 504 can be integrated into various types of storage devices, for example, they can be included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package, etc.). That is, the memory system 502 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 6A, the memory controller 506 and a single 3D memory device 504 can be integrated into a memory card 602. The memory card 602 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 602 can further include a memory card connector 604 that electrically connects the memory card 602 to a host (such as the host 508 in FIG. 5). In another example as shown in FIG. 6B, the memory controller 506 and multiple 3D memory devices 504 can be integrated into an SSD 606. The SSD 606 can further include an SSD connector 608 that electrically connects the SSD 606 to a host (such as the host 508 in FIG. 5). In some implementations, the storage capacity and / or operating speed of the SSD 606 are greater than those of the memory card 602.

[0054] Figures 3A - 3O illustrate a fabrication process for forming an exemplary 3D memory device according to some implementations of the present disclosure. FIG. 4 illustrates a flowchart of a method 400 for forming an exemplary 3D memory device according to some implementations of the present disclosure. Examples of the 3D memory devices depicted in FIGS. 3A - 3O and FIG. 4 include the 3D memory device 100 depicted in FIG. 1. FIGS. 3A - 3O and FIG. 4 will be described together. It is understood that the operations shown in method 400 are not exhaustive and that other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously or in an order different from that shown in FIG. 4.

[0055] Referring to FIG. 4, method 400 begins at operation 402, where peripheral circuitry is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on the silicon substrate 350 using a plurality of processes including, but not limited to, photolithography, etching, thin - film deposition, thermal expansion, implantation, chemical - mechanical polishing (CMP), and any other suitable processes. In some implementations, doped regions (not shown) are formed into the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some implementations, isolation regions (e.g., STI) are also formed into the silicon substrate 350 by wet etching and / or dry etching and thin - film deposition. The transistors can form the peripheral circuitry 352 on the silicon substrate 350.

[0056] As shown in FIG. 3G, a bonding layer 348 is formed over the peripheral circuit 352. The bonding layer 348 includes bonding contacts that are electrically connected to the peripheral circuit 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin-film deposition processes, which can be, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and / or dry etching (e.g., reactive ion etching (RIE)), followed by one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0057] As shown in FIG. 4, method 400 proceeds to operation 404, where a fill layer is formed over a second substrate and a stack structure is formed over the fill layer. The fill layer and the stack structure can be formed on the front side of the second substrate on which a semiconductor device can be formed. The second substrate can be a silicon substrate. Since the second substrate will be removed from the final product, the second substrate can be any suitable material (e.g., in some examples, a portion of a dummy wafer made from glass, sapphire, plastic, silicon, etc., such as a carrier substrate) to reduce the cost of the second substrate. In some implementations, the substrate is a carrier substrate. In some implementations, the fill layer includes polysilicon, a high-k dielectric, or metal, and the stack structure includes a dielectric stack having alternating stack dielectric layers and stack sacrificial layers. In some examples, it is understood that the stack structure can include a memory stack having alternating stack dielectric layers (e.g., silicon oxide layers) and stack conductive layers (e.g., polysilicon layers).

[0058] In order to better control the gauging and surface flatness of various structures to be formed on the second substrate, various stop layers can be formed between the second substrate and the filling layer. In some implementations, a first stop layer, a second stop layer, and a third stop layer are sequentially formed between the second substrate and the filling layer. The first stop layer can include silicon oxide or silicon nitride, the second stop layer can include silicon oxide or polysilicon, and the third stop layer can include silicon nitride or polysilicon. In some implementations, a single stop layer (e.g., a silicon oxide layer or a high-k dielectric layer, etc.) is formed between the second substrate and the filling layer.

[0059] As shown in FIG. 3A, a first stop layer 303 is formed above the carrier substrate 302, a second stop layer 304 is formed above the first stop layer 303, a third stop layer 305 is formed above the second stop layer 304, and a fill layer 306 is formed on the third stop layer 305. The fill layer 306 can include polysilicon, a high-k dielectric, or metal. As described in detail below, the third stop layer 305 can act as an etch stop layer when etching the memory film of the channel structure from the back side, and thus can include any suitable material other than silicon oxide used in the memory film (e.g., polysilicon or silicon nitride, etc.). The second stop layer 304 can act as an etch stop layer when etching the channel hole from the front side, and thus can include any suitable material having a high etch selectivity (e.g., greater than about 5) with respect to the material directly above the second stop layer 304 (e.g., silicon oxide or polysilicon, etc.). The first stop layer 303 can act as a CMP / etch stop layer when removing the carrier substrate 302 from the back side, and thus can include any suitable material other than the material of the carrier substrate 302 (e.g., silicon nitride or silicon oxide, etc.). In some examples, it is understood that a pad oxide layer (e.g., a silicon oxide layer) can be formed between the carrier substrate 302 and the first stop layer 303, or between the second stop layer 304 and the third stop layer 305 to relieve stress between different layers and avoid delamination.

[0060] As shown in FIG. 3A, a stack of a silicon oxide layer (pad oxide layer), a silicon nitride layer (first stop layer 303), a silicon oxide layer (second stop layer 304), and a silicon nitride layer (third stop layer 305) can be sequentially formed on a carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, the fill layer 306 is formed by depositing polysilicon or any other suitable material (such as a high-k dielectric or a metal, etc.) on the third stop layer 305 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. For ease of explanation, the combination of stop layers shown in FIG. 3A has been used throughout this disclosure to explain the fabrication process. However, it is understood that any other suitable combination of stop layers can equally be used in other examples. In one example not shown, a stack of a silicon oxide layer (as the first stop layer 303), a polysilicon layer (as the second stop layer 304), a silicon oxide layer (pad oxide layer), and a polysilicon layer (as the third stop layer 305) can be sequentially formed on a carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In another example not shown, a single oxide layer or a high-k dielectric layer (as the first, second, and third stop layers 303, 304, and 305) can be formed on a carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0061] As shown in FIG. 3B, a dielectric stack 308 including a plurality of pairs of a first dielectric layer (referred to herein as a "stack sacrificial layer" 312) and a second dielectric layer (referred to herein as a "stack dielectric layer" 310; both are referred to herein as a "dielectric layer pair") is formed on the fill layer 306. The dielectric stack 308 includes alternately arranged stack sacrificial layers 312 and stack dielectric layers 310 according to some implementation forms. The stack dielectric layer 310 and the stack sacrificial layer 312 can be alternately formed on the fill layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some implementation forms, each stack dielectric layer 310 includes a layer of silicon oxide, and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As shown in FIG. 3B, a staircase structure can be formed on the edge of the dielectric stack 308. The staircase structure can be formed by performing a plurality of so-called "trim etching" cycles on the dielectric layer pair of the dielectric stack 308 toward the carrier substrate 302. Due to the repeated trim etching cycles applied to the dielectric layer pair of the dielectric stack 308, the dielectric stack 308 can have one or more inclined edges and an upper dielectric layer pair shorter than the bottom one, as shown in FIG. 3B.

[0062] As shown in FIG. 4, method 400 proceeds to operation 406, where a channel structure is formed that extends vertically through the dielectric stack and the fill layer. The channel structure can include a memory film and a semiconductor channel. In some implementations, to form the channel structure, a channel hole is formed that extends vertically through the dielectric stack, the fill layer, and a third stop layer, which stops at the second stop layer, and the memory film and the semiconductor channel are sequentially formed along the sidewall and bottom surface of the channel hole.

[0063] As shown in FIG. 3B, each channel hole is an opening that extends vertically through the dielectric stack 308, the fill layer 306, and the third stop layer 305, which stops at the second stop layer 304. In some implementations, a plurality of openings are formed, and each opening is configured to be a location for growing an individual channel structure 314 in a later process. In some implementations, the fabrication process for forming the channel holes of the channel structure 314 includes wet etching and / or dry etching (e.g., deep RIE (DRIE), etc.). The etching of the channel holes continues, according to some implementations, until stopped by the second stop layer 304 (e.g., silicon oxide or polysilicon, etc.). In some implementations, the etching conditions (e.g., etching rate and time, etc.) can be controlled to ensure that each channel hole reaches and stops at the second stop layer 304 to minimize gouging variation between the channel holes and the channel structures 314 formed therein. Depending on the specific etching selectivity, one or more channel holes can extend slightly into the second stop layer 304, which is still understood to be stopped by the second stop layer 304 in the present disclosure.

[0064] As shown in FIG. 3B, a memory film including a blocking layer 317, a storage layer 316, and a tunneling layer 315, and a semiconductor channel 318 are sequentially formed in this order along the sidewall and bottom surface of the channel hole. In some implementations, the blocking layer 317, the storage layer 316, and the tunneling layer 315 are first deposited in this order along the sidewall and bottom surface of the channel hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form a memory film. Then, the semiconductor channel 318 can be formed by depositing a semiconductor material (e.g., polysilicon (e.g., undoped polysilicon), etc.) on the tunneling layer 315 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (the "SONO" structure) are sequentially deposited to form the blocking layer 317, the storage layer 316, and the tunneling layer 315 of the memory film, as well as the semiconductor channel 318.

[0065] As shown in FIG. 3B, a capping layer is formed within the channel hole and on the semiconductor channel 318, completely or partially filling the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material (e.g., silicon oxide, etc.) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). Then, a channel plug can be formed within the upper portion of the channel hole. In some implementations, a memory film on the upper surface of the dielectric stack 308, the semiconductor channel 318, and a portion of the capping layer are removed and planarized by CMP, wet etching, and / or dry etching. Then, by wet etching and / or dry etching a portion of the semiconductor channel 318 and the capping layer within the upper portion of the channel hole, a recess can be formed within the upper portion of the channel hole. Then, the channel plug can be formed by depositing a semiconductor material (e.g., polysilicon, etc.) into the recess by one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof, etc.). Thereby, the channel structure 314 is formed through the dielectric stack 308, the fill layer 306, and the third stop layer 305 in some implementations, which stops at the second stop layer 304.

[0066] As shown in FIG. 3C, the slit 320 is an opening that extends vertically through the dielectric stack 308 and stops at the fill layer 306. In some implementations, the fabrication process for forming the slit 320 includes wet etching and / or dry etching (e.g., DRIE, etc.). Then, gate exchange can be performed through the slit 320 to exchange the dielectric stack 308 with the memory stack 330 (shown in FIG. 3E).

[0067] As shown in FIG. 3D, the lateral recess 322 is first formed by removing the stack sacrificial layer 312 (shown in FIG. 3C) through the slit 320. In some implementations, the stack sacrificial layer 312 is removed by applying an etchant through the slit 320, creating lateral recesses 322 that are alternately arranged between the stack dielectric layers 310. The etchant can include any suitable etchant that selectively etches the stack sacrificial layer 312 with respect to the stack dielectric layer 310.

[0068] As shown in FIG. 3E, the stack conductive layer 328 (including the gate electrode and the adhesive layer) is deposited into the lateral recess 322 (shown in FIG. 3D) through the slit 320. In some implementations, the gate dielectric layer 332 is deposited into the lateral recess 322 before the stack conductive layer 328, such that the stack conductive layer 328 is deposited on top of the gate dielectric layer 332. The stack conductive layer 328 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, the gate dielectric layer 332 (e.g., a high-k dielectric layer, etc.) is similarly formed along the sidewalls and bottom of the slit 320. Thereby, a memory stack 330 including alternately arranged stack conductive layers 328 and stack dielectric layers 310 is formed, and in some implementations, replaces the dielectric stack 308 (shown in FIG. 3D).

[0069] As shown in FIG. 3E, an insulating structure 336 is formed that extends vertically through the memory stack 330 and terminates at the upper surface of the fill layer 306. The insulating structure 336 is formed by depositing one or more dielectric materials (e.g., silicon oxide, etc.) into the slit 320 and using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to completely or partially fill the slit 320 (e.g., without or with an air gap). In some implementations, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide). Although not shown, in some examples, the dielectric capping layer 334 can partially fill the slit 320 and a polysilicon core layer (not shown) can fill the remaining space of the slit 320 as part of the insulating structure 336 and can adjust the mechanical properties (e.g., hardness or stress, etc.) of the insulating structure 336.

[0070] As shown in FIG. 3F, after the formation of the insulating structure 336, local contacts (including channel local contact 344 and word line local contact 342, as well as peripheral contacts 338 and 340) are formed. By using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof), a local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material (such as silicon oxide or silicon nitride) on the memory stack 330. By using wet etching and / or dry etching (such as RIE) to etch the contact openings through the local dielectric layer (and any other ILD layer), and then using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the contact openings with a conductive material, the channel local contact 344, the word line local contact 342, as well as the peripheral contacts 338 and 340 can be formed.

[0071] As shown in FIG. 3F, a bonding layer 346 is formed over the channel local contact 344, the word line local contact 342, as well as the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts that are electrically connected to the channel local contact 344, the word line local contact 342, as well as the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof), and the bonding contacts are formed through the ILD layer by using wet etching and / or dry etching (such as RIE), and then one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof) follow.

[0072] As shown in FIG. 4, method 400 proceeds to operation 408, where the first substrate and the second substrate are bonded in a face-to-face manner such that the memory stack is above the peripheral circuitry. The bonding can include hybrid bonding. As shown in FIG. 3G, carrier substrate 302 and components formed thereon (e.g., memory stack 330 and channel structure 314 formed therethrough) are turned upside down. According to some implementations, the downward-facing bonding layer 346 is bonded to the upward-facing bonding layer 348, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 354 between carrier substrate 302 and silicon substrate 350. In some implementations, a processing process (e.g., plasma treatment, wet treatment, and / or heat treatment) is applied to the bonding surface prior to bonding. After bonding, the bonding contacts in bonding layer 346 and the bonding contacts in bonding layer 348 are aligned and in contact with each other such that memory stack 330 and channel structure 314 formed therethrough can be electrically connected to peripheral circuitry 352 and be above peripheral circuitry 352.

[0073] As shown in FIG. 4, method 400 proceeds to operation 410, where a second substrate and a portion of the memory film are sequentially removed to expose a portion of the semiconductor channel facing the filling layer. The removal can be performed from the back side of the second substrate. In some implementations, the removed portion of the memory film faces the filling layer. In some implementations, to sequentially remove a portion of the second substrate and the memory film, the second substrate is removed, which stops at the first stop layer, the first stop layer and the second stop layer are removed, which stops at the third stop layer, the third stop layer is patterned to expose the memory film, the exposed memory film is etched, which stops before or at the interface between the stack structure and the filling layer to form a recess surrounding the exposed portion of the semiconductor channel. In some implementations, the exposed portion of the semiconductor channel is doped. The dopant can include an N-type dopant.

[0074] As shown in FIG. 3H, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the first stop layer 303 shown in FIG. 3G) is completely removed from the back side until it is stopped by the first stop layer 303 (e.g., a silicon nitride layer). The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some implementations, the carrier substrate 302 is peeled off. In some implementations where the carrier substrate 302 includes silicon and the first stop layer 303 includes silicon nitride, the carrier substrate 302 can be removed using silicon CMP, which can automatically stop when it reaches the first stop layer 303 having a material other than silicon (i.e., acts as a backside CMP stop layer). In some implementations, the carrier substrate 302 (silicon substrate) is removed using wet etching with tetramethylammonium hydroxide (TMAH), which automatically stops when it reaches the first stop layer 303 having a material other than silicon (i.e., acts as a backside etching stop layer). The first stop layer 303 can ensure complete removal of the carrier substrate 302 without concern for thickness uniformity after thinning.

[0075] As shown in FIG. 3I, the first and second stop layers 303 and 304 (shown in FIG. 3H) can then be similarly completely removed using wet etching with a suitable etchant (such as phosphoric acid and hydrofluoric acid) until stopped by a third stop layer 305 having a material different from the second stop layer 304 (such as silicon nitride). In some implementations, the third stop layer 305 is patterned using lithography and etching to expose the memory film (having a storage layer 316, a blocking layer 317, and a tunneling layer 315) of each channel structure 314 while still covering the fill layer 306. It is understood that the patterning process can be skipped in the case where each channel structure 314 extends and is stopped by the third stop layer 305. In some implementations, the third stop layer 305 is removed after removing the second stop layer 304 using wet etching with phosphoric acid.

[0076] As shown in FIG. 3J, a portion of the storage layer 316, the blocking layer 317, and the tunneling layer 315 (shown in FIG. 3I) facing the filling layer 306 is removed to form a recess 357 surrounding an upper portion of the semiconductor channel 318 extending beyond the memory stack 330. For example, the exposed memory film of the channel structure 314 can be etched, stopping before or at the interface between the memory stack 330 and the filling layer 306, to form a recess 357 surrounding the exposed portion of the semiconductor channel 318. In some implementations, two wet etching processes are performed sequentially. For example, the storage layer 316 containing silicon nitride is selectively removed using wet etching with a suitable etching solution (e.g., phosphoric acid, etc.). The etching of the storage layer 316 can be controlled by controlling the etching time and / or the etching rate so that the etching does not continue beyond the upper surface of the memory stack 330. Next, the blocking layer 317 and the tunneling layer 315 containing silicon oxide can be selectively removed using wet etching with a suitable etching solution (e.g., hydrofluoric acid, etc.) without etching the semiconductor channel 318 containing polysilicon. The etching of the blocking layer 317 and the tunneling layer 315 can be controlled by controlling the etching time and / or the etching rate so that the etching does not continue beyond the upper surface of the memory stack 330. That is, the etching of the memory film can be controlled such that the bottom surface of the resulting recess 357 is above or coplanar with the upper surface of the memory stack 330.

[0077] In some implementations, a third stop layer 305 (shown in FIG. 3I) is used as an etching mask to perform a single dry etching process. For example, the third stop layer 305 may not be removed when performing dry etching, but instead, it can be patterned to expose only the storage layer 316, the blocking layer 317, and the tunneling layer 315 at the upper end of the channel structure 314 while still covering other areas as an etching mask. Then, dry etching can be performed to etch a portion of the storage layer 316, the blocking layer 317, and the tunneling layer 315 facing the filling layer 306. The dry etching can be controlled by controlling the etching time and / or the etching rate so that the etching does not continue beyond the upper surface of the memory stack 330. The third stop layer 305 can be removed after the dry etching is completed.

[0078] Nevertheless, removing a portion of the storage layer 316, the blocking layer 317, and the tunneling layer 315 facing the filling layer 306 from the back side is much less difficult and has a higher production yield compared to known solutions using front-side wet etching through an opening (e.g., slit 320 in FIG. 3D) in a dielectric stack 308 / memory stack 330 having a high aspect ratio (e.g., greater than 50). By avoiding the problems introduced by the high aspect ratio of the slit 320, the manufacturing complexity and cost can be reduced, and the yield can be increased. Also, the vertical scalability (e.g., an increase in the level of the dielectric stack 308 / memory stack 330) can be similarly improved.

[0079] As shown in FIG. 3J, in some implementations, the upper portion of the memory film (including the blocking layer 317, the storage layer 316, and the tunneling layer 315) of each channel structure 314 is removed to form a recess 357, and at least a part of the upper surface and the sidewall portion of the semiconductor channel 318 extending beyond the memory stack 330 (facing the filling layer 306) can be exposed. In some implementations, the upper portion of the semiconductor channel 318 exposed by the recess 357 is doped to increase its conductivity. For example, an inclined ion implantation process can be implemented to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) exposed by the recess 357 with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb) to a desired doping concentration. In some implementations, the bottom surface of the recess 357 is coplanar with the upper surface of the memory stack 330, exposing the entire sidewall portion of a part of the semiconductor channel 318 extending beyond the memory stack 330, maximizing the area for ion implantation.

[0080] As shown in FIG. 4, method 400 proceeds to operation 412, where a doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. In some implementations, the dopant includes an N-type dopant. In some implementations, to form the doped semiconductor layer, a layer of polysilicon is deposited into the recess and on top of the filling layer, and the deposited layer of polysilicon is doped.

[0081] As shown in FIG. 3K, a doped semiconductor layer 360 is formed in the recess 357 (shown in FIG. 3J), which surrounds and is in contact with an exposed portion of the semiconductor channel 318 and the outside of the recess 357 on the filling layer 306. In some implementations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited into the recess 357 in contact with an exposed portion of the semiconductor channel 318 and outside the recess 357 in contact with the filling layer 306 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb, etc.) using ion implantation and / or thermal diffusion. In some implementations, in-situ doping of an N-type dopant (e.g., P, As, or Sb, etc.) is performed when depositing the semiconductor layer into the recess 357 and on the filling layer 306 to form the doped semiconductor layer 360. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360, if necessary.

[0082] As shown in FIG. 4, method 400 proceeds to operation 414, where a doped semiconductor layer and a portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer and a portion of the semiconductor channel to activate the dopants in the doped semiconductor layer and the portion of the semiconductor channel for local activation. The confined area can be between the stack structure and the doped semiconductor layer. In some implementations, the doping concentration of the doped semiconductor layer and the doping concentration of a portion of the semiconductor channel in contact with the doped semiconductor layer are each 10 19 cm -3 from 1021 cm -3 is between

[0083] As shown in FIG. 3L, a doped semiconductor layer 360 and a portion of a semiconductor channel 318 in contact with the doped semiconductor layer 360 are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer 360 and a portion of the semiconductor channel 318 to activate dopants therein (e.g., an N-type dopant (e.g., P, As, or Sb), etc.). For example, the confined area can be vertically between the memory stack 330 and the doped semiconductor layer 360. The heat can be applied and focused by any suitable technique (e.g., annealing, laser, ultrasonic, or any other suitable thermal process, etc.). In some implementations, the confined area that may be affected by heat during the local activation process does not extend up to and beyond the bonding interface 354 to avoid heating the Cu interconnects used to connect the bonding interface 354 and the peripheral circuit 352. The local activation process can activate the dopants doped into the doped semiconductor layer 360 (and, if the semiconductor channel 318 is already doped, the exposed portion of the semiconductor channel 318). As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the exposed portion of the semiconductor channel 318 are each 10 19 cm -3 from 10 21 cm -3is in between. In some implementations, the local activation process is controlled such that dopants in the doped semiconductor layer 360 (and, when the semiconductor channel 318 is already doped, the exposed portion of the semiconductor channel 318) can diffuse from the source of the channel structure 314 towards the drain of the channel structure 314 up to but not facing the word line, as described above with respect to FIG. 2, over the source select gate line (e.g., one or more stack conductive layers 328 closest to the fill layer 306).

[0084] The local activation process can activate the dopants such that the dopants occupy the silicon lattice, reduce the contact resistance between the doped semiconductor layer 360 and the semiconductor channel 318, and also reduce the sheet resistance of the doped semiconductor layer 360. On the other hand, by confining the heat during the local activation process into areas without the thermosensitive structure, any potential damage to the thermosensitive structure (e.g., the bonding interface 354, and Cu interconnects used to connect the peripheral circuit 352, etc.) can be reduced or avoided.

[0085] As shown in FIG. 4, method 400 proceeds to operation 416, where a source contact is formed in contact with a doped semiconductor layer. As shown in FIG. 3M, one or more ILD layers 356 are formed over the doped semiconductor layer 360. The ILD layer 356 can be formed by depositing a dielectric material over the upper surface of the doped semiconductor layer 360 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). As shown in FIG. 3N, a source contact opening 358 can be formed through the ILD layer 356 to expose a portion of the doped semiconductor layer 360. In some implementations, the source contact opening 358 is formed using wet etching and / or dry etching (e.g., RIE, etc.).

[0086] As shown in FIG. 3O, the source contact (as part of the conductive layer 370) is formed in each of the source contact openings 358 (shown in FIG. 3N) at the backside of the fill layer 306. According to some implementations, the source contact is above the doped semiconductor layer 360 and in contact with the doped semiconductor layer 360. In some implementations, a conductive layer 370 (e.g., Al, etc.) is deposited into the source contact opening 358 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the source contact opening 358. Then, a planarization process (e.g., CMP, etc.) can be implemented to remove the excess conductive layer 370.

[0087] As shown in FIG. 3O, in some implementation forms, the conductive layer 370 also includes a redistribution layer, and the redistribution layer is above the source contact portion and in contact with the source contact portion. That is, according to some implementation forms, the conductive layer 370 is deposited not only into the source contact portion opening 358 as a source contact portion, but also outside the source contact portion opening 358 on the ILD layer 356 as a redistribution layer that electrically connects a plurality of source contact portions.

[0088] As shown in FIG. 3O, in some implementation forms, the conductive layer 370 further includes contact portions that extend through the ILD layer 356, the doped semiconductor layer 360, and the filling layer 306. That is, the conductive layer 370 is deposited not only into the source contact portion opening 358 as a source contact portion, but also into the contact portion openings 363 and 361 (shown in FIG. 3N) as contact portions that are electrically connected to the peripheral contact portions 338 and 340. As shown in FIGS. 3M and 3N, the contact portion openings 363 and 361 that respectively extend through the spacer layer 371, the ILD layer 356, the doped semiconductor layer 360, and the filling layer 306 are formed using wet etching and / or dry etching (such as RIE, etc.). In some implementation forms, the contact portion openings 363 and 361 are patterned using lithography so as to be respectively aligned with the peripheral contact portions 338 and 340. The etching of the contact portion openings 363 and 361 can stop at the upper ends of the peripheral contact portions 338 and 340 in order to expose the peripheral contact portions 338 and 340. As shown in FIG. 3N, spacers 362 are formed from the spacer layer 371 along the sidewall portions of the contact portion openings 363 and 361 in order to electrically isolate the doped semiconductor layer 360.

[0089] According to one aspect of the present disclosure, a 3D memory device includes a stack structure including alternating conductive layers and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall portion of a part of the doped portion of the semiconductor channel that extends beyond the stack structure.

[0090] In some implementations, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are each between 10 19 cm -3 and 10 21 cm -3 .

[0091] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

[0092] In some implementations, the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite to the first direction.

[0093] In some implementations, one of the conductive layers includes a source select gate line.

[0094] In some implementations, the 3D memory device further includes a fill layer between the stack structure and another part of the doped semiconductor layer in a first direction.

[0095] In some implementations, the fill layer includes polysilicon, a high-k dielectric, or a metal.

[0096] In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

[0097] In some implementations, one end of the memory film is coplanar with or extends beyond the corresponding surface of the stack structure.

[0098] In some implementations, the 3D memory device is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0099] According to another aspect of the present disclosure, a 3D memory device includes a stack structure including alternating conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure to the doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The doped portion of the semiconductor channel is between the doped semiconductor layer and one of the conductive layers closest to the doped semiconductor layer.

[0100] In some implementations, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are each between 10 19 cm -3 and 10 21 cm -3 .

[0101] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

[0102] In some implementations, one of the conductive layers includes a source select gate line.

[0103] In some implementations, a portion of the doped semiconductor layer is in contact with the doped portion of the semiconductor channel.

[0104] In some embodiments, the 3D memory device further includes a fill layer between the stack structure and another portion of the doped semiconductor layer.

[0105] In some embodiments, the fill layer includes polysilicon, a high-k dielectric, or a metal.

[0106] In some embodiments, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

[0107] In some embodiments, one end of the memory film is coplanar with or extends beyond the corresponding surface of the stack structure.

[0108] In some embodiments, the 3D memory device is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0109] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stack structure is formed over the fill layer. A channel structure is formed extending through the stack structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. A portion of the substrate and a portion of the memory film are sequentially removed to expose a portion of the semiconductor channel facing the fill layer. A doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. The doped semiconductor layer and a portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0110] In some embodiments, to locally activate, heat is applied in a confined area having the doped semiconductor layer and a portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel.

[0111] In some embodiments, each of the channel structures includes a memory film and a semiconductor channel, and the metal silicide layer is in contact with the semiconductor channels of the plurality of channel structures.

[0112] In some embodiments, the confined area is between the stack structure and the doped semiconductor layer.

[0113] In some embodiments, the dopant includes an N-type dopant, and after activation, the doping concentration of the doped semiconductor layer and the doping concentration of a part of the semiconductor channel in contact with the doped semiconductor layer are each between 10 19 cm -3 and 10 21 cm -3 .

[0114] In some embodiments, before forming the doped semiconductor layer, an exposed part of the semiconductor channel is doped.

[0115] In some embodiments, a first stop layer, a second stop layer, and a third stop layer are sequentially formed between the substrate and the filling layer.

[0116] In some embodiments, the first stop layer includes silicon oxide or silicon nitride, the second stop layer includes silicon oxide or polysilicon, the third stop layer includes silicon nitride or polysilicon, and the filling layer includes polysilicon.

[0117] In some embodiments, to form the channel structure, a channel hole is formed to extend through the stack structure, the filling layer, and the third stop layer and stop at the second stop layer, and the memory film and the semiconductor channel are sequentially formed along the sidewall and the bottom surface of the channel hole.

[0118] In some implementations, to sequentially remove a substrate and a portion of a memory film, the substrate is removed and stopped at a first stop layer, the first stop layer and a second stop layer are removed, stopped at a third stop layer, the third stop layer is patterned to expose the memory film, the exposed memory film is etched, stopping before or at an interface between the stack structure and the filling layer to form a recess surrounding an exposed portion of the semiconductor channel.

[0119] In some implementations, to form a doped semiconductor layer, a layer of polysilicon is deposited into the recess and on top of the filling layer, and the deposited layer of polysilicon is doped.

[0120] In some implementations, after locally activating the doped semiconductor layer, a source contact is formed in contact with the doped semiconductor layer.

[0121] According to yet another aspect of the present disclosure, a system includes a 3D memory device configured to store data and a memory controller coupled to and configured to control the 3D memory device. The 3D memory device includes a stack structure including alternating conductive and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A portion of the doped semiconductor layer contacts sidewalls of a portion of the doped portion of the semiconductor channel that extends beyond the stack structure.

[0122] In some implementations, the system further includes a host coupled to the memory controller.

[0123] In some embodiments, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are each between 10 19 cm -3 and 10 21 cm -3 .

[0124] In some embodiments, the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

[0125] In some embodiments, the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite to the first direction.

[0126] In some embodiments, one of the conductive layers includes a source select gate line.

[0127] In some embodiments, the 3D memory device further includes a filling layer between the stack structure and another part of the doped semiconductor layer in the first direction.

[0128] In some embodiments, the filling layer includes polysilicon, a high-k dielectric, or metal.

[0129] In some embodiments, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

[0130] In some embodiments, one end of the memory film is coplanar with or extends beyond the corresponding surface of the stack structure.

[0131] In some embodiments, the 3D memory device is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0132] The foregoing description of the specific embodiments can be readily modified and / or adapted with respect to various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments based on the teachings and guidance presented herein.

[0133] The breadth and scope of the present disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the appended claims and their equivalents.

Description of Reference Numerals

[0134] 100 3D Memory Device 101 Substrate 102 First Semiconductor Structure 104 Second Semiconductor Structure 106 Bonding Interface 108 Peripheral Circuit 110 Bonding Layer 111 Bonding Contact 112 Bonding Layer 113 Bonding Contact 114 Memory Stack 116 Stack Conductive Layer 118 Stack Dielectric Layer 120 Filling Layer 121 First Portion, Plate 122 Doped Semiconductor Layer 123 Plug 124 Channel Structure 126 Memory Film 128 Semiconductor Channel 128a Doped Portion 128b Undoped Portion 129 Channel Plug 130 Insulating Structure 132 Source Contact 133 Interconnection Layer 134 ILD Layer 136 Redistribution Layer 138 Passivation layer 140 Contact pad 142 Contact portion 144 Contact portion 146 Peripheral contact portion 148 Peripheral contact portion 150 Channel local contact portion 152 Word line local contact portion 201 Source select gate line 203 Word line 302 Carrier substrate 303 First stop layer 304 Second stop layer 305 Third stop layer 306 Filling layer 308 Dielectric stack 310 Stack dielectric layer 312 Stack sacrificial layer 314 Channel structure 315 Tunneling layer 316 Storage layer 317 Blocking layer 318 Semiconductor channel 320 Slit 322 Lateral recess 328 Stack conductive layer 330 Memory stack 332 Gate dielectric layer 334 Dielectric capping layer 336 Insulating structure 338 Peripheral contact portion 340 Peripheral contact portion 342 Word line local contact portion 344 Channel local contact portion 346 Bonding layer 348 Bonding layer 350 Silicon substrate 352 Peripheral circuit 354 Bonding interface 356 ILD layer 357 Recess 358 Source contact opening 360 Doped semiconductor layer 361 Contact opening 362 Spacer 363 Contact opening 370 Conductive layer 371 Spacer layer 500 System 502 Memory system 504 3D memory device 506 Memory controller 508 Host 602 Memory card 604 Memory card connector 606 SSD 608 SSD connector

Claims

1. a stack structure including alternating conductive and dielectric layers; a channel structure extending through the stack structure, the channel structure including a memory film and a semiconductor channel, the semiconductor channel including a doped portion and an undoped portion, a portion of the doped portion of the semiconductor channel extending beyond the stack structure in a first direction; a doped semiconductor layer, a portion of the doped semiconductor layer contacting a sidewall of the portion of the doped portion of the semiconductor channel that extends beyond the stack structure; A three-dimensional (3D) memory device comprising:

2. The doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are each 10 １９ cm －３ From 10 ２１ cm －３ 2. The 3D memory device of claim 1 , wherein:

3. 3. The 3D memory device of claim 1 or 2, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

4. 4. The 3D memory device of claim 1, wherein the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite to the first direction.

5. 5. The 3D memory device of claim 4, wherein said one of said conductive layers comprises a source select gate line.

6. 6. The 3D memory device of claim 1, further comprising a fill layer between the stack structure and another portion of the doped semiconductor layer in the first direction.

7. 7. The 3D memory device of claim 6, wherein the fill layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

8. 8. The 3D memory device of claim 1, further comprising a source contact in contact with the doped semiconductor layer.

9. 9. The 3D memory device of claim 1, wherein one end of the memory film is flush with or beyond a corresponding surface of the stack structure.

10. 10. The 3D memory device of claim 1, wherein the 3D memory device is configured to generate a gate-induced drain leakage (GIDL) assisted body bias when performing an erase operation.

11. a stack structure including alternating conductive and dielectric layers; a doped semiconductor layer; a channel structure extending through the stack structure to the doped semiconductor layer, the channel structure including a memory film and a semiconductor channel; Including, 1. A three-dimensional (3D) memory device, wherein the semiconductor channel includes a doped portion, the doped portion of the semiconductor channel being between the doped semiconductor layer and one of the conductive layers that is closest to the doped semiconductor layer.

12. The doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are each 10 １９ cm －３ From 10 ２１ cm －３ 12. The 3D memory device of claim 11, wherein:

13. 13. The 3D memory device of claim 11 or 12, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

14. 14. The 3D memory device of claim 11, wherein the one of the conductive layers comprises a source select gate line.

15. 15. The 3D memory device of claim 11, wherein a portion of the doped semiconductor layer is in contact with the doped portion of the semiconductor channel.

16. 16. The 3D memory device of claim 15, further comprising a fill layer between the stack structure and another portion of the doped semiconductor layer.

17. 17. The 3D memory device of claim 16, wherein the fill layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

18. 18. The 3D memory device of claim 11, further comprising a source contact in contact with the doped semiconductor layer.

19. 19. The 3D memory device of claim 11, wherein one end of the memory film is flush with or beyond a corresponding surface of the stack structure.

20. 20. The 3D memory device of claim 11, wherein the 3D memory device is configured to generate a gate-induced drain leakage (GIDL) assisted body bias when performing an erase operation.

21. forming a fill layer above the substrate; forming a stack structure above the packing layer; forming a channel structure extending through the stack structure and the fill layer, the channel structure including a memory film and a semiconductor channel; sequentially removing the substrate and a portion of the memory film to expose a portion of the semiconductor channel facing the fill layer; forming a doped semiconductor layer in contact with the exposed portion of the semiconductor channel; locally activating the doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer; 16. A method for forming a three-dimensional (3D) memory device, comprising:

22. 22. The method of claim 21 , wherein locally activating comprises applying heat in a confined area having the doped semiconductor layer and the portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel.

23. 23. The method of claim 22, wherein the confined area is between the stack structure and the doped semiconductor layer.

24. The dopant comprises an N-type dopant, and after the activation, a doping concentration of the doped semiconductor layer and a doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are each about 10 １９ cm －３ From 10 ２１ cm －３ 24. The method of claim 22 or 23, wherein

25. 25. The method of any one of claims 21 to 24, further comprising doping the exposed portion of the semiconductor channel prior to forming the doped semiconductor layer.

26. 26. The method of any one of claims 21 to 25, further comprising the steps of sequentially forming a first stop layer, a second stop layer, and a third stop layer between the substrate and the fill layer.

27. 27. The method of claim 26, wherein the first stop layer comprises silicon oxide or silicon nitride, the second stop layer comprises silicon oxide or polysilicon, the third stop layer comprises silicon nitride or polysilicon, and the fill layer comprises polysilicon.

28. The step of forming the channel structure comprises: forming a channel hole extending through the stack structure, the fill layer, and the third stop layer and terminating at the second stop layer; sequentially forming the memory film and the semiconductor channel along sidewalls and a bottom surface of the channel hole; 28. The method of claim 26 or 27, comprising:

29. The step of sequentially removing the substrate and the portion of the memory film comprises: removing the substrate and stopping on the first stop layer; removing the first stop layer and the second stop layer and stopping at the third stop layer; patterning the third stop layer to expose the memory film; etching the exposed memory film, stopping before or at an interface between the stack structure and the fill layer to form a recess surrounding the exposed portion of the semiconductor channel; 29. The method of any one of claims 26 to 28, comprising:

30. The step of forming the doped semiconductor layer comprises: depositing a layer of polysilicon into the recess and over the fill layer; doping the deposited layer of polysilicon; 30. The method of claim 29, comprising:

31. 31. The method of any one of claims 21 to 30, further comprising forming a source contact in contact with the doped semiconductor layer after locally activating the doped semiconductor layer.

32. 1. A three dimensional (3D) memory device configured to store data, the 3D memory device comprising: a stack structure including alternating conductive and dielectric layers; a channel structure extending through the stack structure, the channel structure including a memory film and a semiconductor channel, the semiconductor channel including a doped portion and an undoped portion, a portion of the doped portion of the semiconductor channel extending beyond the stack structure in a first direction; a doped semiconductor layer, a portion of the doped semiconductor layer contacting a sidewall of the portion of the doped portion of the semiconductor channel that extends beyond the stack structure; a 3D memory device comprising: a memory controller coupled to the 3D memory device and configured to control the 3D memory device; Including, the system.

33. 33. The system of claim 32, further comprising a host coupled to the memory controller.

34. The doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are each 10 １９ cm －３ From 10 ２１ cm －３ 34. The system of claim 32 or 33, wherein:

35. 35. The system of claim 32, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each comprise N-type doped polysilicon.

36. 36. The system of claim 32, wherein the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite the first direction.

37. 37. The system of claim 36, wherein the one of the conductive layers comprises a source select gate line.

38. 38. The system of claim 32, further comprising a fill layer between the stack structure and another portion of the doped semiconductor layer in the first direction.

39. 40. The system of claim 38, wherein the fill layer comprises polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

40. 40. The system of any one of claims 32 to 39, further comprising a source contact in contact with the doped semiconductor layer.

41. 41. The system of any one of claims 32 to 40, wherein one end of the memory film is flush with or beyond a corresponding surface of the stack structure.

42. 42. The system of claim 32, wherein the 3D memory device is configured to generate a gate-induced drain leakage (GIDL) assisted body bias when performing an erase operation.

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