Imaging apparatus

Abstract

To provide a solid-state imaging apparatus with good productivity and improved dynamic range.SOLUTION: An imaging apparatus includes a photoelectric conversion element having an i-type semiconductor layer, a functional element, and a wiring, and an area in which the i-type semiconductor layer overlaps the functional element and the wiring in plan view is preferably 35% or less, more preferably 15% or less, and further preferably 10% or less of the area of the i-type semiconductor layer in plan view. A plurality of photoelectric conversion elements are provided in the same semiconductor layer, and therefore, a step of separating photoelectric conversion elements can be omitted. Each of the i-type semiconductor layers included in the plurality of photoelectric conversion elements is separated by a p-type semiconductor layer or an n-type semiconductor layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] One embodiment of the present invention relates to an imaging device. The present invention relates to an imaging device provided with the imaging device, and further to an electronic device having the imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. For example, one embodiment of the present invention is The present invention relates to a process, a machine, a manufactur- ing method, or a method of manufacture. The present invention relates to a structure or composition of matter. One aspect of the present invention relates to a storage device, a processor, a method for driving the same, or a method for manufacturing the same.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes and semiconductor circuits are considered semiconductor devices. The present invention also relates to a display device, a light-emitting device, a lighting device, an electro-optical device, an imaging device, and an electronic device. The above may include semiconductor elements and semiconductor circuits. Devices, electro-optical devices, imaging devices, electronic equipment, and the like may also include semiconductor devices. [Background technology]

[0004] Imaging devices are now standardly built into mobile phones and are becoming increasingly popular (see, for example, patent literature 2). In particular, CMOS image sensors have the following advantages over CCD image sensors: low cost and high They have features such as high resolution and low power consumption, and most imaging devices are made up of CMOS image sensors. It has been made. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 7,046,282 Summary of the Invention [Problem to be solved by the invention]

[0006] In imaging devices using CMOS image sensors, in order to enable imaging in various environments, Therefore, there is a demand for improving the dynamic range.

[0007] In addition, low power consumption is an important feature required for evaluating the performance of imaging devices. In particular, in the case of portable electronic devices such as mobile phones, the power consumption of the imaging device is high. , the continuous usage time will be shortened.

[0008] An object of one embodiment of the present invention is to provide an imaging device or the like with an improved dynamic range. Another embodiment of the present invention is to provide an imaging device or the like that captures high-quality images. Another object of one embodiment of the present invention is to provide an imaging device with low power consumption. Another object of the present invention is to provide an imaging device with high productivity. Another object of the present invention is to provide a novel imaging device or Another object of the present invention is to provide a semiconductor device or a novel semiconductor device.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including a photoelectric conversion element, first to fourth transistors, a capacitor, and a first the photoelectric conversion element has an n-type semiconductor and a p-type semiconductor, The wiring 1 is electrically connected to either the n-type semiconductor or the p-type semiconductor, and The other of the p-type semiconductors is electrically connected to one of the source and drain of the first transistor. The gate of the first transistor is electrically connected to the second wiring. The other of the source and drain of the second transistor is electrically connected to the first node. One of the source and drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the second transistor is electrically connected to the first node. The gate of the capacitor is electrically connected to the fourth wiring, and one electrode of the capacitor is electrically connected to the first node. The other electrode of the capacitance element is electrically connected to the first wiring, and the third transistor The gate of the third transistor is electrically connected to the first node, and the source or drain of the third transistor is One of the drains is electrically connected to the fifth wiring, and is the source or drain of the third transistor. the other input is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to a sixth wiring; A gate of the fourth transistor is electrically connected to the seventh wiring.

[0011] The photoelectric conversion element has an i-type semiconductor, and in plan view, the area where the capacitor element and the i-type semiconductor overlap, and The total area of ​​the overlapping areas of the first to seventh wirings and the i-type semiconductor is It is preferable that it is no more than 35% of the body area.

[0012] The first to fourth transistors each include an oxide semiconductor as a semiconductor in which a channel is formed. is preferred.

[0013] The semiconductors used for the first to fourth transistors are the i-type semiconductors of the photoelectric conversion element. may have a different band gap from

[0014] Another embodiment of the present invention is an imaging device including at least first and second photoelectric conversion elements. The first and second photoelectric conversion elements have an i-type semiconductor, and the first photoelectric conversion element has The i-type semiconductor and the i-type semiconductor of the second photoelectric conversion element are n-type or p-type semiconductors. The imaging device is characterized in that the imaging devices are adjacent to each other via a gap. Effect of the Invention

[0015] According to one embodiment of the present invention, an imaging device or the like with an improved dynamic range can be provided. Alternatively, it is possible to provide an imaging device or the like that can capture images with improved quality. Alternatively, it is possible to provide an imaging device with a short imaging interval. It is possible to provide an imaging device with good productivity. Another object of the present invention is to provide a novel imaging device or a novel semiconductor device. It is possible.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0017] [Figure 1] 1A and 1B illustrate a configuration example of an imaging device of one embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram for explaining a configuration example of a peripheral circuit. [Diagram 3] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 4] 3A and 3B are a plan view and a circuit diagram of a pixel driving circuit, respectively; [Diagram 5] FIG. 2 is a perspective view illustrating an example of the configuration of a pixel. [Figure 6] FIG. 1 is a diagram showing an example in which pixels are arranged in a matrix. [Figure 7] FIG. 2 is a diagram illustrating an example of a circuit configuration of pixels arranged in a matrix. [Figure 8] FIG. 1 is a diagram showing an example in which photoelectric conversion elements are arranged in a matrix. [Figure 9] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 10] 1A to 1C are diagrams illustrating an example of the configuration of a pixel. [Figure 11] FIG. 1 is a diagram illustrating an example of the configuration of an imaging apparatus. [Figure 12] 1A to 1C illustrate an example of a transistor. [Figure 13] FIG. 2 is a diagram for explaining an energy band structure. [Figure 14] 1A to 1C illustrate an example of a transistor. [Figure 15] FIG. 2 illustrates an example of a circuit configuration. [Figure 16] FIG. 2 illustrates an example of a circuit configuration. [Figure 17] FIG. 2 illustrates an example of a circuit configuration. [Figure 18] 1A to 1C illustrate one embodiment of a transistor. [Figure 19] 1A to 1C illustrate one embodiment of a transistor. [Figure 20]1A to 1C illustrate one embodiment of a transistor. [Figure 21] 1A to 1C illustrate one embodiment of a transistor. [Figure 22] 1A to 1C illustrate one embodiment of a transistor. [Diagram 23] 1A to 1C are diagrams illustrating one embodiment of a capacitor. [Figure 24] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. In addition, in all the drawings for explaining the embodiment, the same parts or the same Parts having similar functions are given the same reference numerals, and repeated explanations thereof may be omitted. .

[0019] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0020] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be described in the drawings or text. do.

[0021] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0022] An example of a direct connection between X and Y is The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, An element (e.g., a switch, transistor, or capacitor) that allows electrical connection between X and Y. (capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) In this case, X and Y are connected.

[0023] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function of being controlled to be on and off. A switch can be in a conductive state (on) or a non-conductive state (off) to allow current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This also includes the case where and Y are directly connected.

[0024] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from A If X and Y are transmitted to B, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0025] In addition, if it is explicitly stated that X and Y are electrically connected, When X and Y are electrically connected (i.e., when there is another element or circuit between X and Y), When X and Y are functionally connected (i.e., when X and Y are (X and Y are connected functionally with another circuit between them) and (X and Y are connected directly (i.e., when X and Y are connected without any other element or circuit between them) In other words, it is assumed that the above is disclosed in the present specification. If it is explicitly stated that it is connected, The same contents as those in the above case are deemed to be disclosed in the present specification, etc.

[0026] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0028] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is The second connection path is a path through a transistor between the source (or first terminal, etc.) of the The first connection path is through Z1 and the second connection path is through the drain of the transistor (or the second terminal, etc.) is electrically connected to Y through at least a third connection path. , the third connection path does not have the second connection path, and the third connection path is Or, it can be expressed as "the source of the transistor (or the first A terminal, etc.) is electrically connected to X through Z1 by at least a first connection path. The first connection path does not have a second connection path, and the second connection path is a transistor. The drain (or second terminal, etc.) of the transistor is at least Both are electrically connected to Y through Z2 by a third connection path, and the third connection path is , does not have a second connection path. The source (or first terminal, etc.) of X, the first electrical path does not have a second electrical path, and the first electrical path is electrically connected to X. The second electrical path is from the source (or first terminal, etc.) of the transistor to the drain The drain (or second terminal, etc.) of the transistor is the electrical path to the 2) is electrically connected to Y through Z2 by at least a third electrical path. The third connection path does not have a fourth connection path, and the fourth electrical path is The drain (or second terminal, etc.) of the transistor is connected to the source (or first terminal, etc.) of the transistor. "The electrical path to the power supply (such as a power supply to a power supply) is an electrical path to the power supply (such as a power supply to a power supply). By using the method, the connection paths in the circuit configuration are specified, and the transistor A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) in the technology. The target range can be determined.

[0029] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0030] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0031] In this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Substrates (e.g. single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). The materials used are plastics that can be used for bonding, and synthetic resins that have flexibility, such as acrylic. Examples of films include vinyl, such as polyvinyl fluoride or polyvinyl chloride, polypropylene, Examples of the base film include polyester, polyamide, etc. In particular, semiconductor substrates, single crystal By manufacturing transistors using a substrate or SOI substrate, the characteristics, size, etc. A small-sized transistor with little variation in size or shape, high current capability, and When a circuit is constructed using such transistors, the circuit can be manufactured with low power consumption. This allows for reduced power consumption or higher circuit integration.

[0032] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. In addition to the substrate on which the above-mentioned transistors can be formed, the substrates include paper substrates, cellophane substrates, and the like. substrates made of natural fibers (silk, cotton, hemp), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, regenerated These substrates include raw polyester, leather substrates, and rubber substrates. By using this, it is possible to form transistors with good characteristics and transistors with low power consumption. It is possible to manufacture devices that are less likely to break, have heat resistance, and are lighter or thinner.

[0033] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. For example, In the actual manufacturing process, resist masks, etc., may be unintentionally damaged by etching or other processes. However, in order to make it easier to understand, these may be omitted.

[0034] In order to make the drawings easier to understand, especially in top views (also called "plan views"), Some components may be omitted. Also, some hidden lines may be omitted. There is a match.

[0035] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "the electrode on insulating layer A is directly in contact with the insulating layer A" is not limited to the above. If the expression is "electrode B", it is not necessary for electrode B to be formed directly on insulating layer A. The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0036] The source and drain functions may also be different in some cases, such as when transistors of different polarities are used, or when When the direction of the current changes during operation of the circuit, the two are interchangeable depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be so.

[0037] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. In addition, "perpendicular" and "orthogonal" mean that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it includes the case where the angle is between 85° and 95°. "Straight" refers to two straight lines that form an angle of 60° or more and 120° or less.

[0038] Also, a voltage is a potential and a reference potential (for example, a ground potential (GND potential) or a source potential). Therefore, voltage can be replaced with potential. be.

[0039] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with less than 0.1 atomic percent can be considered impurities. The conductor's DOS (Density of State) increases and the carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, There are elements, group 13 elements, group 14 elements, group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, when the semiconductor is a silicon film, the characteristics of the semiconductor may be deteriorated. Examples of impurities that change the value of the valence number include oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and These include Group 3 elements and Group 15 elements.

[0040] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking, such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to confuse the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. Even if a term has an ordinal number in the specification, a different ordinal number may be used in the claims. In addition, even if a term is given an ordinal number in this specification, In patent claims, ordinal numbers may be omitted.

[0041] Note that the "channel length" refers to, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). The source (source region or source electrode) in the region where the channel is formed The distance between the drain and the transistor (the drain region or the drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value or the maximum value in the region where the channel is formed. , the minimum or average value.

[0042] Also, the "channel width" refers to, for example, the width of a semiconductor (or a semiconductor transistor when it is in the on state). The area where the gate electrode overlaps with the conductor (the part of the conductor where the current flows), or the channel is formed. The length of the part where the source and drain face each other in the region where the source and drain are connected. In a transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. In this specification, the channel width is any one of the values ​​in the region where the channel is formed, This can be the maximum, minimum or average value.

[0043] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in a transistor with a fine, three-dimensional structure, The percentage of the channel region that is formed on the side of the semiconductor, compared to the percentage of the channel region that is formed In that case, the apparent channel width shown in the top view may be larger. In this case, the effective channel width where the channel is actually formed is larger than the width of the channel formed by the MOSFET.

[0044] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0045] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0046] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0047] In addition, in this specification, a high power supply potential VDD (hereinafter, simply referred to as "VDD" or "H potential") The low power supply potential VSS is a power supply potential that is higher than the low power supply potential VSS. VSS (hereinafter simply referred to as "VSS" or "L potential") is the potential lower than the high power supply potential VDD. The lowest power supply potential is also referred to as VDD or VSS. For example, if VDD is at ground potential, VSS is at a potential lower than ground potential, and V When SS is at ground potential, VDD is at a potential higher than ground potential.

[0048] (Embodiment 1) In this embodiment, an imaging device of one embodiment of the present invention will be described with reference to drawings.

[0049] <Configuration example of imaging device 100> FIG. 1A is a plan view illustrating a configuration example of an imaging device 100 according to an embodiment of the present invention. 100 includes a pixel unit 110, a first circuit 260, a second circuit 270, a third circuit 280, and a fourth circuit 290. The pixel section 110 has p rows and q columns (p and q are natural numbers of 2 or more). The first circuit 26 has a plurality of pixels 111 (imaging elements) arranged in a matrix. The 0th to 4th circuits 290 are connected to the plurality of pixels 111 and are used to drive the plurality of pixels 111. In this specification and the like, the first circuit 260 to the third circuit The fourth circuit 290 may be called a "peripheral circuit" or a "drive circuit." For example, The first circuit 260 can be considered as a part of the peripheral circuit.

[0050] For example, the first circuit 260 or the fourth circuit 290 receives the analog signal output from the pixel 111. For example, as shown in FIG. 2, the first circuit 260 has a function of processing a signal. A control circuit 261, a column driving circuit 262, an output circuit 263, and the like may be provided.

[0051] The signal processing circuit 261 shown in FIG. 2 includes a circuit 264 provided for each column. 264 has the function of performing signal processing such as noise removal and analog-to-digital conversion. The circuit 264 shown in FIG. 2 has the function of analog-to-digital conversion. The logic circuit 261 can function as a column-type analog-to-digital conversion device. can.

[0052] The circuit 264 includes a comparator 264a and a counter circuit 264b. 64a is an analog signal input from the wiring 123 provided for each column, and The reference potential signal (for example, a ramp wave signal) input from the The counter circuit 264b receives a clock signal from a wiring 268. 4b is a time period during which the first value is output by the comparison operation of the comparator 264a; and has the function of storing the measurement results as N-bit digital values.

[0053] The column driver circuit 262 is also called a column selection circuit, a horizontal driver circuit, etc. A selection signal is generated to select a column from which a signal is to be read out. The column driver circuit 262 is The columns are sequentially selected by the column driving circuit 262, and the selected columns are The signal output from the circuit 264 is input to the output circuit 263 via the wiring 269 . The wiring 269 can function as a horizontal transfer line.

[0054] The signal input to the output circuit 263 is processed by the output circuit 263 and output to the outside of the imaging device 100. The output circuit 263 may be configured with, for example, a buffer circuit. The output circuit 263 has a function of controlling the timing of outputting a signal to the outside of the imaging device 100. The present invention may have the following functions:

[0055] Also, for example, the second circuit 270 or the third circuit 280 may read out the signal from the pixel 111. The second circuit 270 or the third circuit 271 has a function of generating and outputting a selection signal for selecting the first circuit 270 or the second circuit 271. The third circuit 280 may be called a row selection circuit or a vertical drive circuit.

[0056] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier circuit, or a converter circuit. The transistors and the like used in the peripheral circuits form a photoelectric conversion element 136, which will be described later. The transistors may be formed by using other parts of the semiconductors that form the peripheral circuits. etc. may be formed using another part of the semiconductor forming the pixel driving circuit 112 described later. In addition, the transistors used in the peripheral circuits are made by combining these transistors. In addition, a part or the whole of the peripheral circuits may be implemented as semiconductor devices such as ICs. good.

[0057] In addition, the peripheral circuits may be omitted from among the first circuit 260 to the fourth circuit 290. For example, the function of either the first circuit 260 or the fourth circuit 290 may be omitted. In addition to the other of the first circuit 260 or the fourth circuit 290, One of the circuits 290 may be omitted. Also, for example, the second circuit 270 or the third circuit The function of one of the circuits 270 and 280 is added to the other of the second circuit 270 or the third circuit 280. Either the second circuit 270 or the third circuit 280 may be omitted. The first circuit is realized by adding the function of the other circuit to any one of the circuits 260 to 290. Any one of the circuits 260 to 290 may be omitted.

[0058] As shown in FIG. 1B, in the pixel section 110 of the imaging device 100, the pixel 11 By arranging the pixels 111 at an angle, the This allows the pixel interval (pitch) in the column direction to be shortened. The quality of the captured image can be improved.

[0059] [Example of pixel 111 configuration] A configuration example of the pixel 111 will be described with reference to FIG. 3 to FIG. 5. A transistor 131, a transistor 132, a transistor 133, a transistor 134, and a capacitance element The pixel 111 also includes a functional element such as a photoelectric conversion element 135 and a photoelectric conversion element 136. Among the functional elements, a circuit configured with functional elements other than the photoelectric conversion element 136 is referred to as a pixel driving circuit 11. The pixel driving circuit 112 is electrically connected to the photoelectric conversion element 136. The driving circuit 112 has a function of generating an analog signal according to the amount of light received by the photoelectric conversion element 136. Yes.

[0060] 3A is a plan view of a pixel 111. FIG. 3B is a plan view of a photoelectric conversion element 136. FIG. 4A is a plan view of the pixel driving circuit 112. FIG. 4B is a plan view of the pixel 111. FIG. 5 is a perspective view illustrating the configuration of a pixel 111. The pixel 111 is a The pixel driving circuit 112 is provided above the electric conversion element 136 .

[0061] The photoelectric conversion element 136 includes a p-type semiconductor 221, an i-type semiconductor 222, and an n-type semiconductor 223. The photoelectric conversion element 136 has a p-type semiconductor 221 and an n-type semiconductor 22 The photoelectric conversion element 136 is formed by sandwiching an i-type semiconductor 222 between the photoelectric conversion element 136 and the i-type semiconductor 222. It is also possible to configure the device with only the p-type semiconductor 221 and the n-type semiconductor 223 without providing the conductor 222. By providing the i-type semiconductor 222 in the photoelectric conversion element 136, the light receiving sensitivity can be increased.

[0062] Intrinsic semiconductors (i-type semiconductors) ideally contain no impurities and have a forbidden Fermi level. The semiconductor is located almost in the center of the band, but in this specification, the donor impurities or By adding impurities as acceptors, the Fermi level is positioned almost in the center of the forbidden band. Intrinsic semiconductors also include semiconductors that have been converted into intrinsic semiconductors. Even if a semiconductor contains pure substances, as long as it is in a state where it can function as an intrinsic semiconductor, The semiconductor is included in the intrinsic semiconductor.

[0063] The p-type semiconductor 221 and the n-type semiconductor 223 are formed in a comb-like shape in a plan view, and the i-type semiconductor It is preferable that the p-type semiconductor 221 and the n-type By forming the semiconductor 223 in a comb-like shape, the distance at which the p-type semiconductor 221 and the n-type semiconductor 223 face each other is The distance D can be increased by increasing the distance between the p-type semiconductor 221 and the n-type It can also be said to be the length of the line passing through the center of the i-type semiconductor 222 sandwiched between the semiconductors 223. By reducing the detection sensitivity of the photoelectric conversion element 136, the detection It is possible to provide a highly sensitive imaging device 100. In FIG. 3B, the position of the distance D is indicated by a dashed line. In addition, when the pixel 111 detects visible light, the p-type semiconductor 221 in plan view The distance E from the i-type semiconductor 222 to the n-type semiconductor 223 (the width of the i-type semiconductor 222) is set to 800 nm or more. (See FIG. 3(B)).

[0064] One of the source and the drain of the transistor 131 is electrically connected to the wiring 123. The other of the source and drain is electrically connected to the source or drain of the transistor 132. The gate of the transistor 131 is electrically connected to the wiring 125. The other of the source and the drain of the transistor 132 is electrically connected to the wiring 124. The gate of the transistor 132 is electrically connected to a node 152. One of the source and drain of 133 is electrically connected to the wiring 122. The other drain is electrically connected to node 152. The gate of transistor 133 is The source or drain of the transistor 134 is electrically connected to the wiring 126. One of the sources or drains is electrically connected to a node 151, and the other of the sources or drains is electrically connected to a node 152. The gate of the transistor 134 is electrically connected to the wiring 127. One electrode (for example, a cathode) of the photoelectric conversion element 136 (photodiode) is The other electrode (for example, an anode) is electrically connected to the wiring 121. The two are electrically connected to each other (see FIG. 4(A) and FIG. 4(B)).

[0065] The node 152 functions as a charge storage unit. It functions as a transfer transistor to transfer the charge corresponding to the amount of light received from the photodiode 36 to the node 152. Also, the transistor 133 is a reset circuit for resetting the potential of the node 152. The transistor 132 can also function as a transistor having a stored charge at node 152. The transistor 13 can function as an amplifying transistor for amplifying the charge. 1 is a read transistor for reading out the signal amplified by the transistor 132. It can function.

[0066] The analog signal generated by the photoelectric conversion element 136 and the pixel driving circuit 112 is input to a wiring 123. For example, the wiring 121 has a function of supplying a potential VPD. For example, the wiring 124 supplies a potential VPI. For example, the wiring 125 has a function of supplying a potential SEL. For example, the wiring 126 has a function of supplying a potential PR. For example, the wiring 128 has a function of supplying a potential VPI.

[0067] In this embodiment, the wiring 121 is provided in a net shape so as to surround the outer periphery of the pixel 111. The wiring 121 is electrically connected to the p-type semiconductor 221. By providing the wiring 121, the potential variation of the wiring 121 in the pixel portion 110 is reduced, and the imaging device 100 This makes it possible to stabilize the operation and improve the reliability of the imaging device 100. Either the source or the drain of 34 is electrically connected to the wiring 129, and the wiring 129 is connected to an n-type semiconductor The source of the transistor 131 may be electrically connected to the conductor 223 (see FIG. 5). Alternatively, one of the drains is electrically connected to the wiring 141, and the wiring 141 is electrically connected to the wiring 123. The other of the source and the drain of the transistor 132 may be connected to the wiring 14. 2, and the wiring 142 may be electrically connected to the wiring 124. Either the source or the drain of the transistor 133 is electrically connected to the wiring 143. The other electrode of the capacitor 135 may be electrically connected to the wiring 14. 4, the wiring 144 is electrically connected to the wiring 145, and the wiring 145 is electrically connected to the wiring 12. In this embodiment, the wiring 124 may be intersected and the In this example, a wiring 128 is provided for electrical connection. The potential variation of the wiring 124 in the imaging device 110 is reduced, the operation of the imaging device 100 is stabilized, and the imaging device 100 is imaged. This can improve the reliability of the device 100. Parasitic capacitance may also be used.

[0068] In addition, the functional elements and wiring (electrodes) constituting the pixel 111 are preferably made of the p-type semiconductor 221 and and / or on the n-type semiconductor 223, and do not overlap the i-type semiconductor 222 as much as possible. Specifically, the i-type semiconductor 222 and the functional element and The area where the wiring overlaps is preferably 35% or less of the area of ​​the i-type semiconductor 222 in a plan view. It is preferable that the ratio is set to 10% or less, more preferably 20% or less, and further preferably 10% or less. , the ratio of the area that can actually receive light to the entire area of ​​the i-type semiconductor 222 in a plan view ( The effective aperture ratio is preferably 65% ​​or more, more preferably 80% or more, and Preferably, the effective aperture ratio is set to 90% or more. By increasing the number of the pixels, the detection sensitivity of the imaging device 100 can be improved. The dynamic range can be increased.

[0069] 6 and 7 show examples of arranging a plurality of pixels 111 in a matrix. 1 is arranged in a matrix of 3 rows (n to n+2 rows) and 2 columns (m and m+1 columns). FIG. 7 is a circuit diagram corresponding to FIG. 6. In FIG. 6 and FIG. 7, m columns and m+ Here is an example of swapping the configuration of pixels 111 on one column (for example, odd and even columns) to create a mirror symmetry. It shows.

[0070] In addition, the wiring 128 in the nth row is electrically connected to the wiring 124 having a function of supplying a potential VPI. The wiring 128 in the (n+1)th row is connected to the wiring 122 having a function of supplying a potential VRS. In this manner, the wiring 122 or the wiring 128 is electrically connected to the By changing the wiring 124 at regular intervals, the potentials VPI and VRS in the pixel section 110 are The potential variation is reduced, the operation of the imaging device 100 is stabilized, and the reliability of the imaging device 100 is improved. It can be done.

[0071] FIG. 8 shows the photoelectric conversion elements 136 of the pixels 111 arranged in three rows (n to n+2 rows) and two columns (m and FIG. 1 is a plan view showing an example of a matrix arrangement of photoelectric conversion elements 136 (rows m and m+1). The semiconductor layer can be formed for each pixel 111 without being separated. A semiconductor layer is formed in the entire inside of 110, and the corresponding In the semiconductor layer, a p-type semiconductor 221, an n-type semiconductor 223, and an i-type semiconductor 222 are provided. In addition, the i-type semiconductor 222 and the p-type semiconductor 221 can be formed for each pixel. By surrounding the i-type semiconductor 222 with the light, electrical interference with the i-type semiconductor 222 of the adjacent pixel can be prevented. Since it is not necessary to separate the semiconductor layer constituting the photoelectric conversion element 136 for each pixel, 136 can be efficiently provided in the pixel 111. The degree can be increased.

[0072] The p-type semiconductor 221 may also be used as a part of the wiring for supplying power. The conductor 221 is used as a part of the wiring for supplying power, so that the power supply in the pixel section 110 The variation in the source potential can be reduced. may be used interchangeably.

[0073] [Color filters, etc.] The pixels 111 included in the imaging device 100 are used as sub-pixels, and each of the pixels 111 By providing filters (color filters) that transmit light of different wavelengths, a color image display can be It is possible to obtain information to realize the display.

[0074] FIG. 9E is a plan view showing an example of a pixel 111 for acquiring a color image. (E) is a pixel 111 (hereinafter, A color filter that transmits light in the green (G) wavelength range is provided. Pixel 111 (hereinafter also referred to as "pixel 111G") and a color pixel that transmits light in the blue (B) wavelength range The pixel 111 has a filter (hereinafter, also referred to as "pixel 111B"). The pixel 11R, pixel 111G, and pixel 111B are collectively made to function as one pixel 113.

[0075] The color filters used in the pixel 111 are not limited to red (R), green (G), and blue (B). First, as shown in FIG. 9(A), cyan (C), yellow (Y), and magenta (M) lights are used. A color filter that transmits light of three different wavelength ranges may be used. By providing pixels 111 that detect light, a full-color image can be obtained.

[0076] FIG. 9B shows color filters that transmit red (R), green (G), and blue (B) light, respectively. In addition to the pixel 111 provided with the color filter, a color filter that transmits yellow (Y) light is provided. FIG. 9(C) illustrates a pixel 113 having a pixel 111. The pixel 111 is provided with a color filter that transmits yellow (Y) and magenta (M) light. In addition, the pixel 111 has a color filter that transmits blue (B) light. 3 is an example of a pixel 111 that detects light of four different wavelength ranges in one pixel 113. By providing the above, the color reproducibility of the acquired image can be further improved.

[0077] In addition, for example, the pixel number ratio of the pixel 111R, the pixel 111G, and the pixel 111B (or the receiving The light area ratio does not necessarily have to be 1:1:1. The ratio (light receiving area ratio) of red:green:blue may be 1:2:1 in a Bayer array. The pixel number ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0078] Although the number of pixels 111 provided in the pixel 113 may be one, it is preferable that the number of pixels 111 is two or more. For example, By providing two or more pixels 111 that detect the same wavelength range, redundancy is increased, and the imaging device 10 This can increase the reliability of 0.

[0079] In addition, it acts as a filter by absorbing or reflecting light with wavelengths shorter than the wavelength of visible light, and by blocking infrared light. By using an IR (IR: Infrared) filter that transmits infrared light, infrared light is detected. The imaging device 100 can be realized. In addition, the filter can be used to detect wavelengths longer than the wavelength of visible light. UV (Ultra Viol) et) By using a filter, it is possible to realize an imaging device 100 that detects ultraviolet light. In addition, a scintillator that converts radiation into ultraviolet light or visible light is used as a filter. In this way, the imaging device 100 can function as a radiation detector for detecting X-rays, gamma rays, etc. can.

[0080] In addition, a neutral density (ND) filter is used as the filter 602. When a dark filter is used, a large amount of light enters the photoelectric conversion element (light receiving element). This can prevent the phenomenon of output saturation (hereinafter referred to as "output saturation") that sometimes occurs. By combining ND filters with different light reduction levels, the dynamic range of the imaging device can be improved. The range can be increased.

[0081] In addition to the above-mentioned filter, a lens may be provided in the pixel 113. An example of the arrangement of the pixel 113, the filter 602, and the lens 600 will be described with reference to a cross-sectional view. By providing the lens 600, the incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in FIG. 10A, a lens 600 and a filter 6 02 (filter 602R, filter 602G, filter 602B), and pixel driving circuit 1 12 or the like, light 660 can be made incident on the photoelectric conversion element 136.

[0082] However, as shown in the area surrounded by the two-dot chain line, a part of the light 660 indicated by the arrow is reflected by the wiring layer 604. Therefore, as shown in Fig. 10(B), the light is blocked by a part of the A lens 600 and a filter 602 are formed on the photoelectric conversion element 136 side to direct the incident light to the photoelectric conversion element. The light 660 may be received efficiently by the photoelectric conversion element 136. By making the incident light incident thereon, it is possible to provide an imaging device 100 with high detection sensitivity.

[0083] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0084] (Embodiment 2) In this embodiment, the imaging device 100 shown in the above embodiment is a type of solid-state imaging device. An example of a configuration using a CMOS image sensor will be described with reference to FIGS. 11 to 15. The pixel region 251 shown in FIG. 11 is a cross-sectional view of a part of the pixel 111 included in the imaging device 100. The peripheral circuit region 252 shown in FIG. 12A is an enlarged view of the transistor 134 shown in FIG. FIG. 12B shows an enlarged view of the capacitor 135 shown in FIG. An enlarged view of the transistor 281 is shown in FIG. An enlarged view of 282 is shown in FIG.

[0085] The imaging device 100 exemplified in this embodiment has an insulating layer 102 on a substrate 101. The photoelectric conversion element 136 having a pin-type junction formed thereon is provided on the substrate 102. As described above, the photoelectric conversion element 136 includes a p-type semiconductor 221, an i-type semiconductor 222, and an n-type semiconductor 223. The semiconductor 223 has a structure similar to that of the semiconductor 222 shown in FIG.

[0086] The substrate 101 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like. In addition, a plate, a semiconductor substrate, or the like that can withstand the processing temperature of this embodiment can be used. A plastic substrate having thermal resistance may be used. An example of such a substrate is a semiconductor substrate ( For example, single crystal substrate or silicon substrate), SOI (SOI: Silicon on Ins ulator) substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel Steel substrate, substrate with stainless steel foil, tungsten substrate, tungsten A substrate with a ten-foil is one example of a glass substrate, such as barium borosilicate glass. Examples of such glass include acid glass, aluminoborosilicate glass, and soda-lime glass.

[0087] After the photoelectric conversion element 136 and the pixel driving circuit 112 are formed, mechanical polishing and etching are performed. The substrate 101 may be removed by a bonding method or the like. When a material that can transmit the light to be detected is used, the light is incident on the photoelectric conversion element 136 from the substrate 101 side. It can be shot.

[0088] The insulating layer 102 may be made of aluminum oxide, magnesium oxide, silicon oxide, or silicon oxynitride. gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Oxide materials such as tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as silicon nitride Nitride materials such as silicon oxynitride, aluminum nitride, and aluminum oxynitride The insulating layer 102 can be formed as a single layer or a multilayer. It can be formed by using a D method, a thermal oxidation method, a coating method, a printing method, or the like.

[0089] The p-type semiconductor 221, the i-type semiconductor 222, and the n-type semiconductor 223 are formed, for example, by insulating After forming an island-shaped i-type semiconductor 222 on the layer 102, a mask is placed on the i-type semiconductor 222. The impurity element can be selectively introduced into a part of the i-type semiconductor 222. The introduction of the element can be performed by, for example, ion implantation or ion doping. After the impurity element is introduced, the mask is removed.

[0090] The p-type semiconductor 221, the i-type semiconductor 222, and the n-type semiconductor 223 are single crystal semiconductors, polycrystalline semiconductors, crystalline semiconductor, microcrystalline semiconductor, nanocrystalline semiconductor, semi-amorphous semiconductor, amorphous semiconductor For example, amorphous silicon or microcrystalline germanium can be used. Compound semiconductors such as silicon carbide and gallium arsenide can also be used. It is possible.

[0091] Materials for forming a p-type semiconductor 221, an i-type semiconductor 222, and an n-type semiconductor 223 When silicon is used as the p-type impurity element, for example, a group 13 element is used. As the n-type impurity element, for example, a Group 15 element can be used. do.

[0092] In addition, for example, when the semiconductor is formed of SOI, the insulating layer 102 is a BOX layer (BO X: Buried Oxide).

[0093] The imaging device 100 shown in this embodiment includes a p-type semiconductor 221, an i-type semiconductor 222, and The insulating layer 103 and the insulating layer 104 are disposed on the n-type semiconductor 223. The insulating layer 104 can be formed of the same material and by the same method as the insulating layer 102. Either the edge layer 103 or the insulating layer 104 may be omitted, or an insulating layer may be further laminated to form a Good too.

[0094] In addition, the imaging device 100 shown in this embodiment has an insulating layer having a flat surface on the insulating layer 104. The insulating layer 105 is formed using the same material and method as the insulating layer 102. The insulating layer 105 can be made of a low dielectric constant material (low-k material), siloxane, or the like. Alternatively, polysilicon resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. may be used. In addition, the surface of the insulating layer 105 is polished by chemical mechanical polishing (CMP). A chemical mechanical polishing (CMP) process may be performed. By performing CMP, the unevenness of the sample surface is reduced, and the insulating layer and conductive layer that will be formed later are easily removed. The coverage of the conductive layer can be improved.

[0095] In addition, an opening 224 is formed in the insulating layer 103 to the insulating layer 105 in a region overlapping with the p-type semiconductor 221. An opening 225 is formed in the insulating layer 103 to the insulating layer 105 in a region overlapping with the n-type semiconductor 223. In addition, a contact plug 106 is formed in the opening 224 and the opening 225. The contact plug 106 is formed by filling an opening in an insulating layer with a conductive material. The conductive material is, for example, tungsten, polysilicon, etc. A conductive material with high embedding properties can be used. The bottom surface is covered with a barrier layer (diffusion prevention layer) made of a titanium layer, a titanium nitride layer, or a laminate of these layers. In this case, the barrier film may also be called a contact plug. There is no particular restriction on the number or arrangement of the openings 224 and 225. This makes it possible to realize an imaging device with a high degree of freedom in layout.

[0096] In addition, a wiring 121 and a wiring 129 are formed on the insulating layer 105. The opening 224 is electrically connected to the p-type semiconductor 221 via the contact plug 106. The wiring 129 is connected to the contact plug 106 through the opening 225. It is electrically connected to the n-type semiconductor 223 via a gate electrode 224 .

[0097] In addition, an insulating layer 107 is formed to cover the wiring 121 and the wiring 129. The insulating layer 7 can be formed using the same material and method as the insulating layer 105. 7 The surface may be subjected to CMP treatment. By performing CMP treatment, the unevenness of the sample surface is reduced. This can reduce the amount of deposition of the insulating layer and the conductive layer formed thereafter, thereby improving the coverage of the insulating layer and the conductive layer formed thereafter.

[0098] The wiring 121 and the wiring 129 are made of aluminum, titanium, chromium, nickel, copper, or yttrium. lithium, zirconium, molybdenum, manganese, silver, tantalum, or tungsten The metal may be used as a single layer or a multilayer structure. For example, a single-layer structure of a copper film containing manganese, or an aluminum film stacked on a titanium film, Two-layer structure with a tungsten film on top of an aluminum film; two-layer structure with a copper-magnesium film on top of a tungsten film A two-layer structure in which a copper film is laminated on a titanium film. a two-layer structure in which a copper film is laminated on a tungsten film; a titanium film or a titanium nitride film; An aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further A three-layer structure in which a titanium film or titanium nitride film is formed on top of the molybdenum film or molybdenum nitride film A molybdenum film and an aluminum film or A three-layer structure in which a copper film is laminated and a molybdenum film or molybdenum nitride film is further formed on top of the copper film. A three-layer structure in which a copper film is laminated on a tungsten film, and a tungsten film is further formed on top of that. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, etc. A film of an element selected from the group consisting of aluminum, neodymium, and scandium, or an alloy film made by combining multiple elements. Alternatively, a nitride film may be used.

[0099] In addition, indium tin oxide, zinc oxide, indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium zinc oxide, indium with silicon oxide Conductive materials containing oxygen, such as aluminum tin oxide, and conductive materials containing nitrogen, such as titanium nitride and tantalum nitride. A conductive material may be used. In addition, the above-mentioned material containing a metal element and a conductive material containing oxygen may be used. Also, a laminated structure combining the above-mentioned material containing a metal element and It is also possible to use a laminated structure in which a conductive material containing nitrogen is combined. The product of a combination of a material containing an element, a conductive material containing oxygen, and a conductive material containing nitrogen It may also be a layered structure.

[0100] The transistor 134, the transistor 289, and the capacitor 135 are formed in the insulating layer 108 and the insulating It is formed on the insulating layer 107 via the edge layer 109. The transistor 131, the transistor 132, the transistor 133, etc. are also covered by the insulating layer 108 and the insulating It is formed on the insulating layer 107 via the insulating layer 109. The transistor 134 and the transistor 289 are exemplified as transistors having a top gate structure. However, a bottom gate transistor may be used. The same is true for GENISTA.

[0101] In addition, the transistor may be an inverted staggered transistor or a forward staggered transistor. It is also possible to use a gate electrode. It is also possible to use a dual-gate transistor with a structure in which the transistor is sandwiched between two gates. The present invention is not limited to a transistor having a double-gate structure, but may be applied to a multi-gate transistor having multiple channel formation regions. Alternatively, the transistor may be a gate type transistor, for example a double gate type transistor.

[0102] In addition, the above transistors are available in planar, FIN, and TRI-GATE types. It is possible to use transistors of various configurations, such as tri-gate type and tri-gate type.

[0103] The transistors may have the same structure or different structures. The size of the transistor (e.g., channel length and channel width) may be All of the transistors in the imaging device 100 can be adjusted as needed. If the transistors have the same structure, they can be manufactured simultaneously in the same process. do.

[0104] The transistor 134 has an electrode 243 that can function as a gate electrode and a source electrode 2, an electrode 244 that can function as either a source or drain electrode; The other electrode 245 can function as the drain electrode, and the other electrode 246 can function as the gate insulating layer. The semiconductor layer 242 may include an insulating layer 117 that may be formed on a semiconductor substrate.

[0105] In FIG. 11, the transistor 134 is An electrode 245 that can function as one electrode of the capacitor 135 is provided. Both are formed using the electrode 245. However, one embodiment of the present invention is not limited to this. an electrode serving as the other of the source electrode and the drain electrode of the transistor 134; The electrodes that can function as one electrode of the capacitor 135 are different electrodes. It may be formed using.

[0106] The capacitor 135 has an electrode that can function as one electrode of the capacitor 135. 245 and an electrode 273 that can function as the other electrode are disposed between an insulating layer 277 and a semiconductor The electrode 273 is formed at the same time as the electrode 243. In addition, the insulating layer 277 and the semiconductor layer 272c can function as a dielectric. The insulating layer 277 can be formed at the same time as the insulating layer 177. The insulating layer 277 and the semiconductor layer 242c can be formed at the same time. One of the conductor layers 272c may be omitted.

[0107] The insulating layer 108 prevents the diffusion of impurities such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. It is preferable to form the insulating film using an insulating film having a function of preventing the formation of the oxide film. Silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples of such oxides include yttrium oxide, aluminum oxide, and aluminum oxide nitride. As insulating films, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, and oxide By using aluminum or the like, impurities diffusing from the photoelectric conversion element 136 side are prevented from The insulating layer 108 can be prevented from reaching the surface 242 by sputtering. The insulating layer 108 can be formed by a method such as a CVD method, a vapor deposition method, or a thermal oxidation method. These materials can be used in a single layer or in a laminated form.

[0108] The insulating layer 109 can be formed of the same material and by the same method as the insulating layer 102. When an oxide semiconductor is used as the conductor layer 242, the insulating layer 108 is required to have a stoichiometric composition. It is preferable to form the insulating layer by using an insulating layer containing more oxygen than oxygen. When an insulating layer contains more oxygen than the oxygen that fills it, some of the oxygen is released by heating. Insulating layers that contain more oxygen than meets the theoretical composition are In the TDS analysis, which is performed at a temperature of 00°C or less, preferably 100°C to 500°C , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0×10 20 atoms / cm 3 The insulating layer is as described above.

[0109] In addition, an insulating layer that contains more oxygen than the stoichiometric composition is The treatment of adding oxygen can be carried out under an oxygen atmosphere. Heat treatment, ion implantation equipment, ion doping equipment, or plasma processing equipment is used. The gas for adding oxygen is: 16 O 2 or 18 O 2 Acids such as The gas may be, for example, nitrogen gas, nitrous oxide gas, or ozone gas. The process of adding oxygen is also called "oxygen doping process."

[0110] The semiconductor layers of the transistor 134, the transistor 289, and the like are formed of a single crystal semiconductor or a polycrystalline semiconductor. , microcrystalline semiconductors, nanocrystalline semiconductors, semi-amorphous semiconductors, amorphous semiconductors, etc. For example, amorphous silicon, microcrystalline germanium, etc. can be used. In addition, silicon carbide, gallium arsenide, oxide semiconductors, nitride semiconductors, etc. Compound semiconductors, organic semiconductors, etc. can be used.

[0111] In this embodiment, an example in which an oxide semiconductor is used as the semiconductor layer 242 will be described. In the present embodiment, the semiconductor layer 242 is divided into a semiconductor layer 242a, a semiconductor layer 242b, and a A case where a semiconductor layer 242c and a semiconductor layer 242b are laminated will be described.

[0112] The semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are made of In or Ga. It is formed from a material containing one or both of them. Typically, In-Ga oxide (In and Ga) is used. In-Zn oxide (oxide containing In and Zn), In-M-Zn oxide ( An oxide containing In, element M, and Zn. Element M is Al, Ti, Ga, Y, Zr, La, One or more elements selected from Ce, Nd, or Hf that have stronger bonding strength with oxygen than In. It is a rare metal element.

[0113] The semiconductor layer 242a and the semiconductor layer 242c are formed by removing the metal elements constituting the semiconductor layer 242b. In particular, it is preferable that the material is made of a material containing one or more kinds of the same metal element. When the material is used, the interface between the semiconductor layer 242a and the semiconductor layer 242b and the semiconductor layer This can prevent the occurrence of interface states at the interface between the semiconductor layer 242c and the semiconductor layer 242b. This makes it difficult for carriers to be scattered or captured at the interface, and the field effect mobility of the transistor is improved. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. It becomes.

[0114] The thickness of the semiconductor layer 242a and the semiconductor layer 242c is preferably 3 nm or more and 100 nm or less. The thickness of the semiconductor layer 242b is set to be 3 nm or more and 50 nm or less. 0 nm or less, preferably 3 nm to 100 nm, and more preferably 3 nm to 50 nm m or less.

[0115] The semiconductor layer 242b is an In-M-Zn oxide, and the semiconductor layer 242a and the semiconductor When the layer 242c is also an In-M-Zn oxide, the semiconductor layer 242a and the semiconductor layer 242 c = In:M:Zn=x 1 :y 1 :z 1 [Atomic ratio], semiconductor layer 242b is In:M:Z n=x 2 :y 2 :z 2 [Atomic ratio], y 1 / x 1 y 2 / x 2 is greater than The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b are selected so as to For more information, see y 1 / x 1 y 2 / x 2 The semiconductor layer 242a is 1.5 times larger than the , semiconductor layer 242c, and semiconductor layer 242b. More preferably, y 1 / x 1 y 2 / x 2 The semiconductor layer 242a, the semiconductor layer 242c, and the semiconductor layer 242b. More preferably, y 1 / x 1 y 2 / x 2 More than 3 The semiconductor layers 242a, 242c, and 242b are formed so that the At this time, in the semiconductor layer 242b, y 1 x 1 If the transistor This is preferable because it can provide stable electrical properties to y 1 x 1 When it becomes more than three times , the field effect mobility of the transistor is reduced, so y 1 x 1 Less than three times the By configuring the semiconductor layer 242a and the semiconductor layer 242c as described above, The dielectric layer 242a and the semiconductor layer 242c are less susceptible to oxygen deficiency than the semiconductor layer 242b. It can be a layer.

[0116] When the semiconductor layer 242a and the semiconductor layer 242c are made of In-M-Zn oxide, I The content of n and element M is preferably less than 50 atomic % for In and less than 50 atomic % for M. mic% or more, more preferably In is less than 25 atomic% and the element M is 75 atomic% or more. When the semiconductor layer 242b is an In-M-Zn oxide, In and The content of element M is preferably 25 atomic % or more of In and 75 atomic % or more of element M. %, more preferably In is 34 atomic % or more and the element M is 66 atomic % or less. Less than.

[0117] For example, a semiconductor layer 242a containing In or Ga and a semiconductor layer 242c: In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, Or In-Ga-Zn oxide formed using a target with an atomic ratio of 1:9:6, etc. In-Ga oxide formed using a target with an atomic ratio of In:Ga=1:9 In addition, the semiconductor layer 242b may be made of In:Ga Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 atomic ratio The In-Ga-Zn oxide formed using a target can be used. The atomic ratios of the inorganic layer 242a and the semiconductor layer 242b are calculated by subtracting the above atomic ratios from the atomic ratios as an error. This includes a fluctuation of plus or minus 20%.

[0118] In order to provide a transistor using the semiconductor layer 242b with stable electrical characteristics, The impurities and oxygen vacancies in the semiconductor layer 242b are reduced to make the semiconductor layer 242b highly intrinsic. It is preferable that the oxide semiconductor layer be an oxide semiconductor layer that can be regarded as intrinsic or substantially intrinsic. The channel forming region in the semiconductor layer 242b is a semiconductor layer that can be regarded as intrinsic or substantially intrinsic. It is preferable to set the above.

[0119] Note that an oxide semiconductor layer that can be regarded as substantially intrinsic is an oxide semiconductor layer having a carrier density of , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 The term "oxide semiconductor layer" refers to an oxide semiconductor layer having a thickness of less than 100 nm.

[0120] [Energy band structure of oxide semiconductors] Here, the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 242c are stacked. The function and effect of the semiconductor layer 242 formed will be described with reference to the energy band structure shown in FIG. The explanation will be given using drawings. FIG. 13 shows the enlarged view of the area indicated by the dashed line C1-C2 in FIG. 12(A). FIG. 13 shows the energy band structure of the channel formation region of the transistor 134. The energy band structure is shown.

[0121] In Figure 13, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 are The insulating layer 109, the semiconductor layer 242a, the semiconductor layer 242b, the semiconductor layer 242c, and the insulating The energy of the conduction band minimum of layer 117 is shown.

[0122] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer ( It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) It can be measured using a VersaProbe.

[0123] The In-Ga target with an atomic ratio of In:Ga:Zn=1:3:2 was used. The energy gap of a-Zn oxide is about 3.5 eV and the electron affinity is about 4.5 eV. In addition, the In- The energy gap of Ga-Zn oxide is about 3.4 eV and the electron affinity is about 4.5 eV. In addition, the In was formed using a target with an atomic ratio of In:Ga:Zn=1:3:6. The energy gap of Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV. In addition, the I was formed using a target with an atomic ratio of In:Ga:Zn=1:6:2. The energy gap of n-Ga-Zn oxide is about 3.9 eV, and the electron affinity is about 4.3 eV. In addition, the film was formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of In-Ga-Zn oxide is about 3.5 eV, and the electron affinity is about 4.4 e V. In addition, a target with an atomic ratio of In:Ga:Zn=1:6:10 was used. The energy gap of the In-Ga-Zn oxide is about 3.5 eV and the electron affinity is about 4. The energy of the target is 5 eV. The atomic ratio of In:Ga:Zn is 1:1:1. The energy gap of the synthesized In-Ga-Zn oxide is about 3.2 eV, and the electron affinity is about 4 .7 eV. In addition, a target with an atomic ratio of In:Ga:Zn=3:1:2 was used. The energy gap of the formed In-Ga-Zn oxide is about 2.8 eV, and the electron affinity is about It is 5.0 eV.

[0124] Since the insulating layer 109 and the insulating layer 117 are insulators, Ec382 and Ec386 are Closer to the vacuum level (lower electron affinity) than 3a, Ec383b, and Ec383c .

[0125] Also, Ec383a is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0126] Also, Ec383c is closer to the vacuum level than Ec383b. is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0 .15eV or more and 2eV or less, 1eV or less, 0.5eV or less, or 0.4eV or less It is preferable that the level is close to an unoccupied level.

[0127] In addition, in the vicinity of the interface between the semiconductor layer 242a and the semiconductor layer 242b, and in the vicinity of the interface between the semiconductor layer 242b and the semiconductor layer 242a, In the vicinity of the interface with the semiconductor layer 242c, a mixed region is formed, so that the energy of the conduction band minimum That is, at these interfaces, the levels are almost nonexistent or nonexistent. stomach.

[0128] Therefore, in the stacked structure having the above energy band structure, the electrons Therefore, the interface between the semiconductor layer 242a and the insulating layer 107, Or, even if a level exists at the interface between the semiconductor layer 242c and the insulating layer 117, the level In addition, the boundary between the semiconductor layer 242a and the semiconductor layer 242b is There is almost no level at the interface between the semiconductor layer 242c and the semiconductor layer 242b. Therefore, the movement of electrons in the region is not hindered. The transistor 134 having a stacked conductor structure can achieve high field effect mobility. Cut.

[0129] As shown in FIG. 13, the interface between the semiconductor layer 242a and the insulating layer 109 and the semiconductor layer 2 In the vicinity of the interface between 42c and the insulating layer 117, a trap level 390 due to impurities and defects is formed. However, the semiconductor layer 242a and the semiconductor layer 242c are provided to form a semiconductor This can keep the layer 242b away from the trap level.

[0130] In particular, in the transistor 134 illustrated in this embodiment, the upper surface and the side surface of the semiconductor layer 242b are The lower surface of the semiconductor layer 242b is in contact with the semiconductor layer 242a. In this manner, the semiconductor layer 242b is covered with the semiconductor layer 242a and the semiconductor layer 242c. By forming the gate insulating film in this manner, the influence of the trap order can be further reduced.

[0131] However, if the energy difference between Ec383a or Ec383c and Ec383b is small, In this case, electrons in the semiconductor layer 242b may exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating layer, The threshold voltage of the transistor is shifted in the positive direction.

[0132] Therefore, the energy difference between Ec383a and Ec383c and Ec383b is When each of these is set to 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage of the transistor is Since the voltage fluctuation is reduced and the electrical characteristics of the transistor can be improved, I wish.

[0133] The band gaps of the semiconductor layer 242a and the semiconductor layer 242c are It is preferable that the band gap is wider than that of b.

[0134] According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be provided. Therefore, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a semiconductor device with excellent performance can be realized.

[0135] In addition, the band gap of oxide semiconductors is 2 eV or more, so A transistor that uses an oxide semiconductor for a semiconductor layer can have an extremely small off-state current. Specifically, the off-current per 1 μm of channel width is 1×10 -20 A less than 1×10 -22 A, more preferably less than 1×10 -24 Less than A That is, the on / off ratio can be set to 20 digits or more and 150 digits or less.

[0136] According to one embodiment of the present invention, a transistor with low power consumption can be realized. As a result, an imaging device or semiconductor device with low power consumption can be realized.

[0137] In addition, a transistor that uses an oxide semiconductor for the semiconductor layer (also called an OS transistor) Since the off-state current of the transistor 133 is extremely low, the transistor 134 is an OS transistor. By using a resistor, the capacitance element 135 can be made smaller. Instead of providing the capacitance element 35, the parasitic capacitance of a transistor or the like can be used instead of the capacitance element 135. Therefore, the light receiving area of ​​the photoelectric conversion element 136 can be increased.

[0138] According to one embodiment of the present invention, an imaging device or a semiconductor device with high light-receiving sensitivity can be realized. According to one embodiment of the present invention, an imaging device or a semiconductor device having a wide dynamic range can be realized. It can be realized.

[0139] In addition, since an oxide semiconductor has a wide band gap, a semiconductor device using an oxide semiconductor is not available. According to one aspect of the present invention, an imaging device having a wide operating temperature range is provided. and a semiconductor device.

[0140] The above-mentioned three-layer structure is an example. For example, the semiconductor layer 242a or the semiconductor layer 242c Alternatively, a two-layer structure in which one of the layers is not formed may be used.

[0141] [Oxide semiconductors] Here, an oxide semiconductor film that can be used for the semiconductor layer 242 will be described in detail.

[0142] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0143] First, we will explain the CAAC-OS film.

[0144] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0145] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0146] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0147] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0148] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, InGaZnO 4 CAAC-OS film with crystals In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal of From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0149] In addition, InGaZnO 4 Out-of-plane synthesis of CAAC-OS films with crystallites In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0150] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0151] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0152] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0153] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0154] Next, a microcrystalline oxide semiconductor film will be described.

[0155] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0156] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0157] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0158] Next, the amorphous oxide semiconductor film will be described.

[0159] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0160] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0161] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0162] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0163] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0164] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO 4 The crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. 4 Crystal unit cell of The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aZnO 4 This corresponds to the ab plane of the crystal.

[0165] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0166] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the [number ratio], single crystal InGaZnO having a rhombohedral crystal structure 4 The density of is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0167] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0168] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0169] By the way, even if the oxide semiconductor film is a CAAC-OS film, it is possible to partially form an nc-OS film. Therefore, the CAAC-OS film is considered to have a good diffraction pattern. The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (C It can be expressed as the AAC conversion rate. For example, a good quality CAAC-OS In the case of a membrane, the CAAC content is 50% or more, preferably 80% or more, and more preferably 90% or more. 0% or more, and more preferably 95% or more. The area where the CAAC pattern is observed is referred to as the non-CAAC rate.

[0170] The oxide semiconductor applicable to the semiconductor layer 242a, the semiconductor layer 242b, and the semiconductor layer 108c An example of the oxide is an oxide containing indium. When indium is contained, the carrier mobility (electron mobility) increases. In addition, oxide semiconductors have the following properties: It is preferable to include the element M. The element M is preferably aluminum, gallium, yttrium, or the like. Other elements that can be used for element M include boron, silicon, and Titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, Lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, there are cases where the element M may be a combination of multiple of the above elements. The element M is, for example, an element that has a high bond energy with oxygen. The oxide semiconductor is an element that has the function of increasing the energy gap of the oxide. It is preferable that the oxide contains zinc. When the oxide contains zinc, for example, the oxide is easily crystallized. .

[0171] However, the oxide semiconductor is not limited to an oxide containing indium. For example, zinc tin oxide, gallium tin oxide, and gallium oxide may be used.

[0172] In addition, oxide semiconductors are made of oxides with a large energy gap. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more. It is set to 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0173] The effect of impurities in an oxide semiconductor will be described below. In order to stabilize the electrical characteristics of the oxide semiconductor, it is necessary to reduce the impurity concentration in the oxide semiconductor and to achieve a low carrier density. It is effective to increase the carrier density of oxide semiconductors by 1× 10 17 pieces / cm 3 Less than 1×10 15 pieces / cm 3 Less than or equal to 1 × 10 13 pieces / cm 3 In order to reduce the impurity concentration in the oxide semiconductor, the impurity concentration in the adjacent film is It is preferable to also reduce the intensity.

[0174] For example, silicon in an oxide semiconductor can become a carrier trap or a carrier generation source. Therefore, the silicon concentration in the oxide semiconductor is measured by secondary ion mass spectrometry (SIMS). Secondary Ion Mass Spectrometry (1×1 0 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, more Preferably 2 x 10 18atoms / cm 3 Less than.

[0175] Furthermore, when hydrogen is contained in an oxide semiconductor, the carrier density may be increased. The hydrogen concentration of the oxide semiconductor was 2×10 20 atoms / cm 3 below, Preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atom s / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 The following applies. Also, When nitrogen is contained in an oxide semiconductor, the carrier density may increase. The nitrogen concentration of the semiconductor is 5×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0176] In order to reduce the hydrogen concentration in the oxide semiconductor, the insulating layer 109 in contact with the semiconductor layer 242 is It is preferable to reduce the hydrogen concentration in the insulating layer 109 and the insulating layer 117. The hydrogen concentration in the sample was 2×10 20 atoms / cm 3 Less than or equal to 5x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below , and more preferably 5 × 10 18atoms / cm 3 In addition, the oxide semiconductor In order to reduce the nitrogen concentration, it is preferable to reduce the nitrogen concentration in the insulating layer 109 and the insulating layer 117. The nitrogen concentration of the insulating layer 109 and the insulating layer 117 is preferably 5×10 1 9 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferred: Or 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0177] In this embodiment, first, a semiconductor layer 242a is formed on an insulating layer 109, and then the semiconductor layer 242 A semiconductor layer 242b is formed on the substrate 242a.

[0178] Note that the oxide semiconductor layer is preferably formed by a sputtering method. The sputtering methods include RF sputtering, DC sputtering, and AC sputtering. The DC sputtering method or the AC sputtering method can be used. It is possible to form a film with better uniformity than the F sputtering method.

[0179] In the present embodiment, the semiconductor layer 242a is formed using an In-Ga-Zn oxide target (In :Ga:Zn=1:3:2) was used to deposit a 20 nm thick In-Ga The semiconductor layer 242a is formed of a-Zn oxide. The constituent elements and composition applicable to the semiconductor layer 242a are This is not limited to the above.

[0180] In addition, oxygen doping treatment may be performed after the semiconductor layer 242a is formed.

[0181] Next, the semiconductor layer 242b is formed on the semiconductor layer 242a. As the layer 242b, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 ) to form a 30 nm thick In-Ga-Zn oxide film by sputtering. However, the constituent elements and compositions applicable to the semiconductor layer 242b are not limited to those described above. stomach.

[0182] In addition, an oxygen doping treatment may be performed after the semiconductor layer 242b is formed.

[0183] Next, impurities such as moisture or hydrogen contained in the semiconductor layers 242a and 242b are removed. In order to further reduce the amount of fluorine and to highly purify the semiconductor layers 242a and 242b, A heat treatment may be carried out.

[0184] For example, the method may be carried out under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry atmosphere. Dry air (measured using a CRDS (cavity ring down laser spectroscopy) type dew point meter The moisture content when the air is cooled should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less. The semiconductor layer 242a and the semiconductor layer 242b are exposed to a fluorine-containing gas (preferably air) atmosphere of 10 ppb or less. The oxidizing atmosphere is an oxidizing atmosphere such as oxygen, ozone, or nitrogen oxide. An inert atmosphere is an atmosphere containing 10 ppm or more of oxidizing gases. This refers to an atmosphere in which the gas concentration is less than 10 ppm and which is filled with nitrogen or a rare gas.

[0185] In addition, by performing a heat treatment, the oxygen contained in the insulating layer 109 is removed at the same time as the impurities are released. The semiconductor layer 242a and the semiconductor layer 242b are diffused. It is possible to reduce the oxygen deficiency of 242b. In addition, after heat treatment in an inert gas atmosphere, Heat treatment is performed in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. Note that the heat treatment may be performed at any time after the formation of the semiconductor layer 242b. For example, heat treatment may be performed after selective etching of the semiconductor layer 242b.

[0186] The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. The treatment time should be within 24 hours. Heat treatment for more than 24 hours will lead to a decrease in productivity. Therefore, it is not desirable.

[0187] Next, a resist mask is formed on the semiconductor layer 242b. The insulating layer 242a and the semiconductor layer 242b are selectively etched. A part of 109 may be etched, forming a protrusion on insulating layer 109.

[0188] The semiconductor layer 242a and the semiconductor layer 242b can be etched by a dry etching method or a wafer etching method. After etching is completed, the resist mask is removed. Remove.

[0189] The transistor 134 is provided on the semiconductor layer 242b and in contact with a part of the semiconductor layer 242b. , electrodes 244 and 245. Electrodes 244 and 245 (the same layer The other electrodes or wirings formed by the wiring 121 are formed by the same material and method as the wiring 121. It is possible.

[0190] The transistor 134 has a semiconductor layer 242b, an electrode 244, and an electrode 245. The semiconductor layer 242c includes a semiconductor layer 242b, an electrode 244, and a conductor layer 242c. It contacts a portion of each of the electrodes 245 .

[0191] In this embodiment, the semiconductor layer 242c is grown using an In-Ga-Zn oxide target (In:Ga The semiconductor layer 24 is formed by a sputtering method using a metal oxide film (Zn:Zn=1:3:2). The constituent elements and compositions applicable to 2c are not limited to those described above. For example, a semiconductor layer Gallium oxide may be used as the semiconductor layer 242c. may be carried out.

[0192] The transistor 241 further includes an insulating layer 117 over the semiconductor layer 242c. The insulating layer 117 can function as a gate insulating layer. The insulating layer 117 may be formed by performing oxygen doping treatment. good.

[0193] After the semiconductor layer 242c and the insulating layer 117 are formed, a mask is formed on the insulating layer 117, and the semiconductor layer 242c is The insulating layer 242c and a portion of the insulating layer 117 are selectively etched to form an island-shaped semiconductor layer 24 2c, and the insulating layer 117 may be an island-shaped layer.

[0194] The transistor 134 also has an electrode 243 on the insulating layer 117. The wiring 121 and the other electrodes or wirings (including other electrodes or wirings formed in the same layer) are made of the same material and The method can be formed by the method.

[0195] In this embodiment, an example in which the electrode 243 is a laminate of the electrodes 243a and 243b is shown. For example, the electrode 243a is made of tantalum nitride, and the electrode 243b is made of copper. 243a acts as a barrier layer to prevent the diffusion of copper elements. Therefore, a high-performance semiconductor device can be realized.

[0196] The transistor 241 further includes an insulating layer 118 that covers the electrode 243. The insulating layer 118 can be formed using the same material and method as the insulating layer 102. An elemental doping process may be performed, and a CMP process may be performed on the surface of the insulating layer 118.

[0197] Further, an insulating layer 119 is provided over the insulating layer 118. The insulating layer 119 has the same structure as the insulating layer 105. The insulating layer 119 can be formed by performing a CMP process on the surface of the insulating layer 119. By performing CMP, the unevenness of the sample surface is reduced, and the insulating film formed later is In addition, the insulating layer 119 and the insulating layer 118 can be formed by applying a heat treatment to the insulating layer 119 and the conductive layer. An opening is formed in the portion, and a contact plug is formed in the opening.

[0198] In addition, on the insulating layer 119, a wiring 127 and a wiring 144 (formed in the same layer as these) are provided. The wiring 144 is formed on the insulating layer 119 and the insulating layer In the opening provided in 118, the electrode 273 is electrically connected via a contact plug. The wiring 127 is provided in an opening in the insulating layer 119 and the insulating layer 118. The semiconductor layer 242 is electrically connected to the electrode 243 via a contact plug.

[0199] In addition, the imaging device 100 includes a wiring 127 and a wiring 144 (which are formed in the same layer as these wirings). The insulating layer 115 covers the insulating layer 10. The insulating layer 115 may be formed of the same material and by the same method as those for the insulating layer 115. By performing CMP, the unevenness of the sample surface is reduced, and the subsequent formation In addition, the insulating layer 115 can be provided with an opening, which can improve the coverage of the insulating layer and the conductive layer. is formed.

[0200] In addition, on the insulating layer 115, the wiring 122, the wiring 123, and the wiring 266 (the same layer as these) are formed. In addition, other electrodes or wirings formed by the above-mentioned method are formed.

[0201] In addition, the wiring 122, the wiring 123, and the wiring 266 (other electrodes formed in the same layer as these) Each of the insulating layers includes an opening and a contact plug. It can be electrically connected to wiring or electrodes in other layers via the insulating film.

[0202] In addition, an insulating layer 116 is provided to cover the wiring 122, the wiring 123, and the wiring 266. The insulating layer 116 can be formed using the same material and method as the insulating layer 105. The surface 116 may be subjected to CMP processing.

[0203] As an example of a transistor constituting a peripheral circuit, the transistor 281 shown in FIG. A larger cross-sectional view is shown in FIG. 14A. Also, an enlarged cross-sectional view of the transistor 282 shown in FIG. 14B. In this embodiment, as an example, the transistor 281 is a p-channel When transistor 281 is an n-channel transistor, I will explain this in more detail.

[0204] The transistor 281 includes an i-type semiconductor 283 in which a channel is formed, a p-type semiconductor 285, and an insulator. The i-type semiconductor 283 has an edge layer 286, an electrode 287, and a sidewall 288. A low concentration p-type impurity region 284 is provided in the region overlapping with the

[0205] The i-type semiconductor 283 of the transistor 281 is the same as the i-type semiconductor of the photoelectric conversion element 136. The transistor 281 can be formed at the same time as the body 222. The p-type semiconductor 285 is formed simultaneously with the p-type semiconductor 221 of the photoelectric conversion element 136 in the same process. It can be formed.

[0206] The insulating layer 286 can function as a gate insulating layer, and the electrode 287 can function as a gate electrode. The low concentration p-type impurity region 284 is formed by forming an electrode 287 and before forming a side wall 288. It can be formed by introducing an impurity element using the pole 287 as a mask. That is, the low concentration p-type impurity region 284 can be formed by a self-alignment method. The low-concentration p-type impurity region 284 has the same conductivity type as the p-type semiconductor 285. The concentration of impurities provided thereto is less than that of the p-type semiconductor 285 .

[0207] The transistor 282 has a similar configuration to the transistor 281, but has a low concentration p-type impurity region. Instead of the region 284 and the p-type semiconductor 285, a low concentration n-type impurity region 294 and an n-type semiconductor 295 are The difference is that

[0208] The n-type semiconductor 295 of the transistor 282 is the n-type The transistor 281 and the semiconductor 223 can be formed at the same time in the same process. Similarly, the low concentration n-type impurity region 294 can be formed in a self-aligned manner. The low-concentration n-type impurity region 294 has the same conductivity type as the n-type semiconductor 295 and imparts the conductivity type. The concentration of impurities is less than that of the n-type semiconductor 295 .

[0209] In addition, various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the present specification and the like are formed by sputtering. It can be formed by the ring method or plasma CVD method, but other methods such as thermal CV It may be formed by a Chemical Vapor Deposition (D) method. As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition) is apor deposition method and ALD (Atomic Layer Deposition) method ition) method may also be used.

[0210] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0211] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the pressure inside the chamber is raised to atmospheric pressure. The film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing them on the substrate. This is also possible.

[0212] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. Suitable for making thin FETs (Field Effect Transistors). is.

[0213] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga In the case of forming a -Zn-O film, trimethylindium, trimethylgallium, and dimethyl Methyl zinc is used. The chemical formula for trimethylindium is In(CH 3 ) 3 is The chemical formula for trimethylgallium is Ga(CH 3 ) 3 Also, dimethyl zinc The chemical formula is Zn(CH 3 ) 2 In addition, the combination is not limited to these, and may be any combination. Instead of triethylgallium, triethylgallium (chemical formula Ga(C 2 H 5 ) 3 ) can also be used. Dimethyl zinc can be replaced by diethyl zinc (chemical formula Zn(C 2 H 5 ) 2 ) can also be used. can.

[0214] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and A liquid containing a hafnium precursor compound (hafnium alkoxide solution, typically tetrakis The raw material gas was vaporized with trimethylsilyl dimethylamide hafnium (TDMAH) as an oxidizing agent. Zon (O 3 Two types of gases are used: tetrakisdimethylamidohafnium The formula is Hf[N(CH 3 ) 2 ] 4 Other liquid materials include tetrakis(ethoxy) (dimethylamido) hafnium.

[0215] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (e.g., trimethylaluminum (TMA)) The raw gas is oxidized and H 2 Two types of gases are used: trimethylammonia, trimethylphenylacetone, and trimethylphenylacetone. The chemical formula for aluminum is Al(CH 3 ) 3 Other liquid materials include Tris(diisopropyl alcohol, Methylamido)aluminum, triisobutylaluminum, aluminum tris(2, 2,6,6-tetramethyl-3,5-heptanedionate).

[0216] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O 2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0217] For example, when forming a tungsten film using a deposition system that uses ALD, the WF 6 G S and B 2 H 6 The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF 6 Gas and H 2 The gases are introduced repeatedly in sequence to form a tungsten film. 2 H 6 gas Instead of SiH 4 A gas may also be used.

[0218] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH 3 ) 3 Gas and O 3 Gases were introduced repeatedly in sequence to O layer, and then Ga(CH 3 ) 3 Gas and O 3 The gases were repeatedly introduced in sequence to form GaO layer, and then Zn(CH 3 ) 2 Gas and O 3 The gas was introduced repeatedly in sequence to form ZnO The order of these layers is not limited to this example. By forming mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers, It is okay to do so. 3 H obtained by bubbling an inert gas such as Ar through water instead of gas 2 O gas may be used, but it should be O gas that does not contain H. 3 It is preferable to use gas. CH 3 ) 3 Instead of gas, In(C2 H 5 ) 3 Gas may also be used. 3 ) 3 Instead of gas, Ga(C 2 H 5 ) 3 Gas may also be used. 3 ) 3 G Instead of In(C 2 H 5 ) 3 Gas may also be used. 3 ) 2 Use gas It's fine if you're there.

[0219] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0220] (Embodiment 3) The peripheral circuits and pixel circuits include OR circuits, AND circuits, NAND circuits, and NOR circuits. Logic circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits, integrator circuits, differentiation Circuits, memory elements, and the like can be provided as appropriate.

[0221] In this embodiment, a semiconductor device used for a peripheral circuit and a pixel circuit will be described with reference to FIGS. An example of a CMOS circuit that can be used is shown in FIG. 15(A) to FIG. 15(E). In the circuit diagram, an oxide semiconductor is used as the transistor in order to clearly show that the transistor is formed using an oxide semiconductor. The circuit symbol for a transistor using solid semiconductors is marked with "OS."

[0222] The CMOS circuit shown in FIG. 15A includes a p-channel transistor 281 and an n-channel transistor The transistors 282 are connected in series and the gates of the transistors are connected together. 2 shows an example of the configuration of an inverter circuit.

[0223] The CMOS circuit shown in FIG. 15B includes a p-channel transistor 281 and an n-channel The transistors 282 are connected in parallel to form a so-called analog switch circuit. is.

[0224] The circuit shown in FIG. 15C is a source or drain of an n-channel transistor 289. One of the electrodes is connected to the gate of a p-channel transistor and one of the electrodes of a capacitor 257. The circuit shown in FIG. 15(D) is a configuration example of a so-called memory element. One of the source and drain of an n-channel transistor 289 is connected to the capacitor 257. 1 shows an example of the configuration of a so-called memory element connected to one electrode.

[0225] The circuits shown in FIG. 15(C) and FIG. 15(D) are the source or drain of the transistor 289. The charge input from the other input can be held at node 256. By using a transistor using an oxide semiconductor as the first transistor, the device can be used for a long period of time. The transistor 281 can hold a charge of 6. A transistor including an oxide semiconductor in a semiconductor layer may be used.

[0226] The circuit shown in FIG. 15(E) shows a configuration example of a photosensor. The source or the drain of the transistor 292 is formed using an oxide semiconductor in a semiconductor layer in which a channel is formed. One of the drains is electrically connected to the photodiode 291, and the other of the drains is connected to the source of the transistor 292. The other of the source and drain is electrically connected to the gate of transistor 293 through node 254. A transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed. 292 can make the off current extremely small, so the off current is determined according to the amount of light received. Therefore, the potential of the node 254 is unlikely to fluctuate. In addition, an imaging device with high linearity can be realized.

[0227] In addition, the peripheral circuits include a shift register circuit 1800 and a buffer circuit 19 shown in FIG. 00 may be provided in the peripheral circuit. A register circuit 1810, a buffer circuit 1910, and an analog switch circuit 2100 are combined. Each vertical output line 2110 is connected to an analog switch circuit 2100. The analog switch circuit 2100 outputs an output signal to an output line 2200. The shift register circuit 1810 and the buffer circuit 1910 enable sequential selection.

[0228] In the circuit diagram shown in the above embodiment, the wiring 137 (OUT) is An integrating circuit as shown in FIG. 17(B) or FIG. 17(C) may be connected. This increases the signal-to-noise ratio of the readout signal, making it possible to detect weaker light. That is, the sensitivity of the imaging device can be increased.

[0229] FIG. 17(A) shows an integrator circuit using an operational amplifier circuit (also called an OP amp). The inverting input terminal of the amplifier circuit is connected to the wiring 137 via a resistor R. The non-inverting input terminal is connected to the ground potential. The output terminal of the operational amplifier is connected to the The input terminal is connected to the inverting input terminal of the operational amplifier circuit.

[0230] FIG. 17B shows an integrating circuit using an operational amplifier circuit having a different configuration from that shown in FIG. 17A. The inverting input terminal of the operational amplifier circuit is connected to the wiring 137 (OUT The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the path is connected to the inverting input terminal of the operational amplifier circuit via a capacitive element C2.

[0231] FIG. 17(C) shows a configuration of an operational amplifier circuit different from that shown in FIG. 17(A) and FIG. 17(B). The non-inverting input terminal of the operational amplifier is connected to the wiring 137 via a resistor R. The inverting input terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier. The resistor R and the capacitor C constitute a CR integrator circuit. This forms a uniformity gain buffer.

[0232] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0233] (Embodiment 4) In this embodiment mode, the transistor can be used in place of any of the transistors described in the above embodiment modes. Examples of the structure of a transistor that can achieve this will be described with reference to FIGS.

[0234] [Bottom-gate transistor] The transistor 410 illustrated in FIG. 18A1 is a type of bottom-gate transistor. The transistor 410 is a channel protection transistor having an insulating layer 109. The semiconductor device has an electrode 246 that can function as a gate electrode. Also, an insulating layer 117 is formed on the electrode 246. The electrode 246 is formed of the same material and by the same method as the wiring 121. It is possible.

[0235] In addition, the transistor 410 includes a channel protection layer on the channel formation region of the semiconductor layer 242. The insulating layer 209 can function as a heat sink. The insulating layer 209 can be made of the same material as the insulating layer 117. A part of the electrode 244 and a part of the electrode 249 can be formed by the following method. It is formed on an insulating layer 209 .

[0236] By providing an insulating layer 209 on the channel formation region, the electrodes 244 and 249 are formed. Therefore, the electrode 244 and the electrode 245 can be prevented from being exposed. This can prevent the semiconductor layer 242 from becoming thin during the formation of the insulating film 49. A transistor with good electrical characteristics can be realized.

[0237] The transistor 411 shown in FIG. 18A2 has a back gate electrode over the insulating layer 118. The transistor 410 differs from the transistor 410 in that it has a functioning electrode 213. The electrode 213 is a wiring It can be formed using the same materials and methods as 121.

[0238] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the back gate electrode may be set to the GND potential or any other potential. By changing the gate electrode independently, the threshold voltage of the transistor can be changed. It can be made into a.

[0239] Both the electrode 246 and the electrode 213 can function as a gate electrode. The insulating layer 117, the insulating layer 209, and the insulating layer 118 function as gate insulating layers. It is possible.

[0240] When one of the electrodes 246 and 213 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 411, the electrode 213 is When referring to a "gate electrode," the electrode 246 may be referred to as a "back gate electrode." When the electrode 213 is used as a "gate electrode", the transistor 411 is a top gate. In addition, the electrodes 246 and 213 can be considered as a type of transistor. One of them may be called the "first gate electrode" and the other the "second gate electrode." be.

[0241] By providing the electrode 246 and the electrode 213 with the semiconductor layer 242 interposed therebetween, 6 and the electrode 213 are set to the same potential, the region in which carriers flow in the semiconductor layer 242 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 411 increases, the field effect mobility also increases.

[0242] Therefore, the transistor 411 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 411 is determined for the required on-current. According to one aspect of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0243] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0244] In addition, the electrodes 246 and 213 each have a function of blocking an electric field from the outside. Therefore, the electric charges of the charged particles generated on the insulating layer 109 side or above the electrode 213 are transferred to the semiconductor layer 2. This does not affect the channel formation region of the gate 42. As a result, stress tests (e.g., negative Applying electric charge - GBT (Gate Bias-Temperature) stress test ) degradation is suppressed, and the on-current rise voltage at different drain voltages is This effect is achieved when the electrodes 246 and 213 are of the same potential. This occurs when the potentials are the same or different.

[0245] The BT stress test is a type of accelerated test that measures the transistor damage caused by long-term use. The change in the characteristics of the BT (i.e., aging) can be evaluated in a short time. The amount of change in the threshold voltage of a transistor before and after a stress test is used to check reliability. The smaller the change in threshold voltage before and after the BT stress test, the Therefore, it can be said that this is a highly reliable transistor.

[0246] In addition, the electrode 246 and the electrode 213 are provided, and the electrode 246 and the electrode 213 are set to the same potential. This reduces the amount of variation in threshold voltage. At the same time, the variation in electrical characteristics caused by the semiconductor device is reduced.

[0247] In addition, a transistor with a back gate electrode is called a +GBT, which applies a positive charge to the gate. The change in threshold voltage before and after the stress test was also observed for transistors without a back gate electrode. Smaller than Sta.

[0248] In addition, when light is incident from the back gate electrode side, the back gate electrode is made of a material having a light blocking property. By forming the semiconductor layer from a conductive film, light is prevented from entering the semiconductor layer from the back gate electrode side. This prevents the semiconductor layer from being photodegraded and the threshold voltage of the transistor is shifted. This can prevent deterioration of electrical characteristics such as the occurrence of

[0249] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0250] The transistor 420 illustrated in FIG. 18B1 is a bottom-gate transistor. The transistor 420 is a channel protection transistor having a structure similar to that of the transistor 41. 2. It has a structure similar to that of the semiconductor layer 242, except that the insulating layer 209 covers the semiconductor layer 242. In addition, a portion of the insulating layer 209 overlapping the semiconductor layer 242 is selectively removed to form an opening. At the opening, the semiconductor layer 242 and the electrode 244 are electrically connected. In the opening formed by selectively removing a part of the insulating layer 209 overlapping with the semiconductor layer 42, The insulating layer 209 overlaps with the channel forming region. The region can function as a channel protection layer.

[0251] The transistor 421 illustrated in FIG. 18B2 has a back gate electrode over the insulating layer 118. It differs from transistor 420 in that it has a functioning electrode 213 .

[0252] By providing the insulating layer 209, the semiconductor layer 2 generated during the formation of the electrode 244 and the electrode 249 is prevented from being damaged. Therefore, when the electrodes 244 and 249 are formed, the semiconductor 42 is prevented from being exposed. Thinning of the layer 242 can be prevented.

[0253] In addition, the transistors 420 and 421 are the same as the transistors 410 and The distance between the electrodes 244 and 246 and the distance between the electrodes 249 and 246 are larger than the distance between the electrodes 244 and 246. Therefore, the parasitic capacitance between the electrodes 244 and 246 is reduced. In addition, the parasitic capacitance between the electrode 249 and the electrode 246 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided.

[0254] [Top-gate transistor] The transistor 430 illustrated in FIG. 19A1 is a type of top-gate transistor. The transistor 430 has a semiconductor layer 242 on the insulating layer 109. 42 and the insulating layer 109, an electrode 244 in contact with a part of the semiconductor layer 242 and a semiconductor layer The semiconductor layer 242, the electrode 244, and the electrode 24 9 has an insulating layer 117 thereon, and an electrode 246 is provided on the insulating layer 117 .

[0255] The transistor 430 is connected to the electrodes 246 and 244, and to the electrodes 246 and 246. Since the electrodes 246 and 244 do not overlap, the parasitic capacitance between the electrodes 246 and 244 and the The parasitic capacitance between the electrode 246 and the electrode 249 can be reduced. After forming the semiconductor layer 242, the electrode 246 is used as a mask to introduce the impurity element 255 into the semiconductor layer 242. By introducing the impurity into the semiconductor layer 242, an impurity region is formed in a self-aligned manner in the semiconductor layer 242. According to one embodiment of the present invention, the electrical characteristics of the A good transistor can be realized.

[0256] The impurity element 255 is introduced by an ion implantation device, an ion doping device, or a plasma This can be done using a processing device.

[0257] The impurity element 255 is, for example, at least one of Group 13 elements or Group 15 elements. In addition, when an oxide semiconductor is used for the semiconductor layer 242, In this case, the impurity element 255 is at least one of a rare gas, hydrogen, and nitrogen. It is also possible to use elements.

[0258] The transistor 431 shown in FIG. 19A2 has an electrode 213 and an insulating layer 217. The transistor 431 is formed on the insulating layer 109. The electrode 213 is provided with an insulating layer 217 formed on the electrode 213. The electrode 213 can function as a back gate electrode. The insulating layer 217 can function as a gate insulating layer. and methods.

[0259] Like the transistor 411, the transistor 431 has a large on-state current relative to its area. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 31 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0260] The transistor 440 illustrated in FIG. 19B1 is a top-gate transistor. The transistor 440 is formed by forming the semiconductor layer 2 after forming the electrode 244 and the electrode 249. The transistor 430 is different from the transistor 430 in that the transistor 42 is formed. The transistor 441 has an electrode 213 and an insulating layer 217. In the transistor 440 and the transistor 441, a part of the semiconductor layer 242 A portion of the semiconductor layer 242 is formed on the electrode 244 , and another portion of the semiconductor layer 242 is formed on the electrode 249 .

[0261] Like the transistor 411, the transistor 441 has a large on-state current relative to the area it occupies. That is, for the required on-current, the transistor 4 According to one aspect of the present invention, the area occupied by the transistor 41 can be reduced. Therefore, according to one aspect of the present invention, a highly integrated semiconductor device can be manufactured. It is possible to realize a body device.

[0262] After forming the electrode 246, the transistor 440 and the transistor 441 are also connected to the electrode 24 6 as a mask to introduce an impurity element 255 into the semiconductor layer 242, According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the semiconductor substrate 242. A transistor with favorable electrical characteristics can be realized. This makes it possible to realize a highly integrated semiconductor device.

[0263] [s-channel transistor] In the transistor 450 illustrated in FIG. 20, the upper surface and side surfaces of the semiconductor layer 242b are FIG. 20A is a top view of the transistor 450. 20(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 20(A) (channel FIG. 20(C) is a cross-sectional view in the longitudinal direction. 4 is a cross-sectional view (cross-sectional view in the channel width direction) of the portion.

[0264] By providing the semiconductor layer 242b on the protruding portion provided on the insulating layer 109, the semiconductor layer 242 The side surface of the transistor 450 can be completely covered with the electrode 243. The semiconductor layer 242b can be electrically surrounded by the electric field of the electrode 243. In this way, the electric field of the conductive film electrically connects the semiconductor layer in which the channel is formed. The surrounding transistor structure is called the surrounded channel (s-channel A transistor with an s-channel structure is called a "s-channel" structure. It is also called an "s-channel transistor" or "s-channel transistor."

[0265] In the s-channel structure, a channel is formed in the entire semiconductor layer 242b (bulk). In the s-channel structure, the drain current of the transistor is increased. In addition, the electric field of the electrode 243 can be used to obtain a larger on-state current. As a result, the entire channel formation region formed in the semiconductor layer 242b can be depleted. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. It is possible.

[0266] In addition, by making the protrusion of the insulating layer 109 high and reducing the channel width, The n-nel structure can increase the on-current and reduce the off-current. In addition, when forming the semiconductor layer 242b, the exposed semiconductor layer 242a may be removed. In this case, the side surfaces of the semiconductor layer 242a and the semiconductor layer 242b may be aligned.

[0267] 21, a transistor 451 is provided below the semiconductor layer 242 with an insulating layer interposed therebetween. An electrode 213 may be provided. FIG. 21A is a top view of the transistor 451. 21(B) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 21(C) is a cross-sectional view of the area indicated by the dashed line Y1-Y2 in FIG. 21(A).

[0268] In addition, as in the case of a transistor 452 shown in FIG. 22, a layer 214 is provided above an electrode 243. FIG. 22A is a top view of the transistor 452. FIG. FIG. 22(C) is a cross-sectional view of the portion indicated by the dashed line X1-X2 in FIG. 4A is a cross-sectional view of the portion indicated by the dashed dotted line Y1-Y2 in FIG.

[0269] In FIG. 22, layer 214 is provided on insulating layer 119, but it may also be provided on insulating layer 118. By forming the layer 214 from a material having a light-shielding property, the characteristics of the transistor due to light irradiation can be improved. The layer 214 is made of at least the semiconductor layer 2. The above effect is enhanced by forming the semiconductor layer 242b larger than the semiconductor layer 242b and covering the semiconductor layer 242b with the layer 214. The layer 214 can be made of an organic material, an inorganic material, or a metal material. Also, if the layer 214 is made of a conductive material, a voltage can be applied to the layer 214. Alternatively, the capacitor may be in an electrically floating state.

[0270] In addition, the capacitor 135 described in the above embodiment is turned off when the transistor 134 is turned off. When this happens, the electrode 245 becomes floating and is easily affected by noise and other fluctuations in the surrounding potential. In other words, when the transistor 134 is turned off, the surrounding electric field such as noise is reduced. The effect of this may fluctuate the potential of electrode 245, which may function as node 152.

[0271] As shown in the cross-sectional view of FIG. 23, an electrode 212 is provided below an electrode 245 via an insulating layer. This makes it possible to suppress fluctuations in the potential of the electrode 245 that can function as the node 152. The electrode 212 can be formed using a material and method similar to those of the wiring 121 .

[0272] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0273] (Embodiment 5) In this embodiment, an example of an electronic device using an imaging device according to one embodiment of the present invention will be described. do.

[0274] Examples of electronic devices using an imaging device according to one embodiment of the present invention include display devices such as televisions and monitors, Lighting equipment, desktop or notebook personal computers, word processors The digital content is stored on a recording medium such as a DVD (Digital Versatile Disc). Image reproducing devices that reproduce still or moving images, portable CD players, radios, tape recorders, etc. Coders, headphone stereos, stereos, navigation systems, table clocks, wall-mounted clocks meters, cordless telephone handsets, transceivers, mobile phones, car phones, portable game consoles, tabs Laptop terminals, large game machines such as pachinko machines, calculators, personal digital assistants, electronic organizers, electronic books Books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, Microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, water heaters, electric fans , hair dryers, air conditioners, humidifiers, dehumidifiers and other air conditioning equipment, dishwashers, Dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA Storage freezers, flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines, Fax machines, printers, multi-function printers, automated teller machines (ATMs), vending machines In addition, emergency exit lights, traffic lights, conveyor belts, elevators, escalators, etc. data center, industrial robots, energy storage systems, energy leveling and storage for smart grids In addition, fuel-powered engines and non-aqueous secondary batteries are also used. Mobile objects propelled by electric motors using electric power are also included in the category of electronic devices. The above-mentioned moving body may be, for example, an electric vehicle (EV), a hybrid vehicle that combines an internal combustion engine and an electric motor, or a hybrid vehicle that combines an internal combustion engine and an electric motor. Hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), and their tires and wheels tracked vehicles, including electric-assist bicycles, motorbikes, motorcycles, Electric wheelchairs, golf carts, small or large boats, submarines, helicopters, aircraft, location shooting Examples include satellites, space probes, interplanetary probes, and spacecraft.

[0275] FIG. 24A shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2. The focal point of the lens 945 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0276] FIG. 24B shows a mobile phone. A housing 951 includes a display unit 952, a microphone 957, and a speaker. The device includes a display 954, a camera 959, an input / output terminal 956, and an operation button 955. The imaging device of one embodiment of the present invention can be used for 959.

[0277] FIG. 24C shows a digital camera, which includes a housing 921, a shutter button 922, and a microphone 9 23, a light emitting unit 927, a lens 925, etc. The imaging device according to the present invention may include an imaging device according to the present invention.

[0278] FIG. 24D shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0279] FIG. 24E shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel. The imaging device according to one embodiment of the present invention can be used for the laser 909.

[0280] FIG. 24F shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used for the camera 909.

[0281] Note that the electronic device is not limited to the above-described electronic devices as long as it includes the imaging device according to one embodiment of the present invention. Needless to say, this is not possible.

[0282] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0283] 100 Imaging device 101 Substrate 102 Insulating layer 103 Insulating layer 104 Insulating layer 105 Insulating layer 106 Contact plug 107 Insulating layer 108 Insulating layer 109 Insulating Layer 110 Pixel section 111 pixels 112 Pixel driving circuit 113 pixels 115 Insulating Layer 116 Insulating Layer 117 Insulating Layer 118 Insulating Layer 119 Insulating Layer 121 Wiring 122 Wiring 123 Wiring 124 Wiring 125 Wiring 126 Wiring 127 Wiring 128 Wiring 129 Wiring 131 Transistor 132 Transistor 133 Transistor 134 Transistor 135 Capacitive element 136 Photoelectric conversion element 137 Wiring 141 Wiring 142 Wiring 143 Wiring 144 Wiring 145 Wiring 151 nodes 152 nodes 177 Insulating Layer 205 Insulating layer 209 Insulating Layer 212 Electrode 213 Electrode 214 layers 217 Insulating Layer 221 p-type semiconductors 222 i-type semiconductor 223 n-type semiconductor 224 Aperture 225 Aperture 241 Transistor 242 Semiconductor layer 243 Electrode 244 electrode 245 Electrode 246 Electrode 249 Electrode 251 pixel area 252 Peripheral Circuit Area 254 nodes 255 Impurity elements 256 nodes 257 Capacitive element 260 circuits 261 Signal Processing Circuit 262 Column driver circuit 263 Output Circuit 264 circuits 266 Wiring 267 Wiring 268 Wiring 269 ​​Wiring 270 circuits 273 Electrode 277 Insulating Layer 280 circuits 281 Transistor 282 Transistor 283 i-type semiconductors 284 Low concentration p-type impurity region 285 p-type semiconductors 286 Insulating Layer 287 Electrode 288 Side wall 289 Transistor 290 circuits 291 Photodiode 292 Transistor 293 Transistor 294 Low concentration n-type impurity region 295 n-type semiconductors 382 Ec 386 Ec 390 Trap Levels 410 Transistor 411 Transistor 420 Transistor 421 Transistor 430 Transistor 431 Transistor 440 Transistor 441 Transistor 450 Transistors 451 Transistor 452 Transistor 600 Lens 602 Filter 604 Wiring layer 660 light 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 921 Case 922 Shutter button 923 Mike 925 Lens 927 Light emitting part 931 Case 932 Display section 933 Wristband 939 Camera 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera 1800 Shift register circuit 1810 Shift register circuit 1900 Buffer circuit 1910 Buffer circuit 2100 Analog Switch Circuit 2110 Vertical output line 2200 output line 108c Semiconductor layer 111B pixels 111G pixels 111R pixels 242a Semiconductor layer 242b Semiconductor layer 242c Semiconductor layer 243a electrode 243b Electrode 264a Comparator 264b counter circuit 272c Semiconductor layer 383a Ec 383b Ec 383c Ec 602B Filter 602G Filter 602R Filter

Claims

[Claim 1] a photoelectric conversion element, first to fourth transistors, a capacitor, and first to seventh wirings; The photoelectric conversion element has an n-type semiconductor and a p-type semiconductor, the first wiring is electrically connected to one of the n-type semiconductor and the p-type semiconductor; the other of the n-type semiconductor and the p-type semiconductor is electrically connected to one of the source and the drain of the first transistor; a gate of the first transistor is electrically connected to the second wiring; the other of the source and the drain of the first transistor is electrically connected to a first node; one of a source and a drain of the second transistor is electrically connected to the third wiring; the other of the source and the drain of the second transistor is electrically connected to the first node; a gate of the second transistor is electrically connected to the fourth wiring; one electrode of the capacitance element is electrically connected to the first node; the other electrode of the capacitance element is electrically connected to the first wiring; a gate of the third transistor electrically connected to the first node; one of a source and a drain of the third transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fourth transistor; the other of the source and the drain of the fourth transistor is electrically connected to the sixth wiring; a gate of the fourth transistor is electrically connected to the seventh wiring;

Images