Electronic component

Abstract

To provide an electronic component which can suppress generation of cracks in a ceramic element body.SOLUTION: A chip varistor includes: a ceramic element body; and a sintered metal layer arranged on the ceramic element body. The sintered metal layer includes: a region R1 including plural crystal grains CG1 made of a first metal; a region R2 in contact with the region R1, the region R2 including plural crystal grains CG2 made of a second metal different from the first metal; and a region R3 in contact with the region R2, the region R3 including a glass G1. For the presence ratio of the region G1 and the region R2, the area ratio of the region R1 to the region R2 is larger than 1. The sintered metal layer has a hole V1 in which the region R2 is exposed.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to an electronic component.

Background Art

[0002] Known electronic components include a plurality of ceramic bodies and a sintered metal layer disposed on the ceramic body (see, for example, Patent Document 1). The external electrode contains Ag.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an electronic component, stress may act on the ceramic body from the sintered metal layer. The stress acting on the ceramic body can cause cracks in the ceramic body. The occurrence of cracks may deteriorate the characteristics of the electronic component. A configuration for suppressing the occurrence of cracks in the ceramic body is desired.

[0005] One aspect of the present invention aims to provide an electronic component that suppresses the occurrence of cracks in a ceramic body.

Means for Solving the Problems

[0006] An electronic component according to one aspect of the present invention includes a ceramic body and a sintered metal layer disposed on the ceramic body. The sintered metal layer includes a first region containing a plurality of first crystal grains made of a first metal, and a second region that is in contact with the first region and contains a plurality of second crystal grains made of a second metal different from the first metal. The area ratio of the first region to the second region is greater than 1 with respect to the area ratio of the second region. In the sintered metal layer, pores are formed in which the second region is exposed.

[0007] In the above one aspect, the occupancy ratio of the first region to the second region is greater than 1 in terms of the area ratio of the first region to the second region. The plurality of second crystal grains included in the second region can be in contact with the first region so as to reduce the contact between the plurality of first crystal grains included in the first region having an area ratio larger than that of the second region. Vacancies are formed between the plurality of first crystal grains with reduced mutual contact. The vacancies relieve the stress acting on the ceramic body. Therefore, the above one aspect suppresses the generation of cracks in the ceramic body.

[0008] In the above one aspect, in the cross-section of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1. In the configuration where the area ratio of the first region to the second region in the cross-section of the sintered metal layer is greater than 1, in the above cross-section, the plurality of second crystal grains are more likely to be in contact with the plurality of first crystal grains, and the contact between the plurality of first crystal grains is further reduced. The vacancies formed between the plurality of first crystal grains further relieve the stress acting on the ceramic body. Therefore, this configuration surely suppresses the generation of cracks in the ceramic body.

[0009] In the above one aspect, in the cross-section of the sintered metal layer, the plurality of first crystal grains may have a particle size larger than that of the plurality of second crystal grains. In the configuration where the plurality of first crystal grains have a particle size larger than that of the plurality of second crystal grains in the cross-section of the sintered metal layer, in the above cross-section, the plurality of second crystal grains are likely to be located between the plurality of first crystal grains, and the contact between the plurality of first crystal grains is further reduced. The vacancies formed between the plurality of first crystal grains further relieve the stress acting on the ceramic body. Therefore, this configuration more surely suppresses the generation of cracks in the ceramic body.

[0010] In the above one aspect, in the surface of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1. In a configuration where the area ratio of the first region to the second region is greater than 1 on the surface of the sintered metal layer, on the said surface, a plurality of second crystal grains are more likely to be in contact with a plurality of first crystal grains, and the contact between the plurality of first crystal grains is further reduced. The pores formed between the plurality of first crystal grains further relieve the stress acting on the ceramic body. Therefore, this configuration surely suppresses the generation of cracks in the ceramic body.

[0011] In the above one aspect, on the surface of the sintered metal layer, the plurality of first crystal grains may have a particle size larger than that of the plurality of second crystal grains. In a configuration where the plurality of first crystal grains have a particle size larger than that of the plurality of second crystal grains on the surface of the sintered metal layer, on the said surface, the plurality of second crystal grains are likely to be located between the plurality of first crystal grains, and the contact between the plurality of first crystal grains is further reduced. The pores formed between the plurality of first crystal grains further relieve the stress acting on the ceramic body. Therefore, this configuration more surely suppresses the generation of cracks in the ceramic body.

[0012] In the above one aspect, the sintered metal layer may include a third region that is in contact with the second region and contains glass. The glass contained in the third region may be in contact with the second region and exist between the plurality of first crystal grains with reduced mutual contact. The glass contained in the third region may be in contact with the second region and exist between the plurality of first crystal grains with reduced mutual contact. The denseness of the sintered metal layer is improved. Therefore, this configuration suppresses the characteristic deterioration of the electronic component.

[0013] In the above one aspect, the grain boundary between the first crystal grain and the second crystal grain may include a region where no alloy of the first metal and the second metal exists. In a region where there is no alloy of the first metal and the second metal, the first metal and the second metal exist independently of each other. In a configuration including a region where there is no alloy of the first metal and the second metal, a plurality of second crystal grains are likely to be located between a plurality of first crystal grains, further reducing the contact between the plurality of first crystal grains. The voids formed between the plurality of first crystal grains further relieve the stress acting on the ceramic matrix. Therefore, this configuration more reliably suppresses the generation of cracks in the ceramic matrix.

[0014] In the above one aspect, the second metal may have a melting point higher than that of the first metal. In a configuration where the second metal has a melting point higher than that of the first metal, the second metal is more likely to maintain a solid state than the first metal. A plurality of second crystal grains further reduce the contact between the plurality of first crystal grains. The voids formed between the plurality of first crystal grains further relieve the stress acting on the ceramic matrix. Therefore, this configuration more reliably suppresses the generation of cracks in the ceramic matrix.

[0015] In the above one aspect, the second metal may have an ionization tendency greater than that of the first metal. In a configuration where the second metal has an ionization tendency greater than that of the first metal, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. A plurality of second crystal grains further reduce the contact between the plurality of first crystal grains. The voids formed between the plurality of first crystal grains further relieve the stress acting on the ceramic matrix. Therefore, this configuration more reliably suppresses the generation of cracks in the ceramic matrix.

[0016] In the above one aspect, the ceramic matrix may include a semiconductor ceramic material.

Advantages of the Invention

[0017] One aspect of the present invention provides an electronic component that suppresses the generation of cracks in a ceramic matrix.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Mode for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted.

[0020] With reference to FIGS. 1 to 7, the configuration of the chip varistor T1 according to the present embodiment will be described. FIG. 1 is a perspective view showing the chip varistor according to the present embodiment. FIGS. 2 and 3 are figures showing a cross-sectional configuration of the chip varistor according to the present embodiment. FIGS. 4 and 5 are figures showing a cross-sectional configuration of a sintered metal layer. FIGS. 6 and 7 are figures showing a surface configuration of a sintered metal layer. In the present embodiment, the electronic component is, for example, the chip varistor T1. Hereinafter, the configuration of the chip varistor T1 according to the present embodiment will be described.

[0021] As shown in FIGS. 1 to 3, the chip varistor T1 includes a ceramic body 3, internal electrodes 5, and external electrodes 7. The ceramic body 3 has, for example, a rectangular parallelepiped shape. In this specification, the rectangular parallelepiped shape includes a shape of a rectangular parallelepiped with chamfered corners and edges, or a shape of a rectangular parallelepiped with rounded corners and edges. The internal electrodes 5 are disposed within the ceramic body 3. The external electrodes 7 are disposed on the ceramic body 3. In FIG. 1, the illustration of the internal electrodes 5 is omitted.

[0022] The ceramic body 3 includes a pair of side surfaces 3a facing each other, a pair of side surfaces 3c facing each other, and a pair of side surfaces 3e facing each other. Each of the side surfaces 3a, 3b, 3c, 3e has a rectangular shape. In this specification, the rectangular shape includes, for example, a shape with chamfered corners or a shape with rounded corners. The pair of side surfaces 3a face each other in the first direction D1. The pair of side surfaces 3c face each other in the second direction D2. The side surfaces 3e face each other in the third direction D3. The first direction D1 intersects the second direction D2 and also intersects the third direction D3. The second direction D2 intersects, for example, the third direction D3. For example, the first direction D1, the second direction D2, and the third direction D3 are orthogonal to each other. The side surface 3a is orthogonal to the first direction D1. The side surface 3c is orthogonal to the second direction D2. The side surface 3e is orthogonal to the third direction D3. The side surface 3e extends in the first direction D1 so as to connect the pair of side surfaces 3a. The side surface 3e extends in the second direction D2 so as to connect the pair of side surfaces 3c. The side surface 3a extends in the third direction D3 so as to connect the pair of side surfaces 3e. The side surface 3c extends in the third direction D3 so as to connect the pair of side surfaces 3e.

[0023] The chip varistor T1 is, for example, soldered and mounted on an electronic device. The electronic device includes, for example, a circuit board or another electronic component. In the chip varistor T1, one of the four side surfaces 3a, 3c faces the electronic device. One of the four side surfaces 3a, 3c is arranged to form a mounting surface. One of the four side surfaces 3a, 3c is the mounting surface.

[0024] The ceramic element 3 includes a laminated structure in which a plurality of ceramic layers are laminated. The lamination direction of the plurality of ceramic layers coincides with the first direction D1. Each ceramic layer includes a sintered body that exhibits varistor characteristics. The ceramic element 3 includes, for example, a semiconductor ceramic material. In the actual ceramic element 3, each ceramic layer is integrated to such an extent that the boundary between each ceramic layer cannot be visually recognized. The ceramic element 3 includes a varistor element. The ceramic element 3 mainly contains ZnO (zinc oxide). As secondary components, the ceramic element 3 includes, for example, Co, rare earth metal elements (for example, Pr), group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkaline earth metal elements (Mg, Ca, Sr, Ba) in the form of simple metals. The ceramic element 3 may include oxides of the above simple metals as secondary components. In the present embodiment, the ceramic element 3 includes Co, Pr, Cr, Ca, K, and Al as secondary components. When the total content of all the materials constituting the ceramic element 3 is 100% by weight, the content of ZnO is, for example, 99.8 to 69.0% by weight. The content of the rare earth metal element (Pr) in the ceramic element 3 is, for example, about 0.01 to 10 atomic %. The rare earth metal element can exhibit varistor characteristics.

[0025] The chip varistor T1 includes a coating layer 9. The coating layer 9 is disposed on the outer surface of the ceramic element 3, that is, on a pair of side surfaces 3a, a pair of side surfaces 3c, and a pair of side surfaces 3e. The coating layer 9 covers the outer surface of the ceramic element 3. In the present embodiment, the coating layer 9 covers substantially the entire outer surface of the ceramic element 3. The coating layer 9 is disposed directly on the outer surface of the ceramic element 3, for example. The coating layer 9 includes a glass material. The thickness of the coating layer 9 is, for example, 0.01 to 10 μm. In the present embodiment, the thickness of the coating layer 9 is 0.1 μm. The glass material is, for example, SiO 2 -Al 2 O 3 -LiO 2It includes crystallized glass. The glass material may include amorphous glass. The chip varistor T1 may not include the coating layer 9.

[0026] The chip varistor T1 has, for example, a size of 0402 in JIS notation. The size of 0402 in JIS notation corresponds to the size of 01005 in EIA notation. In this case, the length of the ceramic body 3 in the first direction D1 is, for example, about 0.2 mm. The length of the ceramic body 3 in the second direction D2 is about 0.2 mm. The length of the ceramic body 3 in the third direction D3 is about 0.4 mm.

[0027] As shown in FIGS. 2 and 3, the chip varistor T1 includes a plurality of internal electrodes 5. In this embodiment, the chip varistor T1 includes a pair of internal electrodes 5. The internal electrodes 5 face each other in the first direction D1. The pair of internal electrodes 5 are arranged in the ceramic body 3. Each of the internal electrodes 5 faces the corresponding side surface 3a. Each of the internal electrodes 5 is connected to the corresponding external electrode 7. Each of the internal electrodes 5 is electrically and physically connected to the corresponding external electrode 7.

[0028] When viewed from the first direction D1, the pair of internal electrodes 5 includes a region where they overlap each other. The pair of internal electrodes 5 are spaced apart from each other in the first direction D1. Each of the internal electrodes 5 includes a pair of surfaces facing each other in the first direction D1. One of the pair of surfaces included in the internal electrode 5 faces the corresponding side surface 3a. The other of the pair of surfaces included in the internal electrode 5 faces the other internal electrode 5. Each of the pair of internal electrodes 5 includes an end portion exposed from the corresponding side surface 3e. The end portion included in each of the pair of internal electrodes 5 protrudes from the corresponding side surface 3e and penetrates the coating layer 9. The end portion included in each of the pair of internal electrodes 5 includes a portion exposed from the coating layer 9. The pair of internal electrodes 5 are located in the ceramic body 3 except for the above-mentioned end portions exposed from the coating layer 9.

[0029] Each of the pair of internal electrodes 5 has, for example, a rectangular shape when viewed in the first direction D1. In each of the pair of internal electrodes 5, for example, the length in the third direction D3 is greater than the length in the second direction D2. The sizes of each of the pair of internal electrodes 5 are substantially the same as each other. The thickness of the internal electrode 5 in the first direction D1 is, for example, 0.5 to 4.0 μm. The length of the internal electrode 5 in the second direction D2 is, for example, 100 μm. The length of the internal electrode 5 in the third direction D3 is, for example, 300 μm.

[0030] Each of the pair of internal electrodes 5 contains a noble metal or a noble metal alloy. The noble metal includes, for example, Ag, Pd, Au, or Pt. The noble metal alloy includes, for example, an Ag-Pd alloy. The internal electrode 5 may contain a base metal or a base metal alloy. The base metal includes, for example, Cu or Ni. The internal electrode 5 is an internal conductor disposed within the ceramic body 3 and includes a conductive material commonly used as an internal electrode of a multilayer electronic component. The conductive material includes, for example, a base metal. The conductive material includes, for example, Ni or Cu. The internal electrode 5 is configured as a sintered body of a conductive paste containing the above-described type of conductive material.

[0031] As shown in FIGS. 1 to 3, the chip varistor T1 includes a plurality of external electrodes 7. The chip varistor T1 includes, for example, a pair of external electrodes 7. The pair of external electrodes 7 are disposed on the ceramic body 3. The pair of external electrodes 7 are disposed on the outer surface of the ceramic body 3. The pair of external electrodes 7 are disposed, for example, at both ends of the ceramic body 3 in the third direction D3. The pair of external electrodes 7 face each other in the third direction D3 with the ceramic body 3 interposed therebetween. The pair of external electrodes 7 are spaced apart from each other in the third direction D3. The pair of external electrodes 7 are disposed, for example, on the coating layer 9. Each of the pair of external electrodes 7 is physically and electrically connected to the corresponding internal electrode 5 at the portion exposed from the coating layer 9 among the pair of internal electrodes 5. The coating layer 9 includes a portion covered by the pair of external electrodes 7 and a portion not covered by the pair of external electrodes 7.

[0032] Each of the pair of external electrodes 7 is disposed on the corresponding side surface among the pair of side surfaces 3e. The pair of external electrodes 7 are disposed, for example, on the side surface 3e and on a part of each of the four side surfaces 3a, 3c. The above-mentioned part of each of the side surfaces 3a, 3c is a partial region near the side surface 3e on each of the side surfaces 3a, 3c. In the present embodiment, each of the pair of external electrodes 7 covers the entire corresponding side surface 3e. The pair of external electrodes 7 cover the side surface 3e, the four surfaces of each of the side surfaces 3a, 3c, the corner portions formed by the side surface 3e and the four surfaces, and the ridge line portions connecting the corner portions to each other.

[0033] The external electrode 7 includes a sintered metal layer 7a. The sintered metal layer 7a is formed by applying a conductive paste onto the outer surface of the ceramic body 3 and baking it. The conductive paste includes a metal powder, a glass component, an organic binder, and an organic solvent. The sintered metal layer 7a is formed by sintering the metal component (metal powder) contained in the conductive paste. The sintered metal layer 7a includes a layer formed by sintering the metal powder contained in the conductive paste. The metal powder contained in the conductive paste includes a noble metal powder and a base metal powder. The noble metal includes Ag. The noble metal may include Au, Pt, or Pd. The base metal may include Cu or Ni. In the present embodiment, the sintered metal layer 7a includes Ag and Cu.

[0034] The external electrode 7 includes at least one plating layer on the sintered metal layer 7a. In the present embodiment, the external electrode 7 includes, for example, two plating layers 7b and 7c on the sintered metal layer 7a. The sintered metal layer 7a is a base layer for forming the plating layers 7b and 7b. The plating layer 7b is located between the sintered metal layer 7a and the plating layer 7c, and the plating layer 7b is located between the sintered metal layer 7a and the plating layer 7c. The plating layer 7b includes, for example, a Ni plating layer. Instead of the Ni plating layer, the plating layer 7b may include a Sn plating layer, a Cu plating layer, or an Au plating layer. The plating layer 7c includes a solder plating layer. The solder plating layer includes a Sn plating layer, a Sn-Ag alloy plating layer, a Sn-Bi alloy plating layer, or a Sn-Cu alloy plating layer. These plating layers are formed by a plating method. The plating method includes, for example, an electrolytic plating method. The external electrode 7 may include three plating layers on the sintered metal layer 7a. The thickness of the external electrode 7 is, for example, 10 to 30 μm.

[0035] FIG. 4 is a diagram showing the cross-sectional configuration of the sintered metal layer 7a. FIG. 5 is an enlarged view of a part of the cross-sectional configuration of the sintered metal layer 7a. FIGS. 4 and 5 are diagrams showing the cross-sectional configuration of the sintered metal layer 7a when cut by a plane parallel to the side surface 3c. The sintered metal layer 7a includes a region R1, a region R2 in contact with the region R1, and a region R3 in contact with the region R2. The region R1 includes a plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 is made of a first metal. The region R2 includes a plurality of crystal grains CG2. Each of the plurality of crystal grains CG2 is made of a second metal. The second metal is different from the first metal. In the present embodiment, the first metal includes Ag, and the second metal includes Cu. The crystal grain CG1 includes Ag particles, and the crystal grain CG2 includes Cu particles. The region R3 includes glass G1. The glass G1 includes, for example, SiO 2 or B 2 O 3 and includes. For example, when the region R1 includes a first region, the region R2 includes a second region, and the region R3 includes a third region. For example, when the crystal grain CG1 includes a first crystal grain, the crystal grain CG2 includes a second crystal grain.

[0036] In the cross-section of the sintered metal layer 7a, each of the plurality of crystal grains CG1 is in contact with and arranged adjacent to each other. Each of the plurality of crystal grains CG1 has a region where they are sintered to each other. The plurality of crystal grains CG2 include particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 include, for example, particles located between the plurality of crystal grains CG1 in a state of being in contact with and arranged adjacent to each other. The plurality of crystal grains CG2 include particles located along the grain boundaries formed by the plurality of crystal grains CG1. The plurality of crystal grains CG2 may include a plurality of particles arranged along the grain boundaries formed by the plurality of crystal grains CG1. The plurality of crystal grains CG2 may independently include particles located between the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0037] The cross-section of the sintered metal layer 7a includes the grain boundaries formed by the plurality of crystal grains CG1 and the grain boundaries formed by the plurality of crystal grains CG2. The grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where the alloy of the first metal and the second metal does not exist. In this region where the alloy does not exist, at the location where the crystal grain CG1 and the crystal grain CG2 are in direct contact with each other, the first metal and the second metal are not alloyed with each other. The second metal has an ionization tendency greater than that of the first metal. Therefore, Cu of the second metal reacts more easily with oxygen than Ag of the first metal. In the sintered metal layer 7a, Cu is more likely to exist as an oxide than Ag. In the present embodiment, the oxide of Cu includes, for example, CuО. In the cross-section of the sintered metal layer 7a, the area of the region R1 is larger than the area of the region R2. That is, in the cross-section, the area ratio of the region R1 to the region R2 is greater than 1. The area of the region R1 is the sum of the plurality of crystal grains CG1 exposed in the cross-section of the sintered metal layer 7a. The area of the region R2 is the sum of the plurality of crystal grains CG2 exposed in the cross-section of the sintered metal layer 7a. In the sintered metal layer 7a, the proportion of the existence of the region R1 and the region R2 is greater than 1 in terms of the area ratio of the region R1 to the region R2.

[0038] The area ratio of the regions R1 and R2 is obtained, for example, as follows. Obtain a cross-sectional photograph of the ceramic green body 3 at a position including the regions R1 and R2. The cross-sectional photograph is, for example, a photograph of a cross-section obtained by cutting the sintered metal layer 7a in a plane orthogonal to the thickness direction of the sintered metal layer 7a. The cross-section is, for example, parallel to the side surface 3c. The cross-sectional photograph may be, for example, a photograph of a cross-section of the sintered metal layer 7a when cut in a plane parallel to the side surface 3a or the side surface 3e. The cross-sectional photograph is, for example, an SEM (scanning electron microscope) photograph. The SEM photograph includes, for example, a compositional image photograph. To calculate the areas of the regions R1 and R2, software is used to perform image processing on the obtained cross-sectional photograph. Based on the result of this image processing, the boundaries of each crystal grain CG1 and each crystal grain CG2 are discriminated, and the area of each of the crystal grains CG1 and CG2 is calculated. The area of the region R1 is calculated as the product of the number of crystal grains CG1 included in the region R1 and the area of the crystal grain CG1 in the obtained cross-sectional photograph. The area of the region R2 is calculated as the product of the number of crystal grains CG2 included in the region R2 and the area of the crystal grain CG2 in the obtained cross-sectional photograph. The area ratio of the region R1 to the region R2 is obtained as the ratio of the area of the region R1 calculated above to the area of the region R2 calculated above.

[0039] Regarding the particle sizes of the crystal grains CG1 and CG2, for example, they are calculated as particle sizes converted to an equivalent circle diameter from the areas of the crystal grains CG1 and CG2 calculated above. In the present embodiment, the particle sizes of all the crystal grains CG1 included in the region R1 may be calculated, or the particle sizes of all the crystal grains CG2 included in the region R2 may be calculated. Among the crystal grains CG1 included in the region R1, the particle sizes of any number of crystal grains CG1 may be calculated, and among the crystal grains CG2 included in the region R2, the particle sizes of any number of crystal grains CG2 may be calculated. The arbitrary number is, for example, 50. In the cross-section of the sintered metal layer 7a, the plurality of crystal grains CG1 have a larger grain size than the plurality of crystal grains CG2. The grain size of the crystal grains CG1 is, for example, 0.4 to 3.6 μm. The grain size of the crystal grains CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the grain size of the crystal grains CG1 is larger than the minimum value of the grain size of the crystal grains CG2. The maximum value of the grain size of the crystal grains CG1 is larger than the maximum value of the grain size of the crystal grains CG2.

[0040] The sintered metal layer 7a contains glass G1. The glass G1 is contained in the region R3. The region R3 is formed between the plurality of crystal grains CG1 when the plurality of crystal grains CG1 are sintered together. For example, the glass component contained in the conductive paste for forming the sintered metal layer 7a softens when forming the sintered metal layer 7a and flows into at least a part between the plurality of crystal grains CG1. The glass component, for example, flows into at least a part between the plurality of crystal grains CG1. The above glass component, for example, fills a part between the plurality of crystal grains CG1. The glass solidified between the plurality of crystal grains CG1 constitutes the region R3. There is a second metal around the glass G1 contained in the region R3. Vacancies V1 are formed in the sintered metal layer 7a. The vacancies V1 are formed when forming the sintered metal layer 7a. The vacancies V1 exist between the plurality of crystal grains CG1. In the vacancies V1, the region R2 is exposed. In the vacancies V1, the second metal is exposed. The vacancies V1 are located between the plurality of crystal grains CG1 and the vacancies V1 are not filled with the glass G1.

[0041] FIG. 6 is a diagram showing the configuration of the surface of the sintered metal layer 7a. FIG. 7 is an enlarged view of a part of the configuration of the surface of the sintered metal layer 7a. FIGS. 6 and 7 illustrate the surface 7s of the sintered metal layer 7a viewed from the thickness direction of the sintered metal layer 7a. The thickness direction of the sintered metal layer 7a includes, for example, the third direction D3. In the present embodiment, the surface 7s of the sintered metal layer 7a has the same configuration as the cross-section of the sintered metal layer 7a illustrated in FIG. 4.

[0042] On the surface 7s of the sintered metal layer 7a, each of the plurality of crystal grains CG1 is in contact with and arranged adjacent to each other. Each of the plurality of crystal grains CG1 has a region where they are sintered to each other. The plurality of crystal grains CG2 include particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 include, for example, particles located between the plurality of crystal grains CG1 in a state of being in contact with and arranged adjacent to each other. The plurality of crystal grains CG2 include particles located along the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0043] The surface 7s of the sintered metal layer 7a includes the grain boundaries formed by the plurality of crystal grains CG1 and the grain boundaries formed by the plurality of crystal grains CG2. The grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where the alloy of the first metal and the second metal does not exist. In this region where the alloy does not exist, the first metal and the second metal are not alloyed with each other at the location where the crystal grain CG1 and the crystal grain CG2 are in direct contact with each other. On the surface 7s, the area of the region R1 is larger than the area of the region R2. That is, in the cross-section, the area ratio of the region R1 to the region R2 is larger than 1. The area of the region R1 is the sum of the plurality of crystal grains CG1 exposed on the surface 7s. The area of the region R2 is the sum of the plurality of crystal grains CG2 exposed on the surface 7s. On the surface 7s, the existence ratio of the region R1 and the region R2 is larger than 1 in terms of the area ratio of the region R1 to the region R2.

[0044] On the surface 7s of the sintered metal layer 7a, the area ratio of the regions R1 and R2 is obtained, for example, by the same procedure as in the case of the cross-section of the sintered metal layer 7a. That is, a surface photograph of the ceramic green body 3 is acquired at a position including the region R1 and the region R2. The surface photograph is, for example, a photograph of the surface 7s when viewed from the thickness direction of the sintered metal layer 7a. The surface 7s is, for example, parallel to the side surface 3e. The surface photograph may be a photograph of the surface 7s parallel to either of the side surfaces 3a and 3c. The surface photograph is, for example, an FE-SEM (field emission scanning electron microscope) photograph (for example, a secondary electron image photograph). Hereinafter, in the same manner as in the case of the cross section of the sintered metal layer 7a, the area ratio of the regions R1 and R2 is obtained.

[0045] Regarding the particle diameters of the crystal grains CG1 and CG2, for example, they are calculated as the particle diameters converted into equivalent circle diameters from the areas of the crystal grains CG1 and CG2 calculated above. On the surface 7s of the sintered metal layer 7a, the plurality of crystal grains CG1 have larger particle diameters than the plurality of crystal grains CG2. The particle diameter of the crystal grain CG1 is, for example, 0.4 to 3.6 μm. The particle diameter of the crystal grain CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the particle diameter of the crystal grain CG1 is larger than the minimum value of the particle diameter of the crystal grain CG2. The maximum value of the particle diameter of the crystal grain CG1 is larger than the maximum value of the particle diameter of the crystal grain CG2.

[0046] The surface 7s of the sintered metal layer 7a contains the glass G1. The region R3 is formed between the plurality of crystal grains CG1 that sinter with each other when the plurality of crystal grains CG1 forming the surface 7s of the sintered metal layer 7a sinter. For example, the glass component contained in the conductive paste forming the sintered metal layer 7a softens when forming the sintered metal layer 7a and flows into a part between the plurality of crystal grains CG1 located on the surface 7s. The glass component fills, for example, a part between the plurality of crystal grains CG1 located on the surface 7s. Vacancies V1 are formed on the surface 7s of the sintered metal layer 7a. The vacancies V1 are formed when forming the surface 7s of the sintered metal layer 7a. The vacancies V1 exist between the plurality of crystal grains CG1. The region R2 is exposed in the vacancies V1. The second metal is exposed in the vacancies V1.

[0047] The manufacturing method of the chip varistor T1 will be described. In this embodiment, first, a ceramic element 3 in which an internal electrode 5 is disposed inside is prepared. The process of preparing the ceramic element 3 is known in this technical field, and further detailed description thereof is omitted. After forming the ceramic element 3 in which the internal electrode 5 is disposed inside, an external electrode 7 is formed. In forming the external electrode 7, a conductive paste is applied to the side surface 1e of the ceramic element 3. In this embodiment, the conductive paste for the external electrode 7 contains Ag particles, Cu particles, a glass component, and an organic binder. In the conductive paste, the content of Ag particles is, for example, 65 to 80% by weight. The content of Cu particles is, for example, 1 to 4% by weight. The content of the glass component is, for example, 3 to 7% by weight. The glass component contains, for example, SiO 2 or B 2 O 3 . In the conductive paste, the particle size of Ag particles is, for example, 0.04 to 9.0 μm. The particle size of Cu particles is, for example, 0.15 to 0.7 μm.

[0048] Subsequently, in a firing furnace, the conductive paste is baked to form a sintered metal layer 7a. By the firing process, the conductive paste is baked and the sintered metal layer 7a is formed. The firing process of the conductive paste includes, for example, a first temperature rising process, a first heat retaining process, a second temperature rising process, a second heat retaining process, and a temperature lowering process. In the first heat retaining process after the first temperature rising process, the organic binder is removed. After the first heat retaining process, in the second temperature rising process, the glass is melted. After the glass starts to melt, the sintering of Ag starts. The temperature at which the sintering of Ag starts is higher than when the conductive paste does not contain Cu. At the temperature at which the sintering of Ag starts, Cu is difficult to melt and remains in a solid state. Cu has a melting point higher than the melting point of Ag. Cu reduces the contact between the first metals and delays the start of the sintering of Ag. For example, in the second temperature rising process, Cu forms an oxide.

[0049] A plurality of voids V1 are formed between the sintered Ag. Cu suppresses the contact between the plurality of Ag, and Cu is likely to be exposed in the plurality of voids V1. In the present embodiment, during the second heating process, the softened glass flows into the space between the plurality of Ag. Through the second heat preservation process and the cooling process, a sintered metal layer 7a is formed. The glass G1 that has flowed into the space between the plurality of Ag solidifies. In the present embodiment, subsequently, for example, plating layers 7b and 7c are formed on the sintered metal layer 7a by a wet plating method. The wet plating method includes an electrolytic plating method.

[0050] Through the above process, the chip varistor T1 is manufactured. In the present embodiment, the ceramic body 3 may be subjected to an annealing process. The ceramic body 3 may not be subjected to an annealing process. In the chip varistor T1, in the sintered metal layer 7a, the content of Ag particles is, for example, 88 to 94% by weight. The content of copper oxide particles is, for example, 2 to 4% by weight. The content of the glass is, for example, 4 to 8% by weight. Copper oxide contains, for example, CuО.

[0051] As described above, in the chip varistor T1, the ratio of the existence of the region R1 to the region R2 is greater than 1 in terms of the area ratio of the region R1 to the region R2. The plurality of crystal grains CG2 included in the region R2 can be in contact with the region R1 so as to reduce the contact between the plurality of crystal grains CG1 included in the region R1 having a larger area ratio than the region R2. Voids V1 are formed between the plurality of crystal grains CG1 with reduced mutual contact. The voids V1 relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 suppresses the generation of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is suppressed. The characteristics of the chip varistor T1 include, for example, electrical characteristics. In the present embodiment, the voids V1 can constitute a discharge path of the gas generated from the organic binder in the sintered metal layer 7a.

[0052] In the chip varistor T1, in the cross section of the sintered metal layer 7a, the area ratio of the region R1 to the region R2 is greater than 1. In the chip varistor T1, in the above cross section, a plurality of crystal grains CG2 are more likely to be in contact with a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 surely suppresses the occurrence of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is surely suppressed.

[0053] In the chip varistor T1, in the cross section of the sintered metal layer 7a, a plurality of crystal grains CG1 have a larger particle size than that of the plurality of crystal grains CG2. In the chip varistor T1, in the above cross section, a plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is more surely suppressed.

[0054] In the chip varistor T1, on the surface 7s of the sintered metal layer 7a, the area ratio of the region R1 to the region R2 is greater than 1. In the chip varistor T1, on the surface 7s, a plurality of crystal grains CG2 are more likely to be in contact with a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 surely suppresses the occurrence of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is surely suppressed.

[0055] In the chip varistor T1, on the surface 7s of the sintered metal layer 7a, a plurality of crystal grains CG1 have a larger particle size than that of the plurality of crystal grains CG2. In the chip varistor T1, on the surface 7s, among the plurality of crystal grains CG2, it is easy for them to be located between the plurality of crystal grains CG1, and the contact between the plurality of crystal grains CG1 is further reduced. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the generation of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is more surely suppressed.

[0056] In the above one aspect, the sintered metal layer 7a is in contact with the region R2 and includes the region R3 containing the glass G1. In the chip varistor T1, the glass G1 contained in the region R3 is in contact with the region R2 and can exist between the plurality of crystal grains CG1 with reduced mutual contact. The denseness of the sintered metal layer 7a is improved. Therefore, the characteristic deterioration of the chip varistor T1 is suppressed.

[0057] In the chip varistor T1, the grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where no alloy of the first metal and the second metal exists. In the region where no alloy of the first metal and the second metal exists, the first metal and the second metal exist independently of each other. In the chip varistor T1, among the plurality of crystal grains CG2, it is easy for them to be located between the plurality of crystal grains CG1, and the contact between the plurality of crystal grains CG1 is further reduced. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the generation of cracks in the ceramic body 3. The characteristic deterioration of the chip varistor T1 is more surely suppressed.

[0058] In the chip varistor T1, the second metal has a melting point higher than that of the first metal. In chip varistor T1, the second metal is more likely to maintain a solid state than the first metal. The plurality of crystal grains CG2 further reduces the contact between the plurality of crystal grains CG1. The pores V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The characteristic deterioration of chip varistor T1 is more surely suppressed.

[0059] In chip varistor T1, the second metal has an ionization tendency greater than that of the first metal. In chip varistor T1, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. The plurality of crystal grains CG1 further reduces the contact between the plurality of crystal grains CG1. The pores V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The characteristic deterioration of chip varistor T1 is more surely suppressed.

[0060] In chip varistor T1, for example, even when a plating layer is formed on the sintered metal layer 7a by a wet plating method, the glass G1 suppresses the inflow of moisture containing the plating solution into the sintered metal layer 7a. The glass G1 suppresses the moisture containing the plating solution from passing through the sintered metal layer 7a and reaching the interface between the sintered metal layer 7a and the ceramic body 3. The characteristic deterioration of chip varistor T1 is suppressed. In chip varistor T1, for example, even when a plating layer is formed on the sintered metal layer 7a by a wet plating method, the glass G1 suppresses the inflow of moisture containing the plating solution into the sintered metal layer 7a. The glass G1 suppresses the moisture containing the plating solution from passing through the sintered metal layer 7a and reaching the interface between the sintered metal layer 7a and the ceramic body 3. The characteristic deterioration of chip varistor T1 is suppressed.

[0061] As described above, the embodiments of the present invention have been explained. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications are possible without departing from the gist thereof.

[0062] The plurality of crystal grains CG1 may not have a particle size larger than that of the plurality of crystal grains CG2. In a configuration where the plurality of crystal grains CG1 have a particle size larger than that of the plurality of crystal grains CG2, as described above, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The grain boundary between the crystal grains CG1 and the crystal grains CG2 may not include a region where the alloy of the first metal and the second metal does not exist. In a configuration where the grain boundary between the crystal grains CG1 and the crystal grains CG2 includes a region where the alloy of the first metal and the second metal does not exist, as described above, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The second metal may not have a melting point higher than that of the first metal. In a configuration where the second metal has a melting point higher than that of the first metal, as described above, the second metal is more likely to maintain a solid state than the first metal. The plurality of crystal grains CG2 further reduce the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relieve the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more surely suppresses the occurrence of cracks in the ceramic body 3. The second metal does not necessarily have an ionization tendency greater than that of the first metal. In the configuration where the second metal has an ionization tendency greater than that of the first metal, as described above, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. The plurality of crystal grains CG1 further reduces the contact between the plurality of crystal grains CG1. The voids V1 formed between the plurality of crystal grains CG1 further relax the stress acting on the ceramic body 3. Therefore, the chip varistor T1 more reliably suppresses the occurrence of cracks in the ceramic body 3.

[0063] In the above-described embodiment, the chip varistor has been described as an example of an electronic component, but the applicable electronic components are not limited to chip varistors. Applicable electronic components are, for example, electronic components such as capacitors, inductors, piezoelectric actuators, thermistors, solid-state battery components, or composite components. The applicable electronic components may be multilayer electronic components.

[0064] As can be understood from the description of the above-described embodiment, this specification includes the disclosure of the following aspects. (Appendix 1) A ceramic body, A sintered metal layer disposed on the ceramic body, Comprising: The sintered metal layer, A first region including a plurality of first crystal grains made of a first metal, A second region that is in contact with the first region and includes a plurality of second crystal grains made of a second metal different from the first metal, The area ratio of the first region to the second region is greater than 1 in terms of the area ratio of the first region to the second region, An electronic component in which voids exposing the second region are formed in the sintered metal layer. (Appendix 2) In the cross-section of the sintered metal layer, the area ratio of the first region to the second region is greater than 1. The electronic component according to Appendix 1. (Appendix 3) In the cross section, the plurality of first crystal grains have a grain size larger than that of the plurality of second crystal grains. The electronic component according to Supplementary Note 2. (Supplementary Note 4) On the surface of the sintered metal layer, the area ratio of the first region to the second region is greater than 1. The electronic component according to Supplementary Note 1. (Supplementary Note 5) On the surface, the plurality of first crystal grains have a grain size larger than that of the plurality of second crystal grains. The electronic component according to Supplementary Note 4. (Supplementary Note 6) The sintered metal layer is in contact with the second region and includes a third region containing glass. The electronic component according to any one of Supplementary Notes 1 to 5. (Supplementary Note 7) The grain boundaries between the first crystal grains and the second crystal grains include regions where there is no alloy of the first metal and the second metal. The electronic component according to any one of Supplementary Notes 1 to 6. (Supplementary Note 8) The second metal has a melting point higher than that of the first metal. The electronic component according to any one of Supplementary Notes 1 to 7. (Supplementary Note 9) The second metal has an ionization tendency greater than that of the first metal. The electronic component according to any one of Supplementary Notes 1 to 8. (Supplementary Note 10) The ceramic body includes a semiconductor ceramic material. The electronic component according to any one of Supplementary Notes 1 to 9.

Explanation of Reference Numerals

[0065] 3... Ceramic body, 7a... Sintered metal layer, R1, R2, R3... Regions, CG1, CG2... Crystal grains, V1... Vacancies, T1... Chip varistor.

Claims

1. A ceramic body, A sintered metal layer disposed on the ceramic body, Comprising: The sintered metal layer, A first region including a plurality of first crystal grains made of a first metal, In contact with the first region and including a second region including a plurality of second crystal grains made of a second metal different from the first metal, The proportion of the existence of the first region and the second region is greater than 1 in terms of the area ratio of the first region to the second region, In the sintered metal layer, pores where the second region is exposed are formed, an electronic component.

2. In the cross section of the sintered metal layer, the area ratio of the first region to the second region is greater than 1, the electronic component according to Claim 1.

3. In the cross section, the plurality of first crystal grains have a larger particle size than the particle size of the plurality of second crystal grains, the electronic component according to Claim 2.

4. On the surface of the sintered metal layer, the area ratio of the first region to the second region is greater than 1, the electronic component according to Claim 1.

5. On the surface, the plurality of first crystal grains have a larger particle size than the particle size of the plurality of second crystal grains, the electronic component according to Claim 4.

6. The sintered metal layer is in contact with the second region and includes a third region including glass, the electronic component according to Claim 1.

7. The grain boundary between the first crystal grains and the second crystal grains includes a region where no alloy of the first metal and the second metal exists, the electronic component according to Claim 1 or 2.

8. The second metal has a melting point higher than the melting point of the first metal, the electronic component according to Claim 1.

9. The second metal has an ionization tendency greater than the ionization tendency of the first metal, the electronic component according to Claim 1.

10. The ceramic body includes a semiconductor ceramic material, the electronic component according to Claim 1.

Images