Electronic component

Abstract

To provide an electronic component which suppresses degradation of properties.SOLUTION: A chip varistor includes: a ceramic element body; and a sintered metal layer arranged on the ceramic element body. The sintered metal layer includes: a region R1 including plural crystal grains CG1 made of a first metal; a region R2 in contact with the region R1, the region R2 including plural crystal grains CG2 made of a second metal different from the first metal; and a region R3 in contact with the region R2, the region R3 including a glass G1. For the presence ratio of the region G1 and the region R2, the area ratio of the region R1 to the region R2 is larger than 1.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to electronic components.

Background Art

[0002] Known electronic components include a plurality of ceramic bodies and a sintered metal layer disposed on the ceramic bodies (see, for example, Patent Document 1). The external electrodes contain Ag.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In electronic components, there is a risk that characteristics may deteriorate due to the ingress of moisture. Electronic components may include a plating layer outside the sintered metal layer. The plating layer is formed, for example, by a wet plating method. When the plating solution used in the wet plating method reaches the ceramic body, there is a risk that the characteristics of the electronic component may deteriorate. Not only the plating solution but also moisture present in the external environment of the electronic component may ingress into the electronic component.

[0005] One aspect of the present invention aims to provide an electronic component that suppresses characteristic deterioration.

Means for Solving the Problems

[0006] An electronic component according to one aspect of the present invention includes a ceramic body and a sintered metal layer disposed on the ceramic body. The sintered metal layer includes a first region containing a plurality of first crystal grains made of a first metal, a second region that is in contact with the first region and contains a plurality of second crystal grains made of a second metal different from the first metal, and a third region that is in contact with the second region and contains glass. The area ratio of the first region to the second region is greater than 1.

[0007] In the above aspect, the area ratio of the first region to the second region is greater than 1. The plurality of second crystal grains included in the second region are likely to be in contact with the plurality of first crystal grains included in the first region having a larger area ratio than the second region. The plurality of second crystal grains reduce the contact between the plurality of first crystal grains. The glass included in the third region is in contact with the second region and may exist between the plurality of first crystal grains with reduced mutual contact. The density of the sintered metal layer is improved. Therefore, the above aspect suppresses the deterioration of the characteristics of the electronic component.

[0008] In the above aspect, in the cross-section of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1. In the configuration where the area ratio of the first region to the second region in the cross-section of the sintered metal layer is greater than 1, in the above cross-section, the plurality of second crystal grains are more likely to be in contact with the plurality of first crystal grains, and the contact between the plurality of first crystal grains is further reduced. The glass included in the third region is in contact with the second region and may further exist between the plurality of first crystal grains with reduced mutual contact. The density of the sintered metal layer is further improved. Therefore, this configuration surely suppresses the deterioration of the characteristics of the electronic component.

[0009] In the above aspect, in the cross-section of the sintered metal layer, the plurality of first crystal grains may have a larger particle size than the particle size of the plurality of second crystal grains. In a configuration where, in the cross-section of the sintered metal layer, a plurality of first crystal grains have a larger particle size than that of a plurality of second crystal grains, in the above cross-section, the plurality of second crystal grains are likely to be located between the plurality of first crystal grains, further reducing the contact between the plurality of first crystal grains. The glass contained in the third region is in contact with the second region and can further exist between the plurality of first crystal grains with reduced mutual contact. The denseness of the sintered metal layer is further improved. Therefore, this configuration more reliably suppresses the characteristic deterioration of the electronic component.

[0010] In the above one aspect, on the surface of the sintered metal layer, the area ratio of the first region to the second region may be greater than 1. In a configuration where, on the surface of the sintered metal layer, the area ratio of the first region to the second region is greater than 1, on the above surface, the plurality of second crystal grains are more likely to be in contact with the plurality of first crystal grains, further reducing the contact between the plurality of first crystal grains. The glass contained in the third region is in contact with the second region and can further exist between the plurality of first crystal grains with reduced mutual contact. The denseness of the sintered metal layer is further improved. Therefore, this configuration reliably suppresses the characteristic deterioration of the electronic component.

[0011] In the above one aspect, on the surface of the sintered metal layer, the plurality of first crystal grains may have a larger particle size than that of the plurality of second crystal grains. In a configuration where, on the surface of the sintered metal layer, the plurality of first crystal grains have a larger particle size than that of the plurality of second crystal grains, on the above surface, the plurality of second crystal grains are likely to be located between the plurality of first crystal grains, further reducing the contact between the plurality of first crystal grains. The glass contained in the third region is in contact with the second region and can further exist between the plurality of first crystal grains with reduced mutual contact. The denseness of the sintered metal layer is further improved. Therefore, this configuration more reliably suppresses the characteristic deterioration of the electronic component.

[0012] In the above one aspect, pores through which the second region is exposed may be formed in the sintered metal layer. A structure in which pores are formed with the second region exposed in the sintered metal layer relaxes the stress acting on the sintered metal layer and suppresses the occurrence of cracks in the ceramic body. Therefore, this structure more reliably suppresses, for example, the deterioration of the characteristics of electronic components.

[0013] In the above one aspect, the grain boundary between the first crystal grains and the second crystal grains may include a region where there is no alloy of the first metal and the second metal. In a region where there is no alloy of the first metal and the second metal, the first metal and the second metal exist independently of each other. In a configuration including a region where there is no alloy of the first metal and the second metal, a plurality of second crystal grains are likely to be located between a plurality of first crystal grains, further reducing the contact between the plurality of first crystal grains. The glass contained in the third region may be in contact with the second region and further exist between the plurality of first crystal grains with reduced mutual contact. The density of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses the deterioration of the characteristics of electronic components.

[0014] In the above one aspect, the second metal may have a melting point higher than that of the first metal. In a configuration where the second metal has a melting point higher than that of the first metal, the second metal is more likely to maintain a solid state than the first metal. A plurality of second crystal grains further reduce the contact between the plurality of first crystal grains. The glass contained in the third region may be in contact with the second region and further exist between the plurality of first crystal grains with reduced mutual contact. The density of the sintered metal layer is further improved. Therefore, this structure more reliably suppresses the deterioration of the characteristics of electronic components.

[0015] In the above one aspect, the second metal may have an ionization tendency greater than that of the first metal. In a configuration where the second metal has a greater ionization tendency than the first metal, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. The plurality of second crystal grains further reduce the contact between the plurality of first crystal grains. The glass contained in the third region is in contact with the second region and can further exist between the plurality of first crystal grains with reduced mutual contact. The density of the sintered metal layer is further improved. Therefore, this configuration more reliably suppresses the characteristic deterioration of the electronic component.

[0016] In one aspect described above, the ceramic body may include a semiconductor ceramic material.

Advantages of the Invention

[0017] One aspect of the present invention provides an electronic component that suppresses characteristic deterioration.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted.

[0020] Referring to FIGS. 1 to 7, the configuration of the chip varistor T1 according to the present embodiment will be described. FIG. 1 is a perspective view showing the chip varistor according to the present embodiment. FIGS. 2 and 3 are diagrams showing the cross-sectional configuration of the chip varistor according to the present embodiment. FIGS. 4 and 5 are diagrams showing the configuration of the cross-section of the sintered metal layer. FIGS. 6 and 7 are diagrams showing the configuration of the surface of the sintered metal layer. In the present embodiment, the electronic component is, for example, the chip varistor T1. Hereinafter, the configuration of the chip varistor T1 according to the present embodiment will be described.

[0021] As shown in FIGS. 1 to 3, the chip varistor T1 includes a ceramic body 3, internal electrodes 5, and external electrodes 7. The ceramic body 3 has, for example, a rectangular parallelepiped shape. In the present specification, the rectangular parallelepiped shape includes a shape in which the corners and edges are chamfered, or a shape in which the corners and edges are rounded, of a rectangular parallelepiped. The internal electrodes 5 are disposed within the ceramic body 3. The external electrodes 7 are disposed on the ceramic body 3. In FIG. 1, the illustration of the internal electrodes 5 is omitted.

[0022] The ceramic body 3 includes a pair of side surfaces 3a facing each other, a pair of side surfaces 3c facing each other, and a pair of side surfaces 3e facing each other. Each of the side surfaces 3a, 3b, 3c, 3e has a rectangular shape. In the present specification, the rectangular shape includes, for example, a shape in which each corner is chamfered, or a shape in which each corner is rounded. The pair of side surfaces 3a face each other in the first direction D1. The pair of side surfaces 3c face each other in the second direction D2. The side surfaces 3e face each other in the third direction D3. The first direction D1 intersects the second direction D2 and also intersects the third direction D3. The second direction D2 intersects, for example, the third direction D3. For example, the first direction D1, the second direction D2, and the third direction D3 are orthogonal to each other. The side surface 3a is orthogonal to the first direction D1. The side surface 3c is orthogonal to the second direction D2. The side surface 3e is orthogonal to the third direction D3. The side surface 3e extends in the first direction D1 so as to connect the pair of side surfaces 3a. The side surface 3e extends in the second direction D2 so as to connect the pair of side surfaces 3c. The side surface 3a extends in the third direction D3 so as to connect the pair of side surfaces 3e. The side surface 3c extends in the third direction D3 so as to connect the pair of side surfaces 3e.

[0023] The chip varistor T1 is, for example, soldered and mounted on an electronic device. The electronic device includes, for example, a circuit board or another electronic component. In the chip varistor T1, one of the four side surfaces 3a, 3c faces the electronic device. One of the four side surfaces 3a, 3c is arranged so as to constitute a mounting surface. One of the four side surfaces 3a, 3c is the mounting surface.

[0024] The ceramic body 3 includes a laminated structure in which a plurality of ceramic layers are laminated. The lamination direction of the plurality of ceramic layers coincides with the first direction D1. Each ceramic layer includes a sintered body that exhibits varistor characteristics. The ceramic body 3 includes, for example, a semiconductor ceramic material. In the actual ceramic body 3, each ceramic layer is integrated to such an extent that the boundary between the ceramic layers cannot be visually recognized. The ceramic body 3 includes a varistor body. The ceramic body 3 contains ZnO (zinc oxide) as a main component. As sub-components, the ceramic body 3 contains, for example, Co, rare earth metal elements (for example, Pr), group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkaline earth metal elements (Mg, Ca, Sr, Ba) in the form of simple metals. The ceramic body 3 may contain oxides of the above simple metals as sub-components. In the present embodiment, the ceramic body 3 contains Co, Pr, Cr, Ca, K, and Al as sub-components. When the total content of all the materials constituting the ceramic body 3 is 100% by weight, the content of ZnO is, for example, 99.8 to 69.0% by weight. The content of the rare earth metal element (Pr) in the ceramic body 3 is, for example, about 0.01 to 10 atomic %. The rare earth metal element can exhibit varistor characteristics.

[0025] The chip varistor T1 includes a coating layer 9. The coating layer 9 is disposed on the outer surface of the ceramic body 3, that is, on a pair of side surfaces 3a, a pair of side surfaces 3c, and a pair of side surfaces 3e. The coating layer 9 covers the outer surface of the ceramic body 3. In the present embodiment, substantially the entire outer surface of the ceramic body 3 is covered. The coating layer 9 is disposed directly on the outer surface of the ceramic body 3, for example. The coating layer 9 includes a glass material. The thickness of the coating layer 9 is, for example, 0.01 to 10 μm. In the present embodiment, the thickness of the coating layer 9 is 0.1 μm. The glass material is, for example, SiO 2 -Al 2 O 3 -LiO 2 -based crystallized glass. The glass material may include amorphous glass. The chip varistor T1 may not include the coating layer 9.

[0026] The chip varistor T1 has, for example, a 0402 size in JIS notation. The 0402 size in JIS notation corresponds to the 01005 size in EIA notation. In this case, the length of the ceramic body 3 in the first direction D1 is, for example, about 0.2 mm. The length of the ceramic body 3 in the second direction D2 is about 0.2 mm. The length of the ceramic body 3 in the third direction D3 is about 0.4 mm.

[0027] As shown in FIGS. 2 and 3, the chip varistor T1 includes a plurality of internal electrodes 5. In the present embodiment, the chip varistor T1 includes a pair of internal electrodes 5. The internal electrodes 5 face each other in the first direction D1. The pair of internal electrodes 5 are disposed in the ceramic body 3. Each of the internal electrodes 5 faces a corresponding side surface 3a. Each of the internal electrodes 5 is connected to a corresponding external electrode 7. Each of the internal electrodes 5 is electrically and physically connected to a corresponding external electrode 7.

[0028] When viewed from the first direction D1, the pair of internal electrodes 5 includes a region where they overlap each other. The pair of internal electrodes 5 are spaced apart from each other in the first direction D1. Each of the internal electrodes 5 includes a pair of surfaces facing each other in the first direction D1. One of the pair of surfaces included in the internal electrode 5 faces the corresponding side surface 3a. The other of the pair of surfaces included in the internal electrode 5 faces the other internal electrode 5. Each of the pair of internal electrodes 5 includes an end portion exposed from the corresponding side surface 3e. The end portion included in each of the pair of internal electrodes 5 protrudes from the corresponding side surface 3e and penetrates the coating layer 9. The end portion included in each of the pair of internal electrodes 5 includes a portion exposed from the coating layer 9. The pair of internal electrodes 5 are located within the ceramic element 3 except for the above-mentioned end portions exposed from the coating layer 9.

[0029] Each of the pair of internal electrodes 5, when viewed from the first direction D1, exhibits, for example, a rectangular shape. In each of the pair of internal electrodes 5, for example, the length in the third direction D3 is greater than the length in the second direction D2. The sizes of each of the pair of internal electrodes 5 are substantially the same as each other. The thickness of the internal electrode 5 in the first direction D1 is, for example, 0.5 to 4.0 μm. The length of the internal electrode 5 in the second direction D2 is, for example, 100 μm. The length of the internal electrode 5 in the third direction D3 is, for example, 300 μm.

[0030] Each of the pair of internal electrodes 5 contains a noble metal or a noble metal alloy. The noble metal includes, for example, Ag, Pd, Au, or Pt. The noble metal alloy includes, for example, an Ag-Pd alloy. The internal electrode 5 may contain a base metal or a base metal alloy. The base metal includes, for example, Cu or Ni. The internal electrode 5 is an internal conductor disposed within the ceramic element 3 and contains a conductive material commonly used as an internal electrode of a multilayer electronic component. The conductive material includes, for example, a base metal. The conductive material includes, for example, Ni or Cu. The internal electrode 5 is configured as a sintered body of a conductive paste containing a conductive material of the above-described type.

[0031] As shown in FIGS. 1 to 3, the chip varistor T1 includes a plurality of external electrodes 7. The chip varistor T1 includes, for example, a pair of external electrodes 7. The pair of external electrodes 7 are disposed on the ceramic body 3. The pair of external electrodes 7 are disposed on the outer surface of the ceramic body 3. The pair of external electrodes 7 are disposed, for example, at both ends in the third direction D3 of the ceramic body 3. The pair of external electrodes 7 face each other in the third direction D3 with the ceramic body 3 interposed therebetween. The pair of external electrodes 7 are spaced apart from each other in the third direction D3. The pair of external electrodes 7 are disposed, for example, on the coating layer 9. Each of the pair of external electrodes 7 is physically and electrically connected to the corresponding internal electrode 5 at the portion exposed from the coating layer 9 among the pair of internal electrodes 5. The coating layer 9 includes a portion covered by the pair of external electrodes 7 and a portion not covered by the pair of external electrodes 7.

[0032] Each of the pair of external electrodes 7 is disposed on the corresponding side surface among the pair of side surfaces 3e. The pair of external electrodes 7 are disposed, for example, on the side surface 3e and on a part of each of the four side surfaces 3a, 3c. The above-mentioned part of each of the side surfaces 3a, 3c is a partial region near the side surface 3e on each of the side surfaces 3a, 3c. In the present embodiment, each of the pair of external electrodes 7 covers the entire corresponding side surface 3e. The pair of external electrodes 7 cover the corner portion formed by the side surface 3e and the four surfaces of each of the side surfaces 3a, 3c, and the ridge line portion connecting the corner portions to each other.

[0033] The external electrode 7 includes a sintered metal layer 7a. The sintered metal layer 7a is formed by applying a conductive paste onto the outer surface of the ceramic body 3 and baking it. The conductive paste includes metal powder, a glass component, an organic binder, and an organic solvent. The sintered metal layer 7a is formed by sintering the metal component (metal powder) contained in the conductive paste. The sintered metal layer 7a includes a layer formed by sintering the metal powder contained in the conductive paste. The metal powder contained in the conductive paste includes noble metal powder and base metal powder. The noble metal includes Ag. The noble metal may include Au, Pt, or Pd. The base metal may include Cu or Ni. In this embodiment, the sintered metal layer 7a includes Ag and Cu.

[0034] The external electrode 7 includes at least one plating layer on the sintered metal layer 7a. In this embodiment, the external electrode 7 includes, for example, two plating layers 7b and 7c on the sintered metal layer 7a. The sintered metal layer 7a is a base layer for forming the plating layers 7b and 7b. The plating layer 7b is located between the sintered metal layer 7a and the plating layer 7c, and the plating layer 7b is located between the sintered metal layer 7a and the plating layer 7c. The plating layer 7b includes, for example, a Ni plating layer. The plating layer 7b may include a Sn plating layer, a Cu plating layer, or an Au plating layer instead of the Ni plating layer. The plating layer 7c includes a solder plating layer. The solder plating layer includes a Sn plating layer, a Sn-Ag alloy plating layer, a Sn-Bi alloy plating layer, or a Sn-Cu alloy plating layer. These plating layers are formed by a plating method. The plating method includes, for example, an electrolytic plating method. The external electrode 7 may include three plating layers on the sintered metal layer 7a. The thickness of the external electrode 7 is, for example, 10 to 30 μm.

[0035] FIG. 4 is a diagram showing the cross-sectional configuration of the sintered metal layer 7a. FIG. 5 is an enlarged view of a part of the cross-sectional configuration of the sintered metal layer 7a. FIGS. 4 and 5 are diagrams showing the cross-sectional configuration of the sintered metal layer 7a when cut by a plane parallel to the side surface 3c. The sintered metal layer 7a includes a region R1, a region R2 in contact with the region R1, and a region R3 in contact with the region R2. The region R1 includes a plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 is made of a first metal. The region R2 includes a plurality of crystal grains CG2. Each of the plurality of crystal grains CG2 is made of a second metal. The second metal is different from the first metal. In the present embodiment, the first metal contains Ag, and the second metal contains Cu. The crystal grain CG1 contains Ag particles, and the crystal grain CG2 contains Cu particles. The region R3 includes glass G1. The glass G1 contains, for example, SiO 2 or B 2 O 3 and the like. For example, when the region R1 includes a first region, the region R2 includes a second region, and the region R3 includes a third region. For example, when the crystal grain CG1 includes a first crystal grain, the crystal grain CG2 includes a second crystal grain.

[0036] In the cross-section of the sintered metal layer 7a, each of the plurality of crystal grains CG1 is arranged in contact with each other. Each of the plurality of crystal grains CG1 has a region where they are sintered to each other. The plurality of crystal grains CG2 contain particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 contain particles located between the plurality of crystal grains CG1, for example, in a state of being arranged in contact with each other. The plurality of crystal grains CG2 contain particles located along the grain boundary formed by the plurality of crystal grains CG1. The plurality of crystal grains CG2 may contain a plurality of particles arranged along the grain boundary formed by the plurality of crystal grains CG1. The plurality of crystal grains CG2 may contain particles located alone between the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0037] The cross-section of the sintered metal layer 7a includes the grain boundary formed by the plurality of crystal grains CG1 and the grain boundary formed by the plurality of crystal grains CG2. The grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where no alloy of the first metal and the second metal exists. In this region where the alloy does not exist, the first metal and the second metal are not alloyed with each other at the location where the crystal grain CG1 and the crystal grain CG2 are in direct contact with each other. The second metal has an ionization tendency greater than that of the first metal. Therefore, Cu of the second metal is more likely to react with oxygen than Ag of the first metal. In the sintered metal layer 7a, Cu is more likely to exist as an oxide than Ag. In the present embodiment, the oxide of Cu contains, for example, CuО. In the cross-section of the sintered metal layer 7a, the area of the region R1 is larger than the area of the region R2. That is, in the cross-section, the area ratio of the region R1 to the region R2 is greater than 1. The area of the region R1 is the sum of a plurality of crystal grains CG1 exposed in the cross-section of the sintered metal layer 7a. The area of the region R2 is the sum of a plurality of crystal grains CG2 exposed in the cross-section of the sintered metal layer 7a. In the sintered metal layer 7a, the occupancy ratio of the region R1 and the region R2 is greater than 1 in terms of the area ratio of the region R1 to the region R2.

[0038] The area ratio of the regions R1 and R2 is obtained, for example, as follows. A cross-sectional photograph of the ceramic element 3 is acquired at a position including the regions R1 and R2. The cross-sectional photograph is, for example, a photograph taken of a cross-section when the sintered metal layer 7a is cut in a plane orthogonal to the thickness direction of the sintered metal layer 7a. The cross-section is, for example, parallel to the side surface 3c. The cross-sectional photograph may be, for example, a photograph taken of a cross-section of the sintered metal layer 7a when cut in a plane parallel to the side surface 3a or the side surface 3e. The cross-sectional photograph is, for example, an SEM (scanning electron microscope) photograph. The SEM photograph includes, for example, a composite image photograph. For calculating the areas of the regions R1 and R2, software is used to perform image processing on the acquired cross-sectional photograph. Based on the result of this image processing, the boundaries of each crystal grain CG1 and each crystal grain CG2 are discriminated, and the area of each of the crystal grains CG1 and CG2 is calculated. The area of the region R1 is calculated as the product of the number of crystal grains CG1 included in the region R1 and the area of the crystal grain CG1 in the acquired cross-sectional photograph. The area of the region R2 is calculated as the product of the number of crystal grains CG2 included in the region R2 and the area of the crystal grain CG2 in the acquired cross-sectional photograph. The area ratio of the region R1 to the region R2 is obtained as the ratio of the area of the region R1 calculated as above to the area of the region R2 calculated as above.

[0039] Regarding the grain sizes of the crystal grains CG1 and CG2, for example, they are calculated as the grain sizes converted to the equivalent circle diameter from the areas of the crystal grains CG1 and CG2 calculated above. In the present embodiment, the grain sizes of all the crystal grains CG1 included in the region R1 may be calculated, or the grain sizes of all the crystal grains CG2 included in the region R2 may be calculated. Among the crystal grains CG1 included in the region R1, the grain sizes of any number of crystal grains CG1 may be calculated, or among the crystal grains CG2 included in the region R2, the grain sizes of any number of crystal grains CG2 may be calculated. The arbitrary number is, for example, 50. In the cross-section of the sintered metal layer 7a, the plurality of crystal grains CG1 have larger grain sizes than the plurality of crystal grains CG2. The grain size of the crystal grains CG1 is, for example, 0.4 to 3.6 μm. The grain size of the crystal grains CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the grain size of the crystal grains CG1 is larger than the minimum value of the grain size of the crystal grains CG2. The maximum value of the grain size of the crystal grains CG1 is larger than the maximum value of the grain size of the crystal grains CG2.

[0040] The sintered metal layer 7a contains the glass G1. The glass G1 is included in the region R3. The region R3 is formed between the plurality of crystal grains CG1 when the plurality of crystal grains CG1 are sintered together. For example, the glass component contained in the conductive paste for forming the sintered metal layer 7a softens when forming the sintered metal layer 7a and flows into at least a part between the plurality of crystal grains CG1. The glass component, for example, flows into at least a part between the plurality of crystal grains CG1. The above glass component, for example, fills a part between the plurality of crystal grains CG1. The glass solidified between the plurality of crystal grains CG1 constitutes the region R3. A second metal exists around the glass G1 included in the region R3. Vacancies V1 are formed in the sintered metal layer 7a. The vacancies V1 are formed when forming the sintered metal layer 7a. The vacancies V1 exist between the plurality of crystal grains CG1. The region R2 is exposed in the vacancies V1. The second metal is exposed in the vacancies V1. The vacancies V1 are located between the plurality of crystal grains CG1, and the vacancies V1 are not filled with the glass G1.

[0041] FIG. 6 is a diagram showing the configuration of the surface of the sintered metal layer 7a. FIG. 7 is an enlarged view of a part of the configuration of the surface of the sintered metal layer 7a. FIGS. 6 and 7 illustrate the surface 7s of the sintered metal layer 7a as viewed from the thickness direction of the sintered metal layer 7a. The thickness direction of the sintered metal layer 7a includes, for example, the third direction D3. In the present embodiment, the surface 7s of the sintered metal layer 7a has the same configuration as the cross section of the sintered metal layer 7a illustrated in FIG. 4.

[0042] On the surface 7s of the sintered metal layer 7a, each of the plurality of crystal grains CG1 is in contact with and arranged adjacent to each other. Each of the plurality of crystal grains CG1 has a region where they are sintered to each other. The plurality of crystal grains CG2 include particles located between the plurality of crystal grains CG1. The plurality of crystal grains CG2 include, for example, particles located between the plurality of crystal grains CG1 in a state of being in contact with and arranged adjacent to each other. The plurality of crystal grains CG2 include particles located along the grain boundaries formed by the plurality of crystal grains CG1. Each of the plurality of crystal grains CG1 and each of the plurality of crystal grains CG2 are, for example, in direct contact with each other.

[0043] The surface 7s of the sintered metal layer 7a includes the grain boundaries formed by the plurality of crystal grains CG1 and the grain boundaries formed by the plurality of crystal grains CG2. The grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where the alloy of the first metal and the second metal does not exist. In this region where the alloy does not exist, the first metal and the second metal are not alloyed with each other at the locations where the crystal grain CG1 and the crystal grain CG2 are in direct contact with each other. On the surface 7s, the area of the region R1 is larger than the area of the region R2. That is, in the cross section, the area ratio of the region R1 to the region R2 is greater than 1. The area of the region R1 is the sum of the plurality of crystal grains CG1 exposed on the surface 7s. The area of the region R2 is the sum of the plurality of crystal grains CG2 exposed on the surface 7s. On the surface 7s, the occupancy ratio of the region R1 and the region R2 is greater than 1 in terms of the area ratio of the region R1 to the region R2.

[0044] On the surface 7s of the sintered metal layer 7a, the area ratio of the regions R1 and R2 is obtained, for example, by the same procedure as in the case of the cross section of the sintered metal layer 7a described above. That is, a surface photograph of the ceramic green body 3 is acquired at a position including the regions R1 and R2. The surface photograph is, for example, a photograph of the surface 7s when viewed from the thickness direction of the sintered metal layer 7a. The surface 7s is, for example, parallel to the side surface 3e. The surface photograph may be a photograph of the surface 7s parallel to either of the side surfaces 3a and 3c. The surface photograph is, for example, an FE-SEM (field emission scanning electron microscope) photograph (for example, a secondary electron image photograph). Hereinafter, in the same manner as in the case of the cross section of the sintered metal layer 7a, the area ratio of the regions R1 and R2 is obtained.

[0045] Regarding the particle sizes of the crystal grains CG1 and CG2, for example, they are calculated as the particle sizes converted into the equivalent circle diameters from the areas of the crystal grains CG1 and CG2 calculated above. On the surface 7s of the sintered metal layer 7a, the plurality of crystal grains CG1 have a larger particle size than the particle sizes of the plurality of crystal grains CG2. The particle size of the crystal grains CG1 is, for example, 0.4 to 3.6 μm. The particle size of the crystal grains CG2 is, for example, 0.2 to 1.4 μm. The minimum value of the particle size of the crystal grains CG1 is larger than the minimum value of the particle size of the crystal grains CG2. The maximum value of the particle size of the crystal grains CG1 is larger than the maximum value of the particle size of the crystal grains CG2.

[0046] The surface 7s of the sintered metal layer 7a contains the glass G1. The region R3 is formed between the plurality of crystal grains CG1 that sinter with each other when the surface 7s of the sintered metal layer 7a is formed. For example, the glass component contained in the conductive paste for forming the sintered metal layer 7a softens when forming the sintered metal layer 7a and flows into a part between the plurality of crystal grains CG1 located on the surface 7s. The glass component fills, for example, a part between the plurality of crystal grains CG1 located on the surface 7s. Vacancies V1 are formed on the surface 7s of the sintered metal layer 7a. The vacancies V1 are formed when the surface 7s of the sintered metal layer 7a is formed. The vacancies V1 exist between the plurality of crystal grains CG1. The region R2 is exposed in the vacancies V1. The second metal is exposed in the vacancies V1.

[0047] A method for manufacturing the chip varistor T1 will be described. In this embodiment, first, a ceramic element body 3 in which an internal electrode 5 is disposed inside is prepared. The process of preparing the ceramic element body 3 is known in this technical field, and further detailed description thereof is omitted. After forming the ceramic element body 3 in which the internal electrode 5 is disposed inside, an external electrode 7 is formed. In forming the external electrode 7, a conductive paste is applied to the side surface 1e of the ceramic element body 3. In this embodiment, the conductive paste for the external electrode 7 contains Ag particles, Cu particles, a glass component, and an organic binder. In the conductive paste, the content of the Ag particles is, for example, 65 to 80% by weight. The content of the Cu particles is, for example, 1 to 4% by weight. The content of the glass component is, for example, 3 to 7% by weight. The glass component contains, for example, SiO 2 or B 2 O 3 . In the conductive paste, the particle size of the Ag particles is, for example, 0.04 to 9.0 μm. The particle size of the Cu particles is, for example, 0.15 to 0.7 μm.

[0048] Subsequently, in a firing furnace, the conductive paste is baked to form a sintered metal layer 7a. By the firing process, the conductive paste is baked to form the sintered metal layer 7a. The firing process of the conductive paste includes, for example, a first temperature rising process, a first heat retaining process, a second temperature rising process, a second heat retaining process, and a temperature lowering process. In the first heat retaining process after the first temperature rising process, the organic binder is removed. After the first heat retaining process, in the second temperature rising process, the glass is melted. After the glass starts to melt, the sintering of Ag starts. The temperature at which the sintering of Ag starts is higher than when the conductive paste does not contain Cu. At the temperature at which the sintering of Ag starts, Cu is difficult to melt and remains in a solid state. Cu has a melting point higher than the melting point of Ag. Cu reduces the contact between the first metals and delays the start of the sintering of Ag. For example, in the second temperature rising process, Cu forms an oxide.

[0049] A plurality of voids V1 are formed between the sintered Ag. Cu suppresses the contact between the plurality of Ag, and Cu is likely to be exposed in the plurality of voids V1. In the present embodiment, during the second heating process, the softened glass flows into the space between the plurality of Ag. Through the second heat preservation process and the cooling process, a sintered metal layer 7a is formed. The glass G1 that has flowed into the space between the plurality of Ag solidifies. In the present embodiment, subsequently, for example, plating layers 7b and 7c are formed on the sintered metal layer 7a by a wet plating method. The wet plating method includes an electrolytic plating method.

[0050] Through the above process, the chip varistor T1 is manufactured. In the present embodiment, an annealing process may be performed on the ceramic body 3. The annealing process may not be performed on the ceramic body 3. In the chip varistor T1, in the sintered metal layer 7a, the content rate of Ag particles is, for example, 88 to 94% by weight. The content rate of copper oxide particles is, for example, 2 to 4% by weight. The content rate of glass is, for example, 4 to 8% by weight. Copper oxide contains, for example, CuO.

[0051] As described above, in the chip varistor T1, the existence ratio of the region R1 and the region R2 is larger than 1 in terms of the area ratio of the region R1 to the region R2. The plurality of crystal grains CG2 included in the region R2 are likely to contact the plurality of crystal grains CG1 included in the region R1 having a larger area ratio than the region R2. The plurality of crystal grains CG2 reduce the contact between the plurality of crystal grains CG1. The glass G1 included in the region R3 may be in contact with the region R2 and exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is improved. Therefore, the characteristic deterioration of the chip varistor T1 is suppressed. The characteristics of the chip varistor T1 include, for example, electrical characteristics. In a chip varistor, the sintered metal layer that does not contain a second metal tends to have a structure in which glass oozes out onto the surface of the sintered metal layer. The sintered metal layer 7a containing a second metal is such that glass G1 hardly oozes out from the surface 7s of the sintered metal layer 7a. The glass floating on the surface 7s of the sintered metal layer 7a is reduced. In the chip varistor T1, the glass G1 existing between the plurality of crystal grains CG1 improves the densification of the sintered metal layer 7a.

[0052] In the chip varistor T1, in the cross-section of the sintered metal layer 7a, the area ratio of the region R1 to the region R2 is greater than 1. In the chip varistor T1, in the above cross-section, the plurality of crystal grains CG2 are more likely to be in contact with the plurality of crystal grains CG1, and the contact between the plurality of crystal grains CG1 is further reduced. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The densification of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is surely suppressed.

[0053] In the chip varistor T1, in the cross-section of the sintered metal layer, the plurality of crystal grains CG1 have a larger particle size than the plurality of crystal grains CG2. In the chip varistor T1, in the above cross-section, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, and the contact between the plurality of crystal grains is further reduced. The glass G1 contained in the region R is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The densification of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more surely suppressed.

[0054] In the chip varistor T1, on the surface 7s of the sintered metal layer 7a, the area ratio of the region R1 to the region R2 is greater than 1. In the chip varistor T1, on the surface 7s, a plurality of crystal grains CG2 are more likely to be in contact with a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 included in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic degradation of the chip varistor T1 is surely suppressed.

[0055] In the chip varistor T1, on the surface 7s of the sintered metal layer 7a, a plurality of crystal grains CG1 have a larger particle size than the particle size of the plurality of crystal grains CG2. In the chip varistor T1, on the surface 7s, a plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 included in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic degradation of the chip varistor T1 is more surely suppressed.

[0056] In the above one aspect, in the sintered metal layer 7a, voids V1 where the region R2 is exposed are formed. The chip varistor T1 relaxes the stress acting on the sintered metal layer 7a and suppresses the generation of cracks in the ceramic body 3. Therefore, the characteristic degradation of the chip varistor T1 is even more surely suppressed.

[0057] In the chip varistor T1, the grain boundary between the crystal grain CG1 and the crystal grain CG2 includes a region where no alloy of the first metal and the second metal exists. In the region where there is no alloy of the first metal and the second metal, the first metal and the second metal exist independently of each other. In the chip varistor T1, a plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed.

[0058] In the chip varistor T1, the second metal has a melting point higher than that of the first metal. In the chip varistor T1, the second metal is more likely to maintain a solid state than the first metal. A plurality of crystal grains CG2 further reduce the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed.

[0059] In the chip varistor T1, the second metal has an ionization tendency greater than that of the first metal. In the chip varistor T1, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. A plurality of crystal grains CG1 further reduce the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed.

[0060] In the chip varistor T1, the second metal contained in the region R2 is likely to suppress the sintering of the first metal contained in the region R1. In the sintered metal layer 7a where the sintering of the first metal is suppressed, the molten glass is likely to flow into the gaps between the plurality of crystal grains CG1. In the sintered metal layer that does not contain the second metal, since the sintering of the first metal proceeds early, it is difficult for the molten glass to flow into the gaps between the plurality of crystal grains CG1. In the chip varistor T1, for example, even when a plating layer is formed on the sintered metal layer 7a by a wet plating method, the glass G1 suppresses the inflow of the moisture containing the plating solution into the sintered metal layer 7a. The glass G1 suppresses the moisture containing the plating solution from passing through the sintered metal layer 7a and reaching the interface between the sintered metal layer 7a and the ceramic body 3. The characteristic deterioration of the chip varistor T1 is more reliably suppressed.

[0061] As described above, the embodiments of the present invention have been described. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the gist thereof.

[0062] The plurality of crystal grains CG1 do not necessarily have a particle size larger than that of the plurality of crystal grains CG2. In the configuration where the plurality of crystal grains CG1 have a particle size larger than that of the plurality of crystal grains CG2, as described above, the plurality of crystal grains CG2 are likely to be located between the plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains. The glass G1 contained in the region R is in contact with the region R2 and can further exist between the plurality of crystal grains CG1 with reduced mutual contact. The denseness of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed. The grain boundary between crystal grains CG1 and crystal grains CG2 does not necessarily need to include a region where the alloy of the first metal and the second metal does not exist. In a configuration where the grain boundary between crystal grains CG1 and crystal grains CG2 includes a region where the alloy of the first metal and the second metal does not exist, as described above, a plurality of crystal grains CG2 are likely to be located between a plurality of crystal grains CG1, further reducing the contact between the plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between a plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed. The second metal does not necessarily need to have a melting point higher than that of the first metal. In a configuration where the second metal has a melting point higher than that of the first metal, as described above, the second metal is more likely to maintain a solid state than the first metal. A plurality of crystal grains CG2 further reduce the contact between a plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between a plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed. The second metal does not necessarily need to have an ionization tendency greater than that of the first metal. In a configuration where the second metal has an ionization tendency greater than that of the first metal, as described above, the second metal is more likely to form an oxide than the first metal. The second metal does not alloy with the first metal. A plurality of crystal grains CG1 further reduce the contact between a plurality of crystal grains CG1. The glass G1 contained in the region R3 is in contact with the region R2 and can further exist between a plurality of crystal grains CG1 with reduced mutual contact. The density of the sintered metal layer 7a is further improved. Therefore, the characteristic deterioration of the chip varistor T1 is more reliably suppressed.

[0063] In the above-described embodiments, a chip varistor has been described as an example of an electronic component, but applicable electronic components are not limited to chip varistors. Applicable electronic components are, for example, electronic components such as capacitors, inductors, piezoelectric actuators, thermistors, solid-state battery components, or composite components. Applicable electronic components may be multilayer electronic components.

[0064] As can be understood from the description of the above-described embodiments, this specification includes the disclosure of the following aspects. (Appendix 1) A ceramic body, A sintered metal layer disposed on the ceramic body, Comprising: The sintered metal layer, A first region including a plurality of first crystal grains made of a first metal, A second region that is in contact with the first region and includes a plurality of second crystal grains made of a second metal different from the first metal, A third region that is in contact with the second region and includes glass, and An electronic component in which the existence ratio of the first region to the second region is greater than 1 in terms of the area ratio of the first region to the second region. (Appendix 2) In the cross-section of the sintered metal layer, the area ratio of the first region to the second region is greater than 1, and the electronic component according to Appendix 1. (Appendix 3) In the cross-section, the plurality of first crystal grains have a larger particle size than the particle size of the plurality of second crystal grains, and the electronic component according to Appendix 2. (Appendix 4) On the surface of the sintered metal layer, the area ratio of the first region to the second region is greater than 1, and the electronic component according to Appendix 1. (Appendix 5) On the surface, the plurality of first crystal grains have a larger particle size than the particle size of the plurality of second crystal grains, and the electronic component according to Appendix 4. (Appendix 6) The electronic component according to any one of Appendices 1 to 5, wherein pores in which the second region is exposed are formed in the sintered metal layer. (Appendix 7) The electronic component according to any one of Appendices 1 to 6, wherein the grain boundary between the first crystal grains and the second crystal grains includes a region where an alloy of the first metal and the second metal does not exist. (Appendix 8) The electronic component according to any one of Appendices 1 to 7, wherein the second metal has a melting point higher than that of the first metal. (Appendix 9) The electronic component according to any one of Appendices 1 to 8, wherein the second metal has an ionization tendency greater than that of the first metal. (Appendix 10) The electronic component according to any one of Appendices 1 to 9, wherein the ceramic body includes a semiconductor ceramic material.

Description of Reference Numerals

[0065] 3... ceramic body, 7a... sintered metal layer, R1, R2, R3... regions, CG1, CG2... crystal grains, V1... pores, T1... chip varistor.

Claims

1. A ceramic body; A sintered metal layer disposed on the ceramic body; Comprising: The sintered metal layer includes: A first region including a plurality of first crystal grains made of a first metal; A second region in contact with the first region and including a plurality of second crystal grains made of a second metal different from the first metal; A third region in contact with the second region and including glass, and An electronic component, wherein a ratio of presence of the first region to the second region is greater than 1 in terms of an area ratio of the first region to the second region.

2. The electronic component according to claim 1, wherein in a cross section of the sintered metal layer, an area ratio of the first region to the second region is greater than 1.

3. The electronic component according to claim 2, wherein in the cross section, the plurality of first crystal grains have a particle size larger than a particle size of the plurality of second crystal grains.

4. The electronic component according to claim 1, wherein on a surface of the sintered metal layer, an area ratio of the first region to the second region is greater than 1.

5. The electronic component according to claim 4, wherein on the surface, the plurality of first crystal grains have a particle size larger than a particle size of the plurality of second crystal grains.

6. The electronic component according to claim 1, wherein pores are formed in the sintered metal layer such that the second region is exposed.

7. The electronic component according to claim 1 or 2, wherein a grain boundary between the first crystal grains and the second crystal grains includes a region where an alloy of the first metal and the second metal does not exist.

8. The electronic component according to claim 1, wherein the second metal has a melting point higher than a melting point of the first metal.

9. The electronic component according to claim 1, wherein the second metal has an ionization tendency greater than an ionization tendency of the first metal.

10. The electronic component according to claim 1, wherein the ceramic body includes a semiconductor ceramic material.

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