Semiconductor device

Abstract

To improve the dielectric voltage.SOLUTION: A semiconductor device 10 includes a first chip 50 including a first circuit 20, and a second chip 60 disposed apart from the first chip 50 in an X direction and including a second circuit 30. The first chip 50 includes a first semiconductor element 51 including a first semiconductor substrate 51A in which the first circuit 20 is formed, a first element insulating layer 51B formed on the first semiconductor substrate 51A, and a first coil 41 provided in the first element insulating layer 51B and electrically connected to the first circuit 20, a first insulating layer 52 covering a first insulating upper surface 51BS of the first element insulating layer 51B that faces opposite to the first semiconductor substrate 51A, and formed of an organic insulating layer, a second coil 42 formed on the first insulating layer 52 and disposed facing the first coil in a thickness direction X with the first element insulating layer 51B and the first insulating layer 52 held therebetween, and a second insulating layer 53 covering the first insulating layer 52 and the second coil 42.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] The through-chip of Patent Document 1 includes an upper coil and a lower coil that are arranged to face each other in the stacking direction of the insulating layers within the insulating layer stack structure.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In the through-chip as described above, improvement in breakdown voltage may be required. Note that the requirement for improvement in breakdown voltage is not limited to the through-chip including the upper coil and the lower coil, and may similarly be required in a capacitor chip including a capacitor instead of the upper coil and the lower coil.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first die pad, a first chip mounted on the first die pad and including a first circuit, a second die pad disposed apart from the first die pad in a first direction orthogonal to the thickness direction of the first chip, and a second chip mounted on the second die pad and including a second circuit. The first chip includes a first semiconductor substrate on which the first circuit is formed, a first element insulating layer formed on the first semiconductor substrate, and a first conductor provided in the first element insulating layer and electrically connected to the first circuit. The first chip further includes a first insulating layer that covers a first insulating upper surface of the first element insulating layer facing away from the first semiconductor substrate and is constituted by an organic insulating layer, a second conductor formed on the first insulating layer and disposed to face the first conductor in the thickness direction with the first element insulating layer and the first insulating layer interposed therebetween and electrically connected to the second circuit, and a second insulating layer that covers the first insulating layer and the second conductor.

Brief Description of the Drawings

[0006]

Figure 1

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[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a certain scale. Also, for ease of understanding, the hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used herein, the expression "at least one" means "one or more" of the desired options. As an example, as used herein, the expression "at least one" means "only one option" or "both of the two options" if the number of options is two. As another example, as used herein, the expression "at least one" means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used herein, "the dimension (thickness) of A is equal to the dimension (thickness) of B" or "the dimension (thickness) of A and the dimension (thickness) of B are equal to each other" includes a relationship in which the difference between the dimension (thickness) of A and the dimension (thickness) of B is within 10% of the dimension (thickness) of A, for example.

[0011] <First Embodiment> [Schematic Configuration of Semiconductor Device] With reference to FIGS. 1 to 3, the schematic configuration of the semiconductor device 10 according to the first embodiment will be described. FIG. 1 schematically shows the circuit configuration of the semiconductor device 10 according to the first embodiment. FIG. 2 schematically shows an example of the planar structure inside the semiconductor device 10. In FIG. 2, in order to show the internal structure of the semiconductor device 10, the encapsulating resin 100 described later is shown by a two-dot chain line. FIG. 3 schematically shows the cross-sectional structure of the semiconductor device 10 shown in FIG. 2 cut along the line F3-F3. Note that in FIG. 1, since the circuit configuration of the semiconductor device 10 is shown in a simplified manner, the number of external terminals of the semiconductor device 10 in FIG. 2 is larger than the number of external terminals of the semiconductor device 10 in FIG. 1. Here, the number of external terminals of the semiconductor device 10 is the number of external electrodes that can connect the semiconductor device 10 and external electronic components of the semiconductor device 10.

[0012] Also, in the following description, the direction from the first semiconductor substrate 51A of the first chip 50 shown in FIG. 3 toward the second insulating layer 53 is defined as the "upward direction", and the direction from the second insulating layer 53 toward the first semiconductor substrate 51A is defined as the "downward direction".

[0013] As shown in FIG. 1, the semiconductor device 10 includes a first circuit 20, a second circuit 30, and transformers 40A and 40B. The transformers 40A and 40B are configured to electrically insulate between the first circuit 20 and the second circuit 30.

[0014] The first circuit 20 is configured to operate by a first voltage V1. In one example, the first circuit 20 includes a transmission circuit or a reception circuit. In the first embodiment, the first circuit 20 includes a transmission circuit 21. The second circuit 30 is configured to operate by a second voltage V2. In one example, the second circuit 30 includes a transmission circuit or a reception circuit. In the first embodiment, the second circuit 30 includes a reception circuit 31. The first voltage V1 and the second voltage V2 may be the same as each other or different from each other. In one example, the second voltage V2 is equal to the first voltage V1. The semiconductor device 10 may be referred to as a digital isolator. For this reason, the semiconductor device 10 can also be said to be a signal transmission device that transmits a signal from the first circuit 20 to the second circuit 30. In the first embodiment, the ground GND1 of the first circuit 20 and the ground GND2 of the second circuit 30 are provided independently.

[0015] The transformers 40A and 40B are provided corresponding to two signals transmitted from the first circuit 20 toward the second circuit 30. Such a signal is, for example, a signal for driving a switching element, and examples thereof include a set signal (SET) and a reset signal (RESET). The set signal is a signal that transmits the rising edge of a control signal from a control circuit (not shown), and the reset signal is a signal that transmits the falling edge of the control signal from the control circuit. In one example, the transformer 40A is used for transmitting the set signal, and the transformer 40B is used for transmitting the reset signal.

[0016] Each of the transformers 40A and 40B includes a first coil 41 and a second coil 42. The first coil 41 and the second coil 42 are electrically insulated from each other and are configured to be magnetically coupled. The first coil 41 is electrically connected to the transmission circuit 21 of the first circuit 20. The second coil 42 is electrically connected to the reception circuit 31 of the second circuit 30. Here, the first coil 41 of the transformers 40A and 40B is an example of a "first conductor", and the second coil 42 of the transformers 40A and 40B is an example of a "second conductor".

[0017] The first coil 41 of the transformers 40A and 40B is electrically connected to the first circuit 20. The second coil 42 of the transformers 40A and 40B is electrically connected to the second circuit 30.

[0018] An input signal as a control signal from a control circuit is input to the transmission circuit 21 of the first circuit 20. The transmission circuit 21 pulse-drives, for example, the transformer 40A based on the input signal. The pulse signal excited in the first coil 41 of the transformer 40A is input to the reception circuit 31 of the second circuit 30 via the second coil 42 of the transformer 40A. The reception circuit 31 outputs an output signal based on the input pulse signal. Note that the transmission circuit 21 may pulse-drive the transformer 40B.

[0019] (Internal Configuration of Semiconductor Device) As shown in FIG. 2, the semiconductor device 10 includes a configuration in which a plurality of chips are packaged in one package. The semiconductor device 10 includes a first chip 50 and a second chip 60. Note that the semiconductor device 10 may include three or more chips. In this embodiment, the first chip 50 is an example of a "semiconductor chip".

[0020] The package form of the semiconductor device 10 is of the SO (Small Outline) type, and in the first embodiment, it is an SOP (Small Outline Package). Also, the package form of the semiconductor device 10 can be arbitrarily changed. The package form is not limited to SOP, and may be a QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J - leaded Package), or various package structures similar thereto.

[0021] The semiconductor device 10 further includes a first lead frame 80, a second lead frame 90, and a sealing resin 100. The sealing resin 100 is configured to seal the first chip 50 and the second chip 60 and partially seal the first lead frame 80 and the second lead frame 90. The sealing resin 100 is formed of a resin material having electrical insulation properties. This resin material includes, for example, a black epoxy resin. The sealing resin 100 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 100 has four sealing side surfaces 101 - 104. More specifically, the sealing resin 100 has sealing side surfaces 101 and 102 as both end faces in the X direction, and sealing side surfaces 103 and 104 as both end faces in the Y direction. The X direction and the Y direction are directions orthogonal to the Z direction. The X direction and the Y direction are orthogonal to each other when viewed from the Z direction. When viewed from the Z direction, the sealing resin 100 is rectangular with the X direction as the long side direction and the Y direction as the short side direction. Here, the X direction corresponds to the "first direction". In the following description, "plan view" means viewing from the Z direction. Note that the shape of the sealing resin 100 in plan view can be arbitrarily changed. In one example, the sealing resin 100 may be rectangular with the Y direction as the long side direction and the X direction as the short side direction in plan view.

[0022] Each of the first lead frame 80 and the second lead frame 90 is a conductor and is formed of a material containing, for example, Cu (copper), Fe (iron), Al (aluminum), etc. Each lead frame 80, 90 is provided across the inside and outside of the encapsulating resin 100.

[0023] The first lead frame 80 has a first die pad 81 disposed within the encapsulating resin 100 and a plurality of first leads 82 disposed across the inside and outside of the encapsulating resin 100. Each first lead 82 constitutes an external terminal for electrically connecting to an external electronic device of the semiconductor device 10. The plurality of first leads 82 includes a pair of first leads 82A connected to the first die pad 81. The pair of first leads 82A is integrated with the first die pad 81.

[0024] The first die pad 81 has the first chip 50 mounted thereon. In plan view, the first die pad 81 is arranged such that the center in the X direction thereof is closer to the encapsulating side surface 102 than the center in the X direction of the encapsulating resin 100. In the first embodiment, the first die pad 81 is not exposed from the encapsulating resin 100. In one example, the shape of the first die pad 81 in plan view is a rectangular shape in which the Y direction is the long side direction and the X direction is the short side direction.

[0025] The plurality of first leads 82, 82A are arranged spaced apart from each other in the Y direction. The first leads 82 are arranged spaced apart from the first die pad 81 in the X direction. A part of each of the first leads 82, 82A protrudes outward from the encapsulating resin 100 from the encapsulating side surface 102.

[0026] The second lead frame 90 has a second die pad 91 disposed within the encapsulating resin 100 and a plurality of second leads 92 disposed across the inside and outside of the encapsulating resin 100. Each second lead 92 constitutes an external terminal for electrically connecting to an external electronic device of the semiconductor device 10. The plurality of second leads 92 includes a pair of second leads 92A connected to the second die pad 91. The pair of second leads 92A is integrated with the second die pad 91.

[0027] The second die pad 91 has the second chip 60 mounted thereon. In plan view, the second die pad 91 is disposed closer to the sealing side surface 101 than the first die pad 81 in the X direction. That is, the first die pad 81 and the second die pad 91 are arranged spaced apart from each other in the X direction. For this reason, the X direction can be said to be the arrangement direction of both die pads 81, 91. Also, the X direction can be said to be the arrangement direction of both chips 50, 60. And it can be said that the first chip 50 and the second chip 60 are arranged spaced apart from each other in the X direction. In the first embodiment, the second die pad 91 is not exposed from the encapsulating resin 100. In one example, the shape of the second die pad 91 in plan view is a rectangular shape in which the Y direction is the long side direction and the X direction is the short side direction.

[0028] The plurality of second leads 92, 92A are arranged spaced apart from each other in the Y direction. The second lead 92 is disposed spaced apart from the second die pad 91 in the X direction. A part of each of the second leads 92, 92A protrudes outward from the encapsulating resin 100 from the sealing side surface 104.

[0029] In the first embodiment, the number of the second leads 92 is the same as the number of the first leads 82. As shown in FIG. 2, the plurality of first leads 82 and the plurality of second leads 92 are arranged in a direction (Y direction) orthogonal to the arrangement direction (X direction) of the first die pad 81 and the second die pad 91 in plan view. Note that each of the number of the second leads 92 and the number of the first leads 82 can be arbitrarily changed. In one example, the number of the first leads 82 and the number of the second leads 92 may be different from each other.

[0030] In the first embodiment, the first die pad 81 is supported by a pair of first leads 82A integrated with the first die pad 81. The second die pad 91 is supported by a pair of second leads 92A integrated with the second die pad 91.

[0031] The first chip 50 mounted on the first die pad 81 is a semiconductor chip including the first circuit 20 in FIG. 1 and the transformers 40A and 40B. The first chip 50 is formed in a rectangular shape having a short side and a long side in a plan view. In the plan view, the first chip 50 is mounted on the first die pad 81 such that the long side is along the Y direction and the short side is along the X direction.

[0032] As shown in FIG. 3, the first chip 50 includes a first semiconductor element 51, a first insulating layer 52 formed on the first semiconductor element 51, and a second insulating layer 53 formed on the first insulating layer 52. The first semiconductor element 51 includes a first semiconductor substrate 51A and a first element insulating layer 51B formed on the first semiconductor substrate 51A. The first semiconductor element 51 includes an element upper surface 51S and an element back surface 51R facing the side opposite to the element upper surface 51S in the Z direction. The element upper surface 51S is a surface facing the second insulating layer 53 side. The first circuit 20 is formed on the first semiconductor substrate 51A. The first coil 41 of each of the transformers 40A and 40B is formed on the first element insulating layer 51B. The first semiconductor substrate 51A includes a first substrate upper surface 51AS and a first substrate back surface 51AR facing opposite sides to each other in the Z direction. The first substrate upper surface 51AS faces the side opposite to the first die pad 81, and the first substrate back surface 51AR constitutes the element back surface 51R which is the lower surface of the first semiconductor element 51. The first semiconductor substrate 51A is made of a material including, for example, silicon (Si). In one example, an Si substrate is used as the first semiconductor substrate 51A.

[0033] The first element insulating layer 51B is formed on the first substrate upper surface 51AS. The first element insulating layer 51B includes a first insulating upper surface 51BS facing the side opposite to the first semiconductor substrate 51A. The first insulating upper surface 51BS constitutes the element upper surface 51S. The first element insulating layer 51B is made of, for example, an inorganic insulating layer. The first element insulating layer 51B is silicon oxide (SiO 2) and is composed of a material containing at least one of silicon nitride (SiN). In one example, the first element insulating layer 51B contains at least one of a silicon oxide film and a silicon nitride film. The first insulating layer 52 is formed on the first insulating upper surface 51BS. The first insulating layer 52 partially covers the first insulating upper surface 51BS. Therefore, a part of the first insulating upper surface 51BS is exposed from the first insulating layer 52.

[0034] The first chip 50 includes a plurality of first external electrodes 55A. In FIG. 3, one first external electrode 55A is shown. The first external electrode 55A is exposed from the first insulating upper surface 51BS. The first external electrode 55A is disposed at a position different from the first insulating layer 52 when viewed in the Z direction among the first element insulating layer 51B. In the first element insulating layer 51B, the first coils 41 of the transformers 40A and 40B, the internal electrode 70, and the first connection wiring 56 are provided. The internal electrode 70 is configured to connect the first coils 41 of the transformers 40A and 40B to the first circuit 20. The first connection wiring 56 is configured to connect the first external electrode 55A to the first circuit 20. Thus, the first external electrode 55A is electrically connected to the first coils 41 of the transformers 40A and 40B via the first connection wiring 56, the first circuit 20, and the internal electrode 70.

[0035] The first insulating layer 52 is composed of an organic insulating layer. In the first embodiment, the first insulating layer 52 is composed of a material containing polyimide or polybenzoxazole. In one example, the first insulating layer 52 is composed of a material containing polyimide. In the first embodiment, the first insulating layer 52 is composed of polyimide.

[0036] The second insulating layer 53 is formed on the first insulating layer 52. In one example, the second insulating layer 53 covers the entire first insulating layer 52 in plan view. The second insulating layer 53 is composed of an organic insulating layer.

[0037] In the second insulating layer 53, a second coil 42 and a second connection wiring 57 of each of the transformers 40A and 40B are provided. Also, a plurality of second external electrodes 55B are provided in the second insulating layer 53. Although not shown in FIG. 3, a plurality of second external electrodes 55C are provided in the second insulating layer 53. The second coil 42 of each of the transformers 40A and 40B is arranged to face the first coil 41 of each of the transformers 40A and 40B in the Z direction. The second connection wiring 57 is configured to connect the second coil 42 and the second external electrode 55B. Also, although not shown, another second connection wiring 57 is configured to connect the second coil 42 and the second external electrode 55C.

[0038] The first chip 50 is joined to the first die pad 81 by the first joining material 151. The first joining material 151 is interposed in the Z direction between the first semiconductor substrate 51A and the first die pad 81. In the first embodiment, a conductive joining material is used as the first joining material 151. As the conductive joining material, for example, solder paste, silver (Ag) paste, etc. are used.

[0039] As shown in FIG. 2, the second chip 60 mounted on the second die pad 91 is a chip including the second circuit 30 of FIG. 1. The second chip 60 is formed in a rectangular shape having a short side and a long side in a plan view. In a plan view, the second chip 60 is mounted on the second die pad 91 such that the long side is along the Y direction and the short side is along the X direction.

[0040] As shown in FIG. 3, the second chip 60 includes a second semiconductor substrate 61A and a third insulating layer 62. The second chip 60 includes a structure in which the second semiconductor substrate 61A and the third insulating layer 62 are laminated in the Z direction. The second semiconductor substrate 61A includes a second substrate upper surface 61AS facing the opposite side of the second die pad 91 in the Z direction. The second semiconductor substrate 61A is made of a material containing, for example, Si. In one example, an Si substrate is used as the second semiconductor substrate 61A. The second circuit 30 is formed in the second semiconductor substrate 61A.

[0041] Note that each of the semiconductor substrates 51A and 61A may be a wide-gap semiconductor or a compound semiconductor instead of the Si substrate. A wide-gap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. Wide-bandgap semiconductors may be, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ) and the like. The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of aluminum nitride (AlN), indium nitride (InN), GaN, and gallium arsenide (GaAs).

[0042] The third insulating layer 62 is formed on the second substrate upper surface 61AS of the second semiconductor substrate 61A. The third insulating layer 62 includes, for example, at least one of a silicon oxide film and a silicon nitride film. A third external electrode 64A and a fourth external electrode 64B are formed on the third insulating layer 62. Here, the third external electrode 64A and the fourth external electrode 64B are an example of the "external electrode".

[0043] The third insulating layer 62 is provided with a third connection wiring 65 and a fourth connection wiring 66. The third connection wiring 65 is configured to electrically connect the second circuit 30 formed on the second semiconductor substrate 61A and the third external electrode 64A. The fourth connection wiring 66 is configured to electrically connect the second circuit 30 and the fourth external electrode 64B. In one example, the third connection wiring 65 and the fourth connection wiring 66 are constituted by vias extending in the Z direction from the second circuit 30.

[0044] The second chip 60 is joined to the second die pad 91 by the second bonding material 152. The second bonding material 152 is interposed in the Z direction between the second semiconductor substrate 61A and the second die pad 91. In the first embodiment, a conductive bonding material is used as the second bonding material 152. As the conductive bonding material, for example, solder paste, Ag paste, etc. are used.

[0045] The first chip 50 is electrically connected to the first lead frame 80 by a conductive connection member. For example, as shown in FIG. 2, the first chip 50 and the first lead frame 80 are electrically connected by a wire W1. More specifically, a plurality of first external electrodes 55A of the first chip 50 and a plurality of first leads 82 are individually connected by a plurality of wires W1. Some of the plurality of wires W1 are individually connected to a pair of first leads 82A integrated with the first die pad 81. In the first embodiment, a pair of first leads 82A integrated with the first die pad 81 constitutes a ground terminal. Therefore, the first die pad 81 has the same potential as the ground GND1 (see FIG. 1) of the first circuit 20.

[0046] The first chip 50 and the second chip 60 are electrically connected by a conductive connection member. For example, the first chip 50 and the second chip 60 are electrically connected by a wire W2. More specifically, a plurality of second external electrodes 55B, 55C of the first chip 50 and a plurality of third external electrodes 64A of the second chip 60 are individually connected by a plurality of wires W2. Here, the wire W2 is an example of a "conductive connection member".

[0047] The second chip 60 is electrically connected to the second lead frame 90 by a conductive bonding material. For example, the second chip 60 is electrically connected to the second lead frame 90 by a wire W3. More specifically, a plurality of fourth external electrodes 64B of the second chip 60 and a plurality of second leads 92 are individually connected by a plurality of wires W3. Some of the plurality of wires W3 are individually connected to a pair of second leads 92A integrated with the second die pad 91. In the first embodiment, a pair of second leads 92A integrated with the second die pad 91 constitutes a ground terminal. Therefore, the second die pad 91 has the same potential as the ground GND2 (see FIG. 1) of the second circuit 30. Each of the wires W1 to W3 is a bonding wire formed by a wire bonding apparatus and is composed of a conductor containing, for example, gold (Au), Al, Cu, or the like.

[0048] (Configuration of the First Chip) With reference to FIGS. 4 to 6, an example of the configuration of the first chip 50 will be described. FIG. 4 schematically shows the planar structure of the first chip 50. FIG. 5 schematically shows the planar structure of the first semiconductor element 51 of the first chip 50. In FIG. 5, the region where the first circuit 20 is formed is indicated by a two-dot chain line. FIG. 6 schematically shows the cross-sectional structure obtained by cutting the first chip 50, the first bonding material 151, and the first die pad 81 along the line F6-F6 of FIG. 4.

[0049] As shown in FIG. 5, the first semiconductor element 51 has element side surfaces 51C to 51F that connect the element upper surface 51S and the element lower surface 51R (see FIG. 6). The element side surfaces 51C and 51D constitute the end faces of the first semiconductor element 51 in the X direction. The element side surfaces 51E and 51F constitute the end faces of the first semiconductor element 51 in the Y direction.

[0050] In the example shown in FIG. 5, the first circuit 20 is formed in a rectangular shape that is slightly smaller than the first semiconductor element 51 in the X and Y directions. Note that the formation range of the first circuit 20 on the first semiconductor substrate 51A can be arbitrarily changed in a plan view. The first substrate lower surface 51AR is bonded to the first die pad 81 by the first bonding material 151.

[0051] The first insulating upper surface 51BS of the first element insulating layer 51B constitutes the element upper surface 51S. The first coils 41 of the transformers 40A and 40B provided in the first element insulating layer 51B are arranged at positions overlapping the first circuit 20 in a plan view. The first coils 41 of the transformers 40A and 40B are arranged at the same positions in the X direction and separated from each other in the Y direction. In one example, the first coil 41 of the transformer 40A is arranged closer to the element side surface 51E than the first coil 41 of the transformer 40B. Also, these first coils 41 are arranged closer to the element side surface 51C in the X direction. Further, as shown in FIG. 6, the first coils 41 of the transformers 40A and 40B are arranged at the same positions in the Z direction. In one example, the first coils 41 of the transformers 40A and 40B are formed of a material containing Al. In one example, the first coil 41 is formed of an Al wiring.

[0052] As shown in FIG. 5, each first coil 41 is formed in a spiral shape in a plan view. In one example, each first coil 41 may be formed in an oval shape having a length in the X direction larger than a length in the Y direction and including semi-circular shapes at both ends in the X direction in a plan view. Each first coil 41 can have an arbitrary shape such as an oval shape or a square shape with rounded corners in a plan view. Each first coil 41 includes a first inner peripheral end portion 44 and a first outer peripheral end portion 45. The first inner peripheral end portion 44 constitutes the first end on the inner peripheral side of the first coil 41. The first outer peripheral end portion 45 constitutes the second end on the outer peripheral side of the first coil 41.

[0053] The plurality of first external electrodes 55A are arranged closer to the element side surface 51D than the first coils 41 of the transformers 40A and 40B in the X direction. In one example, the plurality of first external electrodes 55A are arranged at positions overlapping the first circuit 20 in a plan view. In one example, the plurality of first external electrodes 55A are arranged at the ends closer to the element side surface 51D among both ends in the X direction of the first semiconductor element 51 in a plan view. The plurality of first external electrodes 55A are arranged at the same positions in the X direction and separated from each other in the Y direction.

[0054] As shown in FIG. 6, the first element insulating layer 51B includes a stacked structure of a plurality of insulating films. In one example, the first element insulating layer 51B includes a first insulating film 51BA formed on the upper surface 51AS of the first substrate, a second insulating film 51BB formed on the first insulating film 51BA, and a third insulating film 51BC formed on the second insulating film 51BB.

[0055] In the first insulating film 51BA, a first connection wiring 56 that connects the first circuit 20 and the first external electrode 55A is formed. In one example, the first connection wiring 56 is a plurality of vias extending in the Z direction. The first connection wiring 56 is disposed at a position overlapping the first circuit 20 in a plan view. In the second insulating film 51BB, a first coil 41 is formed. More specifically, in the second insulating film 51BB, a first coil groove penetrating the second insulating film 51BB in the Z direction is formed. The conductive layer constituting the first coil 41 is embedded in the first coil groove of the second insulating film 51BB. The first coil 41 is covered by the first insulating film 51BA and the third insulating film 51BC in the Z direction. Therefore, it can be said that the first coil 41 is embedded in the first element insulating layer 51B. The third insulating film 51BC constitutes the first insulating upper surface 51BS that is the upper surface of the first semiconductor element 51.

[0056] In the first insulating film 51BA and the second insulating film 51BB, an internal electrode 70 that connects the first circuit 20 and the first coil 41 is formed. The internal electrode 70 includes an inner peripheral electrode 70A that connects the first inner peripheral end portion 44 of the first coil 41 and the first circuit 20, and an outer peripheral electrode 70B that connects the first outer peripheral end portion 45 of the first coil 41 and the first circuit 20. Here, the inner peripheral electrode 70A is an example of the "first internal electrode", and the outer peripheral electrode 70B is an example of the "second internal electrode".

[0057] As shown in FIG. 5, the inner peripheral electrode 70A is formed in the inner region of the first coil 41. The inner region of the first coil 41 is a region located inside the first coil 41 with respect to the first inner peripheral end portion 44 of the first coil 41 in a plan view and is a region where the first coil 41 is not formed. The inner peripheral electrode 70A includes an inner via 71A electrically connected to the first circuit 20, an inner pad 72A electrically connected to the inner via 71A, and an inner connection wiring 73A electrically connecting the inner pad 72A and the first inner peripheral end portion 44 of the first coil 41.

[0058] The inner via 71A is a via penetrating the first insulating film 51BA in the Z direction. The inner via 71A is disposed at a position overlapping the first circuit 20 and the inner pad 72A in a plan view. As shown in FIG. 6, the inner pad 72A is an electrode pad formed on the second insulating film 51BB. The inner connection wiring 73A is a wiring layer connecting the inner pad 72A and the first inner peripheral end portion 44 of the first coil 41 in the second insulating film 51BB. As shown in FIG. 5, the inner connection wiring 73A is a wiring layer extending in the Y direction from the inner pad 72A toward the first inner peripheral end portion 44 of the first coil 41 in a plan view.

[0059] The outer peripheral electrode 70B is formed outside the first coil 41 in a plan view. In one example, the outer peripheral electrode 70B is disposed closer to the element side surface 51C and closer to the element side surface 51E with respect to the first coil 41 in a plan view. The outer peripheral electrode 70B includes an outer via 71B electrically connected to the first circuit 20, an outer pad 72B electrically connected to the outer via 71B, and an outer connection wiring 73B electrically connecting the outer pad 72B and the first outer peripheral end portion 45 of the first coil 41.

[0060] The outer via 71B is a via that penetrates the first insulating film 51BA in the Z direction. The outer via 71B is disposed at a position overlapping the first circuit 20 and the outer pad 72B in a plan view. As shown in FIG. 6, the outer pad 72B is an electrode pad formed on the second insulating film 51BB. The outer connection wiring 73B is a wiring layer that connects the outer pad 72B and the first outer peripheral end portion 45 of the first coil 41 in the second insulating film 51BB. As shown in FIG. 5, the outer connection wiring 73B is a wiring layer that extends in the X direction from the outer pad 72B toward the first outer peripheral end portion 45 of the first coil 41 in a plan view.

[0061] As shown in FIG. 6, the third insulating film 51BC includes openings 58A that expose each of the plurality of first external electrodes 55A in the Z direction. In the example shown in FIG. 5, the opening 58A is formed in a rectangular shape in a plan view. The opening 58A is slightly smaller than the first external electrode 55A in a plan view. The opening 58A exposes a region inside the outer peripheral edge of the first external electrode 55A in a plan view.

[0062] The material constituting each of the inner via 71A, the outer via 71B, the inner pad 72A, the outer pad 72B, the inner connection wiring 73A, the outer connection wiring 73B, the first connection wiring 56, and the first external electrode 55A is appropriately selected from one or more of, for example, Al, Cu, titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0063] As shown in FIG. 4, the first insulating layer 52 is smaller than the first semiconductor element 51 in a plan view. In one example, the dimension of the first insulating layer 52 in the X direction is smaller than the dimension of the first semiconductor element 51 in the X direction. In one example, the dimension of the first insulating layer 52 in the Y direction is equal to the dimension of the first semiconductor element 51 in the Y direction. The first insulating layer 52 is formed so as to overlap with the entire first coil 41 of the transformers 40A and 40B in a plan view. The first insulating layer 52 is disposed offset in the X direction with respect to the first semiconductor element 51 in a plan view. In one example, the first insulating layer 52 is disposed closer to the element side surface 51C of the first semiconductor element 51. As a result, the plurality of first external electrodes 55A are disposed at positions different from the first insulating layer 52 in the X direction in a plan view. In one example, the first insulating layer 52 has side surfaces flush with the respective element side surfaces 51C, 51E, and 51F of the first semiconductor element 51. In this embodiment, the first insulating layer 52 is composed of a single layer. Note that the first insulating layer 52 may have a stacked structure of a plurality of organic insulating layers.

[0064] The second insulating layer 53 is formed in a region overlapping with the first insulating layer 52 in a plan view. In one example, the second insulating layer 53 is formed over the entire upper surface of the first insulating layer 52. That is, the dimensions of the second insulating layer 53 in the X direction and the Y direction are the same as those of the first insulating layer 52. The second insulating layer 53 has a second insulating upper surface 53S facing the side opposite to the first semiconductor element 51.

[0065] The second insulating layer 53 includes a plurality of stacked structures. In one example, the second insulating layer 53 includes an insulating film 53A and a passivation film 53B. The passivation film 53B constitutes the second insulating upper surface 53S. The second coil 42 of the transformers 40A and 40B is provided in the insulating film 53A. More specifically, a second coil groove penetrating the insulating film 53A in the Z direction is formed in the insulating film 53A. The conductive layer constituting the second coil 42 is embedded in the second coil groove of the insulating film 53A.

[0066] The second coils 42 of the transformers 40A and 40B are arranged at the same position in the X direction and separated from each other in the Y direction. In one example, the second coil 42 of the transformer 40A is arranged closer to the element side surface 51E than the second coil 42 of the transformer 40B. Also, these second coils 42 are arranged closer to the element side surface 51C in the X direction. In one example, the second coil 42 of the transformer 40A is arranged at a position overlapping the first coil 41 of the transformer 40A in a plan view. The second coil 42 of the transformer 40B is arranged at a position overlapping the first coil 41 of the transformer 40B in a plan view.

[0067] As shown in FIG. 6, the second coils 42 of the transformers 40A and 40B are arranged at the same position in the Z direction. In the example shown in FIG. 6, the second coils 42 of the transformers 40A and 40B are formed on the first insulating layer 52 so as to be in contact with the upper surface of the first insulating layer 52. The second coil 42 of the transformer 40A is arranged to face the first coil 41 of the transformer 40A in the Z direction with the first element insulating layer 51B and the first insulating layer 52 interposed therebetween. More specifically, the second coil 42 of the transformer 40A is arranged to face the first coil 41 of the transformer 40A in the Z direction with the third insulating film 51BC and the first insulating layer 52 interposed therebetween. The second coil 42 of the transformer 40B is arranged to face the first coil 41 of the transformer 40B in the Z direction with the first element insulating layer 51B and the first insulating layer 52 interposed therebetween. More specifically, the second coil 42 of the transformer 40B is arranged to face the first coil 41 of the transformer 40B in the Z direction with the third insulating film 51BC and the first insulating layer 52 interposed therebetween. In one example, the second coils 42 of the transformers 40A and 40B are made of a material containing Cu. In one example, the second coil 42 is made of Cu.

[0068] As shown in FIG. 4, each second coil 42 is formed in a spiral shape in a plan view. In one example, each second coil 42 may be formed in an oval shape having a length in the X direction larger than a length in the Y direction in a plan view and including semi-circular shapes at both ends in the X direction. Each second coil 42 can have an arbitrary shape such as an oval shape or a square shape with rounded corners in a plan view. Each second coil 42 includes a second inner peripheral end portion 46 and a second outer peripheral end portion 47. The second inner peripheral end portion 46 constitutes the first end on the inner peripheral side of the second coil 42. The second outer peripheral end portion 47 constitutes the second end on the outer peripheral side of the second coil 42.

[0069] The insulating film 53A is provided with second external electrodes 55B and 55C and second connection wirings 57A and 57B that connect the second external electrodes 55B and 55C to the second coil 42. Therefore, it can be said that the second external electrodes 55B and 55C and the second connection wirings 57A and 57B are arranged at the same position as each other in the Z direction. As shown in FIG. 4, the second external electrode 55B is electrically connected to the second inner peripheral end portion 46 of the second coil 42 by the second connection wiring 57A. The second external electrode 55C is electrically connected to the second outer peripheral end portion 47 of the second coil 42 by the second connection wiring 57B.

[0070] The second external electrode 55B is arranged at a position overlapping with the inner region 43 of the second coil 42 in a plan view. The second connection wiring 57A is a wiring that extends in the Y direction from the second inner peripheral end portion 46 of the second coil 42 toward the second external electrode 55B in a plan view. In one example, the second connection wiring 57A is arranged at a position overlapping with the second inner peripheral end portion 46 and the second external electrode 55B of the second coil 42 when viewed from the Y direction.

[0071] The second external electrode 55C is formed outside the second coil 42 in a plan view. In one example, the second external electrode 55C is arranged closer to the element side surface 51C and closer to the element side surface 51E than the second coil 42 in a plan view. The second connection wiring 57A is a wiring that extends in the X direction from the second outer peripheral end portion 47 toward the second external electrode 55B in a plan view. In one example, the second connection wiring 57B is arranged at a position overlapping the second outer peripheral end portion 47 of the second coil 42 and the second external electrode 55C when viewed from the X direction.

[0072] Each of the second external electrodes 55B, 55C and the second connection wirings 57A, 57B is made of a material containing, for example, Cu. Note that the material constituting each of the second external electrodes 55B, 55C and the second connection wirings 57A, 57B can be arbitrarily changed, and may be appropriately selected from one or more of Al, Ti, TiN, and W, for example.

[0073] As shown in FIG. 6, the passivation film 53B is formed on the insulating film 53A. The passivation film 53B covers the second coils 42 of the transformers 40A, 40B. In one example, the passivation film 53B is formed over the entire upper surface of the insulating film 53A. The passivation film 53B includes openings 58B that expose each of the plurality of second external electrodes 55B, 55C in the Z direction. In the example shown in FIG. 4, the openings 58B are formed in a rectangular shape in a plan view. The openings 58B are slightly smaller than the second external electrodes 55B, 55C in a plan view. The openings 58B expose a region inside the outer peripheral edges of the second external electrodes 55B, 55C in a plan view.

[0074] As shown in FIG. 6, the thickness relationship in the first chip 50 of the first embodiment is as follows. The thickness TA1 of the first insulating layer 52 is thicker than the thickness TB1 of the first coil 41. In other words, the thickness TA1 of the first insulating layer 52 is thicker than the thickness of the second insulating film 51BB. The thickness TA1 of the first insulating layer 52 is thicker than the thickness TB2 of the second coil 42. In other words, the thickness TA1 of the first insulating layer 52 is thicker than the thickness of the insulating film 53A. The thickness TA1 of the first insulating layer 52 is thicker than the thickness TA2 of the first element insulating layer 51B. In one example, the thickness TA1 of the first insulating layer 52 is thicker than twice the thickness TA2 of the first element insulating layer 51B. The thickness TA1 of the first insulating layer 52 is thicker than the thickness TA3 of the second insulating layer 53. In one example, the thickness TA1 of the first insulating layer 52 is thicker than the sum of the thickness TA2 of the first element insulating layer 51B and the thickness TA3 of the second insulating layer 53 (TA1>TA2 + TA3). In one example, the thickness TA1 of the first insulating layer 52 is 8 μm. The thickness TB2 of the second coil 42 is thicker than the thickness TB1 of the first coil 41.

[0075] (Method for manufacturing the first chip) Next, an example of the manufacturing method of the first chip 50 will be described. The first chip 50 of the first embodiment is formed by diverting the process of WLCSP (Wafer-Level Chip-Size Packaging). In the description of the manufacturing method of the first chip 50, refer to the reference numerals of the first chip 50 in FIGS. 1 to 6 for the reference numerals of each component of the first chip 50.

[0076] The manufacturing method of the first chip 50 includes a step of preparing a first semiconductor substrate 51A on which the first circuit 20 is formed. The first semiconductor substrate 51A is constituted by a semiconductor wafer. In one example, the first semiconductor substrate 51A is constituted by a Si wafer. The semiconductor wafer is configured to include a plurality of first semiconductor substrates 51A. The first circuit 20 is formed on each first semiconductor substrate 51A.

[0077] Subsequently, the manufacturing method of the first chip 50 includes a step of forming a first element insulating layer 51B on the first semiconductor substrate 51A. Here, a part of the step of forming the first element insulating layer 51B on the first semiconductor substrate 51A is carried out. That is, a first insulating film 51BA is formed on the first semiconductor substrate 51A. The first insulating film 51BA is composed of an inorganic insulating film. The first insulating film 51BA is formed on the first substrate upper surface 51AS of the first semiconductor substrate 51A by, for example, a CVD (Chemical Vapor Deposition) method.

[0078] Subsequently, the manufacturing method of the first chip 50 includes a step of forming an inner via 71A of the internal electrode 70 and a first connection wiring 56 in the first element insulating layer 51B in the first insulating film 51BA. The inner via 71A and the first connection wiring 56 are formed in the first insulating film 51BA of the first element insulating layer 51B. The inner via 71A, the outer via 71B, and the first connection wiring 56 penetrate the first insulating film 51BA in the Z direction. The inner via 71A, the outer via 71B, and the first connection wiring 56 are individually and electrically connected to the first circuit 20. The material constituting each of the inner via 71A, the outer via 71B, and the first connection wiring 56 is appropriately selected from, for example, one or more of Al, Cu, Ti, TiN, and W.

[0079] Subsequently, the step of forming the first element insulating layer 51B on the first semiconductor substrate 51A is carried out again. More specifically, a second insulating film 51BB is formed on the first insulating film 51BA. The second insulating film 51BB is composed of an inorganic insulating film. The second insulating film 51BB is formed by, for example, the CVD method in the same manner as the first insulating film 51BA.

[0080] Subsequently, the manufacturing method of the first chip 50 includes a step of forming the first coils 41 of the transformers 40A and 40B in the first element insulating layer 51B. The step of forming the first coil 41 includes, for example, a step of forming a coil groove that penetrates the second insulating film 51BB in the Z direction, and a step of filling the coil groove with a conductive layer. The coil groove is formed in a spiral shape in plan view. Therefore, the conductive layer filled in the coil groove is formed in a spiral shape in plan view. Thereby, the first coil 41 is formed. Also, this conductive layer is in contact with the upper surface of the first insulating film 51BA. That is, the first coil 41 is in contact with the upper surface of the first insulating film 51BA.

[0081] In addition, the manufacturing method of the first chip 50 includes a step of forming a plurality of first external electrodes 55A, and inner pads 72A, outer pads 72B, inner connection wirings 73A, and outer connection wirings 73B of the internal electrode 70 in the first element insulating layer 51B. Each of the plurality of first external electrodes 55A, the inner pads 72A, the outer pads 72B, the inner connection wirings 73A, and the outer connection wirings 73B is formed in the second insulating film 51BB. Each of the plurality of first external electrodes 55A, the inner pads 72A, the outer pads 72B, the inner connection wirings 73A, and the outer connection wirings 73B penetrates the second insulating film 51BB in the Z direction. The inner pad 72A is in contact with the inner via 71A. The inner connection wiring 73A connects the inner pad 72A and the first coil 41. The outer pad 72B is in contact with the outer via 71B. The outer connection wiring 73B connects the outer pad 72B and the first coil 41. The first external electrode 55A is in contact with the first connection wiring 56. The conductive layer is composed of, for example, Al. That is, the first coil 41 is formed of Al. The inner pads 72A, the outer pads 72B, the inner connection wirings 73A, and the outer connection wirings 73B are appropriately selected from, for example, one or more of Al, Cu, Ti, TiN, and W.

[0082] In the manufacturing method of the first chip 50, the step of forming the first coils 41 of the transformers 40A and 40B in the first element insulating layer 51B, and the step of forming a plurality of first external electrodes 55A and the inner pads 72A, outer pads 72B, inner connection wirings 73A, and outer connection wirings 73B of the internal electrode 70 in the first element insulating layer 51B may be implemented as common steps.

[0083] Subsequently, the step of forming the first element insulating layer 51B on the first semiconductor substrate 51A is implemented again. More specifically, this step includes the step of forming the third insulating film 51BC on the second insulating film 51BB. The third insulating film 51BC is composed of an inorganic insulating film. The third insulating film 51BC is formed, for example, by the CVD method in the same manner as the first insulating film 51BA. The third insulating film 51BC is formed so as to contact the upper surfaces of the inner pads 72A of the internal electrode 70, the upper surfaces of the outer pads 72B, the upper surfaces of the inner connection wirings 73A, the upper surfaces of the outer connection wirings 73B, the upper surface of the first coil 41, and the upper surfaces of the first external electrodes 55A. The step of forming the first element insulating layer 51B on the first semiconductor substrate 51A includes the step of forming an opening 58A in the third insulating film 51BC. The opening 58A is formed, for example, by exposing and developing the third insulating film 51BC. Thereby, the first external electrodes 55A are exposed from the third insulating film 51BC through the opening 58A. Note that the first to third insulating films 51BA to 51BC may be formed by a thermal oxidation method instead of the CVD method.

[0084] Subsequently, the manufacturing method of the first chip 50 includes a step of forming a first insulating layer 52 so as to cover the first insulating upper surface 51BS of the first element insulating layer 51B. The first insulating layer 52 is formed of an organic insulating layer. In the first embodiment, the first insulating layer 52 is composed of a single layer. Note that the first insulating layer 52 may have a stacked structure of a plurality of organic insulating layers. The organic insulating layer is formed of a material containing, for example, polyimide or polybenzoxazole. In one example, an organic insulating layer thicker than the first element insulating layer 51B is used. Therefore, the thickness TA1 of the first insulating layer 52 is greater than the thickness TA2 of the first element insulating layer 51B. The step of forming the first insulating layer 52 includes a step of applying an organic insulating layer on the first element insulating layer 51B. In one example, the number of times of applying the organic insulating layer is one. The organic insulating layer is formed, for example, over the entire upper surface of the third insulating film 51BC. Subsequently, the step of forming the first insulating layer 52 includes a step of removing the opening 58A and its periphery in the organic insulating layer by exposure and development. As a result, a part of the first insulating upper surface 51BS of the first element insulating layer 51B is exposed from the first insulating layer 52.

[0085] Subsequently, the manufacturing method of the first chip 50 includes a step of forming a second insulating layer 53 that covers the first insulating layer 52. In one example, the insulating film 53A is formed over the entire upper surface of the first insulating layer 52. The insulating film 53A is formed of an organic insulating layer, for example. The insulating film 53A is formed, for example, by applying an organic insulating layer on the first insulating layer 52.

[0086] Subsequently, the manufacturing method of the first chip 50 includes a step of forming the second coils 42 of the transformers 40A and 40B on the first insulating layer 52 in the second insulating layer 53. The step of forming the second coils 42 includes, for example, a step of forming coil grooves penetrating the insulating film 53A in the Z direction, and a step of filling the coil grooves with a conductive layer. The coil grooves are formed in a spiral shape in a plan view. Therefore, the conductive layer filled in the coil grooves is formed in a spiral shape in a plan view. Thereby, the second coils 42 are formed. Also, this conductive layer is in contact with the upper surface of the first insulating layer 52. That is, the second coils 42 are in contact with the upper surface of the first insulating layer 52. The conductive layer is composed of, for example, Cu. That is, the second coils 42 are formed of Cu.

[0087] Further, the manufacturing method of the first chip 50 includes a step of forming a plurality of second external electrodes 55B and second connection wirings 57A and 57B in the second insulating layer 53. Each of the plurality of second external electrodes 55B and second connection wirings 57A and 57B is formed so as to penetrate the insulating film 53A. Therefore, each of the plurality of second external electrodes 55B and second connection wirings 57A and 57B is in contact with the upper surface of the first insulating layer 52. The plurality of second external electrodes 55B and the second connection wirings 57A and 57B are formed of, for example, Cu. The insulating film 53A, the second coils 42, the plurality of second external electrodes 55B, and the second connection wirings 57A and 57B constitute a rewiring layer. Note that the materials of the second coils 42, the plurality of second external electrodes 55B, and the second connection wirings 57A and 57B can be arbitrarily changed.

[0088] Subsequently, the step of forming the second insulating layer 53 covering the first insulating layer 52 is performed again. More specifically, a passivation film 53B is formed on the insulating film 53A. The passivation film 53B is formed of, for example, an organic insulating film. The step of forming the passivation film 53B includes a step of applying an organic insulating film on the insulating film 53A. The organic insulating film is applied over the entire upper surface of the insulating film 53A. Subsequently, the step of forming the passivation film 53B includes a step of forming an opening 58B by exposure and development. The second external electrode 55B is exposed from the passivation film 53B through the opening 58B.

[0089] Subsequently, the method for manufacturing the first chip 50 includes a singulation step. By this step, the first chip 50 is formed. In one example, this step includes a step of cutting a semiconductor wafer for each region where the first chip 50 is to be formed using, for example, a dicing blade. In this case, the second insulating layer 53, the first insulating layer 52, and the first element insulating layer 51B are also cut. Through the above steps, the first chip 50 is manufactured.

[0090] [Operation of the First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described. In the first chip as a through-chip, improvement in breakdown voltage may be required. The breakdown voltage of the first chip is mainly determined by the distance between the first coil 41 and the second coil 42. Therefore, in order to improve the breakdown voltage, it is conceivable to increase the distance between the first coil 41 and the second coil 42. Here, in a configuration in which the first coil 41 and the second coil 42 are arranged to face each other in an insulating layer formed on the same semiconductor substrate, in order to increase the distance between the first coil 41 and the second coil 42, it is necessary to thicken the insulating layer. However, since the number of insulating film layers is increased to thicken the insulating layer, the time required for forming the insulating layer increases. As a result, the manufacturing lead time of the first chip becomes longer.

[0091] In this regard, in the first chip 50 of the semiconductor device 10 of the first embodiment, the first insulating layer 52 formed of an organic insulating layer is interposed between the first coil 41 formed in the first element insulating layer 51B formed on the first semiconductor substrate 51A and the second coil 42 formed in the second insulating layer 53.

[0092] When forming an insulating layer using an organic insulating layer, a single insulating film can be formed thicker compared to the case of forming an insulating layer using an inorganic insulating layer. In the first embodiment, since a part of the insulating layer (first insulating layer 52) interposed between the first coil 41 and the second coil 42 is constituted by an organic insulating layer, the number of stacked insulating films interposed between the first coil 41 and the second coil 42 can be reduced. Therefore, the time required for forming the insulating layer interposed between the first coil 41 and the second coil 42 is shorter compared to the case where the insulating layer interposed between the first coil 41 and the second coil 42 is constituted by a stacked structure of inorganic insulating layers. In particular, in the first embodiment, since the first insulating layer 52 is constituted by a single-layer organic insulating layer, the time required for forming the insulating layer is further shortened. Therefore, the manufacturing lead time of the first chip 50 can be shortened. In addition, the thickness of the organic insulating layer can be easily adjusted. For this reason, the distance between the first coil 41 and the second coil 42 can be adjusted by changing the thickness TA1 of the first insulating layer 52. Therefore, it is possible to easily provide the first chip 50 having different breakdown voltages without changing the configurations of the first semiconductor element 51 and the second insulating layer 53.

[0093] [Effects of the First Embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a first die pad 81, a first chip 50 mounted on the first die pad 81 and including a first circuit 20, a second die pad 91 disposed apart from the first die pad 81 in the X direction, and a second chip 60 mounted on the second die pad 91 and including a second circuit 30. The first chip 50 includes a first semiconductor substrate 51A on which the first circuit 20 is formed, a first element insulating layer 51B formed on the first semiconductor substrate 51A, and a first coil 41 provided in the first element insulating layer 51B and electrically connected to the first circuit 20. The first semiconductor element 51 includes a first insulating upper surface 51BS of the first element insulating layer 51B facing away from the first semiconductor substrate 51A, a first insulating layer 52 formed of an organic insulating layer covering the first insulating upper surface 51BS, a second coil 42 formed on the first insulating layer 52 and disposed to face the first coil 41 in the Z direction with the first element insulating layer 51B and the first insulating layer 52 interposed therebetween and electrically connected to the second circuit 30, and a second insulating layer 53 covering the first insulating layer 52 and the second coil 42.

[0094] According to this configuration, the first insulating layer 52 of the organic insulating layer is interposed between the first coil 41 and the second coil 42. The first insulating layer 52 is provided separately from the first element insulating layer 51B. Since the first insulating layer 52 of the organic insulating layer can be easily thickened as compared with an inorganic insulating layer, the number of stacked insulating layers interposed between the first coil 41 and the second coil 42 can be reduced. Thereby, the manufacturing lead time of the first chip 50 can be shortened. Therefore, the manufacturing cost of the semiconductor device 10 can be reduced.

[0095] Furthermore, the first insulating layer 52 and the second insulating layer 53 are provided separately from the first semiconductor element 51. For this reason, the distance in the Z direction between the first coil 41 and the second coil 42 can be adjusted by changing the thickness TA1 of the first insulating layer 52. In other words, the first semiconductor element 51 can be shared for a plurality of types of first chips 50 having different breakdown voltages. Therefore, the manufacturing costs of a plurality of types of first chips 50 having different breakdown voltages can be reduced.

[0096] (1-2) The first chip 50 includes a first external electrode 55A electrically connected to the first circuit 20, and second external electrodes 55B and 55C electrically connected to the second coil 42. The first insulating layer 52 exposes a part of the first insulating upper surface 51BS. The first external electrode 55A is disposed at a position different from that of the first insulating layer 52 in the first element insulating layer 51B when viewed from the Z direction, and is exposed from the first insulating upper surface 51BS.

[0097] According to this configuration, the first external electrode 55A is exposed from the first insulating upper surface 51BS in the Z direction. Therefore, for example, when forming the wire W1 on the first external electrode 55A by a wire bonding device, it is possible to suppress the formation of the wire W1 from being hindered by the first insulating layer 52.

[0098] (1-3) The first chip 50 includes a first external electrode 55A electrically connected to the first circuit 20, and second external electrodes 55B and 55C electrically connected to the second coil 42 and the second circuit 30. The first external electrode 55A is located on the side opposite to the second chip 60 in the X direction. The second external electrodes 55B and 55C are located closer to the second chip 60 in the X direction. The semiconductor device 10 includes a first lead 82 that is located on the side opposite to the second chip 60 with respect to the first die pad 81 and is electrically connected to the first external electrode 55A.

[0099] According to this configuration, since the first external electrode 55A is located closer to the first lead 82 than the second external electrodes 55B and 55C, the wire W1 connecting the first external electrode 55A and the first lead 82 can be shortened. Also, since the second external electrodes 55B and 55C are located closer to the second chip 60 than the first external electrode 55A, the wire W2 electrically connecting the second circuit 30 and the second external electrodes 55B and 55C can be shortened.

[0100] (1-4) The thickness TA1 of the first insulating layer 52 is greater than the thickness TA2 of the first element insulating layer 51B. According to this configuration, since the space between the first coil 41 and the second coil 42 is configured by the laminated structure of the first insulating layer 52 and the first element insulating layer 51B, if the thickness TA1 of the first insulating layer 52 is increased, it is not necessary to excessively increase the thickness of the first element insulating layer 51B. In addition, since the first insulating layer 52 is made of an organic insulating layer, it is easy to form a thick film. Therefore, compared with the configuration in which the first element insulating layer 51B is made thicker than the first insulating layer 52, the number of laminated layers of the insulating layer interposed between the first coil 41 and the second coil 42 can be reduced. Therefore, the manufacturing lead time and manufacturing cost of the first chip 50 can be suppressed.

[0101] (1-5) The first insulating layer 52 is made of an organic insulating layer. The organic insulating layer is made of a material containing polyimide or polybenzoxazole. According to this configuration, the organic insulating layer containing polyimide or polybenzoxazole can be easily thickened by applying it on the first element insulating layer 51B. Therefore, since the manufacturing lead time of the first chip 50 can be shortened, the manufacturing cost of the first chip 50 can be reduced.

[0102] (1-6) The second insulating layer 53 is made of an organic insulating layer. According to this configuration, compared with the case where the second insulating layer 53 is made of an inorganic insulating layer, it is easier to thicken the second insulating layer 53. As a result, since the thickness TB2 of the second coil 42 provided in the second insulating layer 53 can be made thicker, the electrical resistance of the second coil 42 can be reduced.

[0103] (1-7) The thickness TA3 of the second insulating layer 53 is thinner than the thickness TA1 of the first insulating layer 52. According to this configuration, by making the second insulating layer 53 thinner than the first insulating layer 52, the first chip 50 can be made thinner.

[0104] (1-8) The thickness TA1 of the first insulating layer 52 is thicker than the sum of the thickness TA2 of the first element insulating layer 51B and the thickness TA3 of the second insulating layer 53. According to this configuration, since the space between the first coil 41 and the second coil 42 is formed by the laminated structure of the first insulating layer 52 and the first element insulating layer 51B, if the thickness TA1 of the first insulating layer 52 is increased, it is not necessary to excessively increase the thickness of the first element insulating layer 51B. In addition, since the first insulating layer 52 is formed of an organic insulating layer, it is easy to form a thick film. Therefore, compared with the configuration in which the first element insulating layer 51B is made thicker than the first insulating layer 52, the number of laminated insulating layers intervening between the first coil 41 and the second coil 42 can be reduced. Accordingly, the manufacturing lead time and manufacturing cost of the first chip 50 can be suppressed.

[0105] (1-9) The first insulating layer 52 is formed of a single-layer organic insulating layer. According to this configuration, the manufacturing lead time of the first chip 50 can be shortened as compared with the case where the first insulating layer 52 is formed of, for example, a laminated structure of a plurality of organic insulating layers. Accordingly, the manufacturing cost of the first chip 50 can be reduced.

[0106] <Second Embodiment> With reference to FIGS. 7 to 9, the semiconductor device 10 of the second embodiment will be described. The semiconductor device 10 of the second embodiment is different from the first embodiment in that it includes a double insulation structure by a transformer. Hereinafter, differences from the first embodiment will be described in detail, and the same reference numerals will be given to the components common to the semiconductor device 10 of the first embodiment, and the description thereof will be omitted.

[0107] FIG. 7 schematically shows the electrical configuration of the semiconductor device 10 of the second embodiment. FIG. 8 schematically shows the internal planar structure of the semiconductor device 10 of the second embodiment. FIG. 9 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 of the second embodiment along the line F9-F9 in FIG. 8.

[0108] As shown in FIG. 7, the semiconductor device 10 includes transformers 110A and 110B that electrically insulate between the first circuit 20 and the second circuit 30. In one example, similar to the first embodiment, the transformer 110A is used for transmitting a set signal, and the transformer 110B is used for transmitting a reset signal.

[0109] Transformer 110A includes a first transformer 111A and a second transformer 112A connected in series with each other. The first transformer 111A includes a first coil 121A and a second coil 122A that is electrically insulated from the first coil 121A and configured to be magnetically coupled therewith. The second transformer 112A includes a third coil 123A and a fourth coil 124A that is electrically insulated from the third coil 123A and configured to be magnetically coupled therewith.

[0110] The first coil 121A is electrically connected to the first circuit 20. The first circuit 20 includes a transmission circuit 21 as in the first embodiment. The first coil 121A is electrically connected to the transmission circuit 21. The fourth coil 124A is electrically connected to the second circuit 30. The second circuit 30 includes a reception circuit 31 as in the first embodiment. The fourth coil 124A is electrically connected to the reception circuit 31. The second coil 122A and the third coil 123A are in an electrically floating state and are electrically connected to each other.

[0111] Transformer 110B includes a first transformer 111B and a second transformer 112B connected in series with each other. The first transformer 111B includes a first coil 121B and a second coil 122B that is electrically insulated from the first coil 121B and configured to be magnetically coupled therewith. The second transformer 112B includes a third coil 123B and a fourth coil 124B that is electrically insulated from the third coil 123B and configured to be magnetically coupled therewith.

[0112] The first coil 121B is electrically connected to the first circuit 20. The first coil 121B is electrically connected to the transmission circuit 21. The fourth coil 124B is electrically connected to the second circuit 30. The fourth coil 124B is electrically connected to the reception circuit 31. The second coil 122B and the third coil 123B are in an electrically floating state and are electrically connected to each other.

[0113] The semiconductor device 10 includes a first chip 50P and a second chip 60P. The second chip 60P of the second embodiment is different from the second chip 60 of the first embodiment in that it has an insulation structure by second transformers 112A and 112B. Note that the arrangements of the first chip 50P and the second chip 60P are the same as those of the first chip 50 and the second chip 60 of the first embodiment. Here, in the second embodiment, the first chip 50P and the second chip 60P are each an example of a "semiconductor chip".

[0114] The first chip 50P of the second embodiment has the same configuration as the first chip 50 of the first embodiment. The first chip 50P includes first transformers 111A and 111B of transformers 110A and 110B instead of the first coil 41 and the second coil 42 of the transformers 40A and 40B of the first chip 50 of the first embodiment. The configurations and arrangements of the first coils 121A and 121B and the second coils 122A and 122B of the first transformers 111A and 111B are the same as those of the first coil 41 and the second coil 42 of the first embodiment. That is, the first coils 121A and 121B and the second coils 122A and 122B are arranged to face each other in the Z direction with the first element insulation layer 51B and the first insulation layer 52 interposed therebetween. Here, in the second embodiment, the first coils 121A and 121B of the first transformers 111A and 111B are an example of a "first conductor". The second coils 122A and 122B of the first transformers 111A and 111B are an example of a "second conductor".

[0115] The second chip 60P includes second transformers 112A and 112B of transformers 110A and 110B. As shown in FIG. 8, the second chip 60P includes a plurality of third external electrodes 69A and a plurality of fourth external electrodes 69B and 69C. The plurality of third external electrodes 69A are electrically connected to the second circuit 30 (see FIG. 7). The plurality of fourth external electrodes 69B and 69C are electrically connected to the third coils 123A and 123B of the second transformers 112A and 112B.

[0116] The semiconductor device 10 of the second embodiment includes a plurality of wires W1 to W3, similar to the semiconductor device 10 of the first embodiment. The plurality of wires W1 individually connect the plurality of first leads 82 of the first lead frame 80 and the plurality of first external electrodes 55A of the first chip 50P. The plurality of wires W2 individually connect the plurality of second external electrodes 55B and 55C of the first chip 50P and the plurality of fourth external electrodes 69B and 69C of the second chip 60P. The plurality of wires W3 individually connect the plurality of third external electrodes 69A of the second chip 60P and the plurality of second leads 92.

[0117] As shown in FIG. 9, each of the first coils 121A and 121B of the first transformers 111A and 111B is provided in the first element insulating layer 51B. Each of the second coils 122A and 122B of the first transformers 111A and 111B is provided in the second insulating layer 53. The first coil 121A of the first transformer 111A in the first chip 50P is electrically connected to the first external electrode 55A. The second coil 122A is electrically connected to the second external electrodes 55B and 55C. Although not shown, the first coil 121B of the first transformer 111B in the first chip 50P is electrically connected to the first external electrode 55A. The second coil 122B is electrically connected to the second external electrodes 55B and 55C.

[0118] The second chip 60P has the same configuration as the first chip 50P. The second chip 60P includes a second semiconductor element 61 including a second semiconductor substrate 61A, a second element insulating layer 61B, and fourth coils 124A and 124B of second transformers 112A and 112B. The second chip 60P also includes a third insulating layer 67, a fourth insulating layer 68, and third coils 123A and 123B of second transformers 112A and 112B. Here, in the second embodiment, the fourth coils 124A and 124B of the second transformers 112A and 112B are an example of a "third conductor". The third coils 123A and 123B of the second transformers 112A and 112B are an example of a "fourth conductor".

[0119] The second semiconductor substrate 61A is a Si substrate, similar to the first semiconductor substrate 51A. The second semiconductor substrate 61A is different from the first semiconductor substrate 51A in that the second circuit 30 is formed thereon.

[0120] The second element insulating layer 61B has the same configuration as the first element insulating layer 51B of the first chip 50P. In the second element insulating layer 61B, fourth coils 124A and 124B of the second transformers 112A and 112B are provided. The second element insulating layer 61B includes a second insulating upper surface 61BS. The second insulating upper surface 61BS faces the same side as the first insulating upper surface 51BS of the first element insulating layer 51B in the first chip 50P. A plurality of third external electrodes 69A are exposed from the second element insulating layer 61B.

[0121] The third insulating layer 67 has the same configuration as the first insulating layer 52 of the first chip 50P. The fourth insulating layer 68 has the same configuration as the second insulating layer 53 of the first chip 50P. Therefore, the second insulating upper surface 61BS is exposed from the third insulating layer 67. That is, it can be said that a plurality of third external electrodes 69A are exposed from the third insulating layer 67.

[0122] In the fourth insulating layer 68, third coils 123A and 123B of the second transformers 112A and 112B are provided. The configurations and arrangement modes of the third coils 123A and 123B are the same as those of the second coils 122A and 122B. The configurations and arrangement modes of the fourth coils 124A and 124B are the same as those of the first coils 121A and 121B. That is, the third coils 123A and 123B and the fourth coils 124A and 124B are arranged to face each other in the Z direction with the second element insulating layer 61B and the third insulating layer 67 interposed therebetween.

[0123] In the fourth insulating layer 68, fourth external electrodes 69B and 69C are provided. The fourth external electrodes 69B and 69C are exposed from the fourth insulating layer 68 through openings (not shown) provided in the fourth insulating layer 68.

[0124] The third coil 123A of the second transformer 112A in the second chip 60P is electrically connected to the fourth external electrodes 69B and 69C. The fourth coil 124A of the second transformer 112A is electrically connected to the third external electrode 69A. Although not shown, the third coil 123B of the second transformer 112B in the second chip 60P is electrically connected to another pair of fourth external electrodes 69B and 69C. The fourth coil 124B of the second transformer 112B is electrically connected to another third external electrode 69A.

[0125] The thickness relationship of the first chip 50P in the second embodiment is the same as that of the first chip 50 in the first embodiment. The thickness relationship of the second chip 60P is the same as that of the first chip 50P.

[0126] The first chip 50P in the second embodiment is bonded to the first die pad 81 by the first bonding material 151, similar to the first chip 50 in the first embodiment. The second chip 60P is bonded to the second die pad 91 by the second bonding material 152, similar to the second chip 60 in the first embodiment.

[0127] The encapsulating resin 100 encapsulates the first chip 50P, the second chip 60P, the first die pad 81, the second die pad 91, and the wires W1 to W3. The encapsulating resin 100 partially encapsulates each of the plurality of first leads 82 and each of the plurality of second leads 92.

[0128] [Effects of the Second Embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The second chip 60P includes a second semiconductor substrate 61A on which the second circuit 30 is formed, and a second element insulating layer 61B formed on the second semiconductor substrate 61A. The second chip 60P includes a second semiconductor element 61 provided in the second element insulating layer 61B and electrically connected to the second circuit 30, and including third coils 123A and 123B; a third insulating layer 67 covering the second insulating upper surface 61BS of the second element insulating layer 61B and composed of an organic insulating layer; fourth coils 124A and 124B formed on the third insulating layer 67 and arranged to face the third coils 123A and 123B in the Z direction with the second element insulating layer 61B and the third insulating layer 67 interposed therebetween; and a fourth insulating layer 68 covering the third insulating layer 67 and the fourth coils 124A and 124B.

[0129] According to this configuration, the semiconductor device 10 of the second embodiment has a double insulation structure by the first transformers 111A and 111B and the second transformers 112A and 112B connected in series. Therefore, compared with the semiconductor device 10 of the first embodiment, the breakdown voltage insulation of the semiconductor device 10 can be improved.

[0130] (2-2) The second chip 60P includes a third external electrode 69A electrically connected to the second circuit 30, and fourth external electrodes 69B and 69C electrically connected to the fourth coils 124A and 124B. The third insulating layer 67 exposes a part of the second insulating upper surface 61BS. The third external electrode 69A is arranged at a position different from that of the third insulating layer 67 in the second element insulating layer 61B when viewed from the Z direction, and is exposed from the second insulating upper surface 61BS.

[0131] According to this configuration, the third external electrode 69A is exposed from the second insulating upper surface 61BS in the Z direction. Therefore, for example, when forming the wire W3 on the third external electrode 69A by a wire bonding device, it is possible to suppress the formation of the wire W3 from being hindered by the third insulating layer 67.

[0132] (2-3) The second chip 60P includes a third external electrode 69A electrically connected to the second circuit 30, and fourth external electrodes 69B and 69C electrically connected to the third coils 123A and 123B. The third external electrode 69A is located on the side opposite to the first chip 50P in the X direction. The fourth external electrodes 69B and 69C are located closer to the first chip 50P in the X direction. The semiconductor device 10 includes a second lead 92 that is located on the side opposite to the first chip 50P with respect to the second die pad 91 and is electrically connected to the third external electrode 69A.

[0133] According to this configuration, since the third external electrode 69A is located closer to the second lead 92 than the fourth external electrodes 69B and 69C, the wire W3 connecting the third external electrode 69A and the second lead 92 can be shortened. Also, since the fourth external electrodes 69B and 69C are located closer to the first chip 50P than the third external electrode 69A, the wire W2 connecting the second external electrodes 55B and 55C of the first chip 50P and the fourth external electrodes 69B and 69C can be shortened.

[0134] <Third Embodiment> With reference to FIGS. 10 to 12, the semiconductor device 10 of the third embodiment will be described. The semiconductor device 10 of the third embodiment is different from the first embodiment in that the insulation structure by a transformer is changed to an insulation structure by a capacitor. Hereinafter, the points different from the first embodiment will be described in detail, and the same reference numerals will be given to the components common to the semiconductor device 10 of the first embodiment, and the description thereof will be omitted.

[0135] FIG. 10 schematically shows the electrical configuration of the semiconductor device 10 of the third embodiment. FIG. 11 schematically shows the cross-sectional structure of the semiconductor device 10 of the third embodiment. The cross-sectional position of the cross-sectional structure in FIG. 11 is the same as the cross-sectional position of the cross-sectional structure in FIG. 3, for example. FIG. 12 schematically shows the cross-sectional structure of the first chip 50Q described later. The cross-sectional position of the cross-sectional structure in FIG. 12 is the same as the cross-sectional position of the cross-sectional structure in FIG. 6, for example.

[0136] As shown in FIG. 10, the semiconductor device 10 includes capacitors 130A and 130B instead of transformers 40A and 40B. The capacitors 130A and 130B are configured to electrically insulate between the first circuit 20 and the second circuit 30. In one example, similar to the first embodiment, the capacitor 130A is used for transmitting a set signal, and the capacitor 130B is used for transmitting a reset signal.

[0137] The capacitors 130A and 130B include a first electrode 131 and a second electrode 132. The first electrode 131 of the capacitors 130A and 130B is electrically connected to the first circuit 20. The second electrode 132 of the capacitors 130A and 130B is electrically connected to the second circuit 30. Here, the first electrode 131 of the capacitors 130A and 130B is an example of the "first conductor", and the second electrode 132 of the capacitors 130A and 130B is an example of the "second conductor".

[0138] As shown in FIG. 11, the semiconductor device 10 includes a first chip 50Q instead of the first chip 50 of the first embodiment. The first chip 50Q includes the first circuit 20, the capacitors 130A and 130B, a first connection portion 141, and a second connection portion 142. Also, different from the first chip 50, the second external electrodes 55B and 55C (see FIG. 4) are omitted in the first chip 50Q. Also, the second chip 60Q has the same configuration as the second chip 60 of the first embodiment. For this reason, the wire W2 electrically connects the third external electrode 69A of the second chip 60Q and the second electrode 132 of the first chip 50Q. Here, in the third embodiment, the first chip 50Q is an example of the "semiconductor chip".

[0139] The first chip 50Q is mounted on the first die pad 81. The first chip 50Q is bonded to the first die pad 81 by the first bonding material 151. The first bonding material 151 is the same as the first bonding material 151 of the first embodiment.

[0140] As shown in FIG. 12, the first chip 50Q includes a first semiconductor substrate 51A, a first element insulating layer 51B, a first insulating layer 52, and a second insulating layer 53, similar to the first chip 50. The first element insulating layer 51B includes first to third insulating films 51BA to 51BC, similar to the first embodiment. The second insulating layer 53 includes an insulating film 53A and a passivation film 53B, similar to the first embodiment.

[0141] The first electrodes 131 of the capacitors 130A and 130B are provided in the first element insulating layer 51B. The second electrodes 132 of the capacitors 130A and 130B are provided in the second insulating layer 53. The first electrode 131 and the second electrode 132 are formed in a flat plate shape with the Z direction as the thickness direction. In one example, the first electrode 131 and the second electrode 132 are formed in a rectangular shape in plan view. Note that the shapes of the first electrode 131 and the second electrode 132 in plan view can be arbitrarily changed. Here, in the third embodiment, the first electrode 131 and the second electrode 132 are an example of "electrode plates".

[0142] The first electrodes 131 and the second electrodes 132 of the capacitors 130A and 130B are arranged to face each other in the Z direction with the first element insulating layer 51B and the first insulating layer 52 interposed therebetween. The first electrode 131 is arranged closer to the first semiconductor substrate 51A than the second electrode 132 in the Z direction. Both the first electrode 131 and the second electrode 132 are formed in a rectangular flat plate shape with the Z direction as the thickness direction.

[0143] The first electrode 131 is provided in the second insulating film 51BB of the first element insulating layer 51B. More specifically, a first capacitor groove penetrating the second insulating film 51BB in the Z direction is provided in the second insulating film 51BB. The first electrode 131 is formed by embedding a conductive layer in the first capacitor groove. The first electrode 131 is covered by the first insulating film 51BA and the second insulating film 51BB, and the third insulating film 51BC formed on the second insulating film 51BB. Therefore, it can be said that the first electrode 131 is embedded in the first element insulating layer 51B.

[0144] The first external electrode 55A is provided at the same position as the first electrode 131 in the Z direction. The first external electrode 55A is exposed from the first element insulating layer 51B through the opening 58A, similar to the first embodiment. Also, since the second insulating layer 53 has the same shape as in the first embodiment, it can be said that the first external electrode 55A is exposed from the second insulating layer 53.

[0145] The second electrode 132 is provided on the insulating film 53A of the second insulating layer 53. More specifically, the insulating film 53A is provided with a second capacitor groove that penetrates the insulating film 53A in the Z direction. The second electrode 132 is formed by embedding a conductive layer in the second capacitor groove. The second electrode 132 is covered by the insulating film 53A and a passivation film 53B formed on the insulating film 53A. Therefore, it can be said that the second electrode 132 is embedded in the second insulating layer 53.

[0146] The first electrode 131 is electrically connected to the first circuit 20 by the first connection portion 141. The first connection portion 141 is constituted by, for example, a plurality of vias extending in the Z direction so as to penetrate the first insulating film 51BA.

[0147] The first circuit 20 is electrically connected to the first external electrode 55A by the second connection portion 142. The second connection portion 142 includes a via that penetrates the first insulating film 51BA of the first element insulating layer 51B in the Z direction. The second connection portion 142 is arranged at a position overlapping the first external electrode 55A in plan view.

[0148] An opening 58B is formed in the passivation film 53B. The second electrode 132 is exposed through the opening 58B. The portion of the second electrode 132 exposed through the opening 58B constitutes a second external electrode to which the wire W2 is connected. That is, the second electrode 132 also serves as the second external electrode. Note that the second electrode 132 and the "second external electrode" may be provided separately.

[0149] In the third embodiment, the first electrode 131 and the second electrode 132 are made of different materials. In one example, the first electrode 131 is made of a material containing Al. In the third embodiment, the first electrode 131 is made of Al. In one example, the second electrode 132 is made of a material containing Cu. In the third embodiment, the second electrode 132 is made of Cu.

[0150] The first connection portion 141 and the second connection portion 142 are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0151] The thickness relationship in the first chip 50Q of the third embodiment is as follows. Similar to the first embodiment, the thickness TA1 of the first insulating layer 52 is thicker than the thickness TA2 of the first element insulating layer 51B. The thickness TA1 of the first insulating layer 52 is thicker than the thickness TA3 of the second insulating layer 53. The thickness TB4 of the second electrode 132 is thicker than the thickness TB3 of the first electrode 131. According to the semiconductor device 10 of the third embodiment, the same effect as the semiconductor device 10 of the first embodiment can be obtained.

[0152] <Modification example> Each of the above embodiments can be implemented with the following modifications. Also, the following modification examples can be implemented in combination with each other as long as they do not technically conflict.

[0153] · In the third embodiment, the configuration of the second embodiment can be applied. That is, the semiconductor device 10 may include a double insulation structure by a capacitor. In this case, the second chip 60P includes a capacitor composed of a third electrode as an example of a third conductor and a fourth electrode as an example of a fourth conductor.

[0154] · In each embodiment, the first chips 50, 50P, 50Q may include a fifth insulating layer 54 that covers the first substrate back surface 51AR of the first semiconductor substrate 51A. The fifth insulating layer 54 is constituted by an organic insulating layer. In the example shown in FIG. 13, the thickness TA4 of the fifth insulating layer 54 is thicker than the thickness TA3 of the second insulating layer 53. According to this configuration, by increasing the thickness of the fifth insulating layer 54, it is possible to improve the breakdown voltage of the first chip 50.

[0155] The thickness TA4 of the fifth insulating layer 54 is thinner than the thickness TA1 of the first insulating layer 52. Note that the relationship between the thickness TA4 of the fifth insulating layer 54 and the thickness TA1 of the first insulating layer 52 can be arbitrarily changed. The thickness TA4 of the fifth insulating layer 54 may be equal to the thickness TA1 of the first insulating layer 52, or may be thicker than the thickness TA1 of the first insulating layer 52.

[0156] · In each embodiment, the first external electrode 55A may be exposed from the second insulating upper surface 53S. For example, in the first chip 50 shown in FIG. 14, the first external electrode 55A is provided on the second insulating layer 53. More specifically, the first insulating layer 52 is formed over the entire surface of the first insulating upper surface 51BS of the first element insulating layer 51B. Therefore, the first insulating upper surface 51BS shown in FIG. 14 is not exposed from the first insulating layer 52. In addition, the second insulating layer 53 is formed over the entire surface of the upper surface of the first insulating layer 52. The first external electrode 55A is provided so as to penetrate the insulating film 53A. Therefore, the first external electrode 55A is in contact with the upper surface of the first insulating layer 52. Further, an opening 58A for exposing the first external electrode 55A is formed in the passivation film 53B. As a result, the first external electrode 55A is exposed from the second insulating upper surface 53S. In one example, the first external electrode 55A is formed at the same position in the Z direction as the second external electrodes 55B and 55C and the second coil 42. In one example, the first external electrode 55A includes a portion overlapping the first circuit 20 in plan view. In this case, the first chip 50 includes a first connection wiring 56T that electrically connects the first circuit 20 and the first external electrode 55A. In one example, the first connection wiring 56T is a plurality of vias extending in the Z direction. The first connection wiring 56T penetrates the first element insulating layer 51B and the first insulating layer 52. Note that in the first chip 50 shown in FIG. 14, the third insulating film 51BC may be omitted from the first element insulating layer 51B.

[0157] ·In each embodiment, the thickness relationship among the first insulating layer 52, the first element insulating layer 51B, and the second insulating layer 53 can be arbitrarily changed. The thickness TA1 of the first insulating layer 52 may be equal to the sum of the thickness TA2 of the first element insulating layer 51B and the thickness TA3 of the second insulating layer 53. The thickness TA1 of the first insulating layer 52 may be thinner than the sum of the thickness TA2 of the first element insulating layer 51B and the thickness TA3 of the second insulating layer 53. The thickness TA1 of the first insulating layer 52 may be thinner than the thickness TA2 of the first element insulating layer 51B, or may be equal to the thickness TA2 of the first element insulating layer 51B. The thickness TA1 of the first insulating layer 52 may be thinner than the thickness TA3 of the second insulating layer 53, or may be equal to the thickness TA3 of the second insulating layer 53. The thickness TA3 of the second insulating layer 53 may be equal to the thickness TA2 of the first element insulating layer 51B, or may be thinner than the thickness TA2 of the first element insulating layer 51B. The thickness of the insulating film 53A may be equal to the thickness of the second insulating film 51BB, or may be thinner than the thickness of the second insulating film 51BB. Note that in the second embodiment, the thickness relationship among the third insulating layer 67, the second element insulating layer 61B, and the fourth insulating layer 68 can be arbitrarily changed in the same manner as the thickness relationship among the first insulating layer 52, the first element insulating layer 51B, and the second insulating layer 53.

[0158] ·In the first and second embodiments, the relationship between the thickness TB1 of the first coil 41 and the thickness TB2 of the second coil 42 can be arbitrarily changed. The thickness TB2 of the second coil 42 may be thinner than the thickness TB1 of the first coil 41, or may be equal to the thickness TB1 of the first coil 41.

[0159] ·In the third embodiment, the relationship between the thickness TB3 of the first electrode 131 and the thickness TB4 of the second electrode 132 can be arbitrarily changed. The thickness TB4 of the second electrode 132 may be thinner than the thickness TB3 of the first electrode 131, or may be equal to the thickness TB3 of the first electrode 131.

[0160] ·In each embodiment, the first bonding material 151 and the second bonding material 152 may be composed of an insulating bonding material. As the insulating bonding material, for example, a material containing an epoxy resin may be used.

[0161] · In the first and second embodiments, the inner connection wiring 73A and the outer connection wiring 73B may be formed at positions different from those of the first coil 41 or the second coil 42 in the Z direction. In this case, the first element insulating layer 51B may further include an insulating film for providing the inner connection wiring 73A and the outer connection wiring 73B, separately from the first to third insulating films 51BA to 51BC of each embodiment.

[0162] · In the first and second embodiments, one of the first inner peripheral end 44 and the first outer peripheral end 45 of the first coil 41 of the transformers 40A and 40B may be electrically connected to the ground GND1. In this case, the other end of the first coil 41 is electrically connected to the first circuit 20. Also, one of the second inner peripheral end 46 and the second outer peripheral end 47 of the second coil 42 of the transformers 40A and 40B may be electrically connected to the ground GND2. In this case, the other end of the second coil 42 is electrically connected to the second circuit 30.

[0163] · In the first and second embodiments, the configuration of each of the connection wirings 56 and 57 can be arbitrarily changed. In one example, each of the connection wirings 56 and 57 may include a wiring layer extending in a direction orthogonal to the Z direction. The wiring layer extending in the direction orthogonal to the Z direction may be formed, for example, at the same position as the first coil 41 in the Z direction. Note that the first element insulating layer 51B and the second insulating layer 53 may further include an insulating film provided with a wiring layer extending in a direction orthogonal to the Z direction, separately from the insulating films of each embodiment.

[0164] · In the third embodiment, the configuration of the first connection portion 141 and the second connection portion 142 can be arbitrarily changed. In one example, the first connection portion 141 and the second connection portion 142 may include a wiring layer extending in a direction orthogonal to the Z direction. The wiring layer extending in the direction orthogonal to the Z direction may be formed at the same position as the first electrode 131 or the second electrode 132 in the Z direction, or may be formed at a different position.

[0165] ·In the first and third embodiments, the configurations of the third connection wiring 65 and the fourth connection wiring 66 can be arbitrarily changed. In one example, the third connection wiring 65 and the fourth connection wiring 66 may include a wiring layer extending in a direction orthogonal to the Z direction. The wiring layer extending in the direction orthogonal to the Z direction may be formed at the same position as the first electrode 131 or the second electrode 132 in the Z direction, or may be formed at different positions.

[0166] ·In the first embodiment, the materials of the first coil 41 and the second coil 42 can be arbitrarily changed. The first coil 41 and the second coil 42 may be configured of the same material as each other. In one example, both the first coil 41 and the second coil 42 may be configured of Cu.

[0167] ·In the second embodiment, the materials of the first coils 121A, 121B and the second coils 122A, 122B can be arbitrarily changed. The first coils 121A, 121B and the second coils 122A, 122B may be configured of the same material as each other. In one example, each of the first coils 121A, 121B and the second coils 122A, 122B may be configured of Cu.

[0168] ·In the second embodiment, the materials of the third coils 123A, 123B and the fourth coils 124A, 124B can be arbitrarily changed. The third coils 123A, 123B and the fourth coils 124A, 124B may be configured of the same material as each other. In one example, each of the third coils 123A, 123B and the fourth coils 124A, 124B may be configured of Cu.

[0169] ·In the third embodiment, the materials of the first electrode 131 and the second electrode 132 can be arbitrarily changed. The first electrode 131 and the second electrode 132 may be configured of the same material as each other. In one example, both the first electrode 131 and the second electrode 132 may be configured of Cu.

[0170] · In each embodiment, the first insulating layer 52 may be made of a material other than polyimide or polybenzoxazole. The first insulating layer 52 only needs to include an organic insulating layer.

[0171] · In each embodiment, the second insulating layer 53 may be made of an inorganic insulating layer instead of an organic insulating layer. · In each embodiment, the first element insulating layer 51B does not necessarily need to include at least one of a silicon oxide film and a silicon nitride film. Also, the first element insulating layer 51B does not necessarily need to be an inorganic insulating layer. The first element insulating layer 51B may include an organic insulating material.

[0172] · In the second embodiment, the third insulating layer 67 may be made of a material other than polyimide or polybenzoxazole. The third insulating layer 67 only needs to include an organic insulating material.

[0173] · In the second embodiment, the fourth insulating layer 68 may be made of an inorganic insulating layer instead of an organic insulating layer. · In the second embodiment, the second element insulating layer 61B does not necessarily need to include at least one of a silicon oxide film and a silicon nitride film. Also, the second element insulating layer 61B does not necessarily need to be an inorganic insulating layer. The second element insulating layer 61B may include an organic insulating material.

[0174] · In each embodiment, the semiconductor device 10 may be configured such that signals can be transmitted bidirectionally between the first circuit 20 and the second circuit 30. In one example, in the first embodiment, in addition to the transformers 40A and 40B as the first transformers that transmit the first signal from the first circuit 20 shown in FIG. 1 to the second circuit 30, the semiconductor device 10 may include a second transformer that transmits the second signal from the second circuit 30 to the first circuit 20. The configuration of the second transformer may be the same as that of the transformers 40A and 40B.

[0175] One or more of the various examples described in this specification can be combined within a technically consistent range. As used herein, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "the first element is disposed on the second element" is intended that in some embodiments, the first element may be in direct contact with the second element and disposed directly on the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. That is, the term "on" does not exclude a structure in which other elements are formed between the first element and the second element.

[0176] The Z direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to be completely coincident with the vertical direction. Thus, various structures according to the present disclosure are not limited to the "up" and "down" in the Z direction described herein being the "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0177] <Appendix> The technical idea that can be grasped from the present disclosure is described below. For the purpose of assisting understanding rather than limitation, the components described in the appendix are assigned the reference numerals of the corresponding components in the above embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0178] [Appendix 1] A first die pad (81), a first chip (50 / 50P / 50Q) mounted on the first die pad (81) and including a first circuit (20), a second die pad (91) disposed spaced apart from the first die pad (81) in a first direction (X direction) orthogonal to the thickness direction (Z) of the first chip (50 / 50P / 50Q), a second chip (60) mounted on the second die pad (91) and including a second circuit (30), and the first chip (50 / 50P / 50Q) is A first semiconductor element (51) including a first semiconductor substrate (51A) on which the first circuit (20) is formed, a first element insulating layer (51B) formed on the first semiconductor substrate (51A), and a first conductor (41 / 131) provided in the first element insulating layer (51B) and electrically connected to the first circuit (20). A first insulating layer (52) covering a first insulating upper surface (51BS) of the first element insulating layer (51B) facing away from the first semiconductor substrate (51A) and constituted by an organic insulating layer. A second conductor (42 / 132) formed on the first insulating layer (52), disposed to face the first conductor (41 / 131) in the thickness direction (Z direction) with the first element insulating layer (51B) and the first insulating layer (52) interposed therebetween, and electrically connected to the second circuit (30). A second insulating layer (53) covering the first insulating layer (52) and the second conductor (42 / 132). Including A semiconductor device (10).

[0179] [Appendix 2] The first chip (50 / 50P / 50Q) includes A first external electrode (55A) electrically connected to the first circuit (20), A second external electrode (55B, 55C) electrically connected to the second conductor (42 / 132), Including A part of the first insulating upper surface (51BS) is exposed in the first insulating layer (52), The first external electrode (55A) is disposed at a position different from that of the first insulating layer (52) in the first element insulating layer (51B) when viewed from the thickness direction (Z) and is exposed from the first insulating upper surface (51BS). The semiconductor device according to Appendix 1.

[0180] [Appendix 3] The first chip (50 / 50P / 50Q) includes A first external electrode (55A) electrically connected to the first circuit (20), A second external electrode (55B, 55C) electrically connected to the second conductor (42 / 132) and the second circuit (30), including the first external electrode (55A) is located on the side opposite to the second chip (60) in the first direction (X), the second external electrodes (55B, 55C) are located closer to the second chip (60) in the first direction (X), a first lead (92) located on the side opposite to the second chip (60) with respect to the first die pad (81) and electrically connected to the first external electrode (55A). The semiconductor device according to Appendix 1 or 2.

[0181] [Appendix 4] The first chip (50 / 50P / 50Q) includes a first connection wiring (56) that electrically connects the first external electrode (55A) and the first circuit (20), the first connection wiring (56) is electrically connected to the first circuit (20) and includes a via that extends toward the first external electrode (55A) in the thickness direction (Z). The semiconductor device according to Appendix 2 or 3.

[0182] [Appendix 5] The first semiconductor element (51) includes an internal electrode (70) that is electrically connected to the first circuit (20) and covered by the first element insulating layer (51B), the internal electrode (70) is electrically connected to the first conductor (41 / 131). The semiconductor device according to any one of Appendices 1 to 3.

[0183] [Appendix 6] The internal electrode (70(70A, 70B)) includes an inner via (71A / 141) that connects the first circuit (20) and the first conductor (41 / 131). The semiconductor device according to Appendix 5.

[0184] [Appendix 7] The thickness (TA1) of the first insulating layer (52) is greater than the thickness (TA2) of the first element insulating layer (51B). The semiconductor device according to any one of Appendices 1 to 6.

[0185] [Appendix 8] The thickness (TA1) of the first insulating layer (52) is greater than the thickness (TA3) of the second insulating layer (53). The semiconductor device according to any one of Appendices 1 to 7.

[0186] [Appendix 9] The first insulating layer (52) is composed of a material containing polyimide or polybenzoxazole. The semiconductor device according to any one of Appendices 1 to 8.

[0187] [Appendix 10] The first element insulating layer (51B) is composed of an inorganic insulating layer. The semiconductor device according to any one of Appendices 1 to 9.

[0188] [Appendix 11] The first element insulating layer (51B) includes at least one of a silicon oxide film and a silicon nitride film. The semiconductor device according to any one of Appendices 1 to 10.

[0189] [Appendix 12] The second insulating layer (53) is composed of an organic insulating layer. The semiconductor device according to any one of Appendices 1 to 11.

[0190] [Appendix 13] The thickness (TB2 / TB4) of the second conductor (42 / 132) is greater than the thickness (TB1 / TB3) of the first conductor (41 / 131). The semiconductor device according to any one of Appendices 1 to 12.

[0191] [Appendix 14] The second chip (60) includes an external electrode (64A) electrically connected to the second circuit (30). The external electrode (64A) of the second chip (60) and the second external electrodes (55B, 55C) are connected by a conductive connection member (W2). The semiconductor device according to any one of Appendices 2 to 13.

[0192] [Appendix 15] The first conductor and the second conductor are coils (41, 42). The semiconductor device according to any one of Appendices 1 to 14.

[0193] [Appendix 16] The first semiconductor element (51) is electrically connected to the first circuit (20) and includes an internal electrode (70) covered by the first element insulating layer (51B). The internal electrode (70) a first internal electrode (70A) electrically connected to the inner peripheral end portion (44) of the first conductor (41); a second internal electrode (70B) electrically connected to the outer peripheral end portion (45) of the first conductor (41); and includes The semiconductor device according to Appendix 15.

[0194] [Appendix 17] The first conductor and the second conductor are electrode plates (131, 132). The semiconductor device according to any one of Appendices 1 to 14.

[0195] [Appendix 18] The second chip (60P) a second semiconductor substrate (61A) on which the second circuit (30) is formed, a second element insulating layer (61B) formed on the second semiconductor substrate (61A), and third conductors (124A, 124B) provided in the second element insulating layer (61B) and electrically connected to the second circuit (30), and includes a second semiconductor element (61). covering the second insulating upper surface (61BS) of the second element insulating layer (61B), and a third insulating layer (67) formed of an organic insulating layer, a fourth conductor (123A, 123B) formed on the third insulating layer (67) and disposed to face the third conductor (124A, 124B) in the thickness direction (Z direction) with the second element insulating layer (61B) and the third insulating layer (67) interposed therebetween, a fourth insulating layer (68) covering the third insulating layer (67) and the fourth conductor (123A, 123B), including the semiconductor device according to any one of Appendices 1 to 17.

[0196] [Appendix 19] The second chip (60P) includes a third external electrode (69A) electrically connected to the second circuit (30), and fourth external electrodes (69B, 69C) electrically connected to the fourth conductor (123A, 123B), including a part of the second insulating upper surface (61BS) of the second element insulating layer (61B) is exposed, the third external electrode (69A) is disposed at a position different from the third insulating layer (67) in the second element insulating layer (61B) when viewed from the thickness direction (Z) and is exposed from the second insulating upper surface (61BS) the semiconductor device according to Appendix 18.

[0197] [Appendix 20] the third external electrode (69A) is located on the side opposite to the first chip (50 / 50P / 50Q) in the first direction (X), the fourth external electrodes (69B, 69C) are located closer to the first chip (50 / 50P / 50Q) in the first direction (X), including a second lead (92) located on the side opposite to the first chip (50) with respect to the second die pad (91) and electrically connected to the third external electrode (69A) the semiconductor device according to Appendix 19.

[0198] [Appendix 21] The fourth external electrodes (68B, 69C) and the second external electrodes (55B, 55C) are connected by a conductive connection member (W2). The semiconductor device according to Appendix 19 or 20.

[0199] [Appendix 22] The first conductor (41 / 131) and the second conductor (42 / 132) are made of different materials from each other. The semiconductor device according to any one of Appendices 1 to 21.

[0200] [Appendix 23] The first conductor (41 / 131) is made of a material containing Al, The second conductor (42 / 132) is made of a material containing Cu. The semiconductor device according to Appendix 22.

[0201] [Appendix 24] The first chip (50 / 50P / 50Q) is mounted on the first die pad (81) such that the first semiconductor substrate (51A) is disposed closer to the first die pad (81) than the first element insulating layer (51B). The semiconductor device according to any one of Appendices 1 to 23.

[0202] [Appendix 25] The first semiconductor substrate (51A) is, a first substrate upper surface (51AS) on which the first element insulating layer (51B) is laminated, a first substrate back surface (51AR) facing the side opposite to the first substrate upper surface (51AS), and includes, and includes a fifth insulating layer (54) covering the first substrate back surface (51AR). The semiconductor device according to any one of Appendices 1 to 24.

[0203] [Appendix 26] The fifth insulating layer (54) is made of an organic insulating layer. The semiconductor device described in Supplementary Note 25.

[0204] [Supplementary Note 27] The thickness (TA4) of the fifth insulating layer (54) is greater than the thickness (TA3) of the second insulating layer (53). The semiconductor device described in Supplementary Note 25 or 26.

[0205] [Supplementary Note 28] The thickness (TA4) of the fifth insulating layer (54) is greater than the thickness (TA1) of the first insulating layer (52). The semiconductor device described in any one of Supplementary Notes 25 to 27.

[0206] [Supplementary Note 29] The thickness (TA4) of the fifth insulating layer (54) is less than the thickness (TA1) of the first insulating layer (52). The semiconductor device described in any one of Supplementary Notes 25 to 27.

[0207] [Supplementary Note 30] The first chip (50 / 50P / 50Q) has a first external electrode (55A) electrically connected to the first circuit (20), and a second external electrode (55B, 55C) electrically connected to the second conductor (42 / 132), and the first external electrode (55A) and the second external electrode (55B, 55C) are exposed from a second insulating upper surface (53S) facing the same side as the first insulating upper surface (51BS) of the second insulating layer (53). The semiconductor device described in Supplementary Note 1.

[0208] [Supplementary Note 31] The first chip (50 / 50P / 50Q) is bonded to the first die pad (81) by a conductive bonding material (151). The semiconductor device described in any one of Supplementary Notes 1 to 30.

[0209] [Supplementary Note 32] The second chip (60) is bonded to the second die pad (91) by a conductive bonding material (152). The semiconductor device according to any one of Appendices 1 to 31.

[0210] [Appendix 33] The first chip (50 / 50P / 50Q) is bonded to the first die pad (81) by an insulating bonding material. The semiconductor device according to any one of Appendices 1 to 30.

[0211] [Appendix 34] A first semiconductor substrate (51A) on which a first circuit (20) is formed, A first element insulating layer (51B) formed on the first semiconductor substrate (51A), A first semiconductor element (51) including a first conductor (41 / 131) provided in the first element insulating layer (51B) and electrically connected to the first circuit (20). A first insulating layer (52) covering a first insulating upper surface (51BS) of the first element insulating layer (51B) facing away from the first semiconductor substrate (51A) and composed of an organic insulating layer, A second conductor (42 / 132) formed on the first insulating layer (52) and disposed opposite to the first conductor (41 / 131) in the thickness direction (Z) of the first semiconductor substrate (51A) with the first element insulating layer (51B) and the first insulating layer (52) interposed therebetween, A second insulating layer (53) covering the first insulating layer (52) and the second conductor (42 / 132), Including Semiconductor chip (50 / 50P / 50Q).

[0212] [Appendix 35] A second semiconductor substrate (61A) on which a second circuit (30) is formed, A second element insulating layer (61B) formed on the second semiconductor substrate (61A), A second semiconductor element (61) including a third conductor (124A, 124B) provided in the second element insulating layer (61B) and electrically connected to the second circuit (30). covering a second insulating upper surface (61BS) of the second element insulating layer (61B) facing away from the second semiconductor substrate (61A), and a third insulating layer (67) composed of an organic insulating layer; a fourth conductor (123A, 123B) formed on the third insulating layer (67) and disposed to face the third conductor (124A, 124B) in the thickness direction (Z) of the second semiconductor substrate (61A) with the second element insulating layer (61B) and the third insulating layer (67) interposed therebetween; a fourth insulating layer (68) covering the third insulating layer (67) and the fourth conductor (123A, 123B); including a semiconductor chip (60P).

[0213] [Appendix 36] preparing a first semiconductor substrate (51A) on which a first circuit (20) is formed; forming a first element insulating layer (51B) on the first semiconductor substrate (51A); forming a first conductor (41 / 131) in the first element insulating layer (51B); forming a first insulating layer (52) so as to cover a first insulating upper surface (51BS) of the first element insulating layer (51B) facing away from the first semiconductor substrate (51A); forming a second insulating layer (53) covering the first insulating layer (52); forming a second conductor (42 / 132) on the second insulating layer (53) on the first insulating layer (52); including wherein the first insulating layer (52) is formed of an organic insulating layer; wherein the second conductor (42 / 132) is formed so as to face the first conductor (41 / 131) in the thickness direction (Z) of the first semiconductor substrate (51A) with the first element insulating layer (51B) and the first insulating layer (52) interposed therebetween a method of manufacturing a semiconductor chip.

[0214] The above description is merely illustrative. Those skilled in the art can recognize that there are more possible combinations and substitutions other than the components and methods (manufacturing processes) enumerated for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to encompass all alternatives, modifications, and variations included within the scope of the present disclosure, including the claims.

Description of Reference Numerals

[0215] 10…Semiconductor device 20…First circuit 21…Transmission circuit 30…Second circuit 31…Receiving circuit 40A, 40B…Transformer 41…First coil 42…Second coil 43…Inner region 44…First inner peripheral end 45…First outer peripheral end 46…Second inner peripheral end 47…Second outer peripheral end 50, 50P, 50Q…First chip 51…First semiconductor element 51A…First semiconductor substrate 51AS…First substrate upper surface 51AR…First substrate lower surface 51B…First element insulating layer 51BA…First insulating film 51BB…Second insulating film 51BC…Third insulating film 51BS…First insulating upper surface 51C~51F…Element side surface 51S…Element upper surface 51R…Element lower surface 52…First insulating layer 53…Second insulating layer 53A…Insulating film 53B…Passivation film 53S…Second insulating upper surface 54…Fifth insulating layer 55A…First external electrode 55B, 55C…Second external electrodes 56, 56T… First connection wiring 57, 57A, 57B… Second connection wiring 58A, 58B… Openings 60, 60P, 60Q… Second chip 61… Second semiconductor element 61A… Second semiconductor substrate 61AS… Upper surface of the second substrate 61B… Second element insulating layer 61BS… Upper surface of the second insulation 62… Third insulation layer 62S… Upper surface of the third insulation layer 63… Fourth insulation layer 64A… Third external electrode 64B… Fourth external electrode 65… Third connection wiring 66… Fourth connection wiring 67… Third insulation layer 68… Fourth insulation layer 69A… Third external electrode 69B, 69C… Fourth external electrodes 70… Internal electrode 70A… Inner peripheral electrode 70B… Outer peripheral electrode 71A… Inner via 71B… Outer via 72A… Inner pad 72B… Outer pad 73A… Inner connection wiring 73B… Outer connection wiring 80… First lead frame 81… First die pad 82, 82A… First leads 90… Second lead frame 91… Second die pad 92, 92A… Second leads 100… Encapsulation resin 101~104… Encapsulation side surface 110A, 110B… Transformers 111A, 111B… First transformers 112A, 112B… Second transformers 121A~124A, 121B~124B… First to fourth coils 130A, 130B... Capacitor 131... First electrode 132... Second electrode 141... First connection part 142... Second connection part 151... First bonding material 152... Second bonding material TA1... Thickness of the first insulating layer TA2... Thickness of the first element insulating layer TA3... Thickness of the second insulating layer TA4... Thickness of the fifth insulating layer TB1... Thickness of the first coil TB2... Thickness of the second coil TB3... Thickness of the first electrode TB4... Thickness of the second electrode W1~W3... Wire

Claims

1. a first die pad; a first chip mounted on the first die pad and including a first circuit; a second die pad disposed apart from the first die pad in a first direction orthogonal to the thickness direction of the first chip; a second chip mounted on the second die pad and including a second circuit; comprising the first chip includes a first semiconductor element including a first semiconductor substrate on which the first circuit is formed, a first element insulating layer formed on the first semiconductor substrate, and a first conductor provided in the first element insulating layer and electrically connected to the first circuit; a first insulating layer covering a first insulating upper surface of the first element insulating layer facing away from the first semiconductor substrate and constituted by an organic insulating layer; a second conductor formed on the first insulating layer, disposed to face the first conductor in the thickness direction with the first element insulating layer and the first insulating layer interposed therebetween, and electrically connected to the second circuit; a second insulating layer covering the first insulating layer and the second conductor; including a semiconductor device.

2. the first chip includes a first external electrode electrically connected to the first circuit; a second external electrode electrically connected to the second conductor; including a part of the first insulating upper surface of the first insulating layer is exposed; the first external electrode is disposed at a position different from that of the first insulating layer in the first element insulating layer when viewed from the thickness direction, and is exposed from the first insulating upper surface The semiconductor device according to claim 1.

3. the first chip includes a first external electrode electrically connected to the first circuit; a second external electrode electrically connected to the second conductor and the second circuit; including the first external electrode is located on the side opposite to the second chip in the first direction; the second external electrode is located closer to the second chip in the first direction; including a first lead located on the side opposite to the second chip with respect to the first die pad and electrically connected to the first external electrode The semiconductor device according to claim 1 or 2.

4. the first chip includes a first connection wiring electrically connecting the first external electrode and the first circuit; the first connection wiring includes a via electrically connected to the first circuit and extending toward the first external electrode in the thickness direction The semiconductor device according to claim 3.

5. the first semiconductor element includes an internal electrode electrically connected to the first circuit and covered by the first element insulating layer The internal electrode is electrically connected to the first conductor. The semiconductor device according to claim 3.

6. The internal electrode includes an inner via that connects the first circuit and the first conductor. The semiconductor device according to claim 5.

7. The thickness of the first insulating layer is greater than the thickness of the first element insulating layer. The semiconductor device according to claim 1.

8. The thickness of the first insulating layer is greater than the thickness of the second insulating layer. The semiconductor device according to claim 1.

9. The first insulating layer is composed of a material containing polyimide or polybenzoxazole. The semiconductor device according to claim 1.

10. The first element insulating layer is composed of an inorganic insulating layer. The semiconductor device according to claim 1.

11. The first element insulating layer includes at least one of a silicon oxide film and a silicon nitride film. The semiconductor device according to claim 1.

12. The second insulating layer is composed of an organic insulating layer. The semiconductor device according to claim 1.

13. The thickness of the second conductor is greater than the thickness of the first conductor. The semiconductor device according to claim 1.

14. The second chip includes an external electrode electrically connected to the second circuit, The external electrode of the second chip and the second external electrode are connected by a conductive connection member. The semiconductor device according to claim 3.

15. The first conductor and the second conductor are coils. The semiconductor device according to claim 1.

16. The first semiconductor element is electrically connected to the first circuit and includes an internal electrode covered by the first element insulating layer, The internal electrode is a first internal electrode electrically connected to the inner peripheral end of the first conductor, a second internal electrode electrically connected to the outer peripheral end of the first conductor, and includes The semiconductor device according to claim 1.

17. The first conductor and the second conductor are electrode plates. The semiconductor device according to claim 1.

18. The second chip is a second semiconductor element including a second semiconductor substrate on which the second circuit is formed, a second element insulating layer formed on the second semiconductor substrate, and a third conductor provided in the second element insulating layer and electrically connected to the second circuit, a third insulating layer covering the second insulating upper surface of the second element insulating layer and composed of an organic insulating layer, A fourth conductor formed on the third insulating layer and disposed to face the third conductor in the thickness direction with the second element insulating layer and the third insulating layer interposed therebetween; A fourth insulating layer covering the third insulating layer and the fourth conductor; comprising The semiconductor device according to claim 1.

19. The second chip includes a third external electrode electrically connected to the second circuit; a fourth external electrode electrically connected to the fourth conductor; and a part of the upper surface of the second insulating layer is exposed in the third insulating layer, the third external electrode is disposed at a position different from the third insulating layer in the second element insulating layer when viewed from the thickness direction, and is exposed from the upper surface of the second insulating layer The semiconductor device according to claim 18.

20. The third external electrode is located on the side opposite to the first chip in the first direction, The fourth external electrode is located closer to the first chip in the first direction, including a second lead located on the side opposite to the first chip with respect to the second die pad and electrically connected to the third external electrode The semiconductor device according to claim 19.

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