Semiconductor component and manufacturing method for semiconductor component

Abstract

To provide a semiconductor component and manufacture a semiconductor component.SOLUTION: A semiconductor component includes a source layer doped with a first kind, a drift region doped with the first kind, and a substrate layer. The channel layer exists between the source layer and the substrate layer. The drift region exists between the channel layer and the substrate layer. The semiconductor component further includes a gate groove. The gate groove extends in a direction from the source layer to the drift region in a longitudinal direction, and is adjacent to the channel layer and at least a part of the source layer. The semiconductor component further includes a block region doped with a second kind. The block region extends from the source layer to the drift region in the longitudinal direction, is adjacent to the channel layer and the source layer, and is separated from by the gate groove in a lateral direction. The drift region includes a plurality of drift layers doped with the first kind having different doping concentrations.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to semiconductor components, in particular transistors, such as so-called trench-type MISFETs, and a method for manufacturing such semiconductor components.

Background Art

[0002] In various fields, semiconductor components, such as field effect transistors (FETs), in particular so-called MOSFETs or MISFETs, are used. One form thereof is a so-called trench-type MISFET or T-MISFET in which a channel is formed in the longitudinal direction. In this regard, for example, a channel layer between an n-type doped source layer and a drift layer doped with the same n-type is penetrated by a groove (English "Trench"), and in this case, a gate electrode is disposed in such a groove.

Summary of the Invention

[0003] According to the present invention, a semiconductor component having the features of the independent claims and a method for manufacturing a semiconductor component are proposed. Advantageous forms are the subject of the dependent claims and the following description. The present invention addresses semiconductor components and their manufacture. As semiconductor components, in particular transistors, preferably field effect transistors, especially those provided with grooves or trenches, are considered. Here, for example, it may be a T-MOSFET or a T-MISFET. Different types of doping, specifically n-type doping and p-type doping, are used in the semiconductor material, and different components may be doped differently. Hereinafter, for the sake of clarity, a semiconductor component having a certain specific type of doping will be described, and n-type doping will be the first type of doping and p-type doping will be the second type of doping. However, it is obvious that the n-type doping and the p-type doping may be interchanged, that is, the n-type doping may be the second type of doping and the p-type doping may be the first type of doping.

[0004] A field effect transistor has, for example, an n-type doped source layer, a channel layer (and also a body layer), which is usually p-type doped, an n-type doped drift region, and a substrate layer. The channel layer is between the source layer and the substrate layer and is adjacent to the source layer in particular. The drift region is between the channel layer and the substrate layer. The field effect transistor may also have an n-type doped spread layer between the channel layer and the drift region. In addition, the field effect transistor has, optionally, not only a substrate layer but also a buffer layer, and this buffer layer is adjacent to the substrate layer and further to the drift region.

[0005] In addition, the field effect transistor has, for example, a gate groove, which extends longitudinally from the source layer in the direction of the drift region and is adjacent to the channel layer and at least a part of the source layer. In addition, the field effect transistor has, in particular, a gate electrode, which is insulated from the spread layer, the source layer, and the channel layer and is provided in the gate groove. For this reason, the conductive gate electrode material of the gate electrode is surrounded, at least partially, for example, by a dielectric (such as a so-called gate oxide). The field effect transistor may have a plurality of such gate grooves, and in that case, such a gate electrode may be arranged in each gate groove.

[0006] In addition, the field effect transistor typically has a drain contact layer, for example, a metal, which serves for contact and is adjacent to the substrate layer. The field effect transistor may also have a source contact layer, for example, also a metal, which serves for contact and is adjacent to the source layer. However, the gate electrode is insulated from the source contact layer by an insulating layer. That is, there are source and drain terminals that can be formed in the conventional way.

[0007] Furthermore, such a field effect transistor can have at least one p-type doped shielding region, which extends longitudinally from an n-type doped source layer or a semiconductor surface adjacent to this (n-type doped source layer) to an n-type doped drain layer.

[0008] A special advantage of the trench type MISFET is, for example, that many gate electrodes can be arranged side by side due to the longitudinal arrangement, in which case a high channel density and a low forward resistance can be achieved. The field effect transistor may be formed, inter alia, as a SiC field effect transistor or a GaN field effect transistor, i.e., the substrate and / or the commonly used semiconductor material can be silicon carbide (SiC) or gallium nitride (GaN), because these semiconductor materials have a wide bandgap. However, semiconductor materials with an ultra-wide bandgap, such as gallium oxide, are also considered. However, the present invention can generally be used also in the case of other semiconductor materials, such as gallium nitride (GaN), silicon (Si), or germanium (Ge).

[0009] What is generally desirable for such a field effect transistor, for example, a silicon carbide (SiC) trench gate type power MISFET, is to minimize the forward resistance Ron*A (at the on state of the component and at a low voltage between the drain and the source), and to maximize the blocking voltage (at the off state of the component and at a high voltage between the drain and the source), while at the same time keeping the electric field load of the gate oxide below an acceptable value, and maximizing the robustness of the field effect transistor against short circuit phenomena. These four different requirements have not been able to be optimized independently of each other so far.

[0010] Therefore, within the framework of the present invention, it is proposed that the drift region includes a plurality of n-type doped (or generally doped with a first type) drift layers having different doping concentrations. In particular, the drift region can have four such drift layers.

[0011] The mentioned drift region is conventionally an epitaxially applied layer, for example, homogeneously doped, on a buffer layer or, in some cases, directly on a substrate layer. Here, by providing a plurality of layers with different doping concentrations and thus different functions, it is possible to minimize the contribution of the drift region to the forward resistance and to maximize the blocking voltage of the field-effect transistor to a value approaching the theoretical limit of a unipolar component without superjunction (so-called "non-super-junction-unipolar device").

[0012] In one embodiment, the plurality of drift layers includes a first drift layer on the side of the substrate layer. When a buffer layer is provided, the first drift layer particularly has a lower doping concentration than the buffer layer. This first drift layer serves to reduce the electric field in the longitudinal direction at high voltages between the drain and the source, and the doping concentration can be in the range of 5E15 to 5E16 cm^-3 with a thickness of, for example, 0.5 μm to 10 μm. This layer can be used to generate a high gradient in the electric field in the case of blocking.

[0013] In one embodiment, the plurality of drift layers includes a second drift layer adjacent to the first drift layer, and the second drift layer has a lower doping concentration than the first drift layer. This second drift layer is an intermediate voltage blocking layer (Zwischenspannungssperrschicht), and the doping concentration can be in the range of 1E15 to 5E16 cm^-3 with a thickness of, for example, 0.5 μm to 10 μm. This layer can generate an intermediate gradient in the electric field in the case of blocking compared to other layers and can contribute to assisting the absorption of the blocking voltage in the blocking state.

[0014] In one embodiment, a plurality of drift layers includes a third drift layer adjacent to the second drift layer, and the third drift layer has a doping concentration lower than that of the first drift layer and the second drift layer. This third drift layer is the main blocking voltage layer (Hauptsperrspannungsschicht), and the doping concentration can be in the range of 1E15 to 2E16 cm^-3 for a thickness of, for example, 0.5 μm to 10 μm. This layer can help generate a low gradient within the electric field during blocking, thereby maximizing the height of the blocking voltage (the integration of the electric field in the drift zone) for the same maximum electric field strength.

[0015] In one embodiment, a plurality of drift layers includes a fourth drift layer adjacent to the third drift layer, and the fourth drift layer has a doping concentration higher than that of the second drift layer and the third drift layer. This fourth drift layer can be a spread·epitaxial layer, and the doping concentration can be in the range of 1E15 to 5E16 cm^-3 for a thickness of, for example, 0.5 μm to 10 μm. In one embodiment, the fourth drift layer has a doping concentration below that of the first drift layer. Alternatively, the fourth drift layer can have a doping concentration higher than that of the first drift layer. However, this doping concentration is always higher than that of the second and third drift layers. This fourth drift layer can help distribute the current in the conducting state, that is, minimize the contribution of the forward resistance near the trench. This layer can be additionally enhanced by post-implantation ion implantation in one embodiment.

[0016] The field-effect transistor can have a p-type doped (or generally doped with a second type) shielding region, which extends vertically from the surface or the source layer in the direction of the drift region, is adjacent to the channel layer and the source layer, and is separated laterally by a gate trench. In one embodiment, the field-effect transistor further has a further p-type doped (or generally doped with a second type) shielding region, which extends vertically towards or into the drift region under the gate trench. This further shielding region is connected to the shielding region, for example, by at least one particularly deeply implanted contact region. This further shielding region may be formed, among other things, in a self-aligned manner.

[0017] By providing a (self-aligned) shielding region (also referred to as "Gate-Screening-Implant") under the trench (so-called "bottom p-well" BPW), the requirement for the maximum electric field strength in the gate insulator can be decoupled from the requirements for on-resistance (Ron*A), breakdown voltage, and short-circuit strength. At the same time, this newly created relatively elongated JFET region between the (new) shielding region and possibly an already existing shielding region (as mentioned above) limits the saturation current density of the field-effect transistor in case of a short circuit, thereby limiting the power loss density of the component as well as the heating rate and possible thermal damage, which gives the field-effect transistor improved short-circuit robustness compared to previous cases.

[0018] The invention also relates to a method for manufacturing a semiconductor component or a field-effect transistor as described above. In this regard, a substrate layer is provided, and a plurality of n-type doped or doped with a first type drift layers are applied directly or indirectly on the substrate layer, i.e., in this case, if present, on a buffer layer. Subsequently, a further active region can be formed on the uppermost layer of this plurality of drift layers, i.e., for example, on the fourth drift layer.

[0019] The field-effect transistor as described can be used, alone or together with further field-effect transistors, for example as a power switch. Preferred fields of use are, for example, within the electric power train of a vehicle, where, for example, within a converter (DC / DC converter, inverter), in charging equipment for electric vehicles, or also within a solar inverter.

[0020] Further advantages and aspects of the invention will become apparent from the description of the invention and the accompanying drawings. The invention is schematically illustrated in the drawings based on exemplary embodiments and will be explained below with reference to the drawings.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying Out the Invention

[0022] In FIG. 1, a semiconductor component 100 (or at least a part thereof) for explaining the background of the present invention is schematically shown in detail, in particular as a field-effect transistor of a so-called trench-type MISFET. As the semiconductor material, in particular silicon carbide (SiC), gallium nitride (GaN), or gallium oxide can be used, because these semiconductor materials have a wide - very wide bandgap, which is advantageous for determining the compromise between RonA and the breakdown voltage compared to materials with a narrow bandgap. In this regard, FIG. 1 shows a cross-sectional view of the field-effect transistor 100, where the z-direction is the longitudinal direction and the field-effect transistor 100 has a larger spread in the x-y plane (the y-direction is coming out of the plane of the figure here).

[0023] Hereinafter, a field effect transistor 100 having n-type doping as the first type of doping and p-type doping as the second type of doping will be described. As already mentioned, the types of doping may be replaced.

[0024] The field effect transistor 100 has a substrate layer 101 in the form of a wafer, for example. The substrate layer 101 consists of a semiconductor material (such as SiC) having, among other things, an optionally epitaxially grown buffer layer 101a on the upper side.

[0025] In addition to this, the field effect transistor 100 has an epitaxially grown layer 102 that is n-type doped at a low concentration and has two main functions. Of this layer 102, in the upper part, here represented by 121, the so-called MISFET head, an active functional region with appropriate doping is created (for example, by implantation using an appropriate mask), while in the lower part of the layer 102, known as the drift region and here represented by 120, mainly absorbs high voltage in the case of blocking as part of the p / n junction.

[0026] The active, especially implanted functional regions belong to the following layers: an n+-type doped source layer 108, a p-type doped channel or body layer 106, optionally a p-type doped edge termination (not shown), and an optionally n-type doped spread layer 112, as well as a p+-type doped shielding region 107.

[0027] Thus, the layer 102 can initially be continuously produced like the drift region 120, but then a part of it is adapted by processing to obtain the layers mentioned. However, the drift region 120 remains, and this drift region 120 is in this case a homogeneously doped layer.

[0028] In addition, the trench-type MISFET may further include additional structures, such as gate trench 103, a dielectric gate insulating layer 104, 104a (gate oxide) on the surface of the trench (e.g., SiO2 or another insulating material or a combination of multiple insulating materials), where 104 represents the side layer and 104a represents the bottom layer of the trench. The thicknesses of the side gate insulating layer 104 and the gate insulating layer 104a at the bottom of the trench may be different. The gate electrode (e.g., polysilicon or a metal gate) is represented here by 105, and an insulating layer 110 is applied over the gate electrode.

[0029] The source contact layer of the field effect transistor 100, such as a source metal (e.g., aluminum or copper or a combination of various materials), is represented by 109, and this source contact layer 109 serves for contact with the source layer 108 and the shielding region 107.

[0030] The drain contact layer of the field effect transistor 100, such as a drain metal that contacts the back side of the substrate layer 101, is represented by 111. The challenge in a silicon carbide (SiC) trench-type power MISFET or an equivalent field effect transistor is to achieve good conduction characteristics in the on-state (low forward resistance Ron*A per unit area) together with good short-circuit strength and a high blocking voltage, and, for reasons of reliability, to limit the maximum electric field strength in the gate insulator of the trench to an acceptable value on the order of 3 MV / cm. These four different requirements cannot be optimized independently of each other, and thus a compromise between these requirements is defined.

[0031] In FIG. 2, a semiconductor component 200 (or at least a part thereof) in one embodiment is schematically shown, in particular as a field-effect transistor of a so-called trench-type MISFET. As the semiconductor material, in particular silicon carbide (SiC), gallium nitride (GaN), or gallium oxide can be used, because these semiconductor materials have a wide - very wide bandgap. In this regard, FIG. 2 shows a cross-sectional view of the field-effect transistor 200, where the z-direction is the vertical direction and the field-effect transistor 200 has a greater extent in the x-y plane (the y-direction is coming out of the plane of the figure here).

[0032] Hereinafter, the differences between the field-effect transistor 200 and the field-effect transistor 100 based particularly on FIG. 1 will be described. The same elements, layers, or regions are denoted by the same reference numerals, and different or additional elements, layers, or regions are denoted by different reference numerals.

[0033] The field-effect transistor 200 has a substrate layer 101, for example in the form of a wafer. The substrate layer 101 has a low resistivity and can be doped with a very high n++ concentration. An optional buffer layer 101a is epitaxially grown on the upper side of the substrate layer at a certain n+ doping concentration. This buffer layer is grown for the control and reduction of crystal defects.

[0034] On the buffer layer 101a, in one embodiment, four drift layers with different doping concentrations and functions are grown. The first drift layer 213 serves as a layer for reducing the electric field in the vertical direction at high voltages between the drain and the source and has a lower doping concentration than the buffer layer (for example, with a thickness in the range of 0.5 μm to 10 μm and within the range of 5E15 to 5E16 cm^-3). This layer is used to generate a high gradient in the electric field in the case of blocking.

[0035] The second drift layer 214 serves as an intermediate voltage blocking layer and has a doping concentration lower than that of the first drift layer (for example, within the range of 1E15 to 5E16 cm^-3 with a thickness of 0.5 μm to 10 μm). This drift layer 214, in comparison with layer 213 and layer 215, generates an intermediate gradient within the electric field in the case of blocking and contributes to assisting in the absorption of the blocking voltage in the blocking state.

[0036] The third drift layer 215 serves as the main blocking voltage layer and also has a doping concentration lower than that of the first drift layer and a doping concentration lower than that of the second drift layer (for example, within the range of 1E15 to 2E16 cm^-3 with a thickness of 0.5 μm to 10 μm). This layer helps in generating a low gradient within the electric field in the case of blocking, whereby, for the same maximum electric field strength, the height of the blocking voltage (the integration of the electric field in the drift zone) is maximized.

[0037] The fourth drift layer 222 is, for example, a spread - epitaxial layer and has a doping concentration higher than that of the second and third drift layers (for example, within the range of 1E15 to 5E16 cm^-3 with a thickness of 0.5 μm to 10 μm). In one form, the fourth drift layer 222 is doped at a higher concentration than the first layer, and in a second form, it is doped at a concentration lower than the first layer (but always higher than the second and third layers). This layer is used to disperse the current in the conducting state, that is, to minimize the contribution of the forward resistance near the trench.

[0038] To obtain the fourth drift layer 222, a layer 216 corresponding to layer 102 in FIG. 1 can be generated as a spread - epitaxial layer. In the upper region of layer 216, an active function region with appropriate doping and structure is created. For example, belonging to the injected active function region are the n+-type doped source layer 108, the p - type doped channel or body layer 106, optionally a p - type doped edge termination (not shown), and an optional n - type doped spread layer 112, as well as the p+-type doped shielding region 107.

[0039] Optionally, this layer 216 can be additionally enhanced, for example, by subsequent ion implantation, i.e., an additional spread layer 112 can be formed. This doping does not necessarily have to cover the entire layer 216 and can also have a position-dependent concentration.

[0040] As a result, a part of layer 216, i.e., the fourth drift layer 222, remains, i.e., it is created equivalently to the drift layer 120 based on FIG. 1. However, here, instead of a homogeneous drift region 120, there is a drift region 220 including four drift layers 213, 214, 215, 222 with different doping concentrations.

[0041] Here, additionally, in one embodiment, a further p+-type doped shielding region 217 is added, and the shielding region 217 extends vertically downward under the gate trench and, in the case shown, into the spread layer 112 and generally towards the drift region 220. The shielding region 217 can be directly adjacent to the gate trench or can be vertically spaced from the gate trench. A p+-type doped contact region 218 extends from this shielding region 217 towards the shielding region 107, especially in the horizontal direction.

[0042] This contact region 218 can be selectively created homogeneously in the y direction, i.e., the region 218 can exist in each x-z cross-section at each position y of the cells within the active region of the component except at the cell ends, so it is hatched in a grid pattern. However, instead, the region 218 can be partially interrupted in the y direction, and each segment of the region 218 can have a limited spread in the y direction, so that only the region 112 exists where there is no region 218. In both of the aforementioned cases, the contact region 218 can be arranged in the right half of the cell. When the contact region 218 has an interruption in the y direction, there can be a part of the contact region 218 arranged in the right half of the cell, and another part can be arranged in the left half of the cell, especially arranged alternately.

[0043] In addition to that, the trench-type MISFET may further include additional structures, such as gate trench 103, a dielectric gate insulating layer 104, 104a (gate oxide) (e.g., SiO2 or another insulating material) on the surface of the trench, where 104 represents the sidewall layer and 104a represents the bottom layer of the trench. The gate electrode (e.g., polysilicon or a metal gate) is represented here by 105, and an insulating layer 110 is applied on the gate electrode.

[0044] The source contact layer of the field effect transistor 200, such as a source metal (e.g., aluminum or copper or a combination of various materials), is represented by 109, and this source contact layer 109 serves for contact with the source layer 108 and the shielding region 107.

[0045] The drain contact layer of the field effect transistor 200, such as a drain metal in contact with the back side of the substrate layer 101, is represented by 111. The surface of the gate trench 103 is covered by a gate insulating layer 104, 104a of a specified thickness, and in this regard, the gate insulator at the gate bottom, layer 104a, may have a different thickness, for example, a larger thickness than that of the sidewall, layer 104. This insulator can be, for example, a homogeneous insulator or a heterogeneous insulator, such as an insulator stack composed of various layers. Generally, materials such as SiO2, High-k materials, SiN, Al2O3, HfO can be used. In addition to this, the gate insulator at the bottom of the trench can be made of a different material than that of the sidewall and / or, in the case of an insulator stack, can have a different ratio of insulating materials. The gate electrode 105 is within the trench 103 and adjacent to layers 104, 104a. The gate electrode is separated from the source contact layer 109 by an insulating layer 110 (e.g., an intermetal dielectric).

[0046] The shielding region 217 (also referred to as BPW) located below the bottom of the trench may or may not touch the trench bottom vertically. In principle, the shielding region 217 shields the gate insulating layers 104, 104a, especially in the trench bottom region 104a, from the high electric fields generated during high drain-source voltages. Thus, the p+ shielding region 107 can be made flatter (i.e., not extending very deep in the vertical direction), which simplifies the process, reduces costs, and minimizes crystal damage based on the lower implantation energy used for its creation.

[0047] On the other hand, a flatter p+ shielding region 107 allows for a thinner defined implantation mask and a more finely structured one, which enables smaller critical dimensions and thus smaller cell pitches. In addition to this, a flatter p+ shielding region 107 results in better current spreading in the lateral direction and thus lower on-resistance Ron*A. Moreover, for example, the dynamic behavior of the intrinsic body diode of the MISFET during reverse recovery (RR) is improved by less charge carrier overflow in the drift region during the forward operation of the diode (less total RR charge, smaller snappiness of the intrinsic body diode). Robustness against bipolar degradation is also improved. Furthermore, the electric field relaxation in the gate insulation region by the shielding region 217 reduces short-channel effects such as drain-induced barrier lowering (DIBL) and in principle enables designs with a flatter body surface and shorter channels, which reduces Ron*A.

[0048] The shielding region 217 or a plurality thereof is preferably created at the bottom of the gate trench 103 by self-aligned ion implantation. By doing so, self-alignment of both structures, i.e., the gate trench and the shielding region 217, is achieved, and the best results in shielding the gate insulators 104, 104a against high electric fields are achieved without an adverse effect on Ron*A.

[0049] To protect the n-type regions adjacent to the sidewalls of the trench from compensation by p-type dopant implantation, a special masking layer, for example, may grow or deposit on the inner walls of the trench sidewalls before implantation. Alternatively, the shielding region 217 may be created in one step together with the p+-type shielding region 107, in which case it is doped through the source layer 108 and the body or channel layer 106 (in the region where the groove would be present) and into it, and subsequently the groove is etched. By this manufacturing method, the processing cost can be reduced at the expense of a small part of the performance.

[0050] The p+-type shielding region 107 may not be deeper than the shielding region 217 and / or the spreading layer 112. The spreading layer 112 may not be deeper than the shielding region 217. The shielding region 217 is connected by the p+-type shielding region 107 and thus the source potential and the deeply implanted contact region 218, and the contact region 218 may be implanted periodically in a third dimension perpendicular to the major longitudinal axis of the groove (in the y direction not shown here).

[0051] The contact region 218 may be implanted at regular intervals, preferably alternately, on one side of the groove (only shown on the left in FIG. 2), but may be present on both sides of the groove at the same position in the third dimension. Alternatively, the contact region 218 may be arranged only on one side of the groove. The spacing from one contact region 218 to the next contact region 218 on the same side of the p+-type shielding region 107 can be freely selected. A suitable compromise between the low resistance of the component and the good connection of the shielding region 217 to the source potential is, for example, about 2 to 20 times the cell pitch of the MISFET. The connection of the shielding region 217 to the source potential gives the shielding region 217 the function of reducing the saturation current of the source-drain current path in case of a short circuit. Thus, the shielding region 217 increases the short-circuit strength of the field-effect transistor.

[0052] The buffer layer 101a doped at a high concentration (compared to 102, 213, 214, 215, 216, or 222) is optional and is used to minimize the on-resistance Ron*A by punch-through design (the high doping level of 101a stops the depletion zone from reaching the substrate before the component is in the blocking state), and to achieve the robustness of the MISFET against bipolar degradation (the high doping level of 101a is associated with a short minority carrier lifetime, which contributes to the reduction of the plasma concentration in the buffer layer).

[0053] Optionally, an additional doping layer (RR optimization layer, not shown) can be inserted between the buffer layer 101a and the first drift layer 213. The doping and thickness of this layer can be optimized to achieve better reverse recovery of the body diode that may be required in some applications.

[0054] The spread layer 112 is also optional as mentioned. To achieve a low forward resistance, it can be doped at a higher concentration than the drift region 120 or 220 and extend vertically from the channel or body layer 106 to below the p+ type shielding region 107. The spread layer 112 can have non-uniform doping in the vertical and / or horizontal directions and can be created by multiple ion implantations with different doses and energies. In particular, the doping profile of the spread layer 112 can be retrograde, i.e., the doping concentration reaches a maximum at a certain depth in the vertical direction downward from the surface.

[0055] As mentioned, the proposed embodiment is not limited to the n-channel MISFET described, but can also be applied to a p-channel MISFET by reversing the n-type doping with p-type doping. Moreover, the proposed embodiment is not limited to SiC, but can also be applied to other materials with a wide bandgap, such as GaN, or materials without a wide bandgap, such as Si.

[0056] FIG. 3 schematically shows the flow of the method in the preferred embodiment, more specifically, the flow of the method for manufacturing a field effect transistor as exemplified in FIG. 2. Basically, the manufacturing has already been described in detail in relation to FIG. 2, and will be briefly summarized again below.

[0057] In step 300, a substrate layer can be prepared first, and an optional buffer layer is applied in step 302 thereon. Further thereon, in step 304, a plurality of drift layers including a wide fourth layer doped with the first type can be applied. Thereafter, in this wide fourth layer, layers such as the mentioned layer, source layer, channel layer, implant for enhancing the spread layer, etc. can be applied, resulting in the final fourth layer. In this further process, in step 306, an (additional) active region can be formed on the uppermost layer of the plurality of drift layers. Such an active region includes, for example, the mentioned shielding region, channel layer, source layer, etc.

Description of the reference numerals

[0058] 101 Substrate layer 101a Buffer layer 103 Gate trench 104 Side gate insulating layer 104a Gate insulating layer at the bottom of the trench 105 Gate electrode 106 Channel layer 107 Shielding region 108 Source layer 109 Source contact layer 110 Insulating layer 111 Drain contact layer 112 Spread layer 121 Upper part of 216 200 Semiconductor component 213 First drift layer 214 Second drift layer 215 Third drift layer 216 Layer 217 Further shielding region 218 Contact region 220 Drift region 222 Fourth drift layer

Claims

1. A semiconductor component (200), in particular a transistor, a source layer (108) doped to a first type, a channel layer (106) doped in particular to the second type, a drift region (220) doped to a first type, - has a substrate layer (101), the channel layer is between the source layer and the substrate layer, and in particular adjacent to the source layer; the drift region (220) is between the channel layer and the substrate layer; The semiconductor component (200) further comprises a gate groove (103), the gate groove (103) extending vertically from the source layer (108) toward the drift region and adjacent to the channel layer (106) and at least a portion of the source layer (108); The semiconductor component (200) further comprises a shielding region (107) doped with a second type of doping, the shielding region (107) extending vertically from the source layer (108) in the direction of the drift region, adjacent to the channel layer (106) and the source layer (108) and separated laterally by the gate groove (103); The semiconductor component (200), wherein the drift region (220) includes a plurality of first-type doped drift layers each having a different doping concentration.

2. The plurality of drift layers are a first drift layer (213) on the side of said substrate layer; a second drift layer (214) adjacent to the first drift layer, the second drift layer (214) having a lower doping concentration than the first drift layer; a third drift layer (215) adjacent to the second drift layer, the third drift layer (215) having a lower doping concentration than the first drift layer and than the second drift layer; and a fourth drift layer (222) adjacent to the third drift layer, the fourth drift layer (222) having a doping concentration higher than the second drift layer and than the third drift layer; The semiconductor component (200) of claim 1, comprising:

3. The semiconductor component (200) of claim 2, wherein the fourth drift layer (222) has a doping concentration equal to or less than the first drift layer, or the fourth drift layer has a doping concentration higher than the first drift layer.

4. The semiconductor device further comprises a buffer layer (101 a) doped with a first type and disposed on the substrate layer, the buffer layer (101 a) being between the first drift layer and the substrate layer; The semiconductor component (200) according to claim 2 or 3, wherein the first drift layer (213) has in particular a lower doping concentration than the buffer layer.

5. 5. The semiconductor component (200) according to claim 1, further comprising a further shielding region (217) doped to a second type, the further shielding region (217) extending vertically below the gate groove (103) towards or into the drift region (220), the further shielding region (217) being connected to the shielding region (107) by means of at least one particularly deeply implanted contact region (218).

6. The semiconductor component (200) of claim 5, wherein the shielding region (217) is formed in a self-aligned manner.

7. The semiconductor component (200) of any one of the preceding claims, further comprising a spreading layer (112) doped to a first type between the channel layer (106) and the drift region.

8. 8. The semiconductor component (200) according to any one of claims 1 to 7, further comprising a gate electrode (105), said gate electrode (105) being insulated with respect to said spreading layer (112) and said channel layer and being applied within said gate groove (103).

9. The semiconductor component (200) according to any one of the preceding claims, which is formed as a SiC field effect transistor or a GaN field effect transistor or a gallium oxide field effect transistor.

10. A method for manufacturing a semiconductor component (200) according to any one of claims 1 to 9, comprising the steps of: Providing (300) the substrate layer; applying (304) the plurality of first type doped drift layers directly or indirectly over the substrate layer; forming (306) a further active region on a topmost layer of the plurality of drift layers; Included are manufacturing methods.

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