Semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor substrate SUB includes a p-type substrate region SB, an n-type buried layer BL on the p-type substrate region SB, and a p-type semiconductor layer EP on the n-type buried layer BL. An n-type semiconductor region DN is formed in the semiconductor layer EP so as to surround the transistor in a plan view and to extend from a main surface of the semiconductor substrate SUB to the n-type buried layer BL. A DTI region 3 is formed so as to penetrate the n-type semiconductor region DN and the n-type buried layer BL and to reach the p-type substrate region SB.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having a transistor as a power switching element and a method for manufacturing the same.

Background Art

[0002] In a power conversion circuit such as an inverter circuit, a power switching element such as an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) is used. The power switching element is formed on a semiconductor substrate. In some cases, transistors constituting other circuits are also formed together on the semiconductor substrate on which the power switching element is formed.

[0003] In FIGS. 19 and 20 of Patent Document 1 (Japanese Patent Application Laid-Open No. 2011-3608), a technique for separating an array arrangement region ARA of an LDMOS transistor by an n-type separation region SR is described. In FIGS. 21 and 22 of Patent Document 1 (Japanese Patent Application Laid-Open No. 2011-3608), a technique for separating an array arrangement region ARA of an LDMOS transistor by a filling insulating film BIS that fills a separation trench TRS is described.

[0004] Patent Document 2 (Japanese Patent Application Laid-Open No. 2011-66067) describes a technique for forming a DTI structure that surrounds, in a plan view, an n-type sinker region NDR in contact with an n-type embedded region NBR and a formation region of a high breakdown voltage lateral MOS transistor.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a semiconductor device having a power switching element, it is desirable to improve the performance as much as possible.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] According to one embodiment, a semiconductor device includes a semiconductor substrate and a transistor formed on a main surface of the semiconductor substrate. The semiconductor substrate has a substrate region of a first conductivity type, a buried layer of a second conductivity type formed on the substrate region, and a semiconductor layer of the first conductivity type formed on the buried layer. A first semiconductor region of the second conductivity type is formed in the semiconductor layer so as to surround the transistor in a plan view and reach the buried layer from the main surface. The semiconductor device further has an insulating region that penetrates the first semiconductor region and the buried layer and reaches the substrate region.

Advantages of the Invention

[0009] According to one embodiment, the performance of the semiconductor device can be improved. Alternatively, the semiconductor device can be miniaturized. Or, the performance of the semiconductor device can be improved and the semiconductor device can be miniaturized.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other. One is related to a modification, details, supplementary explanation, etc. of a part or all of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified and unless it is clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly considered otherwise in principle, those substantially approximating or similar to the shape, etc. are included. This also applies to the above numerical values and ranges.

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Also, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0013] In addition, in the drawings used in the embodiments, hatching may be omitted even in sectional views for easier viewing of the drawings. Also, hatching may be added even in plan views for easier viewing of the drawings.

[0014] Also, a plan view corresponds to the case of viewing from a plane substantially parallel to the main surface or the back surface of the semiconductor substrate SUB. Also, the bottom surface and the lower surface have the same meaning. Also, the height position corresponds to the distance from the back surface of the semiconductor substrate SUB. Also, the depth position corresponds to the distance from the main surface of the semiconductor substrate SUB.

[0015] In addition, in the present application, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only a MOSFET using an oxide film as a gate insulating film but also a MOSFET using an insulating film other than an oxide film as a gate insulating film. Also, an LDMOSFET may be called an HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or a DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0016] Also, an n-channel type MOSFET can be regarded as an n-type MOSFET, and a p-channel type MOSFET can be regarded as a p-type MOSFET. In this case, the n-type means that the conduction type of the channel during on-state is n-type, and the p-type means that the conduction type of the channel during on-state is p-type.

[0017] (Embodiment 1) The planar region shown in FIG. 2 and the planar region shown in FIG. 3 are the same as each other. In FIG. 2, the n-type semiconductor region DN is hatched, the gate electrode GE is shown by a broken line, and the DTI region 3 is shown by a two-dot chain line. In FIG. 3, the DTI region 3, the n-type semiconductor region DN1, the n-type source region SR, the n-type drain region DR, and the gate electrode GE are each hatched. The cross-sectional view taken along the line A-A in FIGS. 2 and 3 corresponds to FIG. 1.

[0018] The semiconductor device of the first embodiment has a power switching element used in a power conversion circuit such as an inverter circuit. Here, it has an LDMOSFET as a transistor constituting the power switching element.

[0019] As shown in FIGS. 1 to 3, the semiconductor device of the first embodiment includes a semiconductor substrate SUB, a STI region 2, a DTI region 3, an LDMOSFET1 formed on the main surface of the semiconductor substrate SUB, an n-type semiconductor region DN formed in the semiconductor substrate SUB, and an insulating film IL formed on the main surface of the semiconductor substrate SUB.

[0020] As shown in FIG. 1, the semiconductor substrate SUB includes a p-type substrate region SB, an n-type buried layer BL formed on the p-type substrate region SB, and a p-type semiconductor layer EP formed on the n-type buried layer BL.

[0021] The p-type substrate region SB is made of, for example, p-type single crystal silicon into which a p-type impurity such as boron (B) is introduced. The n-type buried layer BL is an n-type semiconductor layer. The thickness of the p-type substrate region SB is substantially uniform. The p-type semiconductor layer EP is made of, for example, p-type single crystal silicon formed by epitaxial growth on the n-type buried layer BL.

[0022] The p-type substrate region SB and the n-type buried layer BL constitute the substrate body. For example, the n-type buried layer BL is formed by ion-implanting an n-type impurity into the upper part of a p-type substrate body made of p-type single crystal silicon or the like. In that case, the region below the n-type buried layer BL in the substrate body corresponds to the p-type substrate region SB.

[0023] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the semiconductor layer EP. Also, the back surface of the semiconductor substrate SUB is synonymous with the back surface of the p-type substrate region SB. The main surface of the semiconductor substrate SUB and the back surface of the semiconductor substrate SUB are located on opposite sides of each other.

[0024] The STI (Shallow Trench Isolation) region 2 is composed of an insulating film embedded in a groove formed in the semiconductor substrate SUB. The DTI (Deep Trench Isolation) region 3 is composed of an insulating film embedded in a groove formed in the insulating film IL on the semiconductor substrate SUB and the semiconductor substrate SUB. Both the STI region 2 and the DTI region 3 can be regarded as insulating regions.

[0025] The depth of the DTI region 3 is greater than the depth of the STI region 2. That is, the depth of the bottom surface of the DTI region 3 is greater than the depth of the bottom surface of the STI region 2. The DTI region 3 penetrates through the insulating film IL, the STI region 2, the semiconductor layer EP, and the n-type buried layer BL and reaches the p-type substrate region SB. The bottom surface of the DTI region 3 is deeper than the bottom surface of the n-type buried layer BL and is located in the middle of the thickness of the p-type substrate region SB. The bottom surface of the STI region 2 is shallower than the upper surface of the n-type buried layer BL and is located in the middle of the thickness of the semiconductor layer EP.

[0026] The n-type semiconductor region DN is formed in the semiconductor substrate SUB so as to reach the n-type buried layer BL from the main surface of the semiconductor substrate SUB. The n-type semiconductor region DN is formed in the semiconductor layer EP. The bottom surface of the n-type semiconductor region DN is in contact with the upper surface of the n-type buried layer BL, and the upper surface of the n-type semiconductor region DN reaches the main surface of the semiconductor substrate SUB.

[0027] The n-type semiconductor region DN includes an n-type semiconductor region DN1 and an n-type semiconductor region DN2. The n-type impurity concentration of the n-type semiconductor region DN1 is higher than that of the n-type semiconductor region DN2. The n-type semiconductor region DN1 is formed inside the upper part of the n-type semiconductor region DN, in contact with the main surface of the semiconductor substrate SUB, and is formed over a predetermined depth from the main surface of the semiconductor substrate SUB. The n-type semiconductor region DN2 is located under the STI region 2 and the n-type semiconductor region DN1, and is in contact with the n-type semiconductor region DN1. The bottom surface of the n-type semiconductor region DN2 constitutes the bottom surface of the n-type semiconductor region DN and is in contact with the upper surface of the n-type buried layer BL. The n-type semiconductor region DN1 is electrically connected to the n-type buried layer BL via the n-type semiconductor region DN2.

[0028] In plan view, the n-type semiconductor region DN is formed in the semiconductor layer EP so as to surround the LDMOSFET1. In plan view, the n-type semiconductor region DN has a frame-shaped planar shape. The semiconductor layer EP surrounded by the n-type semiconductor region DN in plan view is referred to as the semiconductor layer EP1. In plan view, the semiconductor layer EP1 is surrounded by the n-type semiconductor region DN.

[0029] The DTI region 3 is formed so as to penetrate the n-type semiconductor region DN. The DTI region 3 penetrates the insulating film IL, the STI region 2, the n-type semiconductor region DN, and the n-type buried layer BL and reaches the p-type substrate region SB. The side surface of the DTI region 3 is in contact with the insulating film IL, the STI region 2, the n-type semiconductor region DN, the n-type buried layer BL, and the p-type substrate region SB, and the bottom surface of the DTI region 3 is in contact with the p-type substrate region SB.

[0030] Since the n-type semiconductor region DN surrounds the LDMOSFET1 in plan view, the DTI region 3 penetrating the n-type semiconductor region DN surrounds the LDMOSFET1 in plan view. Reflecting that the n-type semiconductor region DN has a frame-shaped planar shape in plan view, the DTI region 3 penetrating the n-type semiconductor region DN has a frame-shaped planar shape. In plan view, the DTI region 3 is included in the n-type semiconductor region DN. In plan view, the frame-shaped DTI region 3 has a function of electrically separating the semiconductor layer EP inside the frame-shaped DTI region 3 from the semiconductor layer EP outside the frame-shaped DTI region 3.

[0031] The LDMOSFET1 is an n-type (n-channel type) LDMOSFET.

[0032] The LDMOSFET1 has a p-type well region PB, an n-type drift region ND, an n-type drain region DR, an n-type source region SR, a p-type semiconductor region PR, a gate insulating film GF, and a gate electrode GE.

[0033] The p-type well region PB, the n-type drift region ND, the n-type drain region DR, the n-type source region SR, and the p-type semiconductor region PR are formed in the semiconductor layer EP1. The gate electrode GE is formed on the semiconductor layer EP1 via the gate insulating film GF. The insulating film IL is formed on the main surface of the semiconductor substrate SUB so as to cover the LDMOSFET1.

[0034] The p-type well region (p-type semiconductor region) PB and the n-type drift region (n-type semiconductor region) ND are formed in the upper part of the semiconductor layer EP1. Below the bottom surfaces of the n-type drift region ND and the p-type well region PB respectively, the p-type semiconductor layer EP1 exists. The n-type drift region ND and the p-type well region PB are adjacent to each other in the gate length direction of the LDMOSFET1. Note that the gate length direction of the LDMOSFET1 corresponds to the gate length direction of the gate electrode GE, and the gate width direction of the LDMOSFET1 corresponds to the gate width direction of the gate electrode GE.

[0035] The p-type well region PB is formed so as to surround the n-type source region SR and the p-type semiconductor region PR. The p-type well region PB can function as a back gate. The p-type well region PB can also function as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET1. Between the n-type source region SR and the n-type drain region DR, a channel of the LDMOSFET1 is formed in the upper part of the p-type well region PB located under the gate electrode GE. Hereinafter, the region where the channel of the LDMOSFET1 is formed is referred to as a channel formation region.

[0036] The n-type source region (n-type semiconductor region) SR and the p-type semiconductor region PR are formed in the p-type well region PB. The n-type source region SR is adjacent to the channel formation region of the LDMOSFET1. The p-type impurity concentration of the p-type semiconductor region PR is higher than the p-type impurity concentration of the p-type well region PB.

[0037] In the case of FIGS. 1 to 3, in the gate length direction of the LDMOSFET1, the p-type semiconductor region PR and the n-type source region SR are adjacent to each other. In this case, in a plan view, the n-type source region SR is disposed between the gate electrode GE and the p-type semiconductor region PR. In the gate width direction of the LDMOSFET1, the p-type semiconductor region PR and the n-type source region SR may be alternately arranged.

[0038] The bottom surface of the p-type semiconductor region PR and the bottom surface of the n-type source region SR are in contact with the p-type well region PB. The upper surfaces of the p-type semiconductor region PR and the n-type source region SR reach the main surface of the semiconductor substrate SUB. The p-type semiconductor region PR can function as a contact portion of the p-type well region PB.

[0039] An n-type drain region (n-type semiconductor region) DR is formed within an n-type drift region ND. The upper surface of the n-type drain region DR reaches the main surface of the semiconductor substrate SUB. The n-type impurity concentration of the n-type drain region DR is higher than that of the n-type drift region ND. The n-type drain region DR and the n-type source region SR are spaced apart from each other in the gate length direction of the LDMOSFET1.

[0040] The gate electrode GE is formed on the main surface of the semiconductor substrate SUB between the n-type source region SR and the n-type drain region DR with a gate insulating film GF interposed therebetween. The gate insulating film GF is made of, for example, a silicon oxide film. The gate electrode GE is made of, for example, a single film of a polycrystalline silicon film (doped polysilicon film) or a laminated film of a polycrystalline silicon film and a metal silicide layer.

[0041] In a plan view, an STI region 2 is disposed between the channel formation region of the LDMOSFET1 and the n-type drain region DR, and a part of the gate electrode GE is located on the STI region 2. An n-type drift region ND exists under the STI region 2 intervening between the channel formation region of the LDMOSFET1 and the n-type drain region DR. The bottom surface of the n-type drain region DR is in contact with the n-type drift region ND, and the side surface of the n-type drain region DR is in contact with the STI region 2. Therefore, the n-type drift region ND under the STI region 2 can also function as a conduction path between the channel of the LDMOSFET1 and the n-type drain region DR.

[0042] Note that in FIG. 1, a case where the gate insulating film GF is interposed between the STI region 2 and the gate electrode GE is shown, but there may also be a case where the gate insulating film GF is not interposed between the STI region 2 and the gate electrode GE. Further, sidewall spacers (not shown) made of an insulating film may be formed on both side surfaces of the gate electrode GE.

[0043] A part of the p-type well region PB is located below the gate electrode GE, and a part of the n-type drift region ND is located below the gate electrode GE. A PN junction is formed at the boundary between the p-type well region PB and the n-type drift region ND. This boundary is located below the gate electrode GE and extends in the gate width direction of the LDMOSFET1.

[0044] In a plan view, the gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, a channel composed of an n-type inversion layer is formed in the upper part of the p-type well region PB located below the gate electrode GE. The n-type source region SR and the n-type drain region DR are electrically connected to each other through the channel and the n-type drift region ND.

[0045] In the gate length direction of the LDMOSFET1, the n-type drift region ND is interposed between the p-type well region PB and the n-type drain region DR. Therefore, the n-type drift region ND exists between the channel formation region of the LDMOSFET1 and the n-type drain region DR. Accordingly, in the gate length direction of the LDMOSFET1, the channel formation region and the n-type drift region ND exist between the n-type source region SR and the n-type drain region DR, and the channel formation region is located between the n-type source region SR and the n-type drift region ND. Also, the p-type semiconductor layer EP1 under the n-type drift region ND and under the p-type well region PB can function as a resurf region.

[0046] Also, metal silicide layers (not shown) may be formed on the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the n-type semiconductor region DN1, respectively. This metal silicide layer can be formed using salicide (Self Aligned Silicide) technology.

[0047] Next, the structure on the semiconductor substrate SUB will be described.

[0048] As shown in FIG. 1, the semiconductor device of Embodiment 1 further includes a plurality of plugs (contact plugs) PGD, PGN, PGP, PGS embedded in an insulating film IL, and a plurality of wirings M1D, M1N, M1S formed on the insulating film IL.

[0049] The insulating film IL is formed on the main surface of the semiconductor substrate SUB so as to cover the gate electrode GE. The insulating film IL is composed of, for example, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film. The upper surface of the insulating film IL is planarized.

[0050] A plurality of contact holes (through holes) are formed in the insulating film IL, and a plurality of conductive plugs are formed in the plurality of contact holes. The plurality of plugs includes a plug PGD, a plug PGN, a plug PGS, and a plug PGP. Each of the plugs PGD, PGN, PGP, PGS penetrates the insulating film IL.

[0051] The plug PGD is disposed on the n-type drain region DR and is electrically connected to the n-type drain region DR. The plug PGN is disposed on the n-type semiconductor region DN1 and is electrically connected to the n-type semiconductor region DN1. Therefore, the plug PGN is electrically connected to the n-type semiconductor region DN2 via the n-type semiconductor region DN1, and is further electrically connected to the n-type buried layer BL via the n-type semiconductor region DN2. In plan view, the plug PGN is surrounded by the DTI region 3 (the DTI region 3 penetrating the n-type semiconductor region DN). In other words, in plan view, the plug PGN is disposed in the region surrounded by the DTI region 3.

[0052] The plug PGS is disposed on the n-type source region SR and is electrically connected to the n-type source region SR. The plug PGP is disposed on the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR. Therefore, the plug PGP is electrically connected to the p-type well region PB via the p-type semiconductor region PR.

[0053] Also, plugs are arranged on the gate electrode GE, but in the cross-sectional view of FIG. 1, the plugs on the gate electrode GE are not shown.

[0054] In addition, when a metal silicide layer (not shown) is formed on the n-type drain region DR, the n-type source region SR, the p-type semiconductor region PR, and the n-type semiconductor region DN1, each plug is in contact with the metal silicide layer and is electrically connected to each region under the metal silicide layer through the metal silicide layer.

[0055] A plurality of wirings are formed on the insulating film IL. The plurality of wirings include a source wiring M1S, a drain wiring M1D, and a wiring M1N.

[0056] The drain wiring M1D is electrically connected to the n-type drain region DR through the plug PGD. A drain potential is supplied from the drain wiring M1D to the n-type drain region DR through the plug PGD.

[0057] The wiring M1N is electrically connected to the n-type semiconductor region DN1 through the plug PGN. The potential supplied from the wiring M1N to the n-type semiconductor region DN1 through the plug PGN is further supplied to the n-type buried layer BL through the n-type semiconductor region DN2. The n-type semiconductor region DN functions as a power supply region for supplying power to the n-type buried layer BL. The plug PGN functions as a plug for supplying power to the n-type buried layer BL.

[0058] The source wiring M1S is electrically connected to the n-type source region SR through the plug PGS and is also electrically connected to the p-type semiconductor region PR through the plug PGP. That is, the source wiring M1S is electrically connected to both the plug PGS arranged on the n-type source region SR and the plug PGP arranged on the p-type semiconductor region PR.

[0059] Therefore, the potential supplied from the plug PGS to the n-type source region SR (source potential) and the potential supplied from the plug PGP to the p-type semiconductor region PR are the same as each other. Accordingly, the source potential is supplied from the plug PGS to the n-type source region SR and is also supplied from the plug PGP to the p-type well region PB via the p-type semiconductor region PR.

[0060] A gate wiring that is electrically connected to the gate electrode GE via a plug is formed on the insulating film IL, but the gate wiring is not shown in FIG. 1.

[0061] The source wiring M1S, the drain wiring M1D, the wiring M1N, and the gate wiring are not connected to each other and are separated from each other.

[0062] The illustration and description of the structure above the insulating film IL and the wirings M1D, M1N, and M1S are omitted.

[0063] The LDMOSFET1 may have a configuration in which a plurality of unit LDMOSFETs are connected in parallel. In the cases of FIGS. 1 to 3, the LDMOSFET1 has a configuration in which two unit LDMOSFETs sharing the n-type drain region DR are connected in parallel. The number of unit LDMOSFETs connected in parallel can be set as required.

[0064] <Regarding the manufacturing method of the semiconductor device> As shown in FIG. 4, a semiconductor substrate SUB having a p-type substrate region SB, an n-type buried layer BL on the p-type substrate region SB, and a semiconductor layer EP on the n-type buried layer BL is prepared. In FIG. 4, the entire semiconductor layer EP has a p-type conductivity type. The thickness of the semiconductor layer EP is, for example, about 3 micrometers or more and 15 micrometers or less.

[0065] Before forming the semiconductor layer EP, an n-type buried layer BL can also be formed. For example, after forming the n-type buried layer BL by ion implantation in the surface layer portion of a p-type substrate body composed of a p-type silicon substrate or the like, a p-type semiconductor layer EP can be formed on the n-type buried layer BL using an epitaxial growth method. In that case, the region below the n-type buried layer BL in the substrate body corresponds to the p-type substrate region SB.

[0066] In the first embodiment, a p-type semiconductor substrate is used as the p-type substrate body. An epitaxial substrate composed of a p-type semiconductor substrate and a p-type epitaxial semiconductor layer formed on the p-type semiconductor substrate can also be used as the p-type substrate body.

[0067] Next, as shown in FIG. 5, an n-type semiconductor region DN2 is formed in the semiconductor substrate SUB. For example, after ion implanting n-type impurities into the p-type semiconductor layer EP, a heat treatment (thermal diffusion treatment) for thermally diffusing the n-type impurities is performed to form the n-type semiconductor region DN2. The heat treatment temperature is, for example, about 800 degrees Celsius or higher and 1200 degrees Celsius or lower. The n-type semiconductor region DN2 is formed so as to reach the n-type buried layer BL from the main surface of the semiconductor substrate SUB. The bottom surface of the n-type semiconductor region DN2 is in contact with the n-type buried layer BL. The width W1 of the n-type semiconductor region DN2 is, for example, about 0.5 micrometers or more and 25 micrometers or less.

[0068] Next, as shown in FIG. 6, an n-type drift region ND and a p-type well region PB are formed in the p-type semiconductor layer EP using an ion implantation method or the like, respectively. The p-type impurity concentration of the p-type well region PB is higher than the p-type impurity concentration of the p-type semiconductor layer EP.

[0069] The n-type drift region ND is formed over a predetermined depth from the main surface of the semiconductor substrate SUB. The p-type well region PB is formed over a predetermined depth from the main surface of the semiconductor substrate SUB. Either the n-type drift region ND or the p-type well region PB may be formed first.

[0070] Next, as shown in FIG. 7, the STI region 2 is formed using the STI method.

[0071] After forming a groove in the main surface of the semiconductor substrate SUB, an insulating film made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate SUB so as to fill the groove. Thereafter, the insulating film disposed outside the groove is removed using a method such as CMP (Chemical Mechanical Polishing). Thereby, the STI region 2 made of the insulating film embedded in the groove can be formed.

[0072] Next, as shown in FIG. 8, a gate electrode GE is formed on the main surface of the semiconductor layer EP with a gate insulating film GF interposed therebetween. The gate electrode GE is made of, for example, a polycrystalline silicon film. The gate insulating film GF is made of, for example, a silicon oxide film.

[0073] Next, as shown in FIG. 9, an n-type drain region DR, an n-type source region SR, and an n-type semiconductor region DN1 are formed in the semiconductor layer EP using an ion implantation method or the like.

[0074] The n-type drain region DR is formed in the n-type drift region ND. The n-type impurity concentration of the n-type drain region DR is higher than the n-type impurity concentration of the n-type drift region ND. The n-type source region SR is formed in the p-type well region PB. The n-type semiconductor region DN1 is formed in the n-type semiconductor region DN2. The n-type impurity concentration of the n-type semiconductor region DN1 is higher than the n-type impurity concentration of the n-type semiconductor region DN2. The n-type drain region DR, the n-type source region SR, and the n-type semiconductor region DN1 can be formed by the same ion implantation process to suppress the number of manufacturing steps, but can also be formed by separate ion implantation processes.

[0075] Next, as shown in FIG. 9, a p-type semiconductor region PR is formed in the semiconductor layer EP using an ion implantation method or the like. The p-type semiconductor region PR is formed in the p-type well region PB.

[0076] In the first embodiment, the p-type semiconductor region PR is formed after the n-type source region SR, the n-type drain region DR, and the n-type semiconductor region DN1 are formed. However, the n-type source region SR, the n-type drain region DR, and the n-type semiconductor region DN1 can also be formed after the p-type semiconductor region PR is formed.

[0077] After the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PR, and the n-type semiconductor region DN1 are formed, a metal silicide layer (not shown) may be formed on the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PR, the n-type semiconductor region DN1, and the gate electrode GE. The metal silicide layer is formed using salicide (Self Aligned Silicide) technology.

[0078] Next, as shown in FIG. 10, an insulating film IL is formed on the main surface of the semiconductor substrate SUB by using a method such as CVD (Chemical Vapor Deposition) so as to cover the gate electrode GE. After the formation of the insulating film IL, the upper surface of the insulating film IL can also be polished and planarized by using a method such as CMP.

[0079] Next, as shown in FIG. 11, a groove 4 is formed by etching the insulating film IL, the STI region 2, and the semiconductor substrate SUB using a photoresist pattern (not shown) as an etching mask. Alternatively, the insulating film IL may be etched using a photoresist pattern (not shown) as an etching mask, and after removing the photoresist, the semiconductor substrate SUB may be etched using the insulating film IL as a mask to form the groove 4. The groove 4 penetrates the insulating film IL, the STI region 2, the semiconductor layer EP, and the n-type buried layer BL and reaches the p-type substrate region SB.

[0080] Next, as shown in FIG. 12, a DTI region 3 is formed in the groove 4.

[0081] After forming the groove 4, an insulating film made of a silicon oxide film or the like is formed on the insulating film IL so as to fill the inside of the groove 4. Then, the insulating film disposed outside the groove 4 is removed using a CMP method or the like. Thereby, the DTI region 3 made of the insulating film embedded in the groove 4 can be formed. A void may be formed in the DTI region 3. Also, in the first embodiment, the step of removing the insulating film disposed outside the groove 4 using a CMP method or the like is performed, but this step may not be performed. In that case, the insulating film formed integrally with the DTI region 3 remains on the insulating film IL.

[0082] Next, as shown in FIG. 13, the insulating film IL is etched using a photoresist pattern (not shown) formed on the insulating film IL as an etching mask to form a plurality of contact holes penetrating the insulating film IL. Then, a plurality of conductive plugs are respectively formed in the plurality of contact holes. The plurality of plugs include plugs PGD, PGN, PGP, and PGS.

[0083] For example, a barrier conductor film is formed on the bottom surface of the contact hole, on the side surface of the contact hole, and on the upper surface of the insulating film IL. A main conductor film made of tungsten or the like is formed on the barrier conductor film so as to fill the contact hole. Then, the main conductor film and the barrier conductor film disposed outside the contact hole are removed by a CMP method or the like. Thereby, a plurality of plugs can be formed.

[0084] Next, as shown in FIG. 14, a plurality of wirings are formed on the insulating film IL. The plurality of wirings include wirings M1D, M1N, and M1S. For example, a conductive film is formed on the insulating film IL. Then, the conductive film is patterned using photolithography technology and etching technology to form a plurality of wirings made of the conductive film. The plurality of wirings are preferably aluminum wirings, but wirings using other metal materials, for example, tungsten wirings, can also be applied. Also, as the plurality of wirings, copper wirings formed using damascene technology can be applied.

[0085] By forming an upper insulating film (not shown) and wiring (not shown), a multilayer wiring structure is formed on the semiconductor substrate SUB. The multilayer wiring structure includes a plurality of wiring layers and a plurality of insulating layers. Each of the wirings M1D, M1N, M1S is a wiring of the lowermost wiring layer among the plurality of wiring layers. The multilayer wiring structure includes a plurality of pads (not shown). The plurality of pads include a drain pad electrically connected to the drain wiring M1D, a source pad electrically connected to the source wiring M1S, and a gate pad electrically connected to the gate electrode GE.

[0086] Thereafter, if necessary, after grinding the back surface of the semiconductor substrate SUB, the semiconductor substrate SUB is cut (diced) along the scribe region of the semiconductor substrate SUB. In this way, a semiconductor device as a semiconductor chip can be manufactured.

[0087] <Regarding the process of consideration> FIG. 15 is a circuit diagram showing an inverter circuit INV as an example of a power conversion circuit.

[0088] The inverter circuit INV shown in FIG. 15 has a power transistor TR1 and a power transistor TR2 connected in series. Each of the power transistors TR1, TR2 is a power switching element. The power transistor TR1 is a transistor for a high-side switch (high-potential side switch), and the power transistor TR2 is a transistor for a low-side switch (low-potential side switch). The LDMOSFET1 can be used as the power transistor TR1 or the power transistor TR2.

[0089] Power transistors TR1 and TR2 are connected in series between terminals T1 and T2. The drain D1 of power transistor TR1 is connected to terminal T1. The source S1 of power transistor TR1 is connected to the drain D2 of power transistor TR2. The source S2 of power transistor TR2 is connected to terminal T2. Terminal T3 is electrically connected to both the source S1 of power transistor TR1 and the drain D2 of power transistor TR2. A power supply potential VIN is supplied to terminal T1 from a power supply or the like. A reference potential lower than the power supply potential VIN, for example, a ground potential GND, is supplied to terminal T2. Terminal T3 is an output terminal. Terminal T3 is connected to a load. For example, terminal T3 is connected to a coil CL used in a motor or the like.

[0090] The gate G1 of power transistor TR1 and the gate G2 of power transistor TR2 are connected to a drive circuit, and a gate voltage is supplied from the drive circuit to each of the gates G1 and G2 of power transistors TR1 and TR2. By controlling the gate voltage supplied to the gate G1 of power transistor TR1 and the gate voltage supplied to the gate G2 of power transistor TR2, the operations of power transistors TR1 and TR2 can be controlled.

[0091] Here, a part of the operation of the inverter circuit INV shown in FIG. 15 will be described.

[0092] When the inverter circuit INV is in standby, the gate voltage of power transistor TR1 and the gate voltage of power transistor TR2 are each lower than the threshold voltage (for example, 0V). Therefore, both power transistors TR1 and TR2 are in an off state (non-conducting state), and no current flows through the coil CL.

[0093] Next, while keeping the gate voltage of power transistor TR2 lower than the threshold voltage (e.g., 0V), a gate voltage equal to or higher than the threshold voltage is supplied to the gate G1 of power transistor TR1. Power transistor TR1 turns on (conducts), and power transistor TR2 turns off (non-conducting). The circuit diagram in Fig. 16 shows this state. In the state shown in Fig. 16, current ION flows from terminal T1 to which the power supply potential VIN is supplied, through power transistor TR1 and terminal T3, to coil CL.

[0094] Next, consider the case where, while keeping the gate voltage of power transistor TR2 lower than the threshold voltage (e.g., 0V), the gate voltage of power transistor TR1 is decreased from a voltage equal to or higher than the threshold voltage to a voltage lower than the threshold voltage (e.g., 0V). In this case, when power transistor TR1 is in the on state and power transistor TR2 is in the off state, both power transistors TR1 and TR2 transition to the off state. At this time, an electromotive force acts to suppress the change in the magnetic flux density of coil CL, and a transient state occurs in which terminal T3 becomes a negative potential and current IOF flows from terminal T3 to coil CL. The circuit diagram in Fig. 17 shows this transient state. This transient state (the state where terminal T3 becomes a negative potential) is resolved over time. That is, this transient state (the state where terminal T3 becomes a negative potential) occurs temporarily when both power transistors TR1 and TR2 switch from the on state of power transistor TR1 and the off state of power transistor TR2 to the off state.

[0095] The supply source of current IOF flowing through coil CL is composed of the current flowing from terminal T2, through the parasitic diode formed in power transistor TR2, to terminal T3, and the current supplied from the semiconductor substrate on which power transistor TR2 is formed to the T3 side. That is, in the above transient state shown in Fig. 17, reflecting the fact that current is supplied from the semiconductor substrate on which power transistor TR2 is formed to the T3 side, electrons are injected from the drain D2 of power transistor TR2 into the semiconductor substrate.

[0096] The above transitional state corresponds to a state where the potential of the source S2 of the power transistor TR2 is the ground potential GND and the potential of the drain D2 of the power transistor TR2 is a negative potential. When the LDMOSFET1 of the semiconductor device of the first embodiment is used as the power transistor TR2, in the above transitional state shown in FIG. 17, the potential of the drain region (n-type drain region DR) of the LDMOSFET1 becomes a negative potential.

[0097] When the potential of the drain region (n-type drain region DR) of the LDMOSFET1 becomes a negative potential, electrons are injected from the drain region into the semiconductor substrate SUB. Looking at it from another perspective, reflecting the injection of electrons from the n-type drain region DR into the semiconductor substrate SUB, holes move from the n-type drain region DR to the plug PGD, and further move through the drain wiring M1D and the like to the external terminal T3 of the semiconductor device, so that a current IOF flows from the terminal T3 to the coil CL.

[0098] It is necessary to prevent a problem from occurring in the semiconductor device due to the injection of electrons from the drain region of the LDMOSFET1 into the semiconductor substrate SUB when the drain region of the LDMOSFET1 becomes a negative potential.

[0099] <Regarding the study example> FIG. 18 is a cross-sectional view of a semiconductor device of a study example studied by the present inventor, and a cross-section corresponding to FIG. 1 is shown.

[0100] The semiconductor device of the study example shown in FIG. 18 is different from the semiconductor device of FIG. 1 above in the following points.

[0101] In the case of the study example shown in FIG. 18, the DTI region 3 does not penetrate the n-type semiconductor region DN. In a plan view, the DTI region 3 is arranged so as to surround the entire region including the region surrounded by the n-type semiconductor region DN and the n-type semiconductor region DN.

[0102] <Regarding the features and effects of the first embodiment> As described with reference to FIGS. 15 to 17, when the LDMOSFET1 is used as the power transistor TR2 for the low-side switch, the drain region (n-type drain region DR) of the LDMOSFET1 may have a negative potential. When the n-type drain region DR has a negative potential, electrons are injected from the n-type drain region DR into the semiconductor substrate SUB. The injected electrons are injected into the n-type buried layer BL through the p-type semiconductor layer EP1, and further electrons are injected from the n-type buried layer BL into the p-type substrate region SB under the n-type buried layer BL. When the potential of the n-type drain region DR becomes negative, the potential of the n-type buried layer BL under the p-type semiconductor layer EP1 also tends to become negative. Therefore, electrons are easily injected from the n-type buried layer BL under the p-type semiconductor layer EP1 into the p-type substrate region SB under the n-type buried layer BL. In the p-type semiconductor region, holes are the majority carriers and electrons are the minority carriers. Therefore, when electrons are injected from the n-type buried layer BL into the p-type substrate region SB under the n-type buried layer BL, the electrons injected into the p-type substrate region SB behave as minority carriers. Therefore, electrons can diffuse within the p-type substrate region SB until they recombine with holes and disappear. Therefore, the electrons injected from the n-type buried layer BL into the p-type substrate region SB may move a considerable distance within the p-type substrate region SB. As a result, the electrons that have moved within the p-type substrate region SB may affect the operation of other semiconductor elements formed in the semiconductor substrate SUB. This may affect the characteristics of the other semiconductor elements and lead to a degradation in the performance of the semiconductor device, which is not desirable. Note that the other semiconductor elements are formed in a semiconductor layer EP other than the semiconductor layer EP1 in which the LDMOSFET1 is formed, and are, for example, MOSFETs constituting an information processing circuit or an analog circuit.

[0103] Therefore, in both the semiconductor device of Embodiment 1 shown in FIG. 1 and the semiconductor device of the study example shown in FIG. 18, an n-type semiconductor region DN is formed in the semiconductor substrate SUB. For this reason, a fixed potential can be supplied from the plug PGN to the n-type buried layer BL via the n-type semiconductor region DN. As a result, even when the potential of the n-type drain region DR becomes a negative potential, the potential of the n-type buried layer BL under the p-type semiconductor layer EP1 does not fluctuate and is fixed to the potential supplied from the plug PGN to the n-type buried layer BL via the n-type semiconductor region DN. Therefore, it is possible to prevent the negative potential of the n-type drain region DR from changing the potential of the n-type buried layer BL under the p-type semiconductor layer EP1. As a result, when the potential of the n-type drain region DR becomes a negative potential, it is possible to suppress the phenomenon in which electrons are injected from the n-type buried layer BL under the p-type semiconductor layer EP1 into the p-type substrate region SB. Since the number of electrons injected from the n-type buried layer BL into the p-type substrate region SB can be suppressed, the possibility that the electrons moving in the p-type substrate region SB affect the operation of other semiconductor elements formed in the semiconductor substrate SUB can be reduced. Therefore, the performance of the semiconductor device can be improved.

[0104] However, in the case of the semiconductor device of the study example shown in FIG. 18, in a plan view, the n-type semiconductor region DN is arranged so as to surround the LDMOSFET1, and further, the DTI region 3 is arranged so as to surround the entire region including the region surrounded by the n-type semiconductor region DN and the n-type semiconductor region DN. For this reason, in the case of the semiconductor device of the study example shown in FIG. 18, it is necessary to secure an area for arranging the n-type semiconductor region DN around the LDMOSFET1 and an area for arranging the DTI region 3 around the n-type semiconductor region DN on the main surface of the semiconductor substrate SUB. Therefore, the total area of the semiconductor device becomes large.

[0105] On the other hand, in the case of the semiconductor device of the first embodiment shown in FIGS. 1 to 3, the DTI region 3 is formed so as to penetrate the n-type semiconductor region DN. Therefore, in a plan view, the n-type semiconductor region DN is disposed so as to surround the LDMOSFET 1, and the DTI region 3 is disposed within the n-type semiconductor region DN. In the case of the first embodiment, it is necessary to secure an area for disposing the n-type semiconductor region DN around the LDMOSFET 1 on the main surface of the semiconductor substrate SUB, but it is not necessary to secure an area for disposing the DTI region 3 around the n-type semiconductor region DN. Therefore, compared with the semiconductor device of the study example shown in FIG. 18, in the case of the semiconductor device of the first embodiment shown in FIGS. 1 to 3, the total area of the semiconductor device can be reduced. Accordingly, the semiconductor device can be miniaturized.

[0106] The plug PGN is disposed on the n-type semiconductor region DN1 and is electrically connected to the n-type semiconductor region DN1. The potential supplied from the wiring M1N to the plug PGN is supplied from the plug PGN to the n-type semiconductor region DN1, supplied to the n-type semiconductor region DN2 via the n-type semiconductor region DN1, and further supplied to the n-type buried layer BL via the n-type semiconductor region DN2. The potential supplied from the plug PGN to the n-type buried layer BL via the n-type semiconductor region DN is a fixed potential, preferably a ground potential (zero volts) or a positive potential. That is, as the potential supplied from the plug PGN to the n-type buried layer BL via the n-type semiconductor region DN, a fixed potential that is not a negative potential is preferable. Thereby, the phenomenon that electrons are injected from the n-type buried layer BL into the p-type substrate region SB can be accurately suppressed.

[0107] When the LDMOSFET 1 is used as the power transistor TR2 for the low-side switch, the potential supplied from the plug PGN to the n-type buried layer BL via the n-type semiconductor region DN can be set to the same potential (ground potential) as the source potential supplied from the plug PGS to the n-type source region SR. Thereby, the circuit configuration of the semiconductor device can be simplified.

[0108] When the LDMOSFET1 is used as the power transistor TR1 for the high-side switch, the potential supplied from the plug PGN to the n-type buried layer BL through the n-type semiconductor region DN can be set to the same potential (positive power supply potential) as the drain potential supplied from the plug PGD to the n-type drain region DR. Thereby, the circuit configuration of the semiconductor device can be simplified.

[0109] (Embodiment 2) FIG. 19 is a cross-sectional view of a main part during the manufacturing process of the semiconductor device of the present Embodiment 2.

[0110] Similar to the above Embodiment 1, after preparing the semiconductor substrate SUB shown in FIG. 4 above, in the present Embodiment 2, as shown in FIG. 19, an n-type semiconductor region DN2 is formed in the semiconductor substrate SUB.

[0111] In the present Embodiment 2, the n-type semiconductor region DN2 is formed by a plurality of ion implantation processes. The implantation energies of the plurality of ion implantation processes for forming the n-type semiconductor region DN2 are different from each other.

[0112] For example, by performing ion implantation for forming the n-type semiconductor region DN2a, ion implantation for forming the n-type semiconductor region DN2b, and ion implantation for forming the n-type semiconductor region DN2c, an n-type semiconductor region DN2 composed of the n-type semiconductor region DN2a, the n-type semiconductor region DN2b, and the n-type semiconductor region DN2c can be formed.

[0113] The ion implantation for forming the n-type semiconductor region DN2a, the ion implantation for forming the n-type semiconductor region DN2b, and the ion implantation for forming the n-type semiconductor region DN2c are performed using a common photoresist pattern (not shown) formed on the main surface of the semiconductor substrate SUB as an ion implantation element mask. The implantation energy of the ion implantation for forming the n-type semiconductor region DN2a is greater than the implantation energy of the ion implantation for forming the n-type semiconductor region DN2b, and is also greater than the implantation energy of the ion implantation for forming the n-type semiconductor region DN2c. The implantation energy of the ion implantation for forming the n-type semiconductor region DN2b is greater than the implantation energy of the ion implantation for forming the n-type semiconductor region DN2c.

[0114] As a result, in plan view, the n-type semiconductor region DN2a, the n-type semiconductor region DN2b, and the n-type semiconductor region DN2c overlap with each other, the n-type semiconductor region DN2b is formed under the n-type semiconductor region DN2c, and the n-type semiconductor region DN2a is formed under the n-type semiconductor region DN2b. As a result, the n-type semiconductor region DN2 composed of the n-type semiconductor region DN2a, the n-type semiconductor region DN2b, and the n-type semiconductor region DN2c is formed so as to reach the n-type buried layer BL from the main surface of the semiconductor substrate SUB.

[0115] The subsequent steps in the second embodiment are the same as those in the first embodiment.

[0116] In the first embodiment, the n-type semiconductor region DN2 is formed by one ion implantation and subsequent thermal diffusion treatment. On the other hand, in the second embodiment, the n-type semiconductor region DN2 is formed using a plurality of ion implantations with different implantation energies. Therefore, in the case of the second embodiment, the thermal diffusion distance of the n-type impurity when forming the n-type semiconductor region DN2 can be made smaller than that in the first embodiment. For example, in the second embodiment, after the n-type semiconductor region DN2, no thermal diffusion treatment is performed, or even when thermal diffusion treatment is performed, the temperature of the thermal diffusion treatment can be made lower than the temperature of the thermal diffusion treatment in the first embodiment.

[0117] Therefore, the width W2 (see FIG. 19) of the n-type semiconductor region DN2 in the second embodiment can be made smaller than the width W1 (see FIG. 5) of the n-type semiconductor region DN2 in the first embodiment. For example, the dimension of the width W2 can be set to about 60% to 70% of the width W1. Thereby, the area of the n-type semiconductor region DN disposed around the LDMOSFET1 on the main surface of the semiconductor substrate SUB can be reduced, so that the total area of the semiconductor device can be further reduced. Therefore, the semiconductor device can be further miniaturized.

[0118] (Embodiment 3) FIGS. 20 to 24 are cross-sectional views of main parts during the manufacturing process of the semiconductor device according to the third embodiment. FIG. 20 corresponds to FIG. 10 above, and shows the stage where the insulating film IL is formed.

[0119] In the third embodiment, the step of forming the n-type semiconductor region DN2 in FIG. 5 above is not performed. The other steps are performed in the same manner as in the first embodiment, and the structure of FIG. 20 corresponding to FIG. 10 above is obtained. Therefore, in FIG. 20, the n-type semiconductor region DN2 is not formed in the semiconductor substrate SUB.

[0120] After the insulating film IL is formed, as shown in FIG. 21, the insulating film IL, the STI region 2, and the semiconductor substrate SUB are etched using a photoresist pattern (not shown) as an etching mask to form the groove 4. Alternatively, the insulating film IL is etched using a photoresist pattern (not shown) as an etching mask, the photoresist is removed, and then the semiconductor substrate SUB is etched using the insulating film IL as a mask to form the groove 4. The groove 4 penetrates the insulating film IL, the STI region 2, the semiconductor layer EP, and the n-type buried layer BL and reaches the p-type substrate region SB.

[0121] Next, as shown in FIG. 22, an n-type semiconductor region DN2d is formed in the semiconductor substrate SUB by oblique ion implantation of n-type impurities. The n-type semiconductor region DN2d is formed by implanting n-type impurities into the semiconductor layer EP from the side surface of the groove 4. Therefore, the n-type semiconductor region DN2d is formed so as to be in contact with the side surface of the groove 4. Reflecting this, the groove 4 penetrates the n-type semiconductor region DN2d.

[0122] The conditions for the oblique ion implantation are set according to the thickness of the insulating film IL and the width of the groove 4, etc. For example, the implantation angle of the oblique ion implantation is about 4 degrees or more and 10 degrees or less. Note that the implantation angle of the oblique ion implantation corresponds to the inclination angle with respect to the normal direction of the main surface of the semiconductor substrate SUB.

[0123] The n-type semiconductor region DN2d corresponds to the above-described n-type semiconductor region DN2. The upper surface of the n-type semiconductor region DN2d is in contact with the bottom surface of the n-type semiconductor region DN1, and the bottom surface of the n-type semiconductor region DN2d is in contact with the n-type buried layer BL. Therefore, the n-type semiconductor region DN1 is electrically connected to the n-type buried layer BL via the n-type semiconductor region DN2d. In the third embodiment, the n-type semiconductor region DN2 is formed by the n-type semiconductor region DN2d and the n-type semiconductor region DN1. The n-type impurity concentration of the n-type semiconductor region DN1 is higher than the n-type impurity concentration of the n-type semiconductor region DN2d.

[0124] Next, as shown in FIG. 23, a DTI region 3 is formed in the groove 4.

[0125] After forming the n-type semiconductor region DN2d, an insulating film made of a silicon oxide film or the like is formed on the insulating film IL so as to fill the groove 4. Then, the insulating film disposed outside the groove 4 is removed using a CMP method or the like. Thereby, a DTI region 3 made of an insulating film embedded in the groove 4 can be formed. A void portion may be formed in the DTI region 3. Also, in the third embodiment, the step of removing the insulating film disposed outside the groove 4 using a CMP method or the like is performed, but this step may not be performed. In that case, the insulating film formed integrally with the DTI region 3 remains on the insulating film IL.

[0126] Since the groove 4 penetrates the STI region 2, the n-type semiconductor region DN2d, and the n-type buried layer BL, the DTI region 3 embedded in the groove 4 penetrates the STI region 2, the n-type semiconductor region DN2d, and the n-type buried layer BL.

[0127] Next, as shown in FIG. 24, in the third embodiment, in the same manner as in the first embodiment, a plurality of contact holes are formed in the insulating film IL, a plurality of plugs are formed in the plurality of contact holes, and a plurality of wirings are formed on the insulating film IL.

[0128] The width W3 (see FIG. 22) of the n-type semiconductor region DN2d can be made smaller than the width W1 (see FIG. 5) of the n-type semiconductor region DN2 in the first embodiment and the width W2 (see FIG. 19) of the n-type semiconductor region DN2 in the second embodiment. As a result, the area of the n-type semiconductor region DN disposed around the LDMOSFET1 on the main surface of the semiconductor substrate SUB can be reduced, so that the total area of the semiconductor device can be further reduced. Therefore, further miniaturization of the semiconductor device can be achieved.

[0129] (Embodiment 4) FIG. 25 is a cross-sectional view of a main part of the semiconductor device according to the fourth embodiment.

[0130] In the fourth embodiment, the n-type semiconductor region DN1 is not formed, and instead, an n-type semiconductor region DN2e is formed in place of the n-type semiconductor region DN2. In the fourth embodiment, the n-type semiconductor region DN2e can be formed by the same method as the formation method of the n-type semiconductor region DN2d in the third embodiment.

[0131] The n-type semiconductor region DN2e is formed so as to be in contact with the n-type source region SR. The upper surface of the n-type semiconductor region DN2e is in contact with the bottom surface of the n-type source region SR and the bottom surface of the STI region 2, and the bottom surface of the n-type semiconductor region DN2e is in contact with the n-type buried layer BL. Therefore, the n-type source region SR is electrically connected to the n-type buried layer BL via the n-type semiconductor region DN2e. In Embodiment 4, the n-type semiconductor region DN2 is formed by the n-type semiconductor region DN2e. The n-type impurity concentration of the n-type source region SR is higher than the n-type impurity concentration of the n-type semiconductor region DN2e. The DTI region 3 penetrates the insulating film IL, the STI region 2, the n-type semiconductor region DN2e, and the n-type buried layer BL.

[0132] In the case of FIG. 25, the n-type source region SR and the p-type semiconductor region PR are alternately arranged in the gate width direction of the gate electrode GE. Since FIG. 25 is a cross-sectional view taken across the n-type source region SR, the n-type source region SR is shown in FIG. 25, but the p-type semiconductor region PR is not shown in FIG. 25.

[0133] In Embodiment 4, the plug PGN and the wiring M1N are not formed. In Embodiment 4, the source wiring M1S is electrically connected to the n-type source region SR via the plug PGS, and is further electrically connected to the n-type buried layer BL via the n-type semiconductor region DN2e. Therefore, the potential (source potential) supplied from the plug PGS to the n-type source region SR is further supplied to the n-type buried layer BL via the n-type semiconductor region DN2e. Also, the source wiring M1S is electrically connected to the p-type semiconductor region PR via the plug PGP, and is further electrically connected to the p-type well region PB.

[0134] Therefore, the potential (source potential) supplied from the source wiring M1S to the n-type source region SR via the plug PGS is further supplied to the n-type buried layer BL via the n-type semiconductor region DN2e. Also, the same potential as the potential (source potential) supplied from the source wiring M1S to the n-type source region SR via the plug PGS is supplied from the source wiring M1S to the p-type semiconductor region PR via the plug PGP, and is further supplied from the p-type semiconductor region PR to the p-type well region PB.

[0135] Other configurations of the semiconductor device according to Embodiment 4 are the same as those of the semiconductor device according to Embodiment 3 described above.

[0136] Also, in Embodiment 4, the n-type semiconductor region DN2e is formed by the same method as the method for forming the n-type semiconductor region DN2d in Embodiment 3 described above, but the n-type semiconductor region DN2e can also be formed by the same method as the method for forming the n-type semiconductor region DN2 in Embodiment 1 or Embodiment 2 described above.

[0137] In Embodiment 4, since the n-type semiconductor region DN can be disposed in contact with the n-type source region SR, the total area of the semiconductor device can be further reduced as compared with Embodiments 1, 2, and 3 described above. Therefore, further miniaturization of the semiconductor device can be achieved.

[0138] In the case of Embodiment 4, the potential of the n-type buried layer BL is fixed to the source potential supplied from the plug PGS to the n-type source region SR.

[0139] In the cases of Embodiments 1, 2, and 3 described above, the potential of the n-type buried layer BL is fixed to the potential supplied from the plug PGN to the n-type semiconductor region DN. For this reason, in the cases of Embodiments 1, 2, and 3 described above, the potential of the n-type buried layer BL can be controlled independently of the source potential supplied from the plug PGS to the n-type source region SR.

[0140] (Embodiment 5) FIG. 26 is a cross-sectional view of a main part of a semiconductor package (semiconductor device) PKG1 in which a semiconductor device (semiconductor chip) CP1 according to Embodiment 5 is used.

[0141] As shown in FIG. 26, the semiconductor package PKG1 has a die pad DP and a semiconductor device CP1 disposed on the die pad DP via a conductive bonding material BD. The semiconductor package PKG1 further has a plurality of conductive members (not shown) that electrically connect a plurality of pads (not shown) and a plurality of leads (not shown) of the semiconductor device CP1, respectively. As the conductive member, for example, a bonding wire or a metal plate can be used. The semiconductor package PKG1 further has a resin sealing portion (not shown) that seals the semiconductor device CP1, the die pad DP, the plurality of leads, and the plurality of conductive members.

[0142] The die pad DP is a chip mounting portion for mounting the semiconductor device CP1 and has conductivity. The die pad DP is made of a metal material such as copper. The bonding material BD is made of, for example, solder, silver paste, or conductive DAF (Die Attach Film).

[0143] The configuration of the semiconductor device CP1 will be described below.

[0144] The semiconductor device CP1 of the fifth embodiment has a back surface electrode BE formed on the back surface of the semiconductor substrate SUB. And in the p-type substrate region SB, a p-type semiconductor region PC is formed so as to be in contact with the back surface electrode BE. The back surface electrode BE is electrically connected to the p-type semiconductor region PC. The p-type impurity concentration of the p-type semiconductor region PC is higher than the p-type impurity concentration of the p-type substrate region SB. The p-type semiconductor region PC is formed in a layer so as to be in contact with the back surface electrode BE. The p-type semiconductor region PC and the n-type buried layer BL are separated from each other, and a p-type substrate region SB having a p-type impurity concentration lower than that of the p-type semiconductor region PC is interposed between the p-type semiconductor region PC and the n-type buried layer BL.

[0145] The other configurations of the semiconductor device CP1 of the fifth embodiment are the same as those of any of the semiconductor devices of the first, second, third, and fourth embodiments.

[0146] The manufacturing process of the semiconductor device CP1 of the fifth embodiment will be described below.

[0147] Similar to any of the above-described Embodiments 1, 2, 3, and 4, after performing up to the step of forming a multilayer wiring structure on the semiconductor substrate SUB, the back surface of the semiconductor substrate SUB is ground as necessary.

[0148] Next, in the present Embodiment 5, a p-type semiconductor region PC is formed by ion implantation over a predetermined depth from the back surface of the semiconductor substrate SUB within the p-type substrate region SB.

[0149] Next, a back surface electrode BE is formed on the back surface of the semiconductor substrate SUB using a sputtering method or the like. The back surface electrode BE is formed so as to be in contact with the p-type semiconductor region PC. The back surface electrode BE is electrically connected to the p-type semiconductor region PC.

[0150] Thereafter, the semiconductor substrate SUB is cut (diced) along the scribe region of the semiconductor substrate SUB. Thereby, a semiconductor device CP1 as a semiconductor chip can be obtained.

[0151] The manufacturing process of the semiconductor package PKG1 will be briefly described below.

[0152] The semiconductor device CP1 is disposed on the die pad DP via a conductive bonding material BD. The back surface electrode BE of the semiconductor device CP1 is electrically connected to the die pad DP via the conductive bonding material BD. Next, a plurality of pads (not shown) and a plurality of leads (not shown) of the semiconductor device CP1 are electrically connected to each other via a plurality of conductive members (not shown). Next, a resin sealing portion (not shown) for sealing the semiconductor device CP1, the die pad DP, the plurality of leads, and the plurality of conductive members is formed. Thereafter, as necessary, a cutting process of the lead frame or the like is performed.

[0153] In the semiconductor package PKG1 of the fifth embodiment, the die pad DP is electrically connected to the back surface electrode BE via a conductive bonding material BD, and is further electrically connected to the p-type semiconductor region PC via the back surface electrode BE. The die pad DP of the semiconductor package PKG1 is connected to the ground potential. Therefore, the ground potential is supplied from the die pad DP to the back surface electrode BE via the conductive bonding material BD, and further the ground potential is supplied to the p-type semiconductor region PC via the back surface electrode BE.

[0154] For example, when mounting the semiconductor package PKG1 on a wiring board, the die pad DP of the semiconductor package PKG1 is electrically connected to the ground terminal of the wiring board via solder or the like. Thereby, the ground potential can be supplied from the ground terminal of the wiring board to the die pad DP of the semiconductor package PKG1 via solder or the like, and further the ground potential can be supplied from the die pad DP to the back surface electrode BE via the conductive bonding material BD.

[0155] As described above, when electrons are injected from the n-type buried layer BL into the p-type substrate region SB, the electrons injected into the p-type substrate region SB behave as minority carriers, and thus can move within the p-type substrate region SB by diffusion until they recombine with holes and disappear. In this case, there is a concern that the electrons that have moved within the p-type substrate region SB may affect the operation of other semiconductor elements formed in the semiconductor substrate SUB.

[0156] In the fifth embodiment, since the ground potential is supplied to the p-type semiconductor region PC from the die pad DP via the conductive bonding material BD and the back surface electrode BE, holes can be supplied from the back surface electrode BE to the p-type semiconductor region PC. Thereby, the phenomenon that the electrons injected from the n-type buried layer BL into the p-type substrate region SB move into the p-type semiconductor region PC and recombine with holes in the p-type semiconductor region PC can be promoted. As a result, the number of electrons moving within the p-type substrate region SB can be suppressed, and thus the possibility that the electrons that have moved within the p-type substrate region SB may affect the operation of other semiconductor elements formed in the semiconductor substrate SUB can be reduced. Therefore, the performance of the semiconductor device can be further improved.

[0157] In the semiconductor device CP1 of Embodiment 5, the DTI region 3 is formed so as to penetrate the n-type semiconductor region DN. As a result, as described in Embodiment 1 above, the total area of the semiconductor device CP1 can be reduced, and the semiconductor device CP1 can be miniaturized.

[0158] In the semiconductor device CP1 of the present Embodiment 5, there may be a case where the DTI region 3 does not penetrate the n-type semiconductor region DN, and the DTI region 3 is arranged so as to surround the entire region of the semiconductor layer EP1 and the n-type semiconductor region DN in plan view. Also in that case, since holes can be supplied from the back electrode BE to the p-type semiconductor region PC, electrons injected from the n-type buried layer BL into the p-type substrate region SB move into the p-type semiconductor region PC, and the phenomenon of recombination with holes in the p-type semiconductor region PC can be promoted. As a result, the number of electrons moving in the p-type substrate region SB can be suppressed, so that the possibility that the electrons moving in the p-type substrate region SB affect the operation of other semiconductor elements formed in the semiconductor substrate SUB can be reduced. Therefore, the performance of the semiconductor device can be improved.

[0159] (Embodiment 6) FIG. 27 is a cross-sectional view of a main part of a semiconductor package (semiconductor device) PKG2 in which the semiconductor device (semiconductor chip) CP2 of the present Embodiment 6 is used.

[0160] As shown in FIG. 27, the semiconductor package PKG2 includes a die pad DP and a semiconductor device CP2 disposed on the die pad DP via a conductive bonding material BD. The semiconductor package PKG2 further includes a plurality of conductive members (not shown) that electrically connect a plurality of pads (not shown) and a plurality of leads (not shown) of the semiconductor device CP2, respectively. The semiconductor package PKG2 further includes a resin sealing portion (not shown) that seals the semiconductor device CP2, the die pad DP, the plurality of leads, and the plurality of conductive members.

[0161] The configuration of the semiconductor device CP2 will be described below.

[0162] The semiconductor device CP2 of Embodiment 6 has a back electrode BE formed on the back surface of the semiconductor substrate SUB. And in the p-type substrate region SB, an n-type semiconductor region NC is formed so as to be in contact with the back electrode BE. The back electrode BE is electrically connected to the n-type semiconductor region NC. The n-type semiconductor region NC is formed in a layer so as to be in contact with the back electrode BE. The n-type semiconductor region NC and the n-type buried layer BL are separated from each other, and a p-type substrate region SB is interposed between the n-type semiconductor region NC and the n-type buried layer BL.

[0163] Other configurations of the semiconductor device CP2 of Embodiment 6 are the same as those of any of the semiconductor devices of Embodiments 1, 2, 3, and 4.

[0164] The manufacturing process of the semiconductor device CP2 of Embodiment 6 is the same as that of the semiconductor device CP1 of Embodiment 5, except that an n-type semiconductor region NC is formed instead of the p-type semiconductor region PC.

[0165] The manufacturing process of the semiconductor package PKG2 of Embodiment 6 is the same as that of the semiconductor package PKG1 of Embodiment 5, except that the semiconductor device CP2 is used instead of the semiconductor device CP1.

[0166] In the semiconductor package PKG2 of Embodiment 6, the die pad DP is electrically connected to the back electrode BE via a conductive bonding material BD, and is further electrically connected to the n-type semiconductor region NC via the back electrode BE. The die pad DP of the semiconductor package PKG2 is connected to a positive fixed potential. For this reason, a positive fixed potential is supplied from the die pad DP to the back electrode BE via the conductive bonding material BD, and a positive fixed potential is further supplied to the n-type semiconductor region NC via the back electrode BE. As the positive fixed potential, for example, a positive power supply potential can be used.

[0167] For example, when mounting the semiconductor package PKG2 on a wiring board, the die pad DP of the semiconductor package PKG2 is electrically connected to the terminals of the wiring board via solder or the like. Thereby, a positive fixed potential can be supplied from the terminals of the wiring board to the die pad DP of the semiconductor package PKG2 via solder or the like, and further a positive fixed potential can be supplied from the die pad DP to the back surface electrode BE via the conductive bonding material BD.

[0168] The positive fixed potential supplied to the back surface electrode BE of the semiconductor device CP2 is preferably the same as or higher than the highest potential among the source potential supplied from the plug PGS to the n-type source region SR, the drain potential supplied from the plug PGD to the n-type drain region DR, and the potential supplied from the plug PGN to the n-type semiconductor region DN.

[0169] As described above, when electrons are injected from the n-type buried layer BL into the p-type substrate region SB, the electrons injected into the p-type substrate region SB act as minority carriers, and thus can move by diffusion within the p-type substrate region SB until they recombine with holes and disappear. In this case, there is a concern that the electrons that have moved within the p-type substrate region SB may affect the operation of other semiconductor elements formed in the semiconductor substrate SUB.

[0170] In the sixth embodiment, a positive fixed potential is supplied from the die pad DP to the n-type semiconductor region NC via the conductive bonding material BD and the back surface electrode BE. Therefore, the electrons injected from the n-type buried layer BL into the p-type substrate region SB move to the n-type semiconductor region NC, and further move from the n-type semiconductor region NC to the back surface electrode BE. The electrons that have moved from the n-type semiconductor region NC to the back surface electrode BE can move to the die pad DP via the conductive bonding material BD, and further move from the die pad DP to the terminals of the wiring board on which the semiconductor package PKG2 is mounted.

[0171] By supplying a positive fixed potential to the back electrode BE of the semiconductor device CP2, a part of the electrons injected from the n-type buried layer BL into the p-type substrate region SB can flow to the die pad DP through the n-type semiconductor region NC, the back electrode BE, and the conductive bonding material BD. As a result, the number of electrons moving in the p-type substrate region SB can be suppressed, so that the possibility that the electrons moving in the p-type substrate region SB affect the operation of other semiconductor elements formed in the semiconductor substrate SUB can be reduced. Therefore, the performance of the semiconductor device can be further improved.

[0172] In the semiconductor device CP2 of Embodiment 6, the DTI region 3 is formed so as to penetrate the n-type semiconductor region DN. Thereby, as described in the above Embodiment 1, the total area of the semiconductor device CP2 can be reduced, and the semiconductor device CP2 can be miniaturized.

[0173] In the semiconductor device CP2 of the present Embodiment 6, there may be a case where the DTI region 3 does not penetrate the n-type semiconductor region DN and the DTI region 3 is arranged so as to surround the entire region of the semiconductor layer EP1 and the n-type semiconductor region DN in plan view. Also in that case, since a positive fixed potential can be supplied to the back electrode BE, a part of the electrons injected from the n-type buried layer BL into the p-type substrate region SB can flow to the die pad DP through the n-type semiconductor region NC, the back electrode BE, and the conductive bonding material BD. As a result, the number of electrons moving in the p-type substrate region SB can be suppressed, so that the possibility that the electrons moving in the p-type substrate region SB affect the operation of other semiconductor elements formed in the semiconductor substrate SUB can be reduced. Therefore, the performance of the semiconductor device can be improved.

[0174] As described above, the invention made by the present inventor has been specifically described based on its embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0175] 1 LDMOSFET 2 STI regions 3 DTI regions 4 trenches BD bonding material BE backside electrode BL n-type buried layer CL coil CP1, CP2 semiconductor devices D1, D2 drains DN, DN1, DN2, DN2a, DN2b, DN2c, DN2d, DN2e n-type semiconductor regions DP die pad DR n-type drain region EP, EP1 semiconductor layers G1, G2 gates GE gate electrode GF gate insulating film IL insulating film INV inverter circuit M1N wiring M1D drain wiring M1S source wiring ND n-type drift region PB p-type well region PC, PR p-type semiconductor regions PGD, PGN, PGS plugs PKG1, PKG2 semiconductor packages S1, S2 sources SB p-type substrate region SR n-type source region SUB semiconductor substrate TR1, TR2 power transistors

Claims

1. A semiconductor substrate having a main surface and a back surface opposite to the main surface, a transistor formed on the main surface of the semiconductor substrate, an insulating film formed on the main surface of the semiconductor substrate so as to cover the transistor, a first contact plug embedded in the insulating film, and including the semiconductor substrate has a substrate region of a first conductivity type, an embedded layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, a semiconductor layer of the first conductivity type formed on the embedded layer, a first semiconductor region of the second conductivity type formed in the semiconductor layer so as to surround the transistor in plan view and formed so as to reach the embedded layer from the main surface, and having the first contact plug is disposed on the first semiconductor region and is electrically connected to the first semiconductor region, and further has an insulating region that penetrates the first semiconductor region and the embedded layer and reaches the substrate region, a semiconductor device.

2. In the semiconductor device according to Claim 1, the insulating region is formed so as to surround the transistor in plan view, a semiconductor device.

3. In the semiconductor device according to Claim 2, the insulating region penetrates the insulating film, the first semiconductor region, and the embedded layer and reaches the substrate region, a semiconductor device.

4. In the semiconductor device according to Claim 3, further has an STI region formed on the main surface of the semiconductor substrate, the insulating region is a DTI region, and a bottom surface of the DTI region is deeper than a bottom surface of the STI region, a semiconductor device.

5. In the semiconductor device according to claim 1, the transistor is a power switching element, the semiconductor device.

6. In the semiconductor device according to claim 5, the transistor is the transistor of the second conductivity type, the semiconductor device.

7. In the semiconductor device according to claim 5, the first conductivity type is p-type, the second conductivity type is n-type, the transistor is an n-type MOSFET, the semiconductor device.

8. In the semiconductor device according to claim 7, the transistor is a gate electrode formed on the semiconductor layer via a gate insulating film, a source region formed in the semiconductor layer, a drain region formed in the semiconductor layer, and has the source region and the drain region are surrounded by the first semiconductor region in a plan view, the semiconductor device.

9. In the semiconductor device according to claim 1, in a plan view, the first contact plug is surrounded by the insulating region, a first fixed potential is supplied from the first contact plug to the buried layer through the first semiconductor region, the semiconductor device.

10. In the semiconductor device according to claim 9, the first conductivity type is p-type, the second conductivity type is n-type, the first fixed potential is a ground potential or a positive potential, the semiconductor device.

11. In the semiconductor device according to claim 1, A second semiconductor region of the first conductivity type, which is formed within the substrate region and reaches the back surface; A back surface electrode formed on the back surface of the semiconductor substrate; And further has; The impurity concentration of the second semiconductor region of the first conductivity type is higher than the impurity concentration of the substrate region of the first conductivity type; The semiconductor device is disposed on the die pad via the conductive bonding material such that the back surface electrode faces the die pad via the conductive bonding material; The back surface electrode is electrically connected to the die pad via the bonding material; A semiconductor device in which a ground potential is supplied from the die pad to the back surface electrode via the bonding material.

12. In the semiconductor device according to claim 1, A third semiconductor region of the second conductivity type, which is formed within the substrate region and reaches the back surface; A back surface electrode formed on the back surface of the semiconductor substrate; And further has; The semiconductor device is disposed on the die pad via the conductive bonding material such that the back surface electrode faces the die pad via the conductive bonding material; The back surface electrode is electrically connected to the die pad via the bonding material; A semiconductor device in which a positive second fixed potential is supplied from the die pad to the back surface electrode via the bonding material.

13. (a) A step of preparing a semiconductor substrate having a substrate region of the first conductivity type, a buried layer of the second conductivity type opposite to the first conductivity type formed on the substrate region, and a semiconductor layer of the first conductivity type formed on the buried layer; (b) A step of forming a first semiconductor region of the second conductivity type in the semiconductor layer so as to reach the buried layer from the main surface of the semiconductor substrate; (c) After the step (b), a step of forming a transistor on the main surface of the semiconductor substrate; (d) After the step (c), a step of forming an insulating film on the main surface of the semiconductor substrate so as to cover the transistor; (e) After the step (d), a step of forming an insulating region that penetrates the insulating film, the first semiconductor region, and the embedded layer and reaches the substrate region; (f) After the step (e), a step of forming a first contact plug embedded in the insulating film; having; In plan view, the transistor is surrounded by the first semiconductor region; The first contact plug is electrically connected to the first semiconductor region, and a method for manufacturing a semiconductor device.

14. In the method for manufacturing a semiconductor device according to claim 13, In the step (b), the first semiconductor region is formed by one ion implantation and a heat treatment after the ion implantation, and a method for manufacturing a semiconductor device.

15. In the method for manufacturing a semiconductor device according to claim 13, In the step (b), the first semiconductor region is formed by a plurality of ion implantations, The implantation energies of the plurality of ion implantations are different from each other, and a method for manufacturing a semiconductor device.

16. (a) A step of preparing a semiconductor substrate having a first conductivity type substrate region, an embedded layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a semiconductor layer of the first conductivity type formed on the embedded layer; (b) A step of forming a transistor on the main surface of the semiconductor substrate; (c) After the step (b), a step of forming an insulating film on the main surface of the semiconductor substrate so as to cover the transistor; (d) After the step (c), a step of forming a groove that penetrates the insulating film, the semiconductor layer, and the embedded layer and reaches the substrate region; (e) After the step (d), by implanting the impurity of the second conductivity type into the semiconductor layer from the side surface of the groove using oblique ion implantation, a first semiconductor region of the second conductivity type reaching the embedded layer is formed; (f) After the step (e), a step of forming an insulating region embedded in the groove; (g) After the step (f), a step of forming a first contact plug embedded in the insulating film; having; In a plan view, the transistor is surrounded by the first semiconductor region; The first contact plug is electrically connected to the first semiconductor region, a method of manufacturing a semiconductor device.

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