Epitaxial silicon wafer and method for producing the same

Abstract

To provide an epitaxial silicon wafer and a method for producing the same, capable of enhancing the uniformity of the in-plane distribution of BMD densities.SOLUTION: An epitaxial silicon wafer 1 comprises a silicon wafer 2 in which the entire surface, excluding an edge region E from an outermost edge PE to 2 mm inward, is a COP region, and an epitaxial silicon film 3 formed on the surface of the silicon wafer 2. The average COP size in a peripheral region PX, located within 5 mm inward from the outermost edge PE of a silicon wafer 3, is 75 nm or less.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an epitaxial silicon wafer and a method for manufacturing the same.

Background Art

[0002] Epitaxial silicon wafers are widely used as substrate materials for semiconductor devices. An epitaxial silicon wafer is formed by depositing a silicon epitaxial film on a silicon wafer and has the feature of high crystal perfection.

[0003] Heavy metal impurities in an epitaxial silicon wafer cause deterioration of the characteristics of semiconductor devices, so it is desirable to minimize them. Gettering technology is one of the techniques for reducing the influence of heavy metal impurities. As one of this gettering technology, intrinsic gettering (IG) is known, in which oxygen precipitates (BMD: Bulk Micro Defect) are formed in a silicon wafer and heavy metal impurities are trapped there. In order to enhance the gettering ability, recent epitaxial silicon wafers are required to have a BMD density of 1×10 8 pieces / cm 3 or more.

[0004] Patent Document 1 describes that by performing a heat treatment at a temperature of 700 to 900°C for 15 minutes to 4 hours in advance before performing an epitaxial growth process using a nitrogen-doped silicon wafer, an epitaxial silicon wafer having a BMD density of 3×10 4 / cm 2 or more can be manufactured.

[0005] Further, Patent Document 2 discloses that when the nitrogen concentration is 1×10 12 to 1×10 13 atoms / cm 3An epitaxial silicon wafer is described, which is adjusted to and has an epitaxial silicon film formed on the surface of a silicon wafer composed of a COP region. The internal BMD density of the silicon wafer subjected to the evaluation heat treatment in this epitaxial silicon wafer is 1×10 8 ~3×10 9 / cm 3 across the entire radial direction of the wafer. Also, the average density of BMD in the outer peripheral region 1 to 10 mm inward from the outermost periphery of the silicon wafer is lower than the average density of BMD in the central region, the degree of variation in BMD density in the outer peripheral region is 3 or less, and the residual oxygen concentration in the outer peripheral region is 8×10 17 atoms / cm 3 or more.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] Most of the silicon single crystals used as the substrate material for epitaxial silicon wafers are manufactured by the Czochralski method (CZ method). Conventionally, in the production of silicon single crystals for epitaxial silicon wafers, priority has been given to productivity rather than crystal quality, and the silicon single crystal has been pulled up at the maximum pulling speed at which the crystal does not deform. This is because an epitaxial silicon film is formed on the surface of the silicon substrate, and it has been considered that the influence of the crystal quality of the silicon substrate on the quality of semiconductor devices is extremely small.

[0008] However, the faster the pulling speed, the more COPs (Crystal Originated Particles) are generated in the silicon single crystal, and the larger the COP size becomes. COP is a void defect formed by the aggregation of vacancies, which are point defects. The larger the COP size, the more vacancies are consumed in the silicon single crystal, resulting in fewer residual vacancies. Therefore, there is a tendency for the BMD density to decrease, particularly in the outer peripheral portion of the silicon single crystal. The decrease in the gettering ability due to the decrease in the BMD density leads to a decrease in the yield of semiconductor devices.

[0009] Therefore, an object of the present invention is to provide an epitaxial silicon wafer and a method for manufacturing the same, which can enhance the in-plane distribution uniformity of the BMD density.

Means for Solving the Problems

[0010] In order to solve the above problems, the epitaxial silicon wafer according to the present invention includes a silicon wafer in which the entire surface excluding the edge region from the outermost edge to 2 mm inside is a COP region, and an epitaxial silicon film formed on the surface of the silicon wafer, and is characterized in that the average COP size in the outer peripheral portion within 5 mm from the outermost edge of the silicon wafer is 75 nm or less.

[0011] According to the present invention, it is possible to prevent a decrease in the BMD density in the outer peripheral portion of the wafer due to an increase in the COP size. Therefore, it is possible to provide an epitaxial silicon wafer having a high gettering ability.

[0012] Preferably, the average COP size at the center of the wafer exceeds 100 nm, and more preferably, it is 120 nm or less. Thereby, the in-plane uniformity of the BMD density can be enhanced. In addition, since the pulling speed of the single crystal increases when the average COP size exceeds 100 nm, the productivity of the single crystal is also excellent.

[0013] The silicon wafer having a COP region on the entire surface excluding the edge region may be either a silicon wafer having no COP region in the edge region or a silicon wafer having a COP region in the edge region. The reason for excluding the edge region from 2 mm inside the outermost edge of the wafer is that it is difficult to accurately evaluate the presence or absence of COP near the outermost edge of the wafer. If the entire surface excluding the edge region from 2 mm inside the outermost edge of the wafer is a COP region, the effects of the present invention can be sufficiently obtained.

[0014] After performing oxygen precipitation evaluation heat treatment at 780 °C for 3 hours and 1000 °C for 16 hours, the BMD density of the bulk part (gettering layer) of the silicon wafer in the region excluding the edge region is 5×10 8 / cm 3 or more, and the in-plane variation of the BMD density is preferably 0.6 or less. In this case, the BMD density of the bulk part (gettering layer) is 7×10 9 / cm 3 or less, and the in-plane variation of the BMD density is more preferably 0.5 or less. Thereby, an epitaxial silicon wafer having a uniformly high gettering ability in the plane can be provided.

[0015] In the range from 0 mm to 139 mm in the radial direction from the wafer center, the BMD density is preferably measured at 5 mm intervals in the radial direction starting from the wafer center, and in the range from 139 mm to 148 mm in the radial direction from the wafer center, the BMD density is preferably measured at 1 mm intervals in the radial direction.

[0016] After performing the oxygen precipitation evaluation heat treatment, in the range from 130 mm to 148 mm in the radial direction from the wafer center, the BMD density is 5×10 8 / cm 3 or more, and the in-plane variation of the BMD density is preferably 0.35 or less. In this case, the BMD density is 7×10 9 / cm 3It is more preferable that the following is satisfied. By this, an epitaxial silicon wafer having a uniformly high gettering ability in the plane can be provided.

[0017] The Oi concentration (ASTM_F121, 1979) of the silicon wafer in the region excluding the edge region is 10×10 17 atoms / cm 3 or more and 14×10 17 atoms / cm 3 or less, which is preferable. By this, while preventing excessive precipitation of oxygen precipitates (BMD) in the substrate of the epitaxial wafer after the oxygen precipitation evaluation heat treatment, a sufficient BMD density can be obtained.

[0018] The Oi concentration (ASTM_F121, 1979) of the silicon wafer in the region excluding the edge region before the oxygen precipitation evaluation heat treatment is 10×10 17 atoms / cm 3 or more and 14×10 17 atoms / cm 3 or less, which is preferable. By this, while preventing excessive precipitation of oxygen precipitates (BMD) in the substrate of the epitaxial wafer after the oxygen precipitation evaluation heat treatment, a sufficient BMD density can be obtained.

[0019] The Oi concentration (ASTM_F121, 1979) in the outer peripheral portion within 5 mm from the outermost edge after the oxygen precipitation evaluation heat treatment is 8×10 17 atoms / cm 3 or more and 13×10 17 atoms / cm 3 or less, which is preferable. By this, while securing a desired BMD density in the outer peripheral portion of the wafer, a decrease in wafer strength due to a shortage of the residual oxygen concentration can be suppressed. Therefore, generation of slip dislocations in the wafer outer peripheral region can be prevented while securing a desired gettering ability.

[0020] The nitrogen concentration of the silicon wafer is 3×10 12atoms / cm 3 9×10 or more 13 atoms / cm 3 It is preferably the following. Since a nitrogen-doped silicon wafer forms thermally stable oxygen precipitation nuclei that are difficult to disappear even when subjected to high-temperature heat treatment in the epitaxial process during the silicon single crystal growth stage, it is possible to prevent a decrease in the BMD density. Examples of the method for measuring the nitrogen concentration include SIMS (Secondary Ion Mass Spectrometry) and low-temperature FT-IR method using the infrared absorption spectrum of NO donors (combinations of nitrogen atoms and oxygen atoms).

[0021] The COP size of the silicon wafer is measured by the LST method (optical scattering tomography). The output level of the laser light irradiated on the silicon wafer is 100 mW, the transmittance of the ND filter that reduces the light amount of the scattered light within the dynamic range is 20 - 50%, the scan distance of the laser light is 2000 μm, and the measurement depth of the scattered light is preferably 88.4 - 348.4 μm. Thereby, the measurement accuracy of COP in the silicon wafer can be improved.

[0022] Generally, the sizes of COPs formed in a silicon wafer are not uniform and their shapes are also various. Therefore, the COP size is defined as the diameter of a sphere having the same volume as the volume of the COPs existing in a predetermined measurement region of the silicon wafer. In other words, in the LST method (optical scattering tomography), the COP size is defined as the diameter of a sphere where the intensities of the scattered lights are equal. The average COP size is the average value of the sizes of a plurality of COPs of various sizes defined as above, and is obtained as the value obtained by dividing the sum of the "diameters" corresponding to a plurality of COPs (preferably 50 or more) by the total number of the COPs.

[0023] For the measurement of the average COP size, laser scanning measurement is performed within a range of ±1000 μm in the radial direction of the wafer centered on a certain measurement point. It is desirable that the average COP size be obtained as the average value of 50 or more COP sizes. Therefore, when the number of COPs obtained by a single laser scanning measurement is less than 50, the laser scanning measurement is performed again with the measurement position in the circumferential direction shifted within the range of ±1000 μm, and the measurement is repeated until the cumulative number of COPs becomes 50 or more. That is, the COPs are measured by expanding the measurement range in the circumferential direction.

[0024] The diameter of the silicon wafer is 300 mm, and it is preferable that the outer peripheral portion is located at a position 145 mm away from the center of the silicon wafer in the radial direction, that is, at a position 5 mm inside from the outermost edge of the silicon wafer. Thereby, it is possible to prevent a decrease in the BMD density of the outer peripheral portion of the large-diameter silicon wafer with a diameter of 300 mm.

[0025] Further, the method for manufacturing an epitaxial silicon wafer according to the present invention includes a step of growing a silicon single crystal by the CZ method, a step of processing the silicon single crystal to produce a silicon wafer with a diameter of 300 mm, and a step of forming an epitaxial silicon film on the surface of the silicon wafer. The step of growing the silicon single crystal is characterized by satisfying the following equations at a position 145 mm away from the crystal central axis in the radial direction. V / G1 ≦ 0.1035 × CR1 - 0.0350 V / G1 ≧ 0.183 2.105 ≦ CR1 ≦ 2.839 Here, V represents the pulling speed (mm / min) of the silicon single crystal, G1 represents the temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon (about 1412 °C) to 1350 °C, and CR1 represents the cooling rate (°C / min) of the silicon single crystal at 1100 °C. When the value of the cooling rate is a positive value, it means that the temperature is decreasing with time, and when it is a negative value, it means that the temperature is increasing with time.

[0026] According to the present invention, a silicon wafer having an average COP size of 75 nm or less in the outer peripheral portion within 5 mm from the outermost edge can be manufactured. Therefore, it is possible to prevent a decrease in the BMD density in the outer peripheral portion of the wafer due to an increase in the COP size, and it is possible to provide an epitaxial silicon wafer having a uniformly high gettering ability in the plane.

[0027] In the present invention, in the step of growing the silicon single crystal, it is preferable to satisfy the following equation at the position of the crystal central axis. V / G2 ≦ 0.1096 × CR2 - 0.0387 V / G2 ≧ 0.174 1.940 ≦ CR2 ≦ 2.624 Here, G2 represents the temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon (about 1412°C) to 1350°C, and CR2 represents the cooling rate (°C / min) of the silicon single crystal at 1100°C. When the value of the cooling rate is a positive value, it means that the temperature is decreasing with time, and when it is a negative value, it means that the temperature is increasing with time.

[0028] Furthermore, the method for manufacturing an epitaxial silicon wafer according to the present invention includes a step of growing a silicon single crystal by the CZ method, a step of processing the silicon single crystal to produce a silicon wafer having a diameter of 300 mm, and a step of forming an epitaxial silicon film on the surface of the silicon wafer. In the step of growing the silicon single crystal, the entire surface of the silicon wafer excluding the edge region from the outermost edge to 2 mm inside is a COP region, and the average COP size in the outer peripheral portion within 5 mm from the outermost edge of the silicon wafer is 75 nm or less. A water-cooling body for cooling the silicon single crystal pulled up from the silicon melt is used, the crystal pulling speed is in the range of 60 to 90% of the maximum pulling speed at which the crystal does not deform, the gap between the heat shielding member and the melt surface is 40 to 80 mm, and the intensity of the magnetic field applied near the solid-liquid interface is 2000 to 4000 gauss. The silicon single crystal is pulled up under the process conditions.

[0029] According to the present invention, a silicon wafer having an average COP size of 75 nm or less in the outer peripheral portion within 5 mm from the outermost edge can be manufactured. Therefore, it is possible to prevent a decrease in the BMD density in the outer peripheral portion of the wafer due to an increase in the COP size, and an epitaxial silicon wafer having a uniformly high gettering ability in the plane can be provided.

[0030] In the step of growing the silicon single crystal, it is preferable that the cooling rate CR1 (°C / min) at 1100 °C of the silicon single crystal at a position 145 mm away from the crystal central axis in the radial direction is in the range of 2.105 ≤ CR1 ≤ 2.839. Thereby, the average COP size at a position 145 mm away from the crystal central axis in the radial direction can be made 75 nm or less, and the in-plane uniformity of the BMD density can be enhanced.

[0031] The method for manufacturing an epitaxial silicon wafer according to the present invention preferably further includes a step of experimentally determining the pulling rate of the silicon single crystal at which the average COP size in the outer peripheral portion of the silicon wafer becomes 75 nm or less by examining the in-plane distribution of COPs of a plurality of silicon wafer samples collected from a plurality of silicon single crystal samples pulled at various pulling rates before the step of growing the silicon single crystal. Thereby, a silicon wafer having an average COP size of 75 nm or less in the outer peripheral portion can be manufactured.

[0032] The epitaxial silicon wafer according to the present invention includes a silicon substrate in which the entire surface excluding the edge region from the outermost edge to 2 mm inside is a COP region, and an epitaxial silicon film formed on the surface of the silicon substrate, and is characterized in that the average COP size in the outer peripheral portion within 5 mm from the outermost edge of the silicon substrate is 75 nm or less.

[0033] In the present invention, each COP in the silicon substrate reflects the light intensity when irradiated with laser light, the light intensity corresponding to the diameter of a sphere having the same volume as the COP, and the diameter of the sphere being regarded as the size of the COP, and it is preferable that the average COP size is equal to the average value of the diameters of 50 or more.

[0034] In the present invention, it is preferable that the average COP size at the center of the silicon substrate is 120 nm or less.

[0035] The diameter of the epitaxial silicon wafer according to the present invention is preferably 300 mm, and also preferably 200 mm.

[0036] The epitaxial silicon wafer according to the present invention has 12 ~8.4×10 13 atoms / cm 3 and preferably further has a nitrogen concentration of.

[0037] Further, the epitaxial silicon wafer according to the present invention includes a silicon substrate in which the entire surface excluding the edge region from the outermost edge to 2 mm inside is composed of a COP region, and an epitaxial silicon film formed on the surface of the silicon substrate. When the silicon substrate is heated, it forms bulk microdefects (BMD) in the gettering layer, and is characterized in that the in-plane variation of the BMD density in the entire silicon substrate is 0.6 or less.

[0038] It is preferable that when the epitaxial silicon wafer according to the present invention is heated at about 780 °C for 3 hours and then at about 1000 °C for 16 hours, the BMD is formed in the gettering layer.

[0039] In the present invention, the in-plane variation of the BMD density is defined as follows: In-plane variation of BMD density = (maximum BMD density - minimum BMD density) / average BMD density Here, the maximum BMD density means the maximum density of the BMD, the minimum BMD density means the minimum density of the BMD, and the average BMD density means the average density of the BMD. It is preferable that the BMD density can be measured at regular intervals in the radial direction from the center to the edge of the epitaxial silicon wafer.

[0040] In the present invention, the silicon substrate has an outer peripheral region, and the outer peripheral region is 2 to 11 mm in the radial direction from the edge of the silicon substrate. It is preferable that the fixed interval is 5 mm from the center to the outer peripheral region and 1 mm within the outer peripheral region.

[0041] The epitaxial silicon wafer according to the present invention has a nitrogen concentration of 3.0×10 12 ~8.4×10 13 atoms / cm 3 and preferably further has a nitrogen concentration of.

[0042] In the present invention, it is preferable that the in-plane variation of the BMD density is 0.5 or less.

[0043] The diameter of the epitaxial silicon wafer according to the present invention is preferably 300 mm and also preferably 200 mm.

[0044] Furthermore, the present invention is a method for manufacturing an epitaxial silicon wafer with a diameter of 300 mm, comprising preparing a silicon melt in a crucible and doping the silicon melt with nitrogen; pulling a crystal from the silicon melt at a pulling speed (V) of 60 to 90% of the maximum pulling speed while the silicon melt and the crystal form an interface; applying a cooling system to the crystal such that when an outer portion approximately 145 mm radially away from the central axis of the crystal reaches about 1100 °C, the cooling rate of the outer portion reaches 2.1 to 2.8 °C / min; applying a magnetic field of 2000 to 4000 gauss to the silicon melt; providing a gap of 40 to 80 mm between the silicon melt and a heat shielding member; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one silicon substrate, wherein the maximum pulling speed means the pulling speed at which the crystal begins to deform.

[0045] In the present invention, it is preferable that the ratio (V / G1) of the pulling speed (V) to the temperature gradient (G1) is in the range of 0.183 to 0.218 mm 2 / °C·min, where G1 means the temperature gradient from the temperature of the interface to about 1350 °C.

[0046] In the present invention, it is preferable that the ratio (V / G1) is set to form COPs throughout the crystal, and further that each silicon substrate includes COPs.

[0047] In the present invention, it is preferable that the average COP size in each silicon substrate is 75 nm or less.

[0048] In the present invention, each COP in the silicon substrate reflects the light intensity when irradiated with laser light, the light intensity corresponds to the diameter of a sphere having the same volume as the COP, and it is preferable that the average COP size is equal to the average value of the diameters of 50 or more of the spheres.

[0049] Furthermore, the present invention is a method for manufacturing an epitaxial silicon wafer having a diameter of 300 mm, comprising preparing a silicon melt in a crucible and doping the silicon melt with nitrogen; pulling a crystal from the silicon melt at a pulling speed (V) of 60 to 90% of the maximum pulling speed while the silicon melt and the crystal form an interface; applying a cooling system to the crystal such that when an outer portion approximately 145 mm radially away from the central axis of the crystal reaches approximately 1100° C., a cooling rate (CR1) of the outer portion reaches 2.105 to 2.839° C. / min; applying a magnetic field of 2000 to 4000 gauss to the silicon melt; providing a gap of 40 to 80 mm between the silicon melt and a heat shielding member and maintaining the following conditions: 0.183 ≦ V / G1 ≦ 0.1035 × CR1 - 0.0350 2.105 ≦ CR1 ≦ 2.839 where G1 means a temperature gradient from the temperature of the interface to approximately 1350° C.; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one of the plurality of silicon substrates, wherein the maximum pulling speed means a pulling speed at which the crystal begins to deform.

[0050] In the present invention, V / G1 is set to form COPs throughout the crystal, and it is preferable that at least one silicon substrate includes COPs.

[0051] In the present invention, it is preferable that an average COP size in a region approximately 145 mm radially from the center of at least one of the plurality of silicon substrates is 75 nm or less.

[0052] In the present invention, each COP in the silicon substrate reflects the light intensity when irradiated with laser light, the light intensity corresponds to the diameter of a sphere having the same volume as the COP, and the average COP size is preferably equal to the average value of the diameters of 50 or more of the spheres.

[0053] Furthermore, the present invention is a method for manufacturing an epitaxial silicon wafer having a diameter of 300 mm, comprising: preparing a silicon melt in a crucible and doping the silicon melt with nitrogen; pulling a crystal from the silicon melt at a pulling speed (V) of 60 to 90% of the maximum pulling speed while the silicon melt and the crystal form an interface; applying a cooling system to the crystal such that when the central axis of the crystal reaches about 1100°C, the cooling rate (CR2) of the central axis reaches 1.940 to 2.624°C / min; applying a magnetic field of 2000 to 4000 gauss to the silicon melt; providing a gap of 40 to 80 mm between the silicon melt and a heat shielding member and maintaining the following conditions: 0.174 ≦ V / G2 ≦ 0.1096 × CR2 - 0.0387 1.940 ≦ CR2 ≦ 2.624 where G2 means the temperature gradient from the temperature of the interface to about 1350°C; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one of the plurality of silicon substrates, wherein the maximum pulling speed means the pulling speed at which the crystal begins to deform.

[0054] In the present invention, V / G2 is set to form COPs throughout the crystal, and it is preferable that at least one silicon substrate contains COPs.

[0055] In the present invention, it is preferable that the average COP size at the center of at least one of the plurality of silicon substrates is 120 nm or less.

[0056] In the present invention, each COP in the silicon substrate reflects the light intensity when irradiated with laser light, the light intensity corresponds to the diameter of a sphere having the same volume as the COP, and the average COP size is preferably equal to the average value of the diameters of 50 or more of the above.

Advantages of the Invention

[0057] According to the present invention, it is possible to provide an epitaxial silicon wafer capable of enhancing the uniformity of the in-plane distribution of BMD density and a method for manufacturing the same.

Brief Description of the Drawings

[0058]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0059] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0060] FIG. 1 is a schematic view of an epitaxial silicon wafer according to an embodiment of the present invention, where (a) is a schematic perspective view and (b) is a schematic cross-sectional view.

[0061] As shown in FIGS. 1(a) and (b), the epitaxial silicon wafer 1 is composed of a silicon wafer 2 made of a silicon single crystal and an epitaxial silicon film 3 formed on the surface of the silicon wafer 2.

[0062] The silicon wafer 2 is a substantially circular substrate made of a silicon single crystal grown by the CZ method, and its diameter R is preferably 300 mm (radius r = 150 mm). The silicon single crystal may be an n-type semiconductor containing an n-type dopant such as phosphorus, arsenic, antimony, etc., or a p-type semiconductor containing a p-type dopant such as boron. The silicon wafer 2 contains nitrogen, and the nitrogen concentration is 3×10 12 ~9×10 13 atoms / cm 3 which is preferable. In the nitrogen-doped silicon single crystal, thermally stable oxygen precipitation nuclei that are difficult to disappear even under high-temperature heat treatment in the epitaxial process are formed at the growth stage of the silicon single crystal, so that a decrease in the BMD density can be prevented.

[0063] The entire surface of the silicon wafer 2 excluding the edge region E from the outermost edge P E to the inner 2 mm consists of the COP region. The average COP size in the outer peripheral portion P E 5 mm inside from the outermost edge P X of the silicon wafer 2 is preferably 75 nm or less. In the case of a 300 mm wafer, the measurement position of the outer peripheral portion P X of the COP is a position 145 mm radially away from the center P O of the wafer. Also, the average COP size at the center P O of the silicon wafer 2 is preferably 120 nm or less. Although details will be described later, by reducing the COP size of the outer peripheral portion P X of the wafer, a decrease in the BMD density of the outer peripheral portion P X can be prevented, and the in-plane uniformity of the BMD density can be enhanced.

[0064] COP is a void defect formed by the aggregation of pores, which are point defects, and is assumed to have an octahedral shape. However, there are also shapes in which a plurality of COPs of different sizes are combined, and the actual shape is complex. Therefore, the above COP size is determined as the diameter of a sphere of the same volume. In other words, in the LST method (light scattering tomography), the COP size is defined as the diameter of a sphere at which the intensity of scattered light is equal. Also, since COPs of various sizes are formed in a silicon single crystal, the average COP size is determined as the average size of a plurality (preferably 50 or more) of COPs within the measurement region. That is, the above average COP size is obtained as (the sum of the diameters of a plurality of COPs) / (the total number of COPs).

[0065] COP is measured from a wafer (silicon substrate), preferably using the light scattering tomography (LST) method. To calculate the average COP size, it is recommended to measure 50 or more COPs in an arbitrary space within the wafer (silicon substrate). The specific depth or position of the wafer in this measurement is not important.

[0066] When the epitaxial silicon wafer 1 is subjected to a two-step heat treatment (oxygen precipitation evaluation heat treatment) at 780 °C for 3 hours and 1000 °C for 16 hours, the BMD density in the silicon wafer 2 is 5×10 8 ~7×10 9 / cm 3 is preferably, and the in-plane variation of the BMD density is preferably 0.6 or less. Here, the in-plane variation D V of the BMD density is obtained by measuring the BMD density of the silicon wafer 2 at a predetermined pitch in the radial direction from the center P O to the outermost edge P E of the wafer to obtain a plurality of values, and taking the maximum value among these values as D max , the minimum value as D min、 and the average value as D ave . When D V =(D max -D min ) / D aveIt is defined as follows. For example, in the range of 0 to 139 mm in the radial direction from the wafer center, the BMD density is measured at 5-mm intervals in the radial direction starting from the wafer center. In the range of 139 to 148 mm in the radial direction from the wafer center (the region indicated as OR in FIG. 1), it is preferable to measure the BMD density at 1-mm intervals in the radial direction. By suppressing the average COP size of the outer peripheral portion of the silicon wafer 2 to 75 nm or less, the BMD density in the silicon wafer 2 after device heat treatment or oxygen precipitation evaluation heat treatment simulating the same can be made 5×10 8 ~7×10 9 / cm 3 , and the in-plane variation of the BMD density can be reduced.

[0067] FIG. 12 is a cross-sectional view of the epitaxial wafer according to the present invention after performing oxygen precipitation evaluation heat treatment. The epitaxial wafer 120 includes an epitaxial layer 121 and a silicon substrate 122. The epitaxial wafer 120 forms denuded zones (DZs) 123, 125 and a gettering layer (bulk region) 124 by heating. The gettering layer 124 formed between the first denuded zone 123 and the second denuded zone 125 when heated has BMD. The measurement of the BMD density is performed at desired intervals in the gettering layer 124 as described above. Preferably, the BMD measurement is performed using the LST method. As long as the BMD measurement is performed in the gettering layer 124, a specific depth or the position of the silicon substrate 122 is not important.

[0068] As described above, the measurement of the BMD density can be performed at 5-mm intervals over most of the wafer. However, in the region from about 139 mm to about 148 mm in the radial direction from the wafer center, it is preferable to measure the BMD density at a narrower interval such as 1 mm.

[0069] BMD (bulk microdefects) grow from BMD nuclei by heat treatment. Further, the formation of BMD proceeds by consuming residual vacancies. Therefore, when the number of residual vacancies is insufficient in the formation of BMD, the BMD density decreases.

[0070] As a result of intensive studies, the present inventors have found that by controlling the size of COPs on the outer peripheral side of a silicon single crystal, the in-plane distribution of BMD density can be made uniform. Regardless of the presence or absence of nitrogen doping, the BMD density depends on the density of residual vacancies after COP formation, but the density of residual vacancies tends to decrease toward the outer peripheral side of the silicon single crystal due to the outward diffusion of vacancies. Therefore, the BMD density tends to decrease toward the outer peripheral side of the silicon single crystal. However, the density of residual vacancies on the outer peripheral side of the silicon single crystal can be adjusted by controlling the size of the COPs formed on the outer peripheral side.

[0071] Also, when nitrogen is doped, the BMD can be roughly classified into two types. One is the BMD caused by precipitates (hereinafter referred to as "NV precipitates") in which nitrogen and vacancies aggregate before COP formation, and the other is the BMD caused by residual vacancies after COP formation.

[0072] The BMD caused by NV precipitates depends on the in-plane distribution of vacancies before COP formation, and since the density of vacancies decreases toward the outer peripheral side of the silicon single crystal, the BMD density caused by NV precipitates decreases toward the outer peripheral side of the silicon single crystal.

[0073] The BMD caused by NV precipitates is determined by the nitrogen concentration and the temperature gradient during crystal pulling, but the BMD caused by residual vacancies after COP formation can be adjusted by controlling the COP size. That is, by controlling the size of the COPs on the outer peripheral side of the silicon single crystal, the BMD density caused by residual vacancies after COP formation on the outer peripheral side of the silicon single crystal can be adjusted, and as a result, the in-plane distribution of the final BMD density obtained by adding the BMD density caused by NV precipitates can be made uniform.

[0074] FIG. 2 is a flowchart schematically showing a method for manufacturing an epitaxial silicon wafer 1.

[0075] As shown in Fig. 2, the method for manufacturing the epitaxial silicon wafer 1 includes a step S11 of growing a silicon single crystal by the CZ method, a step S12 of processing the silicon single crystal to produce a silicon wafer 2, and a step S13 of forming an epitaxial silicon film 3 on the surface of the silicon wafer 2.

[0076] In the step S11 of growing a silicon single crystal by the CZ method, a seed crystal is immersed in the liquid surface of the silicon melt accommodated in a quartz crucible, and while rotating the seed crystal and the quartz crucible respectively, the seed crystal is gradually pulled up to grow a large single crystal at the lower end of the seed crystal. Specifically, a liquid contact step of bringing the seed crystal into contact with the silicon melt, a necking step of narrowing the crystal diameter by the dash neck method, a shoulder part growth step of gradually thickening the crystal diameter until it reaches a desired diameter, a straight body part growth step of continuing the growth of the single crystal while maintaining the crystal diameter at the desired diameter, and a tail part growth step of gradually narrowing the crystal diameter and separating it from the silicon melt are sequentially performed.

[0077] When growing a silicon single crystal by the CZ method, the types and distributions of defects contained in the single crystal depend on the ratio V / G of the pulling speed V of the single crystal and the temperature gradient G in the crystal growth direction near the solid-liquid interface.

[0078] Fig. 3 is a diagram showing the general relationship between V / G and the types and distributions of crystal defects.

[0079] As shown in Fig. 3, when V / G is large, pores become excessive and COP, which is an aggregate of pores, occurs. On the other hand, when V / G is small, interstitial silicon atoms become excessive and a dislocation cluster, which is an aggregate of interstitial silicon, occurs. COP and dislocation clusters are Grown-in defects that occur during crystal growth. Further, between the region where COP occurs and the region where dislocation clusters occur, there are three regions in order from the larger V / G side: the OSF region, the Pv region, and the Pi region. The OSF region is a region where OSF (Oxidation Induced Stacking Fault) occurs when thermally oxidized at a high temperature of 1000 to 1200°C. The Pv region and the Pi region are regions called so-called defect-free regions that do not contain Grown-in defects. The Pv region contains oxygen precipitation nuclei in the As-grown state and is a region where oxygen precipitates are likely to occur when subjected to two-step heat treatment at low and high temperatures (for example, 800°C and 1000°C). The Pi region is a region where oxygen precipitates are less likely to occur even when subjected to two-step heat treatment.

[0080] Since the range of V / G in which a silicon single crystal without Grown-in defects can be grown is very narrow, strict control of V / G is required to grow such a silicon single crystal, and V / G must be controlled to be within an appropriate range in the radial direction and the length direction of the single crystal. In the radial direction of the single crystal, since the pulling speed V is constant at any position, the high-temperature region (hot zone) in the CZ furnace must be designed so that the temperature gradient G falls within a predetermined range. In order to keep V / G within an appropriate range, the pulling speed V must be strictly controlled to be within a predetermined range.

[0081] Thus, the control of pulling up a silicon single crystal without grown-in defects is very delicate. However, in the case of an epitaxial silicon wafer, since the surface of the silicon wafer 2 is covered with the epitaxial silicon film 3 and the crystal integrity of the wafer surface is high, the silicon wafer 2 does not necessarily have to be a defect-free crystal and may contain grown-in defects. Therefore, conventionally, giving priority to the production efficiency of silicon single crystals, the pulling-up speed has been as fast as possible. Specifically, the silicon single crystal has been pulled up at the maximum pulling-up speed at which the crystal does not deform. The maximum pulling-up speed refers to the maximum pulling-up speed achievable when pulling up the crystal while keeping the shape of the straight body part of the crystal straight in the longitudinal direction. Specifically, it means the maximum pulling-up speed within the range where the eccentricity distance of the center position of the horizontal cross-section of the straight body part from the line connecting the center points of the horizontal cross-sections at both ends of the straight body part does not exceed 4 mm.

[0082] In contrast, in the present embodiment, the silicon single crystal is pulled up at a pulling-up speed slower than before, specifically, at a predetermined pulling-up speed within the range of 60% to 90% of the maximum pulling-up speed at which the crystal does not deform, so that the average COP size of the outer peripheral portion P of the silicon wafer 2 becomes 75 nm or less. Such a pulling-up speed can be grasped by evaluating the in-plane distribution of COPs of a plurality of silicon wafer samples collected from a plurality of silicon single crystal samples pulled up at various pulling-up speeds. That is, the pulling-up speed at which the average COP size of the outer peripheral portion P of the silicon wafer 2 becomes 75 nm or less is experimentally determined before the process of growing the silicon single crystal. X X

[0083] ​​For example, by repeating the silicon single crystal pulling process and the evaluation of the in-plane distribution of COPs in the silicon single crystal several times to obtain in advance the correspondence between the crystal pulling speed and the average COP size at the outer periphery of the wafer, an appropriate pulling speed at which the average COP size at the outer periphery of the wafer becomes 75 nm or less can be specified. For example, when the COPs at the outer periphery of the wafer sample when pulling a silicon single crystal at a certain pulling speed are larger than 75 nm, based on the previously obtained correspondence between the crystal pulling speed and the average COP size at the outer periphery of the wafer, the pulling speed is further lowered or further increased so that the average COP size becomes smaller, and the pulling of the silicon single crystal is performed again. By repeating the silicon single crystal pulling process and the evaluation of the in-plane distribution of COPs in the silicon single crystal several times in this way, an appropriate pulling speed at which the average COP size at the outer periphery of the wafer becomes 75 nm or less can be specified.

[0084] FIG. 4 is a cross-sectional view schematically showing the configuration of a single crystal pulling apparatus used for manufacturing a silicon single crystal by the CZ method.

[0085] As shown in FIG. 4, the single crystal pulling apparatus 10 includes a water-cooled chamber 11 (CZ furnace), a quartz crucible 12 that holds the silicon melt 4 in the chamber 11, a carbon susceptor 13 that holds the quartz crucible 12, a rotating shaft 14 that supports the carbon susceptor 13, a shaft drive mechanism 15 that drives the rotating shaft 14 to rotate and move up and down, a heater 16 disposed around the carbon susceptor 13, a heat shielding member 17 disposed above the quartz crucible 12, a cylindrical cooling system (water-cooled body) 18 disposed inside the heat shielding member 17, a single crystal pulling wire 19 disposed above the quartz crucible 12 and coaxial with the rotating shaft 14, and a wire winding mechanism 20 disposed above the chamber 11. The single crystal pulling apparatus 10 also includes a magnetic field generating device 21 disposed outside the chamber 11.

[0086] Chamber 11 is composed of a main chamber 11a and an elongated cylindrical pull chamber 11b connected to the upper opening of the main chamber 11a. A quartz crucible 12, a carbon susceptor 13, a heater 16, a heat shielding member 17, and a cooling system (water-cooled body) 18 are provided in the main chamber 11a. At the upper part of the pull chamber 11b, a gas inlet 11c for introducing an inert gas (purge gas) such as argon gas or a dopant gas into the main chamber 11a is provided, and at the lower part of the main chamber 11a, a gas outlet 11d for discharging the atmospheric gas in the main chamber 11a is provided.

[0087] The quartz crucible 12 is a container made of quartz glass having a cylindrical side wall portion and a curved bottom. The carbon susceptor 13 is used to maintain the shape of the quartz crucible 12 softened at high temperature, and is held so as to surround the entire circumference of the bottom surface and the outer peripheral surface of the quartz crucible 12. The quartz crucible 12 and the carbon susceptor 13 constitute a double-structured crucible for supporting the silicon melt in the chamber 11.

[0088] The carbon susceptor 13 is fixed to the upper end portion of the rotating shaft 14, and the lower end portion of the rotating shaft 14 penetrates the bottom of the chamber 11 and is connected to a shaft drive mechanism 15 provided outside the chamber 11.

[0089] The heater 16 is used to melt the polycrystalline silicon raw material filled in the quartz crucible 12 to generate a silicon melt 4 and to maintain the molten state of the silicon melt 4. The heater 16 is a resistance heating type carbon heater and is provided so as to surround the quartz crucible 12 in the carbon susceptor 13.

[0090] The heat shielding member 17 is provided to suppress temperature fluctuations of the silicon melt 4 and form an appropriate hot zone near the crystal growth interface, and to prevent heating of the silicon single crystal 5 by radiant heat from the heater 16 and the quartz crucible 12. The heat shielding member 17 is a substantially cylindrical member made of graphite, and is provided to cover the region above the silicon melt 4 excluding the pulling path of the silicon single crystal 5.

[0091] The diameter of the opening at the lower end of the heat shielding member 17 is larger than the diameter of the silicon single crystal 5, thereby ensuring the pulling path of the silicon single crystal 5. Further, the outer diameter of the lower end portion of the heat shielding member 17 is smaller than the inner diameter of the quartz crucible 12, and since the lower end portion of the heat shielding member 17 is located inside the quartz crucible 12, even if the upper end of the rim of the quartz crucible 12 is raised above the lower end of the heat shielding member 17, the heat shielding member 17 does not interfere with the quartz crucible 12.

[0092] The gap H, which is the distance between the heat shielding member 17 and the silicon melt 4, is preferably 40 to 80 mm. By setting the gap H within this range, it becomes easy to make the types of crystal defects formed in the radial direction of the single crystal the same defect type (for example, COP). Therefore, the yield of the epitaxial silicon wafer in which COP defects occur over the entire surface of the wafer can be increased.

[0093] The cooling system (water-cooled body) 18 is a cylindrical member surrounding the pulling path of the silicon single crystal 5. By cooling the silicon single crystal 5 pulled from the silicon melt 4 using the cooling system (water-cooled body) 18, the temperature gradient G from the melting point of silicon to 1350 °C can be increased, and the COP size in the silicon single crystal 5 can be reduced. When appropriate temperature control is not performed, in wafers obtained from conventional silicon single crystals, a decrease in the BMD density at the outer peripheral portion of the wafer and a lack of effective gettering ability may be observed. The cooling system 18 controls the cooling rate at 1100 °C of the single crystal, and contributes to realizing a smaller COP size particularly at the outer peripheral portion of the single crystal and at the outer peripheral portion PX of the resulting wafer.

[0094] The wire winding mechanism 20 is disposed above the pull chamber 11b. The wire 19 extends downward from the wire winding mechanism 20 through the inside of the pull chamber 11b, and the tip of the wire 19 reaches the internal space of the main chamber 11a. This figure shows a state in which the silicon single crystal 5 during growth is suspended from the wire 19. When pulling up the silicon single crystal 5, the quartz crucible 12 and the silicon single crystal 5 are rotated respectively while gradually pulling up the wire 19 to grow the silicon single crystal 5.

[0095] As the silicon single crystal 5 grows, the amount of the silicon melt in the quartz crucible 12 decreases. By raising the quartz crucible 12 so that the height position of the melt surface becomes constant, the gap H between the heat shielding member 17 and the silicon melt surface can be made constant, and the stability of the temperature gradient G in the crystal growth direction from the melting point of silicon to 1350 ° C can be improved.

[0096] The magnetic field generating device 21 applies a transverse magnetic field (horizontal magnetic field) to the silicon melt 4. The intensity of the magnetic field applied near the solid-liquid interface is preferably 1500 to 6000 gauss. By applying a magnetic field near the solid-liquid interface, the melt convection in the direction perpendicular to the magnetic field lines can be suppressed. Here, as the vicinity of the solid-liquid interface, for example, a position 30 mm below the melt side from the point where the solid-liquid interface and the crystal central axis intersect can be mentioned.

[0097] The intensity of the magnetic field applied near the solid-liquid interface is particularly preferably 2000 to 4000 gauss. By applying a magnetic field of 2000 to 4000 gauss to the silicon melt 4 in the quartz crucible 12, the convection of the silicon melt 4 is stabilized, and the stability of the crystal pulling speed is further increased, so that the control of the size of the COP formed in the single crystal becomes easier.

[0098] In the production of a silicon single crystal 5, first, a quartz crucible 12 is placed inside a carbon susceptor 13, and a polycrystalline silicon raw material is further introduced into the quartz glass crucible. Next, the raw material inside the quartz crucible 12 is heated and melted by a heater 16 to generate a silicon melt 4. Further, a seed crystal attached to the lower end of a wire 19 is lowered and made to contact the silicon melt 4. Thereafter, while maintaining the contact state with the silicon melt 4, the seed crystal is gradually pulled up to grow the silicon single crystal 5. In the process of growing the silicon single crystal, after gradually increasing the diameter to form a shoulder portion, the diameter is maintained constant to form a straight body portion. After forming a straight body portion of a desired length, the diameter is gradually decreased to separate it from the silicon melt 4. Thus, a silicon single crystal ingot is completed.

[0099] The reason for controlling the crystal cooling rate at 1100 °C is as follows. When the silicon melt solidifies and crystallizes at the solid-liquid interface, vacancies are incorporated into the single crystal. Thereafter, in the process of pulling up and cooling the single crystal, the vacancies in the single crystal become supersaturated, and COP defects, which are aggregates of vacancies, are formed. The temperature at which this COP is formed is around 1100 °C. Therefore, by increasing the cooling rate at 1100 °C, the COP formation temperature, the COP size can be efficiently reduced.

[0100] As described above, in the method for producing a silicon single crystal according to this embodiment, since the silicon single crystal is pulled up at a predetermined pulling rate such that the average COP size of the outer peripheral portion is 75 nm or less, a silicon single crystal having a high BMD density in the crystal outer peripheral portion and a high uniformity in the in-plane distribution of the BMD density can be produced.

[0101] Next, the silicon single crystal 5 is processed to produce a silicon wafer 2 (polished wafer) (S12 in Fig. 2). The silicon wafer 2 is produced by cutting a silicon single crystal ingot into a certain block size, performing rounding processing (outer peripheral grinding) to align the crystal diameters, and then undergoing processes such as a slicing process, a beveling process, a lapping process, an etching process, a polishing process, and a cleaning process. The entire surface of the silicon wafer 2 processed in this way consists of a COP region, and the average COP size of the outer peripheral portion is 75 nm or less.

[0102] The COP region shall mean the region where COP is detected by the observation evaluation described below. First, the silicon wafer is subjected to SC-1 cleaning (that is, cleaning with a mixed solution of ammonia water, hydrogen peroxide water, and ultrapure water mixed at 1:1:15), and the surface of the silicon wafer after cleaning is observed and evaluated using a surface defect inspection device (for example, Surfscan SP-2 manufactured by KLA-Tencor) to identify bright point defects (LPD: Light Point Defect) presumed to be surface pits. At that time, the observation mode shall be the Oblique mode (oblique incidence mode), and the presumption of surface pits shall be performed based on the detection size ratio of the Wide Narrow channel. For the LPD thus identified, it is evaluated whether it is a COP or not using an atomic force microscope (AFM). By this observation evaluation, the region where COP is observed is defined as the COP region. In particular, if LPD is observed on the entire surface of the wafer excluding the edge region from the outermost edge to the inner 2 mm, and in the observation using AFM, the LPDs at two locations 5 mm inside from the center of the wafer and the outermost edge of the wafer are COP defects, it can be said that the entire surface of the wafer excluding the edge region from the outermost edge to the inner 2 mm is the COP region.

[0103] Next, an epitaxial silicon film 3 is formed on the surface of the silicon wafer 2 (S13 in FIG. 2). The thickness of the epitaxial silicon film 3 is preferably 0.2 to 200 μm. The method for forming the epitaxial silicon film 3 is not particularly limited, but for large-diameter silicon wafers with a diameter of 300 mm or more, a single-wafer CVD (Chemical Vapor Deposition) apparatus is preferably used. The silicon wafer 2 is set in the chamber of the CVD apparatus, and source gases such as trichlorosilane (SiHCl3) are introduced into the chamber together with carrier gases such as H2 gas and dopant gases. Silicon generated by thermal decomposition or reduction of the source gas is grown on the silicon wafer 2 heated to a high temperature of 1000 to 1200 °C at a reaction rate of 0.5 to 6.0 μm / min. Thereafter, the silicon wafer is cleaned to complete the epitaxial silicon wafer 1.

[0104] The BMD density distribution of the epitaxial silicon wafer 1 manufactured in this way can be confirmed by performing an evaluation heat treatment (oxygen precipitation evaluation heat treatment) simulating the device process to grow oxygen precipitation nuclei. The BMD in the silicon wafer 2 can be observed by cleaving the wafer in the thickness direction after the oxygen precipitation evaluation heat treatment and using the LST method (light scattering tomography). In this embodiment, the BMD density in the silicon wafer 2 after the oxygen precipitation evaluation heat treatment is 5×10 8 / cm 3 or more and 7×10 9 / cm 3 or less, and the in-plane variation of the BMD density is 0.6 or less.

[0105] As described above, the epitaxial silicon wafer 1 according to this embodiment includes a silicon wafer 2 in which the entire surface excluding the edge region E from the outermost edge P E to the inner 2 mm consists of a COP region, and an epitaxial silicon film 3 formed on the surface of the silicon wafer 2. The outermost edge P E of the silicon wafer 2 to the outer peripheral portion P XSince the average COP size in [description] is 75 nm or less, it is possible to prevent a decrease in the BMD density in the outer peripheral portion of the wafer after device heat treatment, thereby enhancing the uniformity of the in-plane distribution of the BMD density.

[0106] As described above, the preferred embodiments of the present invention have been explained. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and it goes without saying that those are also included in the scope of the present invention.

[0107] For example, in the above embodiment, an epitaxial silicon wafer with a diameter of 300 mm was taken as an example. However, the present invention is not limited to wafers having such a diameter, and wafers smaller than 300 mm, such as 200 mm wafers, may be used, and wafers larger than 300 mm, such as 450 mm wafers, may also be used.

Example

[0108] Samples #1 to #4 of silicon single crystals were grown using a Czochralski apparatus. At that time, a silicon melt doped with nitrogen so that the nitrogen concentration in the single crystal was 3×10 12 ~9×10 13 atoms / cm 3 was generated in a quartz crucible, and a silicon single crystal was pulled up from this silicon melt.

[0109] In the growth of samples #1 to #3 (Examples) of silicon single crystals, a Czochralski apparatus equipped with a water-cooled body (see FIG. 4) was used to reduce the COP size in the single crystal. On the other hand, in the growth of sample #4 (Comparative Example) of silicon single crystal, a Czochralski apparatus without such a water-cooled body was used. The silicon single crystal growth process was performed while applying a transverse magnetic field, and the central magnetic field strength at this time was 2000 to 4000 gauss. The crystal rotation speed was 8.5 to 10 rpm, and the crucible rotation speed was 0.2 to 0.4 rpm.

[0110] During the pulling speed V in the straight body growth process of silicon single crystal samples #1 to #3, it was the speed at which COP was formed on the entire surface of the wafer, lower than the maximum pulling speed at which the crystal did not deform, and within the range of 60% to 90% of the maximum pulling speed at which the crystal did not deform. In particular, the pulling speed V of sample #1 was set to be the highest, and then the pulling speeds of sample #2 and sample #3 were set lower in that order. On the other hand, during the pulling speed in the straight body growth process of silicon single crystal sample #4, it was the speed at which COP was formed on the entire surface of the wafer, and it was set as the maximum pulling speed at which the crystal did not deform. In silicon single crystal samples #1 to #3, to ensure the formation of COP on the entire wafer surface and particularly to form smaller COPs at the outer peripheral part of the wafer, the single crystal was pulled up within the range of 60% to 90% of the maximum pulling speed at which the crystal did not deform. At a speed exceeding the maximum pulling speed, shape deformation occurred in the crystal. On the other hand, in sample #4 of the comparative example, the single crystal was pulled up at the maximum pulling speed at which the crystal did not deform.

[0111] Samples #1 to #4 of the silicon single crystal thus grown were processed to produce samples A1 to A6 and B1 to B3 of 300 mm diameter silicon wafers. Here, samples A1 to A4 of the silicon wafers were taken from silicon single crystal sample #1 and were wafers with different sampling positions taken from the same single crystal ingot. Also, sample A5 of the silicon wafer was a wafer taken from silicon single crystal sample #2, and sample A6 of the silicon wafer was a wafer taken from silicon single crystal sample #3. Samples B1 to B3 of the silicon wafers were taken from silicon single crystal sample #4 and were wafers with different sampling positions taken from the same single crystal ingot.

[0112] Next, an epitaxial silicon film with a thickness of about 2 μm was formed on the surfaces of samples A1 to A6 and B1 to B3 of the silicon wafers by the CVD method. Thus, epitaxial silicon wafers (epitaxial wafers) according to Examples 1 to 6 and Comparative Examples 1 to 3 were completed.

[0113] Next, the in-plane distributions of the COP, BMD density, and oxygen concentration of the epitaxial wafers according to Examples 1 to 6 and Comparative Examples 1 to 3 were evaluated, respectively.

[0114] The evaluation of the in-plane distribution of the COP was performed by the LST method using an infrared scattering tomograph (MO-441 manufactured by Mitsui Mining & Smelting Co., Ltd.). In the LST method, the wafer is cleaved, an infrared laser beam is irradiated onto the surface of the wafer, and the light reflected and scattered by crystal defects in the wafer and emitted from the cleavage plane is received by a CCD sensor to measure the size and density of the defects.

[0115] The CCD sensor photographs the cleavage plane through an ND filter. The CCD sensor outputs the intensity of the light scattered by minute defects in the wafer as the magnitude of an electrical signal in 65536 gradations (16 bits), and the maximum value of the electrical signal is taken as the scattering intensity. The scattering intensity is a relative value proportional to the sixth power of the COP size. The COP size is determined by referring to a data table (calibration curve) showing the relationship between the scattering intensity and the COP size obtained in advance. As described above, the average COP size is determined as the average value of the diameters of a plurality of COPs existing within the measurement region.

[0116] The measurement conditions for the COP by the infrared scattering tomograph were as follows: the output level of the laser beam was 100 mW, the transmittance of the ND filter for reducing the light amount of the scattered light was 20 to 50%, the scan distance of the laser beam along the cleavage plane was 2000 μm, and the measurement depth of the scattered light was in the range of 88.4 to 348.4 μm in the depth direction from the surface of the epitaxial film. In the measurement of the COP, the laser beam was irradiated from the surface of the epitaxial wafer having the epitaxial film, and five points at 0 mm, 37.5 mm (1 / 4×r), 75 mm (1 / 2×r), 112.5 mm (3 / 4×r), and 145 mm (r - 5 mm) in the radial direction from the center of the epitaxial wafer were measured. Then, the average COP size at each position was determined.

[0117] The in-plane distribution of BMD density was evaluated by the LST method using an infrared scattering tomography apparatus (LST-310A manufactured by Semilab) after sequentially performing an oxygen precipitation evaluation heat treatment (780 °C × 3 h + 1000 °C × 16 h, O2 atmosphere) and an oxide film removal treatment on the epitaxial wafer. The measurement conditions for BMD density were such that the output level of the laser light was 51 μW, the beam diameter of the laser light was 8 μm, the scan distance of the laser light along the cleavage plane was 375 μm, the measurement depth of the scattered light was 6.5 to 280.5 μm in the depth direction from the surface of the epitaxial film, and the depth was in the range of 8 μm. The measurement of BMD density was performed by measuring the BMD density in the gettering layer 124 formed in the silicon substrate 122 (see Fig. 12). Also, in the measurement of BMD density, starting from the wafer center, a range from 0 to 139 mm in the radial direction from the wafer center was measured at a 5 mm pitch, and a range from 139 to 148 mm in the radial direction from the wafer center was measured at a 1 mm pitch.

[0118] In the measurement of BMD density, laser scan measurement is performed within a range of ±188 μm in the radial direction of the wafer centered on a certain measurement point. BMD density is calculated by dividing the number of BMDs contained in a rectangular parallelepiped formed by the scan distance corresponding to the width of the imaging screen of the cleavage plane, the depth corresponding to the spot diameter of the laser light, and an arbitrary depth direction distance by the volume of the rectangular parallelepiped, and corresponds to the number of BMDs per unit volume (cm 3 ). In the measurement of BMD density, the measurement accuracy of BMD density can be improved by expanding the scan area and increasing the number of BMDs.

[0119] The in-plane distribution of oxygen concentration was evaluated for both the wafer before the oxygen precipitation evaluation heat treatment and the wafer after the oxygen precipitation evaluation heat treatment. The in-plane distribution of oxygen concentration was evaluated using an FT-IR apparatus (QS1200LTS), and in the range up to 145 mm in the radial direction from the wafer center, it was measured at a 5 mm pitch starting from the wafer center.

[0120] FIG. 5 is a graph showing the in-plane distribution of the average COP size of an epitaxial wafer. FIG. 5(a) shows the in-plane distribution of the average COP size of the epitaxial wafers according to Comparative Examples 1 to 3, and FIG. 5(b) shows the in-plane distribution of the average COP size of the epitaxial wafers according to Examples 1 to 4, respectively.

[0121] As shown in FIGS. 5(a) and 5(b), COPs were detected throughout the entire area from the center to the outer periphery of the epitaxial wafers according to Comparative Examples 1 to 3 and Examples 1 to 4. The average COP size was the largest at the wafer center and tended to decrease as the distance from the center increased. As shown in FIG. 5(a), the average COP size of the epitaxial wafers according to Comparative Examples 1 to 3 was 141.8 to 145.0 nm at the wafer center and 79.6 to 85.7 nm at the position with a radius r = 145 mm (outer periphery). On the other hand, as shown in FIG. 5(b), the average COP size of the epitaxial wafers according to Examples 1 to 4 was 103.8 to 119.8 nm at the wafer center and 65.5 to 71.9 nm at the position with a radius r = 145 mm (outer periphery). Thus, it was found that the average COP size at the outer periphery of the epitaxial wafers according to Examples 1 to 4 was smaller than the average COP size at the same position of the epitaxial wafers according to Comparative Examples 1 to 3, and particularly was 75 nm or less.

[0122] Table 1 shows the average COP sizes at various positions of the epitaxial wafers according to Comparative Examples 1 to 3. Table 2 shows the average COP sizes at various positions of the epitaxial wafers according to Examples 1 to 4.

[0123]

Table 1

[0124]

Table 2

[0125] Referring to FIG. 1 again, PO is defined as the center point of the wafer, PE is the edge of the wafer, and PX is defined as the position 5 mm inside PE. PMi indicates the position where the distance from PO is 0.25×r (r is the wafer radius), PMm indicates the position of 0.5×r, and PMo indicates the position of 0.75×r, respectively.

[0126] As shown in Tables 1 and 2, the average COP size in the outer peripheral portion PX of the epitaxial wafers according to Comparative Examples 1 to 3 is 79.6 to 85.7 nm, while the average COP size in the outer peripheral portion PX of the epitaxial wafers according to Examples 1 to 4 is 65.5 to 71.9 nm. It can be seen that the average COP size of Examples 1 to 4 is significantly smaller than that of Comparative Examples 1 to 3. Also, at the center PO of the wafer, the average COP size of the epitaxial wafers according to Comparative Examples 1 to 3 is 141.8 to 145.0 nm, while the average COP size of the epitaxial wafers according to Examples 1 to 4 is 103.8 to 119.8 nm. The average COP size of Examples 1 to 4 shows a smaller value than that of Comparative Examples 1 to 3. Overall, it is confirmed that the epitaxial wafers according to Examples 1 to 4 contain smaller COPs throughout the wafer and the in-plane variation in the density of BMD is improved.

[0127] FIG. 6 is a graph showing the in-plane distribution of the BMD density of the epitaxial wafer. FIG. 6(a) shows the in-plane distribution of the BMD density of the epitaxial wafers according to Comparative Examples 1 to 3, and FIG. 6(b) shows the in-plane distribution of the BMD density of the epitaxial wafers according to Examples 1 to 4, respectively.

[0128] As shown in FIG. 6(a), in the epitaxial wafers according to Comparative Examples 1 to 3, a decrease in the BMD density was observed in the outer peripheral region from 130 to 148 mm from the center of the wafer. On the other hand, as shown in FIG. 6(b), in the epitaxial wafers according to Examples 1 to 4, no decrease in the BMD density was observed in the outer peripheral region from 130 to 148 mm from the center of the wafer, and the in-plane uniformity of the BMD density was high.

[0129] FIG. 7 is a graph showing the relationship between the average COP size and the in-plane variation of the BMD density at a position 5 mm inside from the outermost edge of the wafer (outer peripheral portion). The wafers according to Comparative Examples 1 to 3 are indicated by white markers, and the wafers according to Examples 1 to 6 are indicated by black markers. Also, Table 3 shows the correspondence between the average COP size and the in-plane variation of the BMD density. As described above, the in-plane variation D V of the BMD density V is obtained as D max =(D min - D ave ). This index of the in-plane uniformity of the BMD density indicates that the smaller the value, the better the in-plane uniformity.

[0130]

Table 3

[0131] As shown in FIG. 7 and Table 3, the average COP size at the outer peripheral portion of the epitaxial wafers according to Comparative Examples 1 to 3 was 85.7 nm for Comparative Example 1, 84.8 nm for Comparative Example 2, and 79.6 nm for Comparative Example 3, all of which were larger than 75 nm. On the other hand, the average COP size at the outer peripheral portion of the epitaxial wafers according to Examples 1 to 6 was 71.9 nm for Example 1, 70.5 nm for Example 2, 65.5 nm for Example 3, 68.0 nm for Example 4, 65.3 nm for Example 5, and 43.9 nm for Example 6, all of which were 75 nm or less. Thus, it can be seen that the wafers of Comparative Examples 1 to 3 with a large average COP size have a large in-plane variation of the BMD density, exceeding the preferable value of 0.6. On the other hand, in the wafers according to Examples 1 to 6, the average COP size is small, less than 75 nm, and the in-plane variation of the BMD density is significantly improved, being less than 0.6.

[0132] Also, within the range of 0 to 148 mm from the wafer center (the entire wafer surface), the in-plane variation of the BMD density of the epitaxial wafers according to Comparative Examples 1 to 3 was 0.796 for Comparative Example 1, 0.622 for Comparative Example 2, and 0.822 for Comparative Example 3, all of which were greater than 0.6. On the other hand, the in-plane variation of the BMD density of the epitaxial wafers according to Examples 1 to 6 was 0.375 for Example 1, 0.499 for Example 2, 0.444 for Example 3, 0.478 for Example 4, 0.407 for Example 5, and 0.449 for Example 6, all of which were less than 0.5. Thus, it can be seen that the epitaxial wafers according to Examples 1 to 6 have improved in-plane uniformity of the BMD density compared to Comparative Examples 1 to 3. FIG. 7 shows that the in-plane variation of the BMD density in the bulk region (gettering layer 124) of the wafers according to Comparative Examples 1 to 3 is in the range of 0.622 to 0.822. On the other hand, in the wafers according to Examples 1 to 6, the in-plane variation of the BMD density in the bulk region (gettering layer 124) is significantly lower, falling within the range of 0.375 to 0.499. This result indicates that the wafer of the present invention has an in-plane variation of the BMD density in the bulk region (gettering layer 124) of less than 0.5.

[0133] Also, within the range of 130 to 148 mm from the wafer center (outer peripheral region), the in-plane variation of the BMD density of the epitaxial wafers according to Comparative Examples 1 to 3 was 0.385 for Comparative Example 1, 0.444 for Comparative Example 2, and 0.780 for Comparative Example 3, all of which were greater than 0.35. On the other hand, the in-plane variation of the BMD density of the epitaxial wafers according to Examples 1 to 6 was 0.077 for Example 1, 0.160 for Example 2, 0.197 for Example 3, 0.348 for Example 4, 0.225 for Example 5, and 0.173 for Example 6, all of which were 0.35 or less. Thus, it can be seen that the epitaxial wafers according to Examples 1 to 6 have improved in-plane uniformity of the BMD density in the outer peripheral region compared to Comparative Examples 1 to 3.

[0134] FIG. 8 is a graph showing the in-plane distribution of the oxygen concentration of the epitaxial wafer before the oxygen precipitation evaluation heat treatment. FIG. 8(a) shows the measurement results of the oxygen concentration of the epitaxial wafers according to Comparative Examples 1 to 3, and FIG. 8(b) shows the measurement results of the oxygen concentration of the epitaxial wafers according to Examples 1 to 4, respectively.

[0135] As shown in FIG. 8(a), the in-plane distribution of the oxygen concentration of the epitaxial wafers according to Comparative Examples 1 to 3 is generally uniform, and it can be seen that it falls within the range of 10.7×10 17 ~11.7×10 17 atoms / cm 3 . Also, as shown in FIG. 8(b), the in-plane distribution of the oxygen concentration of the epitaxial wafers according to Examples 1 to 4 is also generally uniform, and it can be seen that it falls within the range of 11.0×10 17 ~12.0×10 17 atoms / cm 3 .

[0136] FIG. 9 is a graph showing the in-plane distribution of the residual Oi concentration of the epitaxial wafer after the oxygen precipitation evaluation heat treatment to make the BMD apparent. FIG. 9(a) shows the measurement results of the epitaxial wafers according to Comparative Examples 1 to 3, and FIG. 9(b) shows the measurement results of the epitaxial wafers according to Examples 1 to 4, respectively.

[0137] As shown in FIG. 9(a), the in-plane distribution of the residual Oi concentration of the epitaxial wafers according to Comparative Examples 1 to 3 is generally uniform, and no decrease in the residual Oi concentration was observed in the outer peripheral portion. Also, as shown in FIG. 9(b), the in-plane distribution of the residual Oi concentration of the epitaxial wafers according to Examples 1 to 4 is also generally uniform, and no decrease in the residual Oi concentration was observed in the outer peripheral portion. As shown in FIG. 6(b), since the BMD density in the outer peripheral portion of the epitaxial wafers according to Examples 1 to 4 is increased compared with Comparative Examples 1 to 3, there was a concern about slip dislocation due to insufficient strength due to a decrease in the residual Oi concentration in the outer peripheral portion. However, the residual Oi concentration of the epitaxial wafers according to Examples 1 to 4 is also 10×10 17 atoms / cm 3It was the remaining Oi concentration as described above and sufficient strength could be ensured. Therefore, it was found that there was no need to worry about slip dislocation due to the decrease in the remaining Oi concentration.

[0138] FIG. 10 shows the region of the present invention where the average COP size at a position 145 mm away from the crystal central axis in the radial direction (outer peripheral part; corresponding to a position 145 mm in the radial direction from the wafer center in the wafer) is 75 nm or less, on the biaxial region formed by the cooling rate CR1 (°C / min) at 1100°C of the silicon single crystal and V / G1 (mm 2 / °C·min). The horizontal axis represents the cooling rate CR1 at 1100°C and the vertical axis represents V / G1, respectively. Table 4 shows the correspondence between the average COP size of the epitaxial wafers according to Comparative Examples 1 to 3 and Examples 1 to 6 shown in FIG. 10 and the growth conditions (cooling rate CR1 and V / G1) of the silicon single crystal samples #1 to #4. The values of the cooling rate CR1 (°C / min) and V / G1 (mm 2 / °C·min) of the silicon single crystal at 1100°C can be obtained by in-furnace heat transfer analysis using numerical simulation.

[0139]

Table 4

[0140] The triangular region in FIG. 10 represents the range where the average COP size is 75 nm or less. This triangular region is determined by the wafers according to Examples 1 to 6 obtained from the crystals grown by the preferred method of the present invention. Further, FIG. 10 shows that under the conventional crystal pulling conditions, the cooling rate is low because there is no cooling system 18, and larger COP sizes occur in the wafers according to Comparative Examples 1 to 3. The large-sized COPs in this outer peripheral part cause a decrease in the BMD density.

[0141] The triangular region in Fig. 10 represents the conditions of V / G1 and cooling rate CR1 obtained from the crystal grown by the preferred method of the present invention, whereby the wafers of the present invention in Examples 1 to 6 can achieve a small COP size at the outer peripheral portion.

[0142] As shown in Fig. 10, the relational expression between the cooling rate CR1 and V / G1 at 1100 °C, which is necessary for growing a silicon single crystal with an average COP size of 75 nm or less at the outer peripheral portion, is obtained as follows from the growth conditions of silicon single crystal samples #1 to #3 (Examples 1 to 6).

[0143] V / G1 ≤ 0.1035 × CR1 - 0.0350

[0144] Here, V represents the pulling rate (mm / min) of the silicon single crystal, G1 represents the temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon to 1350 °C at a position 145 mm radially away from the crystal central axis, and CR1 represents the cooling rate (°C / min) of the silicon single crystal at 1100 °C at a position 145 mm radially away from the crystal central axis, respectively.

[0145] If it is in the region below the diagonal straight line (line segment) drawn in Fig. 10 according to this relational expression, the average COP size can be made 75 nm or less, but if it is in the region above the diagonal straight line, the average COP size will exceed 75 nm. In fact, it can be seen that sample #4 (Comparative Examples 1 to 3) of the silicon single crystal with an average COP size exceeding 75 nm is on the upper left side of the approximate straight line.

[0146] In addition, regarding V / G1, it is necessary to satisfy V / G1 ≥ 0.183. This is because when V / G1 is smaller than 0.183, the vacancy concentration is low, and there is a possibility that the entire wafer cannot be made into a COP region.

[0147] Furthermore, regarding the cooling rate CR1 at 1100°C, it is necessary to satisfy 2.105 ≤ CR1 ≤ 2.839. If the cooling rate CR1 is less than 2.105, the average COP size will be larger than 75 nm. Also, the larger the cooling rate CR1, the smaller the average COP size can be. However, if the cooling rate CR1 is greater than 2.839, there is a risk that the single crystal will rupture due to the thermal stress generated inside the crystal.

[0148] From the above results, it was found that by controlling the crystal pulling conditions so as to be within the range of the right triangle drawn in FIG. 10, appropriate crystal pulling conditions can be obtained such that the average COP size in the outer peripheral portion is 75 nm or less.

[0149] FIG. 11 is a graph showing the region of the present invention where the average COP size on the crystal central axis is 120 nm or less on the biaxial region formed by the cooling rate CR2 (°C / min) of the silicon single crystal at 1100°C and V / G2 (mm 2 / °C·min) on the crystal central axis. The horizontal axis represents the cooling rate CR2 at 1100°C, and the vertical axis represents V / G2, respectively. Table 5 shows the correspondence between the average COP size of the epitaxial wafers according to Comparative Examples 1 to 3 and Examples 1 to 6 shown in FIG. 11 and the growth conditions (cooling rate CR2 and V / G2) of the silicon single crystal samples #1 to #4.

[0150]

Table 5

[0151] FIG. 11 and Table 5 show the relationship between V / G2 on the crystal central axis and the cooling rate of the crystal at 1100°C. Here, the triangular region represents the range where the average COP size is 120 nm or less. This triangular region is determined by the wafers according to Examples 1 to 6 obtained from the crystals grown by the preferred method of the present invention.

[0152] According to Table 5, the average COP size of the wafers according to Examples 1 to 6 is in the range of 76.8 to 119.8 nm. Furthermore, Table 5 shows that the average COP size of the wafers according to Comparative Examples 1 to 3 is 141.8 to 145.0 nm, which greatly exceeds the preferable size of 120 nm or less.

[0153] Also, Table 5 shows that the cooling rate at the central axis in the conventional crystal is 1.858, which is significantly lower because the cooling system 18 is not used. In contrast, it is shown that the cooling rate in the crystal of the present invention is in the range of 1.940 to 2.624. Furthermore, Table 5 also shows the ratio of the pulling rate to the maximum pulling rate.

[0154] As shown in FIG. 11, the relational expression between the cooling rate CR2 and V / G2 at 1100°C, which is necessary to grow a silicon single crystal with an average COP size of 120 nm or less at the crystal central axis, is obtained as follows from the growth conditions of silicon single crystal samples #1 to #3 (Examples 1 to 6).

[0155] V / G2 ≦ 0.1096×CR2 - 0.0387

[0156] Here, V represents the pulling rate (mm / min) of the silicon single crystal, G2 represents the temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon to 1350°C at the crystal central axis, and CR2 represents the cooling rate (°C / min) of the silicon single crystal at 1100°C at the crystal central axis, respectively.

[0157] If it is in the region below the diagonal straight line (line segment) drawn in FIG. 11 according to this relational expression, the average COP size can be made 120 nm or less, but if it is in the region above the straight line, the average COP size will exceed 120 nm. In fact, it can be seen that sample #4 (Comparative Examples 1 to 3) of the silicon single crystal with an average COP size exceeding 120 nm is on the upper left side of the approximate straight line.

[0158] In addition, regarding V / G2, it is necessary to satisfy V / G2 ≥ 0.174. This is because when V / G2 is less than 0.174, the pore density is low, and there is a possibility that the entire wafer surface cannot be made into a COP region.

[0159] Furthermore, regarding the cooling rate CR2 at 1100°C, it is necessary to satisfy 1.940 ≤ CR2 ≤ 2.624. When the cooling rate CR2 is less than 1.940, the average COP size cannot be made 120 nm or less. Also, although the larger the cooling rate CR2, the smaller the average COP size can be, when the cooling rate CR2 is greater than 2.624, there is a risk that the single crystal will rupture due to the thermal stress generated inside the crystal.

[0160] From the above results, it was found that by controlling the crystal pulling conditions so as to be within the range of the right triangle drawn in FIG. 11, appropriate crystal pulling conditions can be obtained where the average COP size at the crystal central axis is 75 to 120 nm.

[0161] The values of the cooling rates CR1, CR2 (°C / min) and V / G1, V / G2 (mm 2 / °C·min) of the silicon single crystal at 1100°C obtained by heat transfer analysis in the furnace using numerical simulation, by pulling the silicon single crystal under the process conditions within the range of the triangle in FIGS. 10 and 11, it becomes possible to grow a silicon single crystal in which the average COP size at the outer peripheral portion is 75 nm or less, and further the average COP size at the crystal central axis is 120 nm or less. The values of the cooling rates CR1, CR2 (°C / min) and V / G1, V / G2 (mm 2 / °C·min) of the silicon single crystal at 1100°C, examples of the process conditions for controlling these values include the installation conditions of the water-cooled body, the pulling speed V, and the gap H. Therefore, the cooling rates CR1, CR2 (°C / min) or V / G1, V / G2 (mm 2When the value of ( / ℃·min) is "outside" the triangular range in FIGS. 10 and 11, it can be made to fall "inside" the triangular range by adjusting conditions such as the presence or absence of the water-cooling body, the pulling speed V, the gap H, etc.

[0162] The pulling speed V of the silicon single crystal is a factor that greatly affects its productivity, and the higher the pulling speed V, the higher the productivity of the single crystal. As described above, for the pulling speed V of the silicon single crystal, Sample #1 (Examples 1-4) is the largest, and Sample #2 (Example 5) and Sample #3 (Example 6) become smaller in this order. Therefore, from the viewpoint of productivity, Sample #1 (Examples 1-4) is preferable. The average COP size at the center of the epitaxial wafer according to Examples 1-4 produced from Sample #1 of the silicon single crystal exceeds 100 nm. On the other hand, the average COP size at the center of the epitaxial wafers according to Example 5 and Example 6 is 100 nm or less. That is, the epitaxial wafers of Examples 1-4 with an average COP size exceeding 100 nm have the characteristic of higher productivity of the single crystal compared to Examples 5 and 6 with an average COP size of 100 nm or less.

Industrial Applicability

[0163] The epitaxial silicon wafer according to the present invention is widely used as a substrate material for semiconductor devices. The semiconductor device is mounted on, for example, a smartphone and realizes the multifunctionality and high performance of the smartphone. For example, it becomes possible to execute a plurality of applications simultaneously or to improve the graphic processing ability to smoothly process high-resolution images and videos. The present invention can promote the development of many industrial fields such as the information and communication industry and transportation infrastructure through semiconductor devices, and can greatly contribute to the solution of various social and environmental problems.

Explanation of Signs

[0164] 1 Epitaxial silicon wafer 2 Silicon wafer (silicon substrate) 3 Epitaxial silicon film 4 Silicon melt 5 Silicon single crystal 10 Single crystal pulling apparatus 11 Chamber 11a Main chamber 11b Pull chamber 11c Gas inlet 11d Gas outlet 12 Quartz crucible 13 Carbon susceptor 14 Rotating shaft 15 Shaft drive mechanism 16 Heater 17 Heat shielding member 18 Cooling system (water-cooled body) 19 Wire 20 Wire winding mechanism 21 Magnetic field generating device 120 Epitaxial wafer 121 Epitaxial layer 122 Silicon substrate 123 First denuded zone 124 Gettering layer (bulk region) 125 Second denuded zone E Edge region of wafer H Gap OR Outer peripheral region P O Center of wafer (central part) P X Peripheral part of wafer P E Outermost edge of wafer S11 Silicon single crystal growth process S12 Silicon wafer fabrication process S13 Epitaxial process

Claims

1. An epitaxial silicon wafer having a diameter of 300 mm, A silicon wafer whose entire surface, excluding an edge region extending from the outermost edge to 2 mm inside, is made of a COP region; an epitaxial silicon film formed on the surface of the silicon wafer; An epitaxial silicon wafer, characterized in that an average COP size in an outer periphery 5 mm inward from the outermost edge of the silicon wafer is 75 nm or less.

2. 2. The epitaxial silicon wafer of claim 1 , wherein the average COP size at the wafer center is greater than 100 nm.

3. 3. The epitaxial silicon wafer of claim 2, wherein the average COP size at the wafer center is 120 nm or less.

4. After the oxygen precipitation evaluation heat treatment was performed at 780° C. for 3 hours and at 1000° C. for 16 hours, the BMD density of the bulk part of the silicon wafer in the region excluding the edge region was 5×10 ８ / cm ３ That's all.

2. The epitaxial silicon wafer according to claim 1, wherein the in-plane variation of BMD density is 0.6 or less.

5. After the oxygen precipitation evaluation heat treatment, the BMD density of the bulk part of the silicon wafer in the region excluding the edge region is 7×10 ９ / cm ３ 5. The epitaxial silicon wafer of claim 4, wherein:

6. 5. The epitaxial silicon wafer according to claim 4, wherein the in-plane variation of BMD density is 0.5 or less.

7. In a range of 0 mm or more and 139 mm or less in a radial direction from the center of the wafer, the BMD density is measured at 5 mm intervals in the radial direction starting from the center of the wafer; 5. The epitaxial silicon wafer according to claim 4, wherein the BMD density is measured at 1 mm intervals in the radial direction within a range of 139 mm to 148 mm from the center of the wafer in the radial direction.

8. After the oxygen precipitation evaluation heat treatment is performed, the BMD density is 5×10 in a range of 130 mm to 148 mm in a radial direction from the center of the wafer. ８ / cm ３ That's all.

5. The epitaxial silicon wafer according to claim 4, wherein the in-plane variation of BMD density is 0.35 or less.

9. After the oxygen precipitation evaluation heat treatment is performed, the BMD density is 7×10 in a range of 130 mm to 148 mm in a radial direction from the center of the wafer. ９ / cm ３ 9. The epitaxial silicon wafer of claim 8, wherein:

10. The Oi concentration (ASTM_F121, 1979) of the silicon wafer in the region excluding the edge region is 10×10 １７ atoms / cm ３ Above 14 x 10 １７ atoms / cm ３ 2. The epitaxial silicon wafer of claim 1 , wherein:

11. The Oi concentration (ASTM_F121, 1979) of the silicon wafer in the region excluding the edge region before the oxygen precipitation evaluation heat treatment is 10×10 １７ atoms / cm ３ Above 14 x 10 １７ atoms / cm ３ 5. The epitaxial silicon wafer of claim 4, wherein:

12. After the oxygen precipitation evaluation heat treatment, the Oi concentration (ASTM_F121, 1979) at the outer periphery 5 mm inside from the outermost edge was 8×10 １７ atoms / cm ３ Above 13 x 10 １７ atoms / cm ３ 12. The epitaxial silicon wafer of claim 11, wherein:

13. The nitrogen concentration of the silicon wafer is 3×10 １２ atoms / cm ３ Above 9 x 10 １３ atoms / cm ３ 13. The epitaxial silicon wafer according to claim 1 , wherein:

14. A step of growing a silicon single crystal by the CZ method; processing the silicon single crystal to produce a silicon wafer having a diameter of 300 mm; forming an epitaxial silicon film on the surface of the silicon wafer; The step of growing the silicon single crystal satisfies the following equation at a position 145 mm radially away from the crystal central axis: V / G1≦0.1035×CR1-0.0350 V / G1≧0.183 2.105≦CR1≦2.839 Here, V represents the pulling speed (mm / min) of the silicon single crystal, G1 represents the temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon to 1350°C, and CR1 represents the cooling rate (°C / min) of the silicon single crystal at 1100°C.

15. The step of growing the silicon single crystal satisfies the following equation at the position of the crystal central axis: V / G2≦0.1096×CR2-0.0387 V / G2≧0.174 1.940≦CR2≦2.624 15. The method for producing an epitaxial silicon wafer according to claim 14, wherein G2 represents a temperature gradient (°C / mm) in the crystal growth direction from the melting point of silicon to 1350°C, and CR2 represents a cooling rate (°C / min) of the silicon single crystal at 1100°C.

16. A step of growing a silicon single crystal by the CZ method; processing the silicon single crystal to produce a silicon wafer having a diameter of 300 mm; forming an epitaxial silicon film on the surface of the silicon wafer; The step of growing the silicon single crystal is carried out so that the entire surface of the silicon wafer excluding the edge region extending from the outermost edge to the inner side by 2 mm is a COP region, and the average COP size in the outer periphery extending 5 mm inward from the outermost edge of the silicon wafer is 75 nm or less. Uses a water-cooled body, The crystal pulling speed is 60 to 90% of the maximum pulling speed at which the crystal does not deform. The gap between the heat shield and the melt surface is 40 to 80 mm. The strength of the magnetic field applied near the solid-liquid interface is 2000 to 4000 gauss. and pulling the silicon single crystal under process conditions such that

17. 17. The method for producing an epitaxial silicon wafer according to claim 16, wherein in the step of growing the silicon single crystal, a cooling rate CR1 (°C / min) of the silicon single crystal at 1100°C at a position 145 mm radially away from a crystal central axis is within a range of 2.105≦CR1≦2.

839.

18. 18. The method for producing an epitaxial silicon wafer according to claim 16 or 17, further comprising, prior to the step of growing the silicon single crystal, a step of investigating in-plane distributions of COPs of a plurality of silicon wafer samples taken from a plurality of silicon single crystal samples pulled at various pulling speeds, and experimentally grasping a pulling speed of the silicon single crystal at which an average COP size in an outer periphery of the silicon wafer is 75 nm or less.

19. a silicon substrate whose entire surface, excluding an edge region extending from the outermost edge to an inner 2 mm region, is made of a COP region; an epitaxial silicon film formed on a surface of the silicon substrate; An epitaxial silicon wafer, characterized in that an average COP size in an outer periphery 5 mm inward from the outermost edge of the silicon substrate is 75 nm or less.

20. 20. The epitaxial silicon wafer of claim 19, wherein each COP in the silicon substrate reflects a light intensity when irradiated with laser light, the light intensity corresponding to a diameter of a sphere having the same volume as the COP, the diameter of the sphere being considered as the size of the COP, and the average COP size being equal to an average value of 50 or more of the diameters.

21. 21. The epitaxial silicon wafer of claim 20, wherein an average COP size in a center portion of the silicon substrate is 120 nm or less.

22. 20. The epitaxial silicon wafer of claim 19, having a diameter of 300 mm.

23. 20. The epitaxial silicon wafer of claim 19, having a diameter of 200 mm.

24. 3.0 x 10 １２ ~8.4 x 10 １３ atoms / cm ３ 20. The epitaxial silicon wafer of claim 19, further having a nitrogen concentration of:

25. a silicon substrate whose entire surface, excluding an edge region extending from the outermost edge to an inner 2 mm region, is made of a COP region; an epitaxial silicon film formed on a surface of the silicon substrate; the silicon substrate forms bulk microdefects (BMDs) in the gettering layer when heated; An epitaxial silicon wafer, wherein the in-plane variation of BMD density over the entire silicon substrate is 0.6 or less.

26. 26. The epitaxial silicon wafer of claim 25, wherein said BMDs form in said gettering layer when heated at about 780° C. for 3 hours, followed by heating at about 1000° C. for 16 hours.

27. The in-plane variation of the BMD density is defined as follows: In-plane variation of BMD density = (maximum BMD density - minimum BMD density) / average BMD density Here, the maximum BMD density means the maximum density of the BMD, the minimum BMD density means the minimum density of the BMD, and the average BMD density means the average density of the BMD, 26. The epitaxial silicon wafer of claim 25, wherein the BMD density is measurable at regular intervals in a radial direction from a center to an edge of the epitaxial silicon wafer.

28. the silicon substrate has a peripheral region, the peripheral region being radially from 2 to 11 mm from an edge of the silicon substrate; 28. The epitaxial silicon wafer of claim 27, wherein the constant spacing is 5 mm from the center to the outer periphery region and 1 mm within the outer periphery region.

29. 3.0 x 10 １２ ~8.4 x 10 １３ atoms / cm ３ 26. The epitaxial silicon wafer of claim 25 further having a nitrogen concentration of:

30. 26. The epitaxial silicon wafer according to claim 25, wherein the in-plane variation of BMD density is 0.5 or less.

31. 26. The epitaxial silicon wafer of claim 25, having a diameter of 300 mm.

32. 26. The epitaxial silicon wafer of claim 25, having a diameter of 200 mm.

33. 1. A method for producing a 300 mm diameter epitaxial silicon wafer, comprising: providing a silicon melt in a crucible and doping the silicon melt with nitrogen; forming an interface between the silicon melt and the crystal while pulling the crystal from the silicon melt at a pulling speed (V) that is 60 to 90% of the maximum pulling speed; applying a cooling system to the crystal such that when an outer portion of the crystal radially separated from the central axis by about 145 mm reaches about 1100° C., the cooling rate of the outer portion reaches 2.1-2.8° C. / min; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; providing a gap of 40 to 80 mm between the silicon melt and the heat shield; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one silicon substrate; The maximum pulling speed means the pulling speed at which the crystal starts to deform.

34. The ratio (V / G1) of the pulling speed (V) and the temperature gradient (G1) is 0.183 to 0.218 mm. ２ / ° C. min range, 34. The method of claim 33, wherein G1 means a temperature gradient from the interface temperature to about 1350°C.

35. 35. The method of claim 34, wherein the ratio (V / G1) is set to form COPs throughout the crystal, and further wherein each silicon substrate includes COPs.

36. 34. The method of claim 33, wherein the average COP size in each silicon substrate is 75 nm or less.

37. 37. The method of claim 36, wherein each COP in the silicon substrate reflects a light intensity when irradiated with laser light, the light intensity corresponding to a diameter of a sphere having the same volume as the COP, the diameter of the sphere being considered the size of the COP, and the average COP size being equal to the average of 50 or more of the diameters.

38. 1. A method for producing a 300 mm diameter epitaxial silicon wafer, comprising: providing a silicon melt in a crucible and doping the silicon melt with nitrogen; forming an interface between the silicon melt and the crystal while pulling the crystal from the silicon melt at a pulling speed (V) that is 60 to 90% of the maximum pulling speed; applying a cooling system to the crystal such that when an outer portion of the crystal radially separated from the central axis by about 145 mm reaches about 1100° C., the cooling rate (CR1) of the outer portion is 2.105-2.839° C. / min; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; A gap of 40 to 80 mm is provided between the silicon melt and the heat shield, and the following conditions are maintained: 0.183≦V / G1≦0.1035×CR1−0.0350 2.105≦CR1≦2.839 Here, G1 means the temperature gradient from the interface temperature to about 1350°C; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one of the plurality of silicon substrates; The maximum pulling speed means the pulling speed at which the crystal starts to deform.

39. 40. The method of claim 38, wherein V / G1 is set to form COPs throughout the crystal, and at least one silicon substrate contains COPs.

40. 40. The method of claim 38, wherein an average COP size in a region of about 145 mm radially from the center of at least one of the plurality of silicon substrates is 75 nm or less.

41. 41. The method of claim 40, wherein each COP in the silicon substrate reflects a light intensity when irradiated with laser light, the light intensity corresponding to a diameter of a sphere having the same volume as the COP, the diameter of the sphere being considered the size of the COP, and the average COP size being equal to the average of 50 or more of the diameters.

42. 1. A method for producing a 300 mm diameter epitaxial silicon wafer, comprising: providing a silicon melt in a crucible and doping the silicon melt with nitrogen; forming an interface between the silicon melt and the crystal while pulling the crystal from the silicon melt at a pulling speed (V) that is 60 to 90% of the maximum pulling speed; applying a cooling system to the crystal such that when the central axis of the crystal reaches about 1100° C., the cooling rate (CR2) of the central axis reaches 1.940-2.624° C. / min; applying a magnetic field of 2000 to 4000 Gauss to the silicon melt; A gap of 40 to 80 mm is provided between the silicon melt and the heat shield, and the following conditions are maintained: 0.174≦V / G2≦0.1096×CR2−0.0387 1.940≦CR2≦2.624 Here, G2 means the temperature gradient from the interface temperature to about 1350°C; cutting the crystal into a plurality of silicon substrates; and forming an epitaxial layer on at least one of the plurality of silicon substrates; The maximum pulling speed means the pulling speed at which the crystal starts to deform.

43. 43. The method of claim 42, wherein V / G2 is set to form COPs throughout the crystal, and at least one silicon substrate contains COPs.

44. 43. The method of claim 42, wherein an average COP size at the center of at least one of the plurality of silicon substrates is 120 nm or less.

45. 45. The method of claim 44, wherein each COP in the silicon substrate reflects a light intensity when irradiated with laser light, the light intensity corresponding to a diameter of a sphere having the same volume as the COP, the diameter of the sphere being considered the size of the COP, and the average COP size being equal to the average of 50 or more of the diameters.

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