Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device that is reducible in possibility of a decrease in reliability.SOLUTION: The present invention relates to a semiconductor device that has: a semiconductor layer 11 having a PN junction 12; a first electrode layer 21 formed on a surface of the semiconductor layer 11; first solder 31 formed on the first electrode layer 21; a second electrode layer 22 formed below a reverse surface of the semiconductor layer 11; second solder 32 formed below the second electrode layer 22; and a separation body 42 formed below the second electrode 22 and arranged around the second soler 32 in plan view, the separation body 42 separating from the second solder so that the second solder 32 is not put on.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] FIG. 4 is a cross-sectional view for explaining a method for manufacturing a conventional mesa diode. This manufacturing method is a method of attaching solders 101 and 102 to both surfaces of a wafer 110 in a wafer state. A photo process using photolithography technology is performed so that Ni plating is performed only on a necessary portion of the back surface of the wafer 110, leaving an oxide film 111 on the back surface, and Ni plating treatment is performed to form a Ni plating electrode on a portion other than the oxide film 111. Then, solder 102 is attached under the second Ni plating electrode 122, and the oxide film 111 on the back surface is irradiated with a laser 131 for chip division to perform a breaking process to form chips. Related techniques are disclosed in Patent Document 1.

[0003] However, in the above manufacturing method, a photo process for leaving the oxide film 111 on the back surface is required, which makes the manufacturing process complicated and increases the manufacturing cost.

[0004] In addition, a conventional mesa diode has a P - type semiconductor layer 112 in contact with an N + type semiconductor layer 110a, and a plurality of first Ni plating electrodes 121 are formed on the P + type semiconductor layer 112. Grooves are formed in the P + type semiconductor layer 112 and the N - type semiconductor layer 110a, and a passivation layer 125 is formed in the grooves. Further, an N - type semiconductor layer 113 in contact with the lower surface of the N + type semiconductor layer 110a is formed, and a plurality of second Ni plating electrodes 122 are formed under the N + type semiconductor layer 113. An oxide film 111 is formed around each of the plurality of second Ni plating electrodes 122, a first solder 101 is formed on the first Ni plating electrode 121, and a second solder 102 is formed under the second Ni plating electrode 122.

[0005] However, the oxide film 111 formed around the second Ni plating electrode 122 may not have sufficiently high corrosion resistance, water resistance, or migration resistance. As a result, the reliability of the diode (semiconductor device) may decrease.

[0006] Therefore, there is a need for a semiconductor device capable of reducing the possibility of a decrease in reliability, and a method for manufacturing a semiconductor device capable of reducing the complexity of the manufacturing process by reducing the photolithography process.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] Various aspects of the present invention aim to provide a semiconductor device capable of reducing the possibility of a decrease in reliability, and a method for manufacturing a semiconductor device capable of reducing the complexity of the manufacturing process by reducing the photolithography process.

Means for Solving the Problems

[0009] Various aspects of the present invention will be described below.

[0010] [1] A semiconductor layer having a PN junction, A first electrode layer formed on the surface of the semiconductor layer, A first solder formed on the first electrode layer, A second electrode layer formed under the back surface of the semiconductor layer, A second solder formed under the second electrode layer, A separator formed under the second electrode layer and disposed around the second solder in a plan view having The semiconductor device is characterized in that the separator separates from the second solder so that the second solder does not land thereon.

[0011] According to the semiconductor device of [1] according to one aspect of the present invention, since the separator on which the second solder does not land is arranged around the second solder in a plan view, there is a possibility that the corrosion resistance, water resistance, or migration resistance can be enhanced. As a result, the reliability of the semiconductor device can be improved.

[0012] [2] In the above [1], an inclined surface of a mesa structure formed on a side surface on the surface side of the semiconductor layer; and a passivation layer formed on the inclined surface characterize the semiconductor device.

[0013] According to the semiconductor device of [2] according to one aspect of the present invention, since the passivation layer is formed on the inclined surface in an environment with high cleanliness, the reliability of the semiconductor device can be enhanced.

[0014] [3] In the above [1] or [2], the semiconductor layer has a first first-conductivity-type semiconductor layer formed from the PN junction to the back surface side; a second first-conductivity-type semiconductor layer that contacts the first first-conductivity-type semiconductor layer and is formed on the back surface side of the semiconductor layer and has a higher impurity concentration than the first first-conductivity-type semiconductor layer; and a second-conductivity-type semiconductor layer formed from the PN junction to the surface side characterize the semiconductor device, wherein the PN junction is located on a surface where the second-conductivity-type semiconductor layer is joined to the first first-conductivity-type semiconductor layer.

[0015] [4] In the above [1] or [2], the separator is characterized by being a solder resist or polyimide.

[0016] According to the semiconductor device of [4] according to one aspect of the present invention, by forming a separator with a solder resist, corrosion resistance and the like can be further enhanced, and the reliability of the semiconductor device can be further improved.

[0017] [5] In the above [1] or [2], A semiconductor device, characterized by having a mold resin disposed on side surfaces of the semiconductor layer and side surfaces of the separator.

[0018] [6] A step (a) of forming a PN junction in the semiconductor wafer by introducing impurities from a front surface side or a back surface side of the semiconductor wafer; A step (b) of forming a groove having a mesa structure on a surface of the semiconductor wafer; A step (c) of forming a passivation layer on an inner surface of the groove; A step (d) of forming a plurality of first electrode layers made of the conductive layer on a surface of the semiconductor wafer by forming a conductive layer on front and back surfaces of the semiconductor wafer; A step (e) of applying a separator for separating so that solder does not land on a region where no solder is disposed under the conductive layer on a back surface of the semiconductor wafer; A step (f) of curing the separator; A step (g) of disposing a first solder on each of the first electrode layers on the surface of the semiconductor wafer and disposing a second solder under the exposed conductive layer on the back surface of the semiconductor wafer having, A method of manufacturing a semiconductor device, characterized in that, in plan view, a center of the separator on a back surface of the semiconductor wafer overlaps a center of the groove of the mesa structure.

[0019] According to the method for manufacturing the semiconductor device of [6] according to one aspect of the present invention, in step (e), a separator for separating so that no solder adheres is applied to a region where no solder is disposed under the conductive layer on the back surface of the semiconductor wafer, whereby the conductive layer on the back surface of the semiconductor wafer can be separated into a plurality of second electrode layers in a plan view. As a result, a second solder can be disposed under the exposed conductive layer on the back surface of the semiconductor wafer. For this reason, steps such as oxide film growth, photolithography, and etching as in the prior art become unnecessary, and the complexity of the manufacturing process can be reduced.

[0020] [7] In the above [6], The separator in the step (e) is a solder resist or polyimide, and a method for manufacturing a semiconductor device is characterized thereby.

[0021] According to the method for manufacturing the semiconductor device of [6] according to one aspect of the present invention, by forming the separator with a solder resist, corrosion resistance and the like can be further enhanced, and the reliability of the semiconductor device can be further improved.

[0022] [8] In the above [7], As a method for applying the separator in the step (e), a coating method such as spraying, printing, or inkjet is used. As a method for curing the separator in the step (f), a curing method by heat or ultraviolet irradiation is used, and a method for manufacturing a semiconductor device is characterized thereby.

[0023] [9] In any one of the above [6] to [8], After the step (g), a step (h) of dividing the semiconductor wafer into a plurality of chips is performed by irradiating a laser for chip dicing or forming a groove with a dicing saw on the separator on the back surface of the semiconductor wafer and then performing a breaking process. The conductive layer on the second solder on the back surface of the plurality of chips divided by the step (h) becomes a second electrode layer, and a method for manufacturing a semiconductor device is characterized thereby.

[0024]

[10] In any one of the above [6] to [8], The manufacturing method of a semiconductor device, wherein the groove in the step (b) is formed by cutting with a dicing blade.

[0025] According to the manufacturing method of the semiconductor device of the above

[10] according to an aspect of the present invention, compared with the case where the groove is formed by wet etching, each process of oxide film growth, photolithography, and etching by photolithography technology becomes unnecessary, so the manufacturing process can be simplified. In addition, a large amount of chemical solution is used for groove formation by wet etching, but in the manufacturing method of the semiconductor device of the above

[10] , only the step of removing a slight strain layer formed by a dicing blade by etching is included, so the usage amount of the chemical solution with a large environmental load can be significantly reduced.

[0026]

[11] In any one of the above [6] to [8], The manufacturing method of a semiconductor device, wherein each of a plurality of regions where the solder without applying the separation material is arranged in the step (e) has a planar shape provided with positioning marks.

[0027] According to the manufacturing method of the semiconductor device of the above

[11] according to an aspect of the present invention, by making each of a plurality of regions where the solder is arranged have a planar shape provided with positioning marks, positioning can be easily performed when mounting the diced semiconductor device on the mounting substrate. [Advantages of the Invention]

[0028] According to various aspects of the present invention, it is possible to provide a semiconductor device capable of reducing the possibility of a decrease in reliability, and a manufacturing method of a semiconductor device capable of reducing the complexity of the manufacturing process by reducing the photographic process using photolithography technology. [Brief Description of the Drawings]

[0029]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying Out the Invention

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

[0031] (First Embodiment) FIGS. 1(A) and (B) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to one aspect of the present invention.

[0032] The method of manufacturing the semiconductor device according to [6] above according to one aspect of the present invention has a step (a) of forming a PN junction 12 in the semiconductor wafer 10 by introducing impurities from the front side or the back side of the semiconductor wafer 10, as shown in FIG. 1(A). For example, a silicon wafer can be used as the semiconductor wafer 10. Specifically, boron and phosphorus are simultaneously diffused over the entire surface from both sides of the N - -type silicon wafer as the semiconductor wafer 10. That is, boron is diffused from the entire surface of the N - -type semiconductor wafer 10, and at the same time, phosphorus is diffused from the entire back surface of the N - -type semiconductor wafer 10. As a result, in the semiconductor wafer 10, a semiconductor layer 11 having a P + -type semiconductor layer (also referred to as a second conductivity type semiconductor layer) 15, an N - -type semiconductor layer (also referred to as a first first conductivity type semiconductor layer) 16, and an N + -type semiconductor layer (also referred to as a second first conductivity type semiconductor layer) 17 is formed.

[0033] On the back side of the semiconductor layer 11 as the semiconductor wafer 10, an N - -type semiconductor layer 17 having a higher impurity concentration than the N + -type semiconductor layer 16 is formed. The N + -type semiconductor layer 17 is in contact with the N - -type semiconductor layer 16. On the front side of the semiconductor layer 11, a P - -type semiconductor layer 15 that is joined to the N + -type semiconductor layer 16 is formed. On the surface where the P + -type semiconductor layer 15 and the N - -type semiconductor layer 16 are joined, a PN junction 12 is formed.

[0034] After that, a mesa-structured groove 10a is formed on the surface of the semiconductor wafer 10 (step (b)). Specifically, a groove 10a having a depth from the surface of the semiconductor wafer 10 on the side of the P + -type semiconductor layer 15 to the middle of the N - -type semiconductor layer 16 is formed by cutting with a dicing blade (not shown).

[0035] In this embodiment, the groove 10a is formed by cutting the semiconductor wafer 10 with a dicing blade, but it is considered that a similar groove can also be formed by laser processing.

[0036] Next, the semiconductor wafer 10 including the inner surface of the groove 10a may be wet-etched to remove the strain on the inner surface of the groove 10a.

[0037] After that, a passivation layer 41 is formed on the inner surface of the groove 10a (step (c)). Specifically, a glass paste is applied to the inner surface of the groove 10a by a printing method, and the glass paste is subjected to a baking process to form a passivation layer 41 made of glass.

[0038] Next, the front and back surfaces of the semiconductor wafer 10 may be wet-etched or sandblasted with BHF (buffered hydrofluoric acid) to remove the oxide films on the electrode formation surfaces of the front and back surfaces of the semiconductor wafer 10.

[0039] Thereafter, by forming a conductive layer 22a on the front and back surfaces of the semiconductor wafer 10, a plurality of first electrode layers 21 made of the conductive layer are formed on the front surface of the semiconductor wafer 10 (step (d)). Specifically, by forming a Ni plating layer as the conductive layer 22a on the front and back surfaces of the semiconductor wafer 10, a Ni plating layer 22a is formed over the entire back surface of the semiconductor wafer 10, and a plurality of first electrode layers 21 made of the Ni plating layer are formed on the front surface of the semiconductor wafer 10 (see Fig. 1(A)).

[0040] Next, a separator 42 for preventing solder from adhering is applied to an area on the back surface of the semiconductor wafer 10 where no solder is to be placed under the conductive layer (Ni plating layer) 22a (step (e)). The separator 42 is preferably a solder resist or polyimide. Also, as a method for applying the separator 42, an application method by spraying, screen printing, dispenser, or inkjet may be used.

[0041] Thereafter, the separator 42 is cured (step (f)). As a method for curing the separator 42 such as a solder resist or polyimide, a curing method by heat or ultraviolet irradiation may be used.

[0042] Thereafter, a first solder 31 is placed on each of the first electrode layers 21 on the front surface of the semiconductor wafer 10, and a second solder 32 is placed under the exposed conductive layer 22a on the back surface of the semiconductor wafer 10 (step (g)). At this time, in plan view, the center of the separator 42 on the back surface of the semiconductor wafer 10 overlaps with the center of the groove 10a of the mesa structure (see Fig. 1(B)). Note that the exposed electrode layer 22a described above serves as the second electrode layer. Specifically, the plurality of first and second solders 31 and 32 may be formed by printing solder paste on the plurality of first and second electrode layers 21 and 22a on both sides of the semiconductor wafer 10 by screen printing.

[0043] Next, after forming a groove 51 in the separator 42 on the back surface of the semiconductor wafer 10 by laser irradiation for chip separation or a dicing saw and then performing a breaking process, the semiconductor wafer 10 is divided into a plurality of chips (step (h)). That is, since the separator 42 is formed on the back surface of the semiconductor wafer 10, it is possible to form the groove 51 from the back surface of the semiconductor wafer 10 by laser irradiation for chip separation or a dicing saw. Note that the laser for chip separation is a laser with a narrow width and a deep depth. Also, the conductive layer 22a on the second solder 32 on the back surfaces of the plurality of divided chips becomes the second electrode layer 22 shown in FIG. 2.

[0044] In the above step (e), each of the plurality of regions where the solder is disposed and the separator 42 is not applied may have a planar shape provided with positioning marks (see FIGS. 3(B) and 3(C)). This will be described in detail below. FIGS. 3(A) to 3(C) are plan views of the chips divided from the semiconductor wafer 10 as viewed from the back surface. FIG. 3(A) is a comparative example in which the planar shape of the second solder 32 is formed in a quadrangular shape and no positioning mark is formed. In contrast, FIG. 3(B) shows that positioning marks 52 for the second electrode layer 22 are formed at the four corners of the quadrangular shape of the second solder 32, and FIG. 3(C) shows that positioning marks 52 for the second electrode layer 22 are formed at the centers of two opposing sides of the quadrangular shape of the second solder 32. By applying the separator 42 in this way, each of the plurality of regions (the plurality of second electrode layers 22) where the solder is disposed has a planar shape provided with the positioning marks 52, so that positioning can be easily performed when mounting the chipped semiconductor device on the mounting substrate, and alignment with the lead frame can also be easily performed.

[0045] In the present embodiment, the positioning mark 52 is shown in the positions and shapes in FIGS. 3(B) and 3(C), but the present invention is not limited thereto, and the positions and shapes of the positioning mark 52 may be changed and implemented.

[0046] According to the present embodiment, by applying the separator 42 that separates so that no solder adheres to a region where no solder is disposed under the conductive layer 22a on the back surface of the semiconductor wafer 10 in step (e), the conductive layer 22a on the back surface of the semiconductor wafer 10 can be separated into a plurality of second electrode layers 22 in a plan view. As a result, the second solder 32 can be disposed under the exposed conductive layer 22a on the back surface of the semiconductor wafer 10. Therefore, each process of oxide film growth, photolithography, and etching as in the prior art becomes unnecessary, and the complexity of the manufacturing process can be reduced.

[0047] Further, according to the present embodiment, by forming the separator 42 with an organic film such as a solder resist, intrusion of moisture can be suppressed, corrosion resistance can be improved, and the reliability of the semiconductor device can be further improved.

[0048] Further, according to the present embodiment, compared with the case where the groove 10a of the mesa structure is formed by wet etching, each process of oxide film growth, photolithography, and etching by photolithography technology becomes unnecessary, so the manufacturing process can be simplified. In addition, a large amount of chemical solution is used for groove formation by wet etching, but in the present embodiment, only the step of removing a slight strain layer formed by a dicing blade by etching is included, so the amount of use of the chemical solution with a large environmental load can be significantly reduced.

[0049] (Second Embodiment) FIG. 2 is a cross-sectional view showing a semiconductor device according to an aspect of the present invention. In this semiconductor device, a first lead frame 61 is electrically connected to a first solder 31 of a semiconductor chip manufactured by the manufacturing method according to the first embodiment, and a second lead frame 62 is electrically connected to a second solder 32 of the semiconductor chip. Then, a part of the semiconductor chip, the first and second lead frames is sealed with a mold resin 50. That is, a part of the first and second lead frames is formed so as to be exposed from the mold resin 50 (see FIG. 2).

[0050] As shown in FIG. 2, the semiconductor device according to an aspect of the present invention has a semiconductor layer 11 having a PN junction 12, and a first electrode layer 21 is formed on the surface of the semiconductor layer 11. A first solder 31 is formed on the first electrode layer 21. A second electrode layer 22 is formed on the back surface of the semiconductor layer 11, and a second solder 32 is formed under the second electrode layer 22. A separator 42 is formed under the second electrode layer 22, and this separator 42 is disposed around the second solder 32 in a plan view. This separator 42 separates from the second solder 32 so that the second solder 32 does not land, and may be a solder resist or polyimide. Resin 50 is disposed on the side surfaces of the separator 42, the side surface of the semiconductor layer 11, and the side surfaces of the first and second solders 31 and 32, and this resin is a mold resin.

[0051] The semiconductor layer 11 has an N-type semiconductor layer (first first conductivity type semiconductor layer) 16 formed on the back surface side from the PN junction 12. - On the back surface side of the semiconductor layer 11, an N-type semiconductor layer (second first conductivity type semiconductor layer) 17 having a higher impurity concentration than the N-type semiconductor layer 16 is formed, and the N-type semiconductor layer 17 is in contact with the N-type semiconductor layer 16. A P-type semiconductor layer (second conductivity type semiconductor layer) 15 is formed on the surface side from the PN junction 12 of the semiconductor layer 11, and the PN junction 12 is formed by the P-type semiconductor layer 15 and the N-type semiconductor layer 16. - type semiconductor layer 16. + type semiconductor layer (second first conductivity type semiconductor layer) 17 is formed, and the N + type semiconductor layer 17 is N - type semiconductor layer 16. + type semiconductor layer (second conductivity type semiconductor layer) 15 is formed on the surface side from the PN junction 12 of the semiconductor layer 11, and the PN junction 12 is formed by the P + type semiconductor layer 15 and the N -It is located on the surface that joins the type semiconductor layer 16.

[0052] An inclined surface 11c of a mesa structure is formed on a side surface 11b on the surface side of the semiconductor layer 11, and a passivation layer 41 is formed on this inclined surface 11c. The passivation layer 41 is formed in a process before the semiconductor wafer 10 is divided as described in the first embodiment. Therefore, the passivation layer 41 can be formed on the inclined surface 11c of the mesa structure in an environment with high cleanliness, and as a result, the reliability of the semiconductor device can be increased.

[0053] According to the present embodiment, since the separator 42 on which the second solder 32 does not mount is arranged around the second solder 32 in plan view, there is a possibility that the corrosion resistance, water resistance, or migration resistance can be increased, and as a result, the reliability of the semiconductor device can be improved. Here, by forming the separator 42 with an organic film such as a solder resist, the corrosion resistance and the like can be further increased, and the reliability of the semiconductor device can be further improved.

[0054] Further, in the prior art, Ni plating may grow even under the oxide film 111, and the solder may bridge to an adjacent electrode. On the other hand, when a solder resist is used for the separator in the present embodiment, the solder can be almost completely prevented from mounting by the solder resist, so that the portion where the second solder 32 mounts and the portion where it does not mount can be clearly separated, and as a result, stable production of the semiconductor device becomes possible. Also, by selecting a resist with high corrosion resistance and water repellency, it becomes possible to supply a product with higher corrosion resistance, water resistance, and migration resistance than in the past.

Explanation of Reference Numerals

[0055] 10 Semiconductor wafer 10a Groove of mesa structure 11 Semiconductor layer 11b Side surface on the surface side of the semiconductor layer 11c Inclined surface of mesa structure 12 PN junction 15 P +p-type semiconductor layer (second conductivity type semiconductor layer) 16 N - n-type semiconductor layer (first n-type semiconductor layer) 17 N + n-type semiconductor layer (second n-type semiconductor layer) 21 First electrode layer 22 Second electrode layer 22a Conductive layer 31 First solder 32 Second solder 41 Passivation layer 42 Isolate

Claims

1. A semiconductor layer having a PN junction, A first electrode layer formed on the surface of the semiconductor layer, A first solder formed on the first electrode layer, A second electrode layer formed under the back surface of the semiconductor layer, A second solder formed under the second electrode layer, A separator formed under the second electrode layer and disposed around the second solder in a plan view, having, The separator is separated from the second solder so that the second solder does not land thereon. A semiconductor device characterized by this.

2. In Claim 1, An inclined surface of a mesa structure formed on a side surface on the surface side of the semiconductor layer, A passivation layer formed on the inclined surface, A semiconductor device characterized by having.

3. In Claim 1 or 2, The semiconductor layer, A first first-conductivity-type semiconductor layer formed from the PN junction toward the back surface side, A second first-conductivity-type semiconductor layer that contacts the first first-conductivity-type semiconductor layer, is formed on the back surface side of the semiconductor layer, and has a higher impurity concentration than the first first-conductivity-type semiconductor layer, A second-conductivity-type semiconductor layer formed from the PN junction toward the surface side, having, The PN junction is located on a surface where the second-conductivity-type semiconductor layer is joined to the first first-conductivity-type semiconductor layer. A semiconductor device characterized by this.

4. In Claim 1 or 2, The separator is a solder resist or polyimide. A semiconductor device characterized by this.

5. In Claim 1 or 2, A semiconductor device, characterized by having a mold resin disposed on side surfaces of the semiconductor layer and side surfaces of the separator.

6. A step (a) of forming a PN junction in the semiconductor wafer by introducing impurities from a front surface side or a back surface side of the semiconductor wafer; A step (b) of forming a groove having a mesa structure on a surface of the semiconductor wafer; A step (c) of forming a passivation layer on an inner surface of the groove; A step (d) of forming a plurality of first electrode layers made of the conductive layer on a surface of the semiconductor wafer by forming a conductive layer on both the front surface and the back surface of the semiconductor wafer; A step (e) of applying a separator for separating so that solder does not adhere to a region where solder is not disposed under the conductive layer on the back surface of the semiconductor wafer; A step (f) of curing the separator; A step (g) of disposing a first solder on each of the first electrode layers on the surface of the semiconductor wafer and disposing a second solder under the exposed conductive layer on the back surface of the semiconductor wafer having, A method for manufacturing a semiconductor device, characterized in that, in a plan view, a center of the separator on the back surface of the semiconductor wafer overlaps a center of the groove of the mesa structure.

7. In Claim 6, the separator in the step (e) is a solder resist or polyimide, the method for manufacturing a semiconductor device being characterized thereby.

8. In Claim 7, a method for applying the separator in the step (e) uses a coating method by spraying, printing or inkjet, a method for curing the separator in the step (f) uses a curing method by heat or ultraviolet irradiation, the method for manufacturing a semiconductor device being characterized thereby.

9. In any one of Claims 6 to 8, After the step (g), a step (h) of dividing the semiconductor wafer into a plurality of chips is performed by irradiating the separation material on the back surface of the semiconductor wafer with a laser for chip division or forming a groove with a dicing saw and then performing a breaking process. A method of manufacturing a semiconductor device, wherein the conductive layer on the second solder on the back surface of the plurality of chips divided by the step (h) becomes a second electrode layer.

10. In any one of claims 6 to 8, A method of manufacturing a semiconductor device, wherein the groove in the step (b) is formed by cutting with a dicing blade.

11. In any one of claims 6 to 8, A method of manufacturing a semiconductor device, wherein each of the plurality of regions where the solder that does not apply the separation material in the step (e) is disposed has a planar shape provided with positioning marks.

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