Integrated circuit device and electronic system including the same

Abstract

To provide an integrated circuit device which prevents an unwanted protruding shape in a gate insulation layer of a channel structure, and an electronic system including the same.SOLUTION: An integrated circuit device 100 includes a peripheral circuit structure and a cell array structure. The cell array structure includes: a gate stack including a plurality of gate electrodes 120 and a plurality of mold insulation layers 122 which extend in a horizontal direction and are alternately stacked in a vertical direction; a channel hole 130H and a channel adjacent hole 131H; a channel structure 130; an insulation pattern layer 112 opening a portion 134P of a top face of the channel layer while conformally covering an upper face of the gate stack, an inner sidewall of the channel adjacent hole and an upper face of a gate insulation layer 132; and a common source line structure 110 filling the channel adjacent hole and being in contact with a portion of the top face of the opened channel layer. A sidewall of the common source line structure disposed in the gate stack has a staircase shape.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an integrated circuit element and an electronic system including the same, and more particularly, to an integrated circuit element including a nonvolatile vertical memory element and an electronic system including the same.

Background Art

[0002] In order to satisfy excellent performance and economy, it is required to increase the integration degree of integrated circuit elements. In particular, the integration degree of memory elements is an important factor that determines the economy of products. Since the integration degree of two-dimensional memory elements is mainly determined by the area occupied by a unit memory cell, it is greatly affected by the level of micro-patterning technology. However, for micro-patterning, expensive equipment is required, and the area of a chip die is limited. Therefore, although the integration degree of two-dimensional memory elements has increased, it is still limited. Accordingly, a vertical memory element having a three-dimensional structure is required.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The problem to be solved by the present invention is to provide an integrated circuit element having excellent operating characteristics and an improved integration degree while simplifying the manufacturing process, and an electronic system including the same.

[0004] The problems to be solved by the technical idea of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0005] An integrated circuit device according to the technical idea of the present invention includes a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure. The cell array structure includes a gate stack including a plurality of gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and a plurality of mold insulating layers, a channel hole and a channel adjacent hole penetrating the gate stack, extending in the vertical direction, and connected to each other, a channel structure including a channel layer disposed in the channel hole and a gate insulating layer that conformally covers the channel layer but opens a part of the uppermost surface of the channel layer, an insulating pattern layer that conformally covers the upper surface of the gate stack, the inner sidewall of the channel adjacent hole, and the upper surface of the gate insulating layer but opens the part of the uppermost surface of the channel layer, and a common source line structure that fills the channel adjacent hole and contacts the part of the uppermost surface of the channel layer opened by the gate insulating layer and the insulating pattern layer. The sidewall of the common source line structure disposed inside the gate stack has a stepped shape.

[0006] An integrated circuit device according to the technical idea of the present invention includes a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure. The cell array structure includes a gate stack including a plurality of gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and a plurality of mold insulating layers, a channel hole and a channel adjacent hole penetrating the gate stack, extending in the vertical direction, and connected to each other, a channel structure including a channel layer disposed in the channel hole and a gate insulating layer that conformally covers the channel layer but opens a part of the uppermost surface of the channel layer, and a common source line structure that fills the channel adjacent hole and contacts the part of the uppermost surface of the channel layer opened by the gate insulating layer. In the channel adjacent hole, a protruding insulating pattern is disposed on the sidewall of the gate electrode facing the sidewall of the common source line structure.

[0007] An electronic system according to the technical idea of the present invention includes a main board, an integrated circuit element on the main board, and a controller on the main board that is electrically connected to the integrated circuit element. The integrated circuit element includes a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure. The cell array structure includes a gate stack including a plurality of gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and a plurality of mold insulating layers, a channel hole and a channel adjacent hole that penetrate the gate stack, extend in the vertical direction, and are connected to each other, and a channel structure disposed in the channel hole, including a channel layer and a gate insulating layer that conformally covers the channel layer but opens a part of the uppermost surface of the channel layer, and an insulating pattern layer that conformally covers the upper surface of the gate stack, the inner side wall of the channel adjacent hole, and the upper surface of the gate insulating layer but opens the part of the uppermost surface of the channel layer, and a common source line structure that fills the channel adjacent hole and contacts the part of the uppermost surface of the channel layer opened by the gate insulating layer and the insulating pattern layer. The side wall of the common source line structure disposed inside the gate stack has a stepped shape.

Advantages of the Invention

[0008] The integrated circuit element according to the technical idea of the present invention proposes a new method for electrical connection between the channel layer of the channel structure and the common source line structure, and has the effect of preventing an unnecessary protrusion shape in the gate insulating layer of the channel structure.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a block diagram of an integrated circuit element according to an embodiment of the technical idea of the present invention.

[0012] Referring to FIG. 1, the integrated circuit element 10 may include a memory cell array 20 and a peripheral circuit 30. The memory cell array 20 includes a plurality of memory cell blocks BLK1, BLK2, …, BLKn. The plurality of memory cell blocks BLK1, BLK2, …, BLKn may each include a plurality of memory cells. The plurality of memory cell blocks BLK1, BLK2, …, BLKn may be connected to the peripheral circuit 30 via bit lines BL, word lines WL, string select lines SSL, and ground select lines GSL.

[0013] The peripheral circuit 30 may include a row decoder 32, a page buffer 34, a data input / output circuit 36, and control logic 38. Although not shown, the peripheral circuit 30 may further include an input / output interface, column logic, a voltage generation unit, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, and the like.

[0014] The memory cell array 20 may be connected to the page buffer 34 via the bit lines BL and may be connected to the row decoder 32 via the word lines WL, string select lines SSL, and ground select lines GSL. In the memory cell array 20, the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, …, BLKn may each be flash memory cells. The memory cell array 20 may include a three-dimensional memory cell array. The three-dimensional memory cell array includes a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of word lines WL stacked vertically on a substrate.

[0015] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the integrated circuit element 10 and may transmit and receive data DATA to and from a device outside the integrated circuit element 10.

[0016] The row decoder 32 can respond to an external address ADDR, select at least one of a plurality of memory cell blocks BLK1, BLK2, …, BLKn, and select a word line WL, a string select line SSL, and a ground select line GSL of the selected memory cell block. The row decoder 32 can transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

[0017] The page buffer 34 can be connected to the memory cell array 20 via a bit line BL. During a program operation, the page buffer 34 operates as a write driver, applies a voltage due to data DATA to be stored in the memory cell array 20 to the bit line BL, and during a read operation, operates as a sense amplifier and can sense the data DATA stored in the memory cell array 20. The page buffer 34 can be operated by a control signal PCTL provided from the control logic 38.

[0018] The data input / output circuit 36 can be connected to the page buffer 34 via data lines DLs. During a program operation, the data input / output circuit 36 receives data DATA from a memory controller (not shown), and based on a column address C_ADDR provided from the control logic 38, can provide the program data DATA to the page buffer 34. During a read operation, based on a column address C_ADDR provided from the control logic 38, the data input / output circuit 36 can provide the read data DATA stored in the page buffer 34 to the memory controller.

[0019] The data input / output circuit 36 can transmit an input address or instruction word to the control logic 38 or the row decoder 32. The peripheral circuit 30 can further include an ESD (electrostatic discharge) circuit and a pull-up / pull-down driver.

[0020] The control logic 38 can receive a command CMD and a control signal CTRL from the memory controller. The control logic 38 can provide a row address R_ADDR to the row decoder 32 and a column address C_ADDR to the data input / output circuit 36. The control logic 38 can generate various internal control signals used within the integrated circuit element 10 in response to the control signal CTRL. For example, the control logic 38 can adjust the voltage levels provided to the word line WL and the bit line BL during the execution of a memory operation such as a program operation or an erase operation.

[0021] FIG. 2 is an equivalent circuit diagram showing a memory cell array of an integrated circuit element according to an embodiment of the technical idea of the present invention.

[0022] Referring to FIG. 2, an equivalent circuit diagram of a vertical NAND flash memory element having a vertical channel structure is illustrated.

[0023] In the integrated circuit element 10 of the present invention, the memory cell array MCA can include a plurality of memory cell strings MS. The memory cell array MCA can include a plurality of bit lines BL, a plurality of word lines WL, at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL.

[0024] A plurality of memory cell strings MS can be formed between the plurality of bit lines BL and the common source line CSL. Although the drawings illustrate a case where the plurality of memory cell strings MS each include two string selection lines SSL, the present invention is not limited thereto. For example, the plurality of memory cell strings MS may each include one string selection line SSL.

[0025] A plurality of memory cell strings MS may each include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, …, MCn-1, MCn. The drain region of the string select transistor SST may be connected to the bit line BL, and the source region of the ground select transistor GST may be connected to the common source line CSL. The common source line CSL may be a region where the source regions of a plurality of ground select transistors GST are commonly connected.

[0026] The string select transistor SST may be connected to the string select line SSL, and the ground select transistor GST may be connected to the ground select line GSL. Each of the plurality of memory cell transistors MC1, MC2, …, MCn-1, MCn may be connected to each of the corresponding plurality of word lines WL1, WL2, …, WLn-1, WLn.

[0027] FIG. 3 is a perspective view showing a representative configuration of an integrated circuit element according to an embodiment of the technical idea of the present invention. FIG. 4 is a planar layout showing an integrated circuit element according to an embodiment of the technical idea of the present invention. FIG. 5 is an enlarged planar view of the AA portion of FIG. 4. FIG. 6 is a cross-sectional view taken along the B-B' line of FIG. 5. FIG. 7 is an enlarged cross-sectional view of the CX1 portion of FIG. 6.

[0028] Referring to FIGS. 3 to 7 together, the integrated circuit element 100 includes a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction.

[0029] The cell array structure CS may include the memory cell array 20 described with reference to FIG. 1, and the peripheral circuit structure PS may include the peripheral circuit 30 described with reference to FIG. 1.

[0030] The cell array structure CS may include a plurality of memory cell blocks BLK1, BLK2, …, BLKn. The plurality of memory cell blocks BLK1, BLK2, …, BLKn may each include three-dimensionally arranged memory cells.

[0031] The peripheral circuit structure PS may include a peripheral circuit transistor 60TR and a peripheral circuit wiring structure 70 disposed on a substrate 50. In the substrate 50, an active region AC may be defined by an element isolation film 52, and a plurality of peripheral circuit transistors 60TR may be formed on the active region AC. The plurality of peripheral circuit transistors 60TR may include a peripheral circuit gate 60G and source / drain regions 62 disposed on portions of the substrate 50 on both sides of the peripheral circuit gate 60G.

[0032] The substrate 50 may include a semiconductor material, for example, a Group-IV semiconductor, a Group-III / V compound semiconductor, or a Group-II / VI compound semiconductor. For example, the Group-IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium. The substrate 50 may be provided as a bulk wafer or an epitaxial layer. In other embodiments, the substrate 50 may also include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0033] The peripheral circuit wiring structure 70 includes a plurality of peripheral circuit contacts 72 and a plurality of peripheral circuit wiring layers 74. An interlayer insulating film 80 covering the peripheral circuit transistor 60TR and the peripheral circuit wiring structure 70 may be disposed on the substrate 50. The plurality of peripheral circuit wiring layers 74 may have a multilayer structure including a plurality of metal layers disposed at different vertical levels. A connection pad 90 is disposed on the interlayer insulating film 80, and the connection pad 90 may electrically connect and bond the peripheral circuit structure PS and the cell array structure CS to each other.

[0034] The cell array structure CS may include a cell region MCR, a connection region CON, and a peripheral circuit connection region PRC. The cell region MCR may be a region where a memory cell block including a plurality of memory cell strings extending in the vertical direction is disposed. In the cell region MCR, a common source line structure 110, a plurality of gate electrodes 120, and a channel structure 130 penetrating the plurality of gate electrodes 120 and extending in the vertical direction and connected to the common source line structure 110 may be disposed.

[0035] In the connection region CON, an extension portion 120E and a pad portion 120P connected to a plurality of gate electrodes 120, and a first plug CP1 penetrating the extension portion 120E and the pad portion 120P and electrically connected to the pad portion 120P may be arranged. Further, in the peripheral circuit connection region PCR, a second plug CP2 extending in the vertical direction and electrically connected to the peripheral circuit wiring structure 70 may be arranged.

[0036] The cell array structure CS may include a first surface CS1 connected to the peripheral circuit structure PS and a second surface CS2 opposite to the first surface CS1. In the drawing, the first surface CS1 of the cell array structure CS is shown to be arranged below the cell array structure CS, and the second surface CS2 of the cell array structure CS is shown to be arranged above the cell array structure CS. For the sake of convenience of explanation, as in the drawing, being arranged near the first surface CS1 of the cell array structure CS is referred to as a lower vertical level, and being arranged near the second surface CS2 of the cell array structure CS is referred to as a higher vertical level.

[0037] The plurality of gate electrodes 120 are arranged to be separated from each other in the vertical direction from the cell region MCR, and the plurality of gate electrodes 120 may be alternately arranged with a plurality of mold insulating layers 122. The plurality of gate electrodes 120 and the plurality of mold insulating layers 122 may be referred to as a gate stack GS. The plurality of gate electrodes 120 extend to the connection region CON, and a part of the plurality of gate electrodes 120 arranged in the connection region CON may be referred to as an extension portion 120E. The extension portion 120E may have a length along a horizontal direction that gradually increases in the direction facing the second surface CS2 of the cell array structure CS (that is, the upward direction in the drawing). The extension portion 120E has a stepped shape, and a pad portion 120P may be connected to an end of the extension portion 120E. The pad portion 120P may have a thickness thicker than that of the extension portion 120E in the vertical direction.

[0038] The plurality of gate electrodes 120 may include an embedded conductive layer 120A and a conductive barrier layer 120B surrounding the upper, bottom, and side surfaces of the embedded conductive layer 120A. For example, the embedded conductive layer 120A may include a metal such as tungsten, nickel, cobalt, tantalum; a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide; doped polysilicon; or a combination thereof. In some embodiments, the conductive barrier layer 120B may include titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.

[0039] In some embodiments, the plurality of gate electrodes 120 may correspond to a ground selection line GSL, a word line WL, and at least one string selection line SSL that constitute a memory cell string MS (FIG. 2). For example, in the drawing, the uppermost one gate electrode 120 functions as a ground selection line GSL, and in the drawing, the lowermost two gate electrodes 120 function as string selection lines SSL, and the remaining gate electrodes 120 may function as word lines WL. Thereby, a memory cell string MS in which a ground selection transistor GST, a string selection transistor SST, and memory cell transistors MC1, MC2, …, MCn-1, MCn therebetween are connected in series may be provided.

[0040] A stack isolation insulating layer WLI may be disposed in a stack isolation opening WLH that penetrates the plurality of gate electrodes 120 and the plurality of mold insulating layers 122 and extends in the vertical direction. The stack isolation insulating layer WLI has an upper surface disposed at a vertical level higher than the uppermost gate electrode 120 and may protrude upward with respect to the uppermost gate electrode 120. In some embodiments, the plurality of gate electrodes 120 disposed between a pair of stack isolation openings WLH may constitute one block BLK. Also, within one block BLK, at least one gate electrode 120 may be separated into two gate electrodes 120 by a string isolation opening SSLH. A string isolation insulating layer SSLI may be disposed in the string isolation opening SSLH.

[0041] In the connection region CON and the peripheral circuit connection region PCR, a stacked insulating layer 124 may be disposed so as to surround a plurality of gate electrodes 120, extension portions 120E, and pad portions 120P. In a plan view, the stacked insulating layer 124 may be disposed so as to surround the plurality of gate electrodes 120, and may have an upper surface disposed at the same level as the uppermost gate electrode 120 in the peripheral circuit connection region PCR.

[0042] In the integrated circuit element 100 of the present invention, channel holes 130H and channel adjacent holes 131H that penetrate a plurality of gate electrodes 120 and a plurality of mold insulating layers 122 and extend in the vertical direction may be formed. Here, the channel structure 130 may be disposed within the channel hole 130H. The channel structure 130 may include a gate insulating layer 132, a channel layer 134, a buried insulating layer 136, and a conductive plug 138. The gate insulating layer 132, the channel layer 134, and the buried insulating layer 136 may be sequentially disposed on the inner wall of the channel hole 130H.

[0043] In some embodiments, the gate insulating layer 132 may be disposed so as to conformally cover the channel layer 134 but open (i.e., not cover) a part 134P of the uppermost surface of the channel layer 134. As used herein, the term "open" means that any part is different from other parts and is not covered by a specific component.

[0044] In some embodiments, the plurality of gate electrodes 120 facing the channel hole 130H and the channel adjacent hole 131H, and the plurality of mold insulating layers 122 may have substantially the same thickness in the same vertical direction.

[0045] The channel structure 130 may include a first end disposed near the peripheral circuit structure PS and a second end opposite to the first end.

[0046] A conductive plug 138 electrically connected to the channel layer 134 may be disposed at the first end of the channel structure 130. The conductive plug 138 is connected to the bit line contact BLC, and the channel layer 134 may be electrically connected to the bit line BL via the conductive plug 138 and the bit line contact BLC.

[0047] In some embodiments, at the second end of the channel structure 130, the end of the channel layer 134 is in a square shape protruding in the horizontal direction, and the end of the gate insulating layer 132 corresponding to the end of the channel layer 134 is conformally formed along the protruding square shape and may have a right-angled side wall protruding in the horizontal direction.

[0048] The gate insulating layer 132 may have a structure including a tunneling dielectric film 132A, a charge resistance film 132B, and a blocking dielectric film 132C in sequence on the outer wall of the channel layer 134. The relative thicknesses of the tunneling dielectric film 132A, the charge resistance film 132B, and the blocking dielectric film 132C forming the gate insulating layer 132 are not limited to what is shown and may be variously deformed.

[0049] The tunneling dielectric film 132A may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc.

[0050] The charge resistance film 132B is a region where electrons passing through the tunneling dielectric film 132A from the channel layer 134 can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric film 132C may be made of silicon oxide, silicon nitride, or a metal oxide having a higher dielectric constant than silicon oxide. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0051] In one embodiment, the charge resistance film 132B may include a ferroelectric material. In that case, the charge resistance film 132B may include a metal oxide having ferroelectric material characteristics. For example, the charge resistance film 132B may include a ferroelectric material capable of storing data by hysteresis behavior due to a voltage applied to the charge resistance film 132B. In one embodiment, the charge resistance film 132B may include at least one of hafnium oxide, zirconium oxide, and hafnium zirconium oxide.

[0052] An insulating pattern layer 112 is disposed on the uppermost mold insulating layer 122, and the insulating pattern layer 112 may include silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the insulating pattern layer 112 may be formed to conformally cover the upper surface of the gate stack GS, the inner wall of the channel adjacent hole 131H, and the upper surface of the gate insulating layer 132, while opening a part 134P of the uppermost surface of the channel layer 134. In one embodiment, the lowermost surface of the insulating pattern layer 112 may be in direct contact with the uppermost surface of the blocking dielectric film 132C.

[0053] The common source line structure 110 may be formed on the insulating pattern layer 112 to be connected to the open channel layer 134 of the channel structure 130 and cover the upper surface of the stack isolation insulating layer WLI. In a plan view, the common source line structure 110 may be disposed over the entire region of the cell region MCR. The common source line structure 110 may include doped polysilicon.

[0054] In one embodiment, the common source line structure 110 may fill the channel adjacent hole 131H and be in direct contact with a part 134P of the uppermost surface of the channel layer 134 opened by the gate insulating layer 132 and the insulating pattern layer 112.

[0055] In one embodiment, within the channel hole 130H, the common source line structure 110 contacts the sidewall of the gate insulating layer 132, and within the channel adjacent hole 131H, the common source line structure 110 may contact the sidewall of the insulating pattern layer 112. That is, the sidewall of the gate insulating layer 132 that contacts the common source line structure 110 and the sidewall of the insulating pattern layer 112 that contacts the common source line structure 110 can be coplanar.

[0056] In one embodiment, the common source line structure 110 may fill the channel adjacent hole 131H, cover the insulating pattern layer 112, and be formed on top of the gate stack GS. Thereby, the lowermost surface of the common source line structure 110 can be positioned inside the channel hole 130H. That is, the vertical level of the uppermost surface of the channel layer 134 and the vertical level of the lowermost surface of the common source line structure 110 can be substantially the same.

[0057] In one embodiment, the second width W2 of the portion of the common source line structure 110 located within the channel adjacent hole 131H may be wider than the first width W1 of the portion located within the channel hole 130H. That is, as shown in the drawing, the sidewalls of the common source line structure 110 disposed inside the gate stack GS can be formed in a stepped shape.

[0058] In one embodiment, the first end of the first plug CP1 is disposed at a position adjacent to the peripheral circuit structure PS, and the second end of the first plug CP1 can be disposed on the side opposite to the first end. The first plug CP1 can have sidewalls inclined such that the width of the first end is wider than the width of the second end.

[0059] In one embodiment, the first plug CP1 may include a metal such as tungsten, nickel, cobalt, tantalum; a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride; a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide; doped polysilicon; or a combination thereof.

[0060] In the peripheral circuit connection region PRC, the second plug CP2 can be arranged so as to penetrate the stack insulating layer 124. The shape and constituent material of the second plug CP2 can be the same as those of the first plug CP1.

[0061] Between the stack insulating layer 124 and the peripheral circuit structure PS, a connection via 152, a connection wiring layer 154, and an interlayer insulating film 156 surrounding the connection via 152 and the connection wiring layer 154 can be arranged. The connection via 152 and the connection wiring layer 154 can be configured in multiple layers so as to be arranged in a plurality of vertical levels. Here, the bit line BL, the first plug CP1, and the second plug CP2 can be electrically connected to the peripheral circuit structure PS via the connection via 152, the connection wiring layer 154, and the connection pad 90.

[0062] An upper insulating layer 142 can be arranged on the common source line structure 110. The upper insulating layer 142 can have a flat upper surface throughout the cell region MCR and the connection region CON. The upper insulating layer 142 can be arranged so as to cover the upper surface of the common source line structure 110 and the upper surface of the first plug CP1.

[0063] The conductive via 144 can penetrate the upper insulating layer 142 and contact the common source line structure 110. The upper surface of the conductive via 144 can be arranged at the same vertical level as the upper surface of the upper insulating layer 142. In some embodiments, the conductive via 144 can include a metal such as tungsten, nickel, cobalt, tantalum; a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride; a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide; or a combination thereof.

[0064] A wiring line 164 may be disposed on the upper insulating layer 142. The wiring line 164 may be electrically connected to the conductive via 144. A passivation layer 162 may be disposed on the wiring line 164, and an opening OP of the passivation layer 162 may be formed to expose a part of the upper surface of the wiring line 164. An external connection terminal (not shown) may be electrically connected to the common source line structure 110 via the wiring line 164 and the conductive via 144.

[0065] Generally, in a vertical NAND flash memory device structure in which a cell array structure CS and a peripheral circuit structure PS are attached by a bonding method, in order to electrically connect the common source line structure 110 to the channel layer 134, a step of wet etching and removing the gate insulating layer 132 located on the sidewall of the channel layer 134 is performed. However, such wet etching of the gate insulating layer 132 has a problem that an unnecessary protrusion shape may occur in some regions because the process variation is relatively large.

[0066] In order to solve such a problem, an integrated circuit device 100 according to the technical idea of the present invention forms a channel adjacent hole 131H for electrical connection between the channel layer 134 of the channel structure 130 and the common source line structure 110, and dry etches a part of the gate insulating layer 132 so as to open a part 134P of the uppermost surface of the channel layer 134, and the common source line structure 110 may be formed to fill the inside of the channel adjacent hole 131H.

[0067] Through such a structure of the present invention, in the channel structure 130, since a general method of wet etching the gate insulating layer 132 located on the sidewall of the channel layer 134 to expose the channel layer 134 can be replaced, the integrated circuit device 100 has an effect of preventing an unnecessary protrusion shape of the gate insulating layer 132.

[0068] Ultimately, according to the technical idea of the present invention, it is possible to provide an integrated circuit device 100 having excellent operating characteristics and an improved integration degree while simplifying some manufacturing processes.

[0069] FIG. 8 is a cross-sectional view showing an integrated circuit element according to another embodiment of the technical idea of the present invention. FIG. 9 is an enlarged cross-sectional view of the CX2 portion of FIG. 8.

[0070] Most of the components constituting the integrated circuit element 200 described below, and the materials forming the components, are substantially the same as or similar to those described in FIGS. 3 to 7 above. Therefore, for convenience of explanation, the description will focus on the differences from the aforementioned integrated circuit element 100.

[0071] Referring to both FIGS. 8 and 9, the integrated circuit element 200 includes a cell array structure CS and a peripheral circuit structure PS that overlap each other in the vertical direction.

[0072] In the integrated circuit element 200 of the present embodiment, a channel hole 130H and a channel adjacent hole 133H that penetrate a plurality of gate electrodes 120 and a plurality of mold insulating layers 122 and extend in the vertical direction can be formed. Here, the channel structure 130 can be disposed within the channel hole 130H. The channel structure 130 can include a gate insulating layer 132, a channel layer 134, a buried insulating layer 136, and a conductive plug 138. The gate insulating layer 132, the channel layer 134, and the buried insulating layer 136 can be sequentially disposed on the inner wall of the channel hole 130H.

[0073] In some embodiments, the gate insulating layer 132 can be arranged to conformally cover the channel layer 134 but open (i.e., not cover) a part 134P of the uppermost surface of the channel layer 134. Also, in some embodiments, the plurality of gate electrodes 120 facing the channel hole 130H and the channel adjacent hole 133H, and the plurality of mold insulating layers 122 can have substantially the same thickness in the same vertical direction.

[0074] In one embodiment, at the second end of the channel structure 130, the end of the channel layer 134 is in a square shape protruding in the horizontal direction, and the end of the gate insulating layer 132 corresponding to the end of the channel layer 134 is conformally formed along the protruding square shape and may have a right-angled side wall protruding in the horizontal direction.

[0075] The gate insulating layer 132 may have a structure including a tunneling dielectric film 132A, a charge resistance film 132B, and a blocking dielectric film 132C in sequence on the outer wall of the channel layer 134. The relative thicknesses of the tunneling dielectric film 132A, the charge resistance film 132B, and the blocking dielectric film 132C forming the gate insulating layer 132 are not limited to what is shown and may be variously deformed.

[0076] The common source line structure 110 may be connected to the open channel layer 134 of the channel structure 130 on the gate stack GS and may be formed to cover the upper surface of the stack isolation insulating layer WLI. In a plan view, the common source line structure 110 may be disposed over the entire region of the cell region MCR. The common source line structure 110 may include doped polysilicon.

[0077] In one embodiment, the common source line structure 110 may fill the channel adjacent hole 133H and directly contact a part 134P of the uppermost surface of the channel layer 134 opened by the gate insulating layer 132. In the channel adjacent hole 133H, a protruding insulating pattern 113 is disposed on the side wall of the gate electrode 120 facing the side wall of the common source line structure 110.

[0078] In one embodiment, the protruding insulating pattern 113 is formed in a semi-circular shape and has a round side wall protruding inside the channel adjacent hole 133H, and the common source line structure 110 may have a round side wall recessed in a region corresponding to the protruding insulating pattern 113. That is, in the channel adjacent hole 133H, the common source line structure 110 may be formed in an hourglass shape.

[0079] In one embodiment, within the channel hole 130H, the common source line structure 110 contacts the sidewall of the gate insulating layer 132, and within the channel adjacent hole 133H, the common source line structure 110 may contact the protruding insulating pattern 113 and the mold insulating layer 122. Further, the common source line structure 110 may directly contact the uppermost surface of the blocking dielectric film 132C.

[0080] In one embodiment, the width W3 of the portion of the common source line structure 110 located within the channel adjacent hole 133H may be wider than the first width W1 of the portion located within the channel hole 130H. That is, as shown in the drawing, the sidewall of the common source line structure 110 disposed inside the gate stack GS may be formed in a stepped shape.

[0081] FIGS. 10 to 18 are cross-sectional views showing a method of manufacturing an integrated circuit element according to an embodiment of the technical idea of the present invention in the order of steps.

[0082] For convenience of explanation and understanding, the manufacturing process related to the CX1S portion in FIG. 6 will be mainly described.

[0083] Referring to FIG. 10, a plurality of mold insulating layers 122 and a plurality of mold sacrificial layers 120M may be alternately formed on the sacrificial substrate 101.

[0084] In one embodiment, the plurality of mold insulating layers 122 may include insulating materials such as silicon oxide and silicon oxynitride, and the plurality of mold sacrificial layers 120M may include silicon nitride, silicon oxynitride, polysilicon, or the like.

[0085] Next, a first sacrificial layer 103 and a second sacrificial layer 105 may be formed through the plurality of mold insulating layers 122 and the plurality of mold sacrificial layers 120M on the upper surface of the sacrificial substrate 101. For example, the first sacrificial layer 103 may be formed of polysilicon, and the second sacrificial layer 105 may be formed of tungsten (W).

[0086] In one embodiment, the width of the first sacrificial layer 103 along the horizontal direction and the width of the second sacrificial layer 105 along the horizontal direction may be the same as each other. Also, the thickness of the second sacrificial layer 105 along the vertical direction may be greater than the thickness of the first sacrificial layer 103 along the vertical direction. However, the relative thicknesses of the first sacrificial layer 103 and the second sacrificial layer 105 along the vertical direction are not limited to what is shown in the drawing and can be variously deformed.

[0087] Referring to FIG. 11, a plurality of mold insulating layers 122 and a plurality of mold sacrificial layers 120M can be alternately formed on the second sacrificial layer 105.

[0088] Covering the second sacrificial layer 105, a plurality of mold insulating layers 122 and a plurality of mold sacrificial layers 120M can be formed by adding up to the number of layers required by the vertical memory element to be formed.

[0089] Referring to FIG. 12, a mask pattern (not shown) can be formed, and using the mask pattern as an etching mask, a plurality of mold insulating layers 122 and a plurality of mold sacrificial layers 120M can be patterned.

[0090] The second sacrificial layer 105 (FIG. 11) can be used as an etching stop film to perform the patterning. Next, all of the second sacrificial layer 105 (FIG. 11) exposed by the patterning can be removed to form a channel hole 130H.

[0091] Referring to FIG. 13, a channel structure 130 (FIG. 7) including a gate insulating layer 132, a channel layer 134, an embedded insulating layer 136, and a conductive plug 138 (FIG. 6) can be formed on the inner wall of the channel hole 130H.

[0092] In one embodiment, at the end of the channel structure 130 (FIG. 7), the end of the channel layer 134 can be in a rectangular shape protruding in the horizontal direction, and the end of the gate insulating layer 132 corresponding to the end of the channel layer 134 is conformally formed along the protruding rectangular shape and can have a right-angled side wall protruding in the horizontal direction.

[0093] Referring to FIG. 14, a mask pattern (not shown) can be formed, and the mask pattern can be used as an etching mask to remove a part of the plurality of mold insulating layers 122 and the plurality of mold sacrificial layers 120M (FIG. 13) to form a stack separation opening WLH (FIG. 6).

[0094] Thereby, the plurality of mold sacrificial layers 120M (FIG. 13) can be exposed on the inner wall of the stack separation opening WLH (FIG. 6). Next, the plurality of mold sacrificial layers 120M (FIG. 13) exposed on the side wall of the stack separation opening WLH (FIG. 6) can be removed to form a plurality of gate spaces. Next, a conductive material can be embedded in the plurality of gate spaces to form a plurality of gate electrodes 120.

[0095] Referring to FIG. 15, the sacrificial substrate 101 (FIG. 14) on which the plurality of gate electrodes 120 are formed can be turned upside down.

[0096] Next, both the sacrificial substrate 101 (FIG. 14) and the first sacrificial layer 103 (FIG. 14) can be removed to form a channel adjacent hole 131H on the channel hole 130H. In other words, a channel hole 130H and a channel adjacent hole 131H that penetrate the plurality of gate electrodes 120 and the plurality of mold insulating layers 122 and extend in the vertical direction can be formed.

[0097] Referring to FIG. 16, an insulating pattern layer 112 can be conformally formed on the uppermost mold insulating layer 122.

[0098] Specifically, the insulating pattern layer 112 can conformally cover the upper surface of the uppermost mold insulating layer 122, the inner wall of the channel adjacent hole 131H, and the uppermost surface of the blocking dielectric film 132C. The insulating pattern layer 112 can include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0099] Next, a mask pattern (not shown) is formed, and the mask pattern is used as an etching mask to remove a portion of the insulating pattern layer 112 within the channel adjacent hole 131H, so that a portion of the uppermost surface of the gate insulating layer 132 can be opened.

[0100] Referring to FIG. 17, a portion 134P of the uppermost surface of the channel layer 134 corresponding to a portion of the uppermost surface of the gate insulating layer 132 opened by the insulating pattern layer 112 can be opened.

[0101] In some embodiments, the channel layer 134 can be used as an etching stop film, and by etching a portion of the uppermost surface of the gate insulating layer 132 opened by the insulating pattern layer 112, a portion 134P of the uppermost surface of the channel layer 134 can be opened.

[0102] Referring to FIG. 18, a common source line structure 110 can be formed to cover the insulating pattern layer 112 and contact a portion 134P of the uppermost surface of the channel layer 134.

[0103] In plan view, the common source line structure 110 can be disposed over the entire region of the cell region MCR (FIG. 6). The common source line structure 110 can include doped polysilicon.

[0104] In some embodiments, the common source line structure 110 can fill the channel adjacent hole 131H and directly contact a portion 134P of the uppermost surface of the channel layer 134 opened by the gate insulating layer 132 and the insulating pattern layer 112.

[0105] Referring again to FIG. 6, an upper insulating layer 142 and a conductive via 144 are formed on the common source line structure 110, and a passivation layer 162 and a wiring line 164 are formed on the upper insulating layer 142, whereby the integrated circuit element 100 according to the present invention can be completed.

[0106] FIGS. 19 to 23 are cross-sectional views showing a method of manufacturing an integrated circuit element according to another embodiment of the technical idea of the present invention in the order of steps.

[0107] For convenience of explanation and understanding, the manufacturing process related to the CX2S portion in FIG. 8 will be mainly described. In addition, the method of forming most of the components included in the method of manufacturing the integrated circuit element 200 described below is substantially the same as or similar to that described in FIGS. 10 to 18 previously. Therefore, the description will focus on the differences from the method of manufacturing the above-described integrated circuit element 100.

[0108] Referring to FIG. 19, a mask pattern (not shown) is formed, and the mask pattern is used as an etching mask to remove a part of a plurality of mold insulating layers 122 and a plurality of mold sacrificial layers (not shown), whereby a stack separation opening WLH (FIG. 8) can be formed.

[0109] Thereby, a plurality of mold sacrificial layers (not shown) can be exposed on the inner wall of the stack separation opening WLH (FIG. 8). Next, a plurality of mold sacrificial layers (not shown) exposed on the side walls of the stack separation opening WLH (FIG. 8) are removed, whereby a plurality of gate spaces can be formed. Next, a conductive material is embedded in the plurality of gate spaces, whereby a plurality of gate electrodes 120 can be formed.

[0110] Referring to FIG. 20, a wet oxidation process is advanced, and a protruding insulating pattern 113 can be formed inside the first sacrificial layer 103 in contact with the gate electrode 120.

[0111] In one embodiment, the protruding insulating pattern 113 formed at the end of the gate electrode 120 by the wet oxidation process may be formed in a semi-circular shape having a round sidewall protruding into the first sacrificial layer 103. Thereby, the first sacrificial layer 103 may have a round sidewall recessed in a region corresponding to the protruding insulating pattern 113.

[0112] Referring to FIG. 21, the sacrificial substrate 101 (FIG. 20) on which the protruding insulating pattern 113 is formed can be turned upside down.

[0113] Next, both the sacrificial substrate 101 (FIG. 20) and the first sacrificial layer 103 (FIG. 20) can be removed, and channel adjacent holes 133H can be formed on the channel hole 130H. In other words, channel holes 130H and channel adjacent holes 133H extending in the vertical direction can be formed through the plurality of gate electrodes 120 and the plurality of mold insulating layers 122.

[0114] Referring to FIG. 22, a part of the uppermost surface of the gate insulating layer 132 opened by the channel adjacent holes 133H can be etched to open a part 134P of the uppermost surface of the channel layer 134.

[0115] In one embodiment, a mask pattern (not shown) can be formed, and the mask pattern can be used as an etching mask to remove a part of the gate insulating layer 132 in the channel adjacent holes 133H to open a part 134P of the uppermost surface of the channel layer 134.

[0116] Referring to FIG. 23, a common source line structure 110 can be formed to cover the uppermost mold insulating layer 122 and contact a part 134P of the uppermost surface of the channel layer 134.

[0117] In plan view, the common source line structure 110 can be disposed over the entire region of the cell region MCR (FIG. 8). The common source line structure 110 may include doped polysilicon.

[0118] In one embodiment, the common source line structure 110 may fill the channel adjacent hole 133H and be in direct contact with a top portion 134P of the channel layer 134 opened by the gate insulating layer 132.

[0119] Referring to FIG. 8 again, an upper insulating layer 142 and a conductive via 144 may be formed on the common source line structure 110, and a passivation layer 162 and a wiring line 164 may be formed on the upper insulating layer 142, thereby completing the integrated circuit element 200 according to the present invention.

[0120] FIG. 24 is a drawing showing an electronic system including an integrated circuit element according to an embodiment of the technical idea of the present invention.

[0121] Referring to FIG. 24, the electronic system 1000 according to the present invention may include an integrated circuit element 1100 and a controller 1200 electrically connected to the integrated circuit element 1100.

[0122] The electronic system 1000 may be a storage device including the integrated circuit element 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive device (SSD device) including at least one integrated circuit element 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0123] The integrated circuit element 1100 can be a non-volatile vertical memory element. For example, the integrated circuit element 1100 can be a NAND flash memory element including at least one of the integrated circuit elements 100 and 200 described with reference to FIGS. 3 to 9 above. The integrated circuit element 1100 can include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be arranged beside the second structure 1100S. The first structure 1100F can be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S can be a memory cell array structure including bit lines BL, a common source line CSL, a plurality of word lines WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a plurality of memory cell strings CSTR between the bit lines BL and the common source line CSL.

[0124] In the second structure 1100S, the plurality of memory cell strings CSTR can each include lower transistors LT1, LT2 adjacent to the common source line CSL, upper transistors UT1, UT2 adjacent to the bit lines BL, and a plurality of memory cell transistors MCT arranged between the lower transistors LT1, LT2 and the upper transistors UT1, UT2. The number of the lower transistors LT1, LT2 and the number of the upper transistors UT1, UT2 can vary diversely according to embodiments.

[0125] In some embodiments, the upper transistors UT1, UT2 can include string selection transistors, and the lower transistors LT1, LT2 can include ground selection transistors. The plurality of gate lower lines LL1, LL2 are also the gate electrodes of the lower transistors LT1, LT2 respectively. The word line WL is also the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1, UL2 are also the gate electrodes of the upper transistors UT1, UT2.

[0126] The common source line CSL, the plurality of lower gate lines LL1, LL2, the plurality of word lines WL, and the plurality of upper gate lines UL1, UL2 can be electrically connected to the decoder circuit 1110 via a plurality of first connection wirings 1115 that extend to the second structure 1100S within the first structure 1100F. The plurality of bit lines BL can be electrically connected to the page buffer 1120 via a plurality of second connection wirings 1125 that extend to the second structure 1100S within the first structure 1100F.

[0127] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for at least one of the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130.

[0128] The integrated circuit element 1100 can communicate with the controller 1200 via the input / output pad 1101 that is electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 via the input / output connection wiring 1135 that extends to the second structure 1100S within the first structure 1100F.

[0129] The controller 1200 can include a processor 1210, a NAND controller 1220, and a host interface 1230. In some embodiments, the electronic system 1000 can include a plurality of integrated circuit elements 1100, in which case the controller 1200 can control the plurality of integrated circuit elements 1100.

[0130] Processor 1210 can control the overall operation of the electronic system 1000 including the controller 1200. Processor 1210 operates according to a predetermined firmware, can control the NAND controller 1220, and access the integrated circuit element 1100. The NAND controller 1220 may include a NAND interface 1221 for processing communication with the integrated circuit element 1100. Through the NAND interface 1221, control commands for controlling the integrated circuit element 1100, data to be recorded in the plurality of memory cell transistors MCT of the integrated circuit element 1100, data to be read from the plurality of memory cell transistors MCT of the integrated circuit element 1100, etc. can be transmitted. The host interface 1230 can provide a communication function between the electronic system 1000 and an external host. When receiving a control command from the external host through the host interface 1230, the processor 1210 can control the integrated circuit element 1100 in response to the control command.

[0131] FIG. 25 is a perspective view showing an electronic system including an integrated circuit element according to an embodiment of the technical idea of the present invention.

[0132] Referring to FIG. 25, an electronic system 2000 according to an embodiment of the present invention may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM (dynamic random access memory) 2004. The semiconductor package 2003 and the DRAM 2004 can be interconnected with the controller 2002 by a plurality of wiring patterns 2005 formed on the main board 2001.

[0133] The main board 2001 may include a connector 2006 that includes a plurality of pins for coupling to an external host. In the connector 2006, the number and arrangement of the plurality of pins may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host by any one of interfaces such as USB, PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In some embodiments, the electronic system 2000 may operate by power supplied from the external host via the connector 2006. The electronic system 2000 may further include a PMIC (power management integrated circuit) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0134] The controller 2002 can record data in the semiconductor package 2003 or read data from the semiconductor package 2003, and can improve the operating speed of the electronic system 2000.

[0135] The DRAM 2004 is also a buffer memory for alleviating the speed difference between the semiconductor package 2003, which is a data storage space, and the external host. The DRAM 2004 included in the electronic system 2000 also operates as a kind of cache memory and can provide a space for temporarily storing data in the control operation for the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0136] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b that are separated from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b can be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 that electrically connects the plurality of semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 that covers the plurality of semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0137] The package substrate 2100 can be a printed circuit board including a plurality of package upper pads 2130. Each of the plurality of semiconductor chips 2200 may include input / output pads 2201. The input / output pads 2201 may correspond to the input / output pads 1101 (FIG. 24). Each of the plurality of semiconductor chips 2200 can include at least one of the integrated circuit elements 100, 200 described above with reference to FIGS. 3 to 9.

[0138] In some embodiments, the connection structure 2400 can be bonding wires that electrically connect the input / output pads 2201 and the package upper pads 2130. Accordingly, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 can be electrically connected to each other in a bonding wire manner and can be electrically connected to the package upper pads 2130 of the package substrate 2100. In some embodiments, in the first semiconductor package 2003a and the second semiconductor package 2003b, the plurality of semiconductor chips 2200 may be electrically connected to each other by a connection structure including TSV (through silicon via) instead of the bonding wire type connection structure 2400.

[0139] In one embodiment, the controller 2002 and the plurality of semiconductor chips 2200 may be included in one package. In some embodiments, the controller 2002 and the plurality of semiconductor chips 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the plurality of semiconductor chips 2200 may be connected to each other by wiring formed on the interposer substrate.

[0140] FIG. 26 is a cross-sectional view showing a semiconductor package including an integrated circuit element according to an embodiment of the technical idea of the present invention.

[0141] Referring to FIG. 26, in the semiconductor package 2003, the package substrate 2100 can be a printed circuit board.

[0142] The package substrate 2100 may include a body portion 2120, package upper pads 2130 (FIG. 25) disposed on the upper surface of the body portion 2120, package lower pads 2125 disposed on the lower surface of the body portion 2120 or exposed through the lower surface, and internal wirings 2135 that electrically connect the package upper pads 2130 (FIG. 25) and the package lower pads 2125 inside the body portion 2120.

[0143] The plurality of lower pads 2125 can be connected to a plurality of wiring patterns 2005 on the main substrate 2001 (FIG. 25) via a plurality of conductive bumps 2800. Each of the plurality of semiconductor chips 2200 can include at least one of the integrated circuit elements 100 and 200 described above with reference to FIGS. 3 to 9.

[0144] As described above, embodiments of the technical idea of the present invention have been described with reference to the accompanying drawings. However, those having ordinary knowledge in the technical field to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Explanation of Symbols

[0145] 10,100,200 integrated circuit element 110 common source line structure 112 insulating pattern layer 120 gate electrode 122 molding insulation layer 130 channel structure 130H channel hole 131H, 133H channel adjacent holes 132 gate insulation layer 134 channel layer 136 buried insulation layer 138 conductive plug 142 upper insulation layer 144 conductive via 152 connecting via 154 connecting wiring layer 156 interlayer insulation film 162 passivation layer 164 wiring line

Claims

1. a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure; The cell array structure includes: a gate stack including a plurality of gate electrodes extending in a horizontal direction and stacked in a vertical direction in an alternating manner and a plurality of mold insulating layers; a channel hole and a channel adjacent hole extending in the vertical direction through the gate stack and connected to each other; a channel structure disposed in the channel hole, the channel structure including a channel layer and a gate insulating layer conformally covering the channel layer but leaving a portion of a top surface of the channel layer open; an insulating pattern layer conformally covering a top surface of the gate stack, an inner wall of the channel adjacent hole, and a top surface of the gate insulating layer, but leaving the portion of the top surface of the channel layer open; a common source line structure filling the channel adjacent hole and contacting the portion of the top surface of the channel layer opened by the gate insulating layer and the insulating pattern layer; 11. An integrated circuit device comprising: a common source line structure disposed within the gate stack, the common source line structure having a sidewall that is stepped.

2. One end of the channel layer has a rectangular shape protruding in the horizontal direction, 2. The integrated circuit device of claim 1, wherein one end of the gate insulating layer corresponding to the one end of the channel layer is conformally formed along the protruding rectangular shape and has a right-angled sidewall protruding in the horizontal direction.

3. the gate insulating layer includes a tunneling dielectric layer, a charge resistive layer, and a blocking dielectric layer, which are sequentially formed on an outer wall of the channel layer; 3. The integrated circuit device of claim 2, wherein a bottom surface of the insulating pattern layer contacts the blocking dielectric film.

4. In the channel hole, the common source line structure contacts a sidewall of the gate insulating layer; 2. The integrated circuit device of claim 1, wherein in said channel adjacent hole, said common source line structure contacts a sidewall of said insulating pattern layer.

5. 5. The integrated circuit device of claim 4, wherein a sidewall of said gate insulating layer in contact with said common source line structure and a sidewall of said insulating pattern layer in contact with said common source line structure are coplanar.

6. the common source line structure fills the channel adjacent hole; 2. The integrated circuit device of claim 1, wherein the common source line structure is formed over the insulating pattern layer and on top of the gate stack.

7. 7. The integrated circuit device of claim 6, wherein a bottom surface of the common source line structure is located within the channel hole.

8. 8. The integrated circuit device of claim 7, wherein the vertical level of the top surface of the channel layer and the vertical level of the bottom surface of the common source line structure are substantially the same.

9. 9. The integrated circuit device of claim 8, wherein a second width of the common source line structure located in the channel adjacent hole is wider than a first width of the common source line structure located in the channel hole.

10. a peripheral circuit structure and a cell array structure disposed on the peripheral circuit structure; The cell array structure includes: a gate stack including a plurality of gate electrodes extending in a horizontal direction and stacked in a vertical direction in an alternating manner and a plurality of mold insulating layers; a channel hole and a channel adjacent hole extending in the vertical direction through the gate stack and connected to each other; a channel structure disposed in the channel hole, the channel structure including a channel layer and a gate insulating layer conformally covering the channel layer but leaving a portion of a top surface of the channel layer open; a common source line structure filling the channel adjacent hole and contacting the portion of the top surface of the channel layer opened by the gate insulating layer; an insulating protruding pattern is disposed on a sidewall of a gate electrode facing a sidewall of the common source line structure in the channel adjacent hole;

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