Semiconductor device manufacturing method

Abstract

To suppress an increase in manufacturing costs, and improve the reliability of a semiconductor device.SOLUTION: An amorphous silicon film (AM1) is formed on a semiconductor substrate SUB located in regions 1A to 4A. The silicon film (AM1) located in the regions 1A and 4A is removed such that the silicon film (AM1) located in the regions 2A and 3A remains. The silicon film (AM1) is crystallized by heat treatment to form a polycrystalline silicon film PL1.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a ferroelectric memory cell.

Background Art

[0002] In recent years, as a semiconductor memory element that operates at a low voltage, a ferroelectric memory cell using a ferroelectric film has been developed. The ferroelectric memory cell is a non-volatile memory cell that changes the write state and the erase state by controlling the direction of polarization of the ferroelectric.

[0003] Patent Document 1 discloses a semiconductor device in which a ferroelectric memory cell and a MISFET (Metal Insulator Semiconductor Field Effect Transistor) constituting a logic circuit are mounted together.

[0004] In the manufacturing method disclosed in Patent Document 1, first, a gate insulating film is formed on a semiconductor substrate in a memory cell region and a peripheral region located around the memory cell region, respectively. Next, a ferroelectric film is formed on each gate insulating film. Next, a titanium nitride film is formed on the ferroelectric film. Next, the titanium nitride film and the ferroelectric film located in the peripheral region are selectively removed. Next, a polycrystalline silicon film is formed on the titanium nitride film in the memory cell region and a polycrystalline silicon film is formed on the gate insulating film in the peripheral region. These polycrystalline silicon films are formed for use as gate electrodes of the ferroelectric memory cell and the MISFET.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a ferroelectric memory cell, when forming a silicon film on a titanium nitride film, conventionally, a polycrystalline silicon film is formed at a film formation temperature of about 600 degrees Celsius by a film formation process using the CVD (Chemical Vapor Deposition) method. However, in that case, it has been clarified by the study of the inventors of the present application that abnormal growth of the polycrystalline silicon film easily occurs on the titanium nitride film. Therefore, the inventors of the present application considered forming an amorphous silicon film at a temperature lower than the film formation temperature of the polycrystalline silicon film instead of the polycrystalline silicon film.

[0007] On the other hand, in the peripheral region, as semiconductor elements other than MISFETs, resistance elements and the like are also formed. The silicon film constituting the resistance element is formed by the same manufacturing process as the silicon film of the ferroelectric memory cell and the silicon film of the MISFET. Here, considering the abnormal growth of the polycrystalline silicon film, it was found that when forming a resistance element with an amorphous silicon film, the characteristics of the resistance element fluctuate. Specifically, it was found that the sheet resistance of the resistance element becomes lower than the sheet resistance when formed with a polycrystalline silicon film in advance. Therefore, there is a need for a technology that can improve the reliability of a semiconductor device by suppressing abnormal growth in a ferroelectric memory cell and suppressing characteristic fluctuations of a resistance element.

[0008] For example, it is conceivable to form an amorphous silicon film in the memory cell region and the peripheral region and adjust the sheet resistance by dose splitting of ion implantation. Specifically, by performing first ion implantation on the silicon film located in the memory cell region and performing second ion implantation on the silicon film located in the peripheral region with a dose amount lower than the dose amount of the first ion implantation, a decrease in the sheet resistance of the resistance element can be suppressed.

[0009] However, the number of manufacturing processes and masks for performing ion implantation increases, and the manufacturing cost increases. Further, when forming two types of resistance elements, p-type and n-type, the number of manufacturing processes and masks further increases.

[0010] In addition, when ion implantation is not performed, it is also conceivable to separately form an amorphous silicon film for a ferroelectric memory cell and a polycrystalline silicon film for a resistance element. In that case, it is necessary to selectively leave only the amorphous silicon film in the memory cell region and only the polycrystalline silicon film in the peripheral region. Therefore, since the formation and patterning of the silicon film are repeated, the manufacturing process and the number of masks increase, and the manufacturing cost increases.

[0011] Therefore, there is a need for a technology that can suppress an increase in manufacturing cost and improve the reliability of a semiconductor device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0012] Among the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

[0013] A method for manufacturing a semiconductor device according to an embodiment includes a step of forming a first amorphous silicon film on the semiconductor substrate located in a first region and a second region, a step of removing the first silicon film located in the first region, a step of forming a first polycrystalline silicon film by crystallizing the first silicon film by a first heat treatment, a step of forming a ferroelectric film on the semiconductor substrate located in the first region and on the first polycrystalline silicon film located in the second region, a step of forming a metal film on the ferroelectric film, a step of removing the metal film and the ferroelectric film located in the second region, and a step of forming a second silicon film on the metal film located in the first region and on the first polycrystalline silicon film located in the second region.

Advantages of the Invention

[0014] According to one embodiment, an increase in manufacturing cost can be suppressed, and the reliability of a semiconductor device can be improved.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0017] (Embodiment 1) <Method for Manufacturing a Semiconductor Device> The semiconductor device has a region 1A and regions 2A, 3A, and 4A located around the region 1A. First, with reference to FIGS. 23 and 24, the semiconductor elements formed in each region will be described.

[0018] As shown in FIG. 23, in region 1A, a ferroelectric memory cell MC is formed as a semiconductor element. The ferroelectric memory cell MC is an electrically rewritable non-volatile memory cell and includes a memory transistor MQ and a selection transistor 1Q. The memory transistor MQ has a ferroelectric film FE, and can change the write state and the erase state by controlling the direction of polarization of the ferroelectric film FE. The selection transistor 1Q controls the supply of the write voltage, the erase voltage, and the read voltage to the drain region of the memory transistor MQ when the ferroelectric memory cell MC is selected and not selected.

[0019] In region 2A, a plurality of MISFETs are formed as semiconductor elements. The plurality of MISFETs include a plurality of n-type and p-type high-voltage-resistant MISFETs and a plurality of n-type and p-type low-voltage-resistant MISFETs. The plurality of high-voltage-resistant MISFETs constitute, for example, part of an I / O circuit. The low-voltage-resistant MISFETs are driven at a voltage lower than that of the high-voltage-resistant MISFETs and have a gate insulating film with a smaller thickness than the gate insulating film for the high-voltage-resistant MISFETs. The plurality of low-voltage-resistant MISFETs constitute, for example, a logic circuit including a CPU and an SRAM. In FIG. 23, an n-type high-voltage-resistant MISFET is exemplified as an example of the MISFETs formed in region 2A.

[0020] As shown in FIG. 24, in region 3A, a plurality of resistance elements RS1 are formed as semiconductor elements. The polycrystalline silicon film PL1 and the polycrystalline silicon film PL2 formed in region 3A function as the resistance element RS1. An n-type or p-type impurity is introduced into the polycrystalline silicon film PL1 and the polycrystalline silicon film PL2. In FIG. 24, a resistance element RS1 including an n-type polycrystalline silicon film PL1 and an n-type polycrystalline silicon film PL2 is exemplified as an example of the resistance elements formed in region 3A.

[0021] In region 4A, a plurality of resistor elements RS2 are formed as semiconductor elements. The polycrystalline silicon film PL3 formed in region 4A functions as the resistor element RS2. The polycrystalline silicon film PL3 has n-type or p-type impurities introduced therein. In FIG. 24, as an example of the resistor element formed in region 4A, a resistor element RS2 including an n-type polycrystalline silicon film PL3 is illustrated.

[0022] Hereinafter, each manufacturing process included in the method for manufacturing a semiconductor device according to Embodiment 1 will be described with reference to FIGS. 1 to 24.

[0023] As shown in FIGS. 1 and 2, first, a semiconductor substrate SUB made of single-crystalline silicon into which, for example, p-type impurities are introduced is prepared. Next, an n-type well region DNW is formed in the semiconductor substrate SUB located in regions 1A to 4A by photolithography technology and ion implantation.

[0024] Next, a plurality of grooves are formed in the semiconductor substrate SUB located in regions 1A to 4A by photolithography and anisotropic etching. Next, an insulating film IF1 is formed so as to fill the inside of the plurality of grooves by a film formation process using, for example, CVD. Next, the insulating film IF1 located outside the plurality of grooves is removed by a polishing process using CMP (Chemical Mechanical Polishing). The insulating film IF1 functions as an element isolation part that isolates the semiconductor elements formed in each region. Note that the depth of the groove is, for example, 300 nm or more and 400 nm or less.

[0025] Next, a p-type well region PW1 is formed in the semiconductor substrate SUB located in region 1A, a p-type well region PW2 is formed in the semiconductor substrate SUB located in region 2A, and a p-type well region PW3 is formed in the semiconductor substrate SUB located in regions 3A and 4A by photolithography technology and ion implantation.

[0026] Also, although not shown in the drawings, an n-type well region is formed by introducing an n-type impurity such as arsenic or phosphorus into a semiconductor substrate SUB in which a p-type MISFET is formed in region 2A by photolithography technology and ion implantation method.

[0027] As shown in FIGS. 3 and 4, a gate insulating film GI3 is formed on the semiconductor substrate SUB located from region 1A to region 4A, for example, by thermal oxidation treatment. The gate insulating film GI3 is, for example, a silicon oxide film and has a thickness of, for example, 8 nm or more and 10 nm or less.

[0028] Next, an amorphous silicon film AM1 is formed on the semiconductor substrate SUB located from region 1A to region 4A via the gate insulating film GI3 or the insulating film IF1. The silicon film AM1 is formed, for example, by a film-forming process using the CVD method and is formed within a temperature range of 400 degrees Celsius or more and 550 degrees Celsius or less. The thickness of the silicon film AM1 is, for example, 15 nm or more and 30 nm or less.

[0029] When the thickness of the silicon film AM1 is relatively thin, such as 30 nm or less, the silicon film AM1 is formed in an amorphous state without crystallization even if the temperature of the film-forming process is 600 degrees Celsius or more.

[0030] As shown in FIGS. 5 and 6, the silicon film AM1 located in regions 1A and 4A is removed so that the silicon film AM1 located in regions 2A and 3A remains.

[0031] First, a resist pattern RP1 is formed on the silicon film AM1. The resist pattern RP1 has a pattern that selectively covers the silicon film AM1 located in the regions 2A and 3A. Next, by performing an anisotropic etching process using the resist pattern RP1 as a mask, the silicon film AM1 exposed from the resist pattern RP1 is removed. Next, by performing an isotropic etching process using the resist pattern RP1 as a mask, the gate insulating film GI3 exposed from the resist pattern RP1 is removed. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0032] As shown in FIGS. 7 and 8, first, for example, by thermal oxidation treatment, a gate insulating film GI2 is formed on the semiconductor substrate SUB located in the region 1A, on the silicon film AM1 located in the region 2A, and on the silicon film AM1 located in the region 3A. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness of, for example, 5 nm or more and 7 nm or less. Next, a resist pattern RP2 is formed on a part of the gate insulating film GI2 located in the region 1A. Next, by performing an isotropic etching process using the resist pattern RP2 as a mask, the gate insulating film GI2 exposed from the resist pattern RP2 is removed. Thereafter, the resist pattern RP2 is removed by an ashing process.

[0033] The portion of the region 1A where the gate insulating film GI2 remains is used for the select transistor 1Q. The portion of the region 1A where the gate insulating film GI2 is removed and the semiconductor substrate SUB is exposed is used for the memory transistor MQ. Also, in the regions 2A and 3A, although the silicon film AM1 is exposed, the thickness of the silicon film AM1 is reduced by the amount of the gate insulating film GI2 that was formed.

[0034] As shown in FIGS. 9 and 10, a polycrystalline silicon film PL1 is formed by crystallizing a silicon film AM1 through heat treatment. This heat treatment is carried out in a nitrogen atmosphere within a temperature range of 800 degrees Celsius or higher and 1000 degrees Celsius or lower, and within a time range of 10 seconds or longer and 100 seconds or shorter. At this point, the thickness of the polycrystalline silicon film PL1 is preferably 20 nm or less.

[0035] As shown in FIGS. 11 and 12, first, a gate insulating film GI1 is formed on a semiconductor substrate SUB located in region 1A, on a polycrystalline silicon film PL1 located in region 2A, and on a polycrystalline silicon film PL1 located in region 3A by a thermal oxidation treatment using an ISSG (In Situ Steam Generation) oxidation method. The gate insulating film GI1 is, for example, a silicon oxide film and has a thickness of, for example, 1 nm or more and 5 nm or less.

[0036] Next, for example, by a film formation process using an ALD (Atomic Layer Deposition) method, a ferroelectric film FE is formed on a semiconductor substrate SUB located in region 1A via a gate insulating film GI1 or a gate insulating film GI2, a ferroelectric film FE is formed on a polycrystalline silicon film PL1 located in regions 2A and 3A via a gate insulating film GI1, and a ferroelectric film FE is formed on a semiconductor substrate SUB located in region 4A via an insulating film IF1. Note that at this point, the ferroelectric film FE is in an amorphous state.

[0037] The ferroelectric film FE is an HfO2 film or an HfO2 film with at least one of zirconium (Zr), silicon (Si), nitrogen (N), carbon (C), and aluminum (Al) added. The thickness of the ferroelectric film FE is, for example, 4 nm or more and 20 nm or less.

[0038] Next, for example, by a film formation process using a CVD method or a sputtering method, a metal film MF is formed on the ferroelectric film FE located in regions 1A to 4A. The metal film MF is, for example, a titanium nitride film. The thickness of the metal film MF is, for example, 10 nm or more and 20 nm or less.

[0039] Next, the ferroelectric film FE is crystallized by heat treatment to form a ferroelectric film FE with a rectangular crystal. This heat treatment is performed within a temperature range of 400 degrees Celsius or higher and 600 degrees Celsius or lower. Here, the metal film MF applies stress to the ferroelectric film FE during the heat treatment and controls the crystal orientation of the ferroelectric film FE. That is, the metal film MF has a function of orienting the crystal phase of the ferroelectric film FE to a rectangular crystal.

[0040] As shown in FIGS. 13 and 14, the metal film MF and the ferroelectric film FE located in regions 2A to 4A are removed so that the metal film MF and the ferroelectric film FE located in region 1A remain.

[0041] First, a resist pattern RP3 is formed on the metal film MF. The resist pattern RP3 has a pattern that selectively covers the metal film MF located in region 1A. Next, anisotropic etching treatment is performed using the resist pattern RP3 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the resist pattern RP3. Thereafter, the resist pattern RP3 is removed by ashing treatment.

[0042] In the anisotropic etching treatment, over-etching is performed so that the metal film MF and the ferroelectric film FE located in regions 2A to 4A are surely removed. This over-etching also removes the gate insulating film GI1 formed on the polycrystalline silicon film PL1 in regions 2A and 3A. Also, the thickness of the polycrystalline silicon film PL1 is reduced by the amount of the gate insulating film GI1 formed.

[0043] The polycrystalline silicon film PL1 functions as a protective film for protecting the gate insulating film GI2 located in region 2A from the over-etching.

[0044] Here, the reason why the thickness of the polycrystalline silicon film PL1 is preferably 20 nm or less at the time points of FIGS. 9 and 10 will be described. The metal film MF and the ferroelectric film FE are formed not only on the upper surface of the polycrystalline silicon film PL1 but also on the side surfaces of the polycrystalline silicon film PL1. Therefore, the greater the thickness of the polycrystalline silicon film PL1, the greater the step, and the higher the height of the metal film MF and the ferroelectric film FE formed on the side surfaces of the polycrystalline silicon film PL1.

[0045] Then, even after removing the metal film MF and the ferroelectric film FE formed on the upper surface of the polycrystalline silicon film PL1, it becomes difficult to completely remove the metal film MF and the ferroelectric film FE formed on the side surfaces of the polycrystalline silicon film PL1. Therefore, in order to reduce such a step and make it easier to completely remove the metal film MF and the ferroelectric film FE, the thickness of the polycrystalline silicon film PL1 is preferably as small as possible, and preferably 20 nm or less.

[0046] Also, considering the purpose of making the polycrystalline silicon film PL1 function as a protective film for the gate insulating film GI2, the polycrystalline silicon film PL1 may not be formed in the region 3A. Further, after removing the metal film MF and the ferroelectric film FE, the polycrystalline silicon film PL1 located in the regions 2A and 3A may be removed.

[0047] In Embodiment 1, the polycrystalline silicon film PL1 is deliberately formed in the region 3A, and the polycrystalline silicon film PL1 is left in the regions 2A and 3A. The reason for this will be described in detail later.

[0048] As shown in FIGS. 15 and 16, first, a silicon film is formed on the metal film MF located in the region 1A, the silicon film is formed on the polycrystalline silicon film PL1 located in the region 2A, the silicon film is formed on the polycrystalline silicon film PL1 located in the region 3A, and the silicon film is formed on the semiconductor substrate SUB located in the region 4A via the insulating film IF1.

[0049] The silicon film is formed by a film formation process using, for example, the CVD method, and is formed within a temperature range of 400 degrees Celsius or higher and 550 degrees Celsius or lower. The thickness of the silicon film is greater than the thickness of the polycrystalline silicon film PL1, and is, for example, 40 nm or more and 100 nm or less.

[0050] In the normal case of the above film formation process, an amorphous silicon film is formed. Therefore, in regions 1A and 4A, the silicon film is formed as an amorphous silicon film AM2. On the other hand, in regions 2A and 3A, since the polycrystalline silicon film PL1 functions as a seed film, the silicon film is formed as a polycrystalline silicon film PL2.

[0051] If the thickness of the polycrystalline silicon film PL1 is too small, the polycrystalline silicon film PL1 may not be able to function as a seed film. In order for the polycrystalline silicon film PL1 to function as a seed film, it is preferable that the thickness of the polycrystalline silicon film PL1 is 5 nm or more. Further, considering the purpose of facilitating the complete removal of the metal film MF and the ferroelectric film FE formed on the side surface of the polycrystalline silicon film PL1 as described above, the thickness of the polycrystalline silicon film PL1 is preferably 5 nm or more and 20 nm or less.

[0052] Next, by photolithography technology and ion implantation method, n-type impurities such as arsenic or phosphorus are introduced into the silicon film AM2 located in region 1A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 2A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 3A, and the silicon film AM2 located in region 4A.

[0053] Although not shown in the figure, by photolithography technology and ion implantation method, p-type impurities such as boron or boron difluoride are introduced into the polycrystalline silicon film that becomes the gate electrode of the p-type MISFET in region 2A, the polycrystalline silicon film that becomes the p-type resistance element in region 3A, and the amorphous silicon film that becomes the p-type resistance element in region 4A.

[0054] Thereafter, for example, by a film formation process using a CVD method, an insulating film IF2 is formed on the silicon film AM2 and the polycrystalline silicon film PL2. The insulating film IF2 is, for example, a silicon nitride film and has a thickness of, for example, 20 nm or more and 40 nm or less.

[0055] In the manufacturing processes of FIGS. 17 to 20, the silicon film AM2, the metal film MF, and the ferroelectric film FE located in region 1A are patterned, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 2A are patterned, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 3A are patterned, and the silicon film AM2 located in region 4A is patterned.

[0056] As shown in FIGS. 17 and 18, first, a resist pattern RP4 is formed on the insulating film IF2. The resist pattern RP4 has a pattern that selectively covers a part of the insulating film IF2 located from region 1A to region 4A. Next, by performing an anisotropic etching process using the resist pattern RP4 as a mask, the insulating film IF2, the silicon film AM2, and the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 exposed from the resist pattern RP4 are removed. Thereafter, the resist pattern RP4 is removed by an ashing process.

[0057] As shown in FIGS. 19 and 20, first, by performing an anisotropic etching process using the insulating film IF2 as a mask, in region 1A, the metal film MF and the ferroelectric film FE exposed from the insulating film IF2 are removed.

[0058] Next, by photolithography technology and an ion implantation method, an n-type extension region (impurity region) EX is formed by introducing an n-type impurity such as arsenic or phosphorus into the semiconductor substrate SUB located from region 1A to region 4A.

[0059] Also, although not shown in the figures, by introducing p-type impurities such as boron or boron difluoride into the semiconductor substrate SUB located in region 2A using photolithography technology and ion implantation, a p-type extension region that serves as the source region or drain region of the p-type MISFET is formed.

[0060] As shown in FIGS. 21 and 22, first, in regions 1A to 4A, for example, a silicon oxide film and a silicon nitride film are sequentially formed on the semiconductor substrate SUB so as to cover the insulating film IF2 by a film formation process using, for example, the CVD method. Next, the sidewall spacer SW is formed by processing the silicon oxide film and the silicon nitride film by anisotropic etching. Note that the insulating film IF2 is removed by this anisotropic etching process.

[0061] In region 1A, the sidewall spacer SW is formed on the side surfaces of each of the ferroelectric film FE, the metal film MF, and the silicon film AM2. In regions 2A and 3A, the sidewall spacer SW is formed on the side surfaces of each of the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1. In region 4A, the sidewall spacer SW is formed on the side surface of the silicon film AM2.

[0062] Next, by introducing n-type impurities such as arsenic or phosphorus into the semiconductor substrate SUB located in regions 1A to 4A using photolithography technology and ion implantation, an n-type diffusion region (impurity region) ND is formed. The diffusion region ND and the extension region EX constitute part of the source region or part of the drain region of the memory transistor MQ and the selection transistor 1Q in region 1A, and constitute part of the source region or part of the drain region of the MISFET 2Q in region 2A.

[0063] When forming the diffusion region ND, n-type impurities are also introduced into the silicon film AM2 located in region 1A, the polycrystalline silicon films PL2 and PL1 located in region 2A, the polycrystalline silicon films PL2 and PL1 located in region 3A, and the silicon film AM2 located in region 4A.

[0064] Although not shown in the figure, by using photolithography technology and ion implantation method, p-type impurities such as boron or boron difluoride are introduced into the semiconductor substrate SUB located in region 2A to form a p-type diffusion region that becomes the source region or drain region of the p-type MISFET.

[0065] When forming the p-type diffusion region, p-type impurities are also introduced into the polycrystalline silicon film that becomes the gate electrode of the p-type MISFET in region 2A, the polycrystalline silicon film that becomes the p-type resistance element in region 3A, and the amorphous silicon film that becomes the p-type resistance element in region 4A.

[0066] As shown in FIGS. 23 and 24, the diffusion region ND and the extension region EX are activated by heat treatment, and the silicon films AM2 located in regions 1A and 4A are crystallized to form polycrystalline silicon films PL3, respectively. This heat treatment is performed by the RTA (Rapid Thermal Annealing) method in a nitrogen atmosphere within a temperature range of 1000 degrees Celsius or more and 1100 degrees Celsius or less and within a time range of 0.1 second or more and 1.0 second or less.

[0067] The polycrystalline silicon film PL3 and the metal film MF located in region 1A function as the gate electrode GE1 of the memory transistor MQ and the gate electrode GE2 of the selection transistor 1Q. The polycrystalline silicon films PL2 and PL1 located in region 2A function as the gate electrode GE3 of the MISFET 2Q. The polycrystalline silicon films PL2 and PL1 located in region 3A function as the resistance element RS1. The polycrystalline silicon film PL3 located in region 4A functions as the resistance element RS2.

[0068] As described above, a ferroelectric memory cell MC including a memory transistor MQ and a selection transistor 1Q is formed in region 1A, a MISFET 2Q is formed in region 2A, a resistance element RS1 is formed in region 3A, and a resistance element RS2 is formed in region 4A.

[0069] <Main features of Embodiment 1> As described with reference to FIGS. 15 and 16, when forming a silicon film for the gate electrode of the ferroelectric memory cell MC on the metal film MF in region 1A, the temperature of the film formation process is set to 400 degrees Celsius or higher and 550 degrees Celsius or lower. As a result, an amorphous silicon film AM2 is formed on the metal film MF. Therefore, the problem that abnormal growth of the polycrystalline silicon film easily occurs when a polycrystalline silicon film is formed on the metal film MF is solved.

[0070] On the other hand, in region 3A, as the resistance element RS1, a silicon film formed in the same manufacturing process as the silicon film of the ferroelectric memory cell MC is applied. As a result, there is no need to separately form a silicon film for the resistance element RS1, the manufacturing process can be simplified, and an increase in manufacturing cost can be suppressed. When an amorphous silicon film AM2 is applied as the resistance element RS1, this silicon film AM2 is crystallized by the heat treatment shown in FIGS. 23 and 24. However, in that case, it has been found that the sheet resistance of the resistance element RS1 becomes lower than the sheet resistance when formed of a polycrystalline silicon film in advance.

[0071] Therefore, in Embodiment 1, as described with reference to FIGS. 9 and 10, the silicon film AM1 formed in regions 2A and 3A is crystallized to form a polycrystalline silicon film PL1. Then, the polycrystalline silicon film PL1 is left in regions 2A and 3A without being removed. When the amorphous silicon film AM2 is formed, in regions 2A and 3A, the polycrystalline silicon film PL1 functions as a seed film, so the silicon films in regions 2A and 3A are formed as polycrystalline silicon films PL2.

[0072] FIG. 25 shows a comparison between the resistance element RS1 (polycrystalline silicon film PL1 / polycrystalline silicon film PL2) of Embodiment 1 and a resistance element of a comparative example. The resistance element of the comparative example is made of a polycrystalline silicon film obtained by crystallizing an amorphous silicon film.

[0073] In the case of the resistance element of the comparative example, ion implantation into the silicon film is performed when the silicon film is in the amorphous state, both during the manufacturing processes of FIGS. 15 and 16 and during the manufacturing processes of FIGS. 21 and 22. As a cause of the low sheet resistance, it is considered that the solid solubility has increased due to ion implantation into the amorphous silicon film. Further, the thickness of the amorphous silicon film is, for example, 40 nm or more and 100 nm or less. As another cause of the low sheet resistance, it is considered that the grains become larger in the polycrystalline silicon film crystallized from the amorphous state.

[0074] In Embodiment 1, since the polycrystalline silicon film PL1 functions as a seed film, when a silicon film is formed on the seed film, many crystal nuclei exist in the silicon film. Therefore, it is considered that the grains in the polycrystalline silicon film PL3 of Embodiment 1 are smaller than those in the polycrystalline silicon film of the comparative example.

[0075] Conventionally, a polycrystalline silicon film formed at a film formation temperature of about 600° C. has been used as a resistance element, but the sheet resistance of the resistance element RS1 of Embodiment 1 was almost the same as that of the conventional resistance element. Thus, in Embodiment 1, reduction of the sheet resistance of the resistance element RS1 can be suppressed, fluctuations in the characteristics of the resistance element RS1 can be suppressed, and the reliability of the semiconductor device can be improved.

[0076] Also, in Embodiment 1, a resistance element RS2 is formed in region 4A. In region 4A, since the polycrystalline silicon film PL1 is removed, the resistance element RS2 is made of a polycrystalline silicon film PL3 obtained by crystallizing an amorphous silicon film AM2. That is, the resistance element RS2 corresponds to the resistance element of the comparative example and has a lower sheet resistance than the resistance element RS1.

[0077] Depending on the product specifications, a plurality of resistance elements having different sheet resistances may be required. As in Embodiment 1, by leaving the polycrystalline silicon film PL1 in region 3A and removing the polycrystalline silicon film PL1 in region 4A, resistance elements RS1 and RS2 having different sheet resistances can be obtained without adding manufacturing steps. In the case of Embodiment 1, n-type resistance element RS1, p-type resistance element RS1, n-type resistance element RS2, and p-type resistance element RS2 having mutually different sheet resistances are obtained.

[0078] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0079] 1A Region (memory cell region) 2A, 3A, 4A Regions (peripheral regions) 1Q Selection transistor 2Q MISFET AM1, AM2 Amorphous silicon films DNW Well region EX Extension region (impurity region) FE Ferroelectric film GE1, GE2, GE3 Gate electrodes GI1, GI2, GI3 Gate insulating films IF1, IF2 Insulating films MC Ferroelectric memory cell MF Metal film MQ Memory transistor ND Diffusion region (impurity region) PL1, PL2, PL3 Polycrystalline silicon films PW1, PW2, PW3 Well regions RP1, RP2, RP3, RP4 Resist patterns RS1, RS2 Resistance elements SUB Semiconductor substrate SW Sidewall spacer

Claims

1. A method for manufacturing a semiconductor device having a first region in which ferroelectric memory cells are formed and a second region located around the first region, comprising: (a) preparing a semiconductor substrate; (b) forming a first silicon film in an amorphous state on the semiconductor substrate located in the first region and the second region; (c) after the step (b), removing the first silicon film located in the first region so that the first silicon film located in the second region remains; (d) after the step (c), crystallizing the first silicon film by a first heat treatment to form a first polycrystalline silicon film; (e) after the step (d), forming a ferroelectric film on the semiconductor substrate located in the first region and on the first polycrystalline silicon film located in the second region; (f) after the step (e), forming a metal film on the ferroelectric film located in the first region and the second region; (g) after the step (f), removing the metal film and the ferroelectric film located in the second region so that the metal film and the ferroelectric film located in the first region remain; (h) after the step (g), forming a second silicon film on the metal film located in the first region and on the first polycrystalline silicon film located in the second region. A method for manufacturing a semiconductor device, comprising the above steps.

2. In the method for manufacturing a semiconductor device according to Claim 1, in the step (h), the second silicon film formed on the metal film is formed in an amorphous state, and the second silicon film formed on the first polycrystalline silicon film is formed as a second polycrystalline silicon film by the first polycrystalline silicon film functioning as a seed film.

3. In the method for manufacturing a semiconductor device according to Claim 2, (i) After the step (h), patterning the second silicon film, the metal film, and the ferroelectric film located in the first region, and patterning the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region; (j) After the step (i), forming an impurity region in the semiconductor substrate located in the first region; (k) After the step (j), by a second heat treatment, activating the impurity region and crystallizing the second silicon film located in the first region to form a third polycrystalline silicon film; A method for manufacturing a semiconductor device, further comprising:

4. In the method for manufacturing a semiconductor device according to claim 3, After the step (k), the third polycrystalline silicon film and the metal film located in the first region function as gate electrodes of transistors included in the ferroelectric memory cell, and the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region function as gate electrodes of a resistance element or a MISFET. A method for manufacturing a semiconductor device.

5. In the method for manufacturing a semiconductor device according to claim 4, Further having a third region located around the first region and different from the second region, In the step (b), the first silicon film is also formed on the third insulating film, In the step (c), the first silicon film located in the first region and the third region is removed so that the first silicon film located in the second region remains, In the step (e), the ferroelectric film is also formed on the third insulating film, In the step (f), the metal film is also formed on the ferroelectric film located in the third region, In the step (g), the metal film and the ferroelectric film located in the second region and the third region are removed so that the metal film and the ferroelectric film located in the first region remain, In the step (h), the amorphous second silicon film is also formed on the semiconductor substrate located in the third region. In the step (i), the second silicon film located in the third region is also patterned. In the step (k), by the second heat treatment, the second silicon film located in the third region is crystallized to form a fourth polycrystalline silicon film. After the step (k), the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region function as a first resistor element, and the fourth polycrystalline silicon film located in the third region functions as a second resistor element, a method for manufacturing a semiconductor device.

6. In the method for manufacturing a semiconductor device according to claim 5, The sheet resistance of the second resistor element is lower than the sheet resistance of the first resistor element, a method for manufacturing a semiconductor device.

7. In the method for manufacturing a semiconductor device according to claim 2, During the step (h), the thickness of the first polycrystalline silicon film is 5 nm or more, a method for manufacturing a semiconductor device.

8. In the method for manufacturing a semiconductor device according to claim 7, During the step (e), the thickness of the first polycrystalline silicon film is 20 nm or less, a method for manufacturing a semiconductor device.

9. In the method for manufacturing a semiconductor device according to claim 1, The thickness of the second silicon film is larger than the thickness of the first polycrystalline silicon film, a method for manufacturing a semiconductor device.

10. In the method for manufacturing a semiconductor device according to claim 9, The thickness of the first polycrystalline silicon film is 5 nm or less and 20 nm or less, The thickness of the second silicon film is 40 nm or less and 100 nm or less, a method for manufacturing a semiconductor device.

11. In the method of manufacturing a semiconductor device according to claim 1, In the step (d), the first heat treatment is performed in a nitrogen atmosphere within a temperature range of 800 degrees Celsius or higher and 1000 degrees Celsius or lower, and within a time range of 10 seconds or longer and 100 seconds or shorter. A method of manufacturing a semiconductor device.

12. In the method of manufacturing a semiconductor device according to claim 1, In the step (h), the second silicon film is formed within a temperature range of 400 degrees Celsius or higher and 550 degrees Celsius or lower. A method of manufacturing a semiconductor device.

13. In the method of manufacturing a semiconductor device according to claim 1, The metal film is a titanium nitride film. A method of manufacturing a semiconductor device.

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