Flip-flop

Abstract

To provide a flip-flop capable of solving problems that, conventionally, although the shift in the threshold voltage of a transistor is suppressed by applying an AC pulse to the gate of the transistor prone to degradation, however, when amorphous silicon is used as the semiconductor layer of the transistor, naturally, the transistors that make up the circuit for generating AC pulse also cause a shift in threshold voltage.SOLUTION: By inputting a signal to the gate electrode of a transistor that is prone to deterioration via a transistor that is turned on, the shift in threshold voltage of the transistor that is prone to deterioration and the shift in threshold voltage of transistors that are turned on are suppressed. That is, the flip-flop has a constitution that via the transistor with the gate electrode to which a high voltage (VDD) is applied (or via an element with a resistive component), an AC pulse is applied to the gate electrode of the transistor that is prone to deterioration.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device having a circuit configured using transistors. In particular, it relates to a display device using an electro-optical element such as liquid crystal or a light-emitting element as a display medium and a driving method thereof.

Background Art

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as liquid crystal televisions. In particular, a technique of integrally forming a driving circuit (hereinafter also referred to as an internal circuit) including a pixel circuit and a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as amorphous silicon) on an insulating substrate has greatly contributed to power consumption reduction and cost reduction, and thus has been actively developed. The internal circuit formed on the insulator is connected to a controller IC or the like (hereinafter also referred to as an external circuit) via an FPC or the like, and its operation is controlled.

[0003] Among the above-described internal circuits, a shift register using a transistor formed of an amorphous semiconductor (hereinafter also referred to as an amorphous silicon transistor) has been devised. The configuration of a flip-flop included in a conventional shift register is shown in FIG. 124(A) (Patent Document 1). The flip-flop in FIG. 124(A) has transistors 11, 12, ​​​A set signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to it. The operation period of the flip-flop in Fig. 124(A) is divided into a set period, a selection period, a reset period, and a non-selection period as shown in the timing chart of Fig. 124(B), and most of the operation period becomes the non-selection period. Here, transistors 12 and 16 are on during the non-selection period. Therefore, since amorphous silicon is used for the semiconductor layers of transistors 12 and 16,

[0004] a variation occurs in the threshold voltage (Vth) due to deterioration or the like. More specifically, the threshold voltage increases. That is, in the conventional shift register, since the threshold voltages of transistors 12 and 16 increase and they cannot be turned on, VSS cannot be supplied to node 41 and wiring 23, resulting in malfunction. To solve this problem, in Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a shift register capable of suppressing the shift of the threshold voltage of transistor 12 has been devised. In Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3, a new transistor (referred to as the first transistor) is arranged in parallel with transistor 12 (referred to as the second transistor), and during the non-selection period, by inputting inverted signals to the gate electrode of the first transistor and the gate electrode of the second transistor respectively, the shift of the threshold voltages of the first transistor and the second transistor is suppressed. Furthermore, in Non-Patent Document 4, not only transistor 12 but also the threshold voltage of transistor 16

[0005]

[0006]

[0006]

[0006] A shift register that can also suppress voltage shift has been devised. In Non-Patent Document 4, a new transistor (referred to as the first transistor) is arranged in parallel with transistor 12 (referred to as the second transistor), and another new transistor (referred to as the third transistor) is arranged in parallel with transistor 16 (referred to as the fourth transistor). Then, during the non-selection period the inverted signals are respectively input to the gate electrode of the first transistor and the gate electrode of the second transistor, and the inverted signals are respectively input to the gate electrode of the third transistor and the gate electrode of the fourth transistor. By doing so, the shift of the threshold voltage of the first transistor, the second transistor, the third transistor, and the fourth transistor is suppressed.

[0007] Furthermore, in Non-Patent Document 5, an AC pulse is applied to the gate electrode of transistor 12 to suppress the shift of the threshold voltage of transistor 12.

[0008] Note that the display devices of Non-Patent Document 6 and Non-Patent Document 7 use a shift register composed of amorphous silicon transistors as a scanning line driving circuit, and further input a video signal from one signal line to the R, G, and B sub-pixels, thereby reducing the number of signal lines by 1 / 3. Thus, the display devices of Non-Patent Document 6 and Non-Patent Document 7 reduce the number of connections between the display panel and the driver IC.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Non-Patent Documents

[0010] [Non-Patent Document 1] Soo Young Yoon, et al., ”Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, p.348-351 [Non-Patent Document 2] Binn Kim, et al., ”a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1073-1076 [Non-Patent Document 3] Mindoo Chun, et al., ”Integrated Gate Driver Using Highly Stable a-Si TFT’s”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1077-1080 [Non-Patent Document 4] Chun-Ching, et al., ”Integrated Gate Driver Circuit Using a-Si TFT”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, p.1023-1026 [Non-Patent Document 5] Yong Ho Jang, et al., ”A-Si TFT lntegrated Gate Driver with AC-Driven Single Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, p.208-211

Non-Patent Document 6

Non-Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0011] According to the conventional technology, by applying an AC pulse to the gate of a transistor that is prone to deterioration, , the shift of the threshold voltage of the transistor is suppressed. However, when amorphous silicon is used as the semiconductor layer of the transistor, of course, the transistors constituting the circuit for generating the AC pulse also have a problem of generating a shift in the threshold voltage. ​ Also, it has been proposed to reduce the number of signal lines to one-third to reduce the number of contacts between the display panel and the driver IC (Non-Patent Documents 6 and 7), but practically, it is required to further reduce the number of contacts of the driver IC. That is, as a problem not solved by the conventional technology, circuit technology for suppressing fluctuations in the threshold voltage of transistors remains an issue. The technology for reducing the number of contacts of the driver IC mounted on the display panel remains an issue. The issue of reducing the power consumption of the display device remains. The issue of increasing the size or increasing the definition of the display device remains. The invention disclosed in this specification aims to provide an industrially beneficial technology by solving one or more of such problems.

[0012] That is, as a problem not solved by the conventional technology, circuit technology for suppressing fluctuations in the threshold voltage of transistors remains an issue. The technology for reducing the number of contacts of the driver IC mounted on the display panel remains an issue. The issue of reducing the power consumption of the display device remains. The issue of increasing the size or increasing the definition of the display device remains.

[0013] The invention disclosed in this specification aims to provide an industrially beneficial technology by solving one or more of such problems. The invention disclosed in this specification aims to provide an industrially beneficial technology by solving one or more of such problems.

Means for Solving the Problem

[0014] The display device according to the present invention suppresses the shift of the threshold voltage of transistors that are likely to deteriorate and the shift of the threshold voltage of turned-on transistors by inputting a signal to the gate electrode of transistors that are likely to deteriorate through turned-on transistors. That is, the present invention includes a configuration in which an AC pulse is applied to the gate electrode of transistors that are likely to deteriorate through transistors to which a high potential (VDD) is applied to the gate electrode (or through an element having a resistance component). That is, the present invention includes a configuration in which an AC pulse is applied to the gate electrode of transistors that are likely to deteriorate through transistors to which a high potential (VDD) is applied to the gate electrode (or through an element having a resistance component). That is, the present invention includes a configuration in which an AC pulse is applied to the gate electrode of transistors that are likely to deteriorate through transistors to which a high potential (VDD) is applied to the gate electrode (or through an element having a resistance component).

[0015] The switches shown in this specification can be of various forms. Examples include electrical switches and mechanical switches. That is, any device that can control the flow of current is acceptable. It is not particularly limited to specific ones. For example, as a switch, a transistor (e.g., bipolar transistor, MOS transistor, etc.), a diode (e.g., PN diode -ode, PIN diode, Schottky diode, MIM (MetalInsulat orMetal) diode, MIS (MetalInsulatorSemicond uctor) diode, diode-connected transistor, etc.), thyristor, etc. can be used. Alternatively, a logic circuit combining these can be used as a switch.

[0016] When using a transistor as a switch, since the transistor operates simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when wanting to suppress the off-current, it is desirable to use a transistor with the polarity having a lower off-current. As a transistor with a low off-current, there are transistors having an LDD region, transistors having a multi-gate structure, etc. Alternatively, when the potential of the source terminal of the transistor operating as a switch operates in a state close to the low-potential side power supply (VSS, GND, 0V, etc.), it is desirable to use an N-channel type transistor. Conversely, when the potential of the source terminal operates in a state close to the high-potential side power supply (VDD, etc.), it is desirable to use a P-channel type transistor. Because when an N-channel type transistor operates with the source terminal close to the low-potential side power supply, and when a P-channel type transistor operates with the source terminal close to the high-potential side power supply, the absolute value of the gate-source voltage can be increased, so the switching characteristics become good. Also, since it is less likely to perform source follower operation, the output characteristics are good. Also, since it is less likely to perform source follower operation, the output ​​​​​​​​This is because the magnitude of the voltage is less likely to decrease.

[0017] Both an N-channel transistor and a P-channel transistor may be used to form a CMOS-type switch. When a CMOS-type switch is used, current can flow if either the P-channel transistor or the N-channel transistor is conducting, making it easier for the switch to function. For example, regardless of whether the input signal voltage to the switch is high or low, the appropriate voltage can be output. Furthermore, since the voltage amplitude value of the signal for turning the switch on and off can be reduced, the power consumption can also be reduced. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. If either the P-channel transistor or the N-channel transistor conducts, current flows, facilitating its function as a switch. For example, whether the input signal voltage to the switch is high or low, the appropriate voltage can be output. Additionally, since the voltage amplitude value of the signal for turning the switch on and off can be decreased, power consumption can also be reduced. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. Whether the input signal voltage to the switch is high or low, the appropriate voltage can be output. Moreover, since the voltage amplitude value of the signal for turning the switch on and off can be reduced, power consumption can also be reduced. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals.

[0018] When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals. When using a transistor as a switch, the switch has an input terminal (either the source terminal or one of the drain terminals), an output terminal (the other of the source terminal or the drain terminal), and a control terminal (the gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, the switch may not have a control terminal for controlling conduction. Therefore, using a diode as a switch rather than a transistor can reduce the wiring for controlling the terminals.

[0019] In this specification, when it is explicitly described that "A and B are connected", it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, In this specification, when it is explicitly described that "A and B are connected", it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, In this specification, when it is explicitly described that "A and B are connected", it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, In this specification, when it is explicitly described that "A and B are connected", it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, In the configuration disclosed in the specification, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but also includes those other than the connection relationship shown in the figure or the text. For example, when A and B are electrically connected, one or more elements (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between A and B may be arranged between A and B. Alternatively, when A and B are functionally connected, one or more circuits (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) that enable the functional connection between A and B may be arranged between A and B. Alternatively, when A and B are directly connected, A and B may be directly connected without other elements or other circuits sandwiched between A and B.

[0020] For example, when A and B are electrically connected, one or more elements (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between A and B may be arranged between A and B. When A and B are electrically connected, one or more elements (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between A and B may be arranged between A and B. One or more of such elements may be arranged between A and B. Or, when A and B are functionally connected, One or more circuits (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) that enable the functional connection between A and B may be arranged between A and B. For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. One or more of such circuits may be arranged between A and B. Or, when A and B are directly connected, A and B may be directly connected without other elements or other circuits sandwiched between A and B. When it is explicitly described that "A and B are directly connected", it shall include the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B). When it is explicitly described that "A and B are directly connected", it shall include the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B). One or more of such circuits may be arranged between A and B. Or, when A and B are directly connected, A and B may be directly connected without other elements or other circuits sandwiched between A and B. That is, A and B may be directly connected without other elements or other circuits intervening between A and B.

[0021] When it is explicitly described that "A and B are directly connected", it shall include the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B). That is, the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B). That is, the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B). That is, the case where A and B are directly connected (that is, the case where they are connected without other elements or other circuits intervening between A and B) and the case where A and B are electrically connected (that is, the case where they are connected with other elements or other circuits sandwiched between A and B).

[0022] When explicitly stating that "A and B are electrically connected," it means that A and B are electrically connected (i.e., connected with another element or another circuit sandwiched between A and B ), or A and B are functionally connected (i.e., functionally connected with another circuit sandwiched between A and B), or A and B are directly connected (i.e., connected without another element or another circuit sandwiched between A and B). That is, when explicitly stating that they are electrically connected, it is considered the same as when only explicitly stating that they are connected.

[0023] A display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, display device, light-emitting element, or light-emitting device, there are EL elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic substances), electron-emitting elements, liquid crystal elements, electrochromic inks, electrophoretic elements, grating light valves (GLV), plasma displays (PDP), digital micromirror devices (DMD), piezoelectric ceramic displays, carbon nanotubes, etc. A display medium whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action can be used. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting Examples of display devices include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), and an example of a display device using electronic ink or electrophoretic elements is electronic paper.

[0024] Various forms of transistors may be used as the transistors described in this specification. Therefore, there is no limitation on the type of transistor to be used. For example, thin-film transistors (TFTs) having an amorphous semiconductor film represented by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal or semi-amorphous) silicon, etc. may be used. When using a TFT, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single-crystalline silicon, the manufacturing cost can be reduced, and the manufacturing equipment can be made smaller. Since the manufacturing equipment can be made smaller, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, it can be manufactured at a low cost. Furthermore, since the manufacturing temperature is low, a substrate with weak heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. And the transmission of light in the display element can be controlled using the transistor on the transparent substrate. Alternatively, since the film thickness of the transistor is thin, a part of the film constituting the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0025] When manufacturing polycrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and it becomes possible to manufacture a transistor with good electrical characteristics. As a result, gate driver circuits (scan line driver circuits), source driver circuits (signal line driver circuits), signals A processing circuit (such as a signal generation circuit, a gamma correction circuit, a DA conversion circuit, etc.) can be integrally formed on a substrate. This can be done.

[0026] When manufacturing microcrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and it becomes possible to manufacture a transistor with good electrical characteristics. At this time, without using a laser and only applying heat treatment, the crystallinity can be improved. As a result , a gate driver circuit (scanning line driving circuit) and a part of a source driver circuit (such as an analog switch etc.) can be integrally formed on a substrate. Furthermore, when not using a laser for crystallization , the unevenness of the crystallinity of silicon can be suppressed. Therefore, a beautiful image can be displayed.

[0027] However, it is possible to manufacture polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel). This is possible.

[0028] Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, etc. In that case, MOS type transistors, junction type transistors, bipolar transistors, etc. can be used as the transistors described in this specification. By these, transistors with little variation in characteristics, size, shape, etc., high current supply ability, and small size can be manufactured. Using these transistors, a circuit with low power consumption can be configured or high integration can be achieved.

[0029] Alternatively, a transistor having a compound semiconductor or an oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO, etc., and furthermore, these compounds It is possible to use a thin film transistor obtained by thinning a semiconductor or an oxide semiconductor, etc. By these, the manufacturing temperature can be lowered, and for example, it becomes possible to manufacture a transistor at room temperature. As a result, it is possible to directly form a transistor on a substrate with low heat resistance, such as a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors can be used not only for the channel portion of a transistor but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as a resistance element, a pixel electrode, and a transparent electrode. Furthermore, they can be formed simultaneously with or formed into a transistor, and the cost can be reduced. Or, it is possible to use a transistor formed by using an inkjet or a printing method. By these, it is possible to manufacture at room temperature, at a low degree of vacuum, or on a large substrate.

[0030] Also, since it is possible to manufacture without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since there is no need to use a resist, the material cost is reduced and the number of processes can be reduced. Moreover, since the film is applied only to the necessary portions, the material is not wasted compared to the manufacturing method of etching after forming a film over the entire surface, and the cost can be reduced. Or, it is possible to use a transistor having an organic semiconductor or a carbon nanotube. By these, it is possible to form a transistor on a substrate that can be bent. Therefore, it can be made resistant to impact. In addition, various transistors can be used.

[0031] In addition, various transistors can be used. By these, it is possible to form a transistor on a substrate that can be bent. Therefore, it can be made resistant to impact.

[0032] In addition, various transistors can be used.

[0033] Various types of substrates on which transistors are formed can be used, and there is no limitation to specific ones. Examples of substrates on which transistors are formed include, for example, single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, rubber substrates, stainless steel substrates, substrates having stainless steel foils, etc. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans can be used as the substrate. Or, transistors are formed on a certain substrate, and then the transistors are transposed onto another substrate and arranged on the other substrate. Examples of substrates onto which transistors are transposed include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), leather substrates, rubber substrates, stainless steel substrates, substrates having stainless steel foils, etc. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans can be used as the substrate. By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture devices that are not easily broken, impart heat resistance, or achieve weight reduction.

[0034] The configuration of the transistor can take various forms and is not limited to a specific configuration. For example a multi-gate structure with two or more gate electrodes may be used. With a multi-gate structure since the channel regions are connected in series, it becomes a configuration in which a plurality of transistors are connected in series. The multi-gate structure can reduce the off-current and improve the reliability by enhancing the breakdown voltage of the transistor. Alternatively, when operating in the saturation region, even if the drain-source voltage changes, the current between the drain and source does not change much, and the slope of the voltage-current characteristics can be made flat. By utilizing the characteristic that the slope of the voltage-current characteristics is flat, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized. Also, a structure in which gate electrodes are arranged above and below the channel may be used. By arranging gate electrodes above and below the channel, the channel region increases, so the current value can be increased. Alternatively, depletion layers are likely to form and the S value can be reduced. When gate electrodes are arranged above and below the channel, it becomes a configuration in which a plurality of transistors are connected in parallel. Moreover, a structure in which a gate electrode is arranged above the channel region or a structure in which a gate electrode is arranged below the channel region may be used. Alternatively, a positive stagger structure or an inverse stagger structure may be used, or the channel region may be divided into a plurality of regions, or the channel regions may be connected in parallel or in series. Also, a source electrode or a drain electrode may overlap the channel region (or a part thereof).

[0035] ​ Forming a structure in which a source electrode or a drain electrode overlaps with a channel region (or a part thereof). This can prevent charges from accumulating in a part of the channel region and causing unstable operation. Also, an LDD region may be provided. By providing an LDD region, it is possible to reduce the off-current and improve the reliability by increasing the breakdown voltage of the transistor. Alternatively, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat. In this specification, one pixel indicates the minimum unit of an image. Therefore, in the case of a full-color display device composed of color elements of R (red), G (green), and B (blue), one pixel is composed of a dot of the R color element, a dot of the G color element, and a dot of the B color element. Note that the color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. When operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat. When operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and the slope of the voltage-current characteristic can be made flat.

[0036] In this specification, one pixel indicates the minimum unit of an image. Therefore, in the case of a full-color display device composed of color elements of R (red), G (green), and B (blue), one pixel is composed of a dot of the R color element, a dot of the G color element, and a dot of the B color element. Note that the color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. In the case of a full-color display device composed of color elements of R (red), G (green), and B (blue), one pixel is composed of a dot of the R color element, a dot of the G color element, and a dot of the B color element. In the case of a full-color display device composed of color elements of R (red), G (green), and B (blue), one pixel is composed of a dot of the R color element, a dot of the G color element, and a dot of the B color element. Note that the color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Note that the color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. For example, white may be added to make it RGBW (W is white). Also, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Or, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Both B1 and B2 are blue, but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. By using such color elements, a display closer to the real thing can be performed, or the power consumption can be reduced. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Note that there may be a plurality of dots of color elements of the same color in one pixel. At that time, the plurality of color elements may each have a different size of the region contributing to the display. Yes. Also, gradation may be represented by controlling each of a plurality of dots of color elements of the same color. This is called the area gradation method. Alternatively, using a plurality of dots of color elements of the same color, the signals supplied to each dot may be made slightly different to widen the viewing angle. That is, the potentials of the pixel electrodes of a plurality of color elements of the same color may each be different. As a result, the voltages applied to the liquid crystal molecules are each different depending on each pixel electrode. Therefore, the viewing angle can be widened. In this specification, one pixel indicates one element capable of controlling brightness. Thus, as an example, one pixel indicates one color element, and the brightness is expressed by that one color element. Therefore, in the case of a color display device composed of color elements of R (red), G (green), and B (blue), the minimum unit of the image is assumed to be composed of three pixels: an R pixel, a G pixel, and a B pixel. Note that the color elements are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used. For example, white may be added to make it RGBW (W is white). Also, for example, one or more colors such as yellow, cyan, magenta, emerald green, and vermilion may be added to RGB. Further, for example, a color similar to at least one of RGB may be added to RGB. For example, it may be R, G, B1, B2. B1 and B2 are both blue but have slightly different frequencies. Similarly, it may be R1, R2, G, B. By using such color elements, a display closer to the actual object can be achieved, or power consumption can be reduced. Also, as another example, one color element

[0037] ​​​​​​​​​​​​​​​​Next, when controlling brightness using a plurality of regions, even if one such region is regarded as one pixel it is acceptable. Thus, as an example, when performing area gradation or when having sub-pixels, for one color element, there are a plurality of regions for controlling brightness, and the gradation is expressed as a whole but it is also acceptable to regard one of the regions for controlling brightness as one pixel. Thus, in that case, one color element will be composed of a plurality of pixels. Alternatively, even if there are a plurality of regions for controlling brightness within one color element, they may be grouped together and regarded as one pixel for one color element. Thus, in that case, one color element will be composed of one pixel. Also, when controlling brightness using a plurality of regions for one color element, depending on the pixel, the size of the region contributing to the display may be different. Also, in the plurality of regions for controlling brightness for one color element, the signals supplied to each may be slightly different so as to widen the viewing angle. That is, for one color element, even if the potentials of the pixel electrodes of the plurality of regions each have are different from each other. As a result, the voltages applied to the liquid crystal molecules are different for each pixel electrode. Thus, the viewing angle can be widened.

[0038] When explicitly described as one pixel (for three colors), it is assumed to be the case where the three pixels of R, G, and B are regarded as one pixel. When explicitly described as one pixel (for one color), it is assumed to be the case where, for one color element, when there are a plurality of regions, they are grouped together and regarded as one pixel.

[0039] In this specification, the pixels may be arranged in a matrix. Here, when the pixels are arranged in a matrix, it means that in the vertical or horizontal direction, the pixels ​including cases where the elements are arranged in a straight line or on a jagged line For example, when performing full-color display with three color elements (e.g., RGB), stripe arrangement is included, and cases where dots of three color elements are delta arranged are also included. Furthermore, cases where Bayer arrangement is used are also included. Note that the color elements are not limited to three, and there can be more well, for example, RGBW (W is white), or adding one or more of yellow, cyan, magenta, etc. to RGB and so on. Also, the size of the display area can be different for each dot of the color element This can reduce power consumption. Or, the life of the display element can be extended.

[0040] In this specification, an active matrix method having an active element in a pixel, or a passive matrix method having no active element in a pixel can be used. In the active matrix method, as the active element (active element, non-linear element), not only a transistor

[0041] but also various active elements (active elements, non-linear elements) can be used. For example, MIM (MetalInsulatorMetal), TFD (Th inFilmDiode), etc. can also be used. These elements have few manufacturing steps so they can be manufactured at low cost. Or, the yield can be increased This is possible. Furthermore, since the size of the element is small, the aperture ratio can be improved and low power consumption and high brightness can be achieved.

[0042] As something other than the active matrix method, an active element (active element, non-linear element) It is also possible to use a passive matrix type that does not use active elements. Since the optical fiber does not use any nonlinear elements, the manufacturing process is reduced and the fiber can be manufactured at low cost. Alternatively, it is possible to increase the yield. Since it does not use any optical elements (electrodes, nonlinear elements), it is possible to improve the aperture ratio, reduce power consumption, and It is possible to increase brightness.

[0043] A transistor has at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region, and the drain region A current can flow through the source region, the channel region, and the source region. The drain varies depending on the transistor structure and operating conditions, so it is unclear which is the source or drain. Therefore, in this specification, it is difficult to determine whether the source is the drain. The regions that function as a source and drain are sometimes not called source or drain. In this case, for example, they may be referred to as a first electrode and a second electrode, respectively.

[0044] A transistor is a device having at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector are also referred to as the first terminal and the second terminal. It may be indicated.

[0045] A gate is a gate electrode and a gate wiring (gate line, gate signal line, scanning line, scanning signal line, etc.). The term "gate electrode" refers to the whole or part of the gate electrode. The semiconductor that forms the channel region and the conductive part that overlaps with the gate insulating film are This refers to the gate film. Note that part of the gate electrode may overlap with the LDD (Lightly Doped Drain) region, or the source and drain regions, via the gate insulating film. The gate wiring refers to the wiring for connecting between the gate electrodes of each transistor, or for connecting the gate electrode to another wiring. However, there are also parts (regions, conductive films, wirings, etc.) that function as both a gate electrode and a gate wiring. Such parts (regions, conductive films, wirings, etc.) may be called a gate electrode or a gate wiring. That is, there are regions where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when a part of the extended gate wiring overlaps with the channel region, that part (region, conductive film, wiring, etc.) functions as a gate wiring but also functions as a gate electrode. Therefore, such a part (region, conductive film, wiring, etc.) may be called a gate electrode or a gate wiring. A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or

[0046] A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or

[0047] A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or A part (region, conductive film, wiring, etc.) formed of the same material as the gate electrode and forming the same island (island) as the gate electrode and connected thereto may also be called a gate electrode. Similarly, a part (region, conductive film, wiring, etc.) formed of the same material as the gate wiring and forming the same island (island) as the gate wiring and connected thereto may also be called a gate wiring. Such parts (regions, conductive films, wirings, etc.) may not overlap with the channel region in a strict sense and may not have the function of connecting to another gate electrode. However, the gate electrode or Formed of the same material as the gate wiring, the same island as the gate electrode or the gate wiring There is a connected part (area, conductive film, wiring, etc.). Such a part (area area, conductive film, wiring, etc.) may also be called the gate electrode or the gate wiring.

[0048] For example, in a multi-gate transistor, one gate electrode and another gate electrode are often connected by a conductive film formed of the same material as the gate electrode. Such a part (area, conductive film, wiring, etc.) is a part (area area, conductive film, wiring, etc.) for connecting the gate electrode and the gate electrode, so it may be called the gate wiring, but since the multi-gate transistor can also be regarded as one transistor, it may also be called the gate electrode. That is, a part (area, conductive film, wiring, etc.) formed of the same material as the gate electrode or the gate wiring, forming and connecting the same island as the gate electrode or the gate wiring may be called the gate electrode or the gate wiring. Furthermore, for example, the conductive film of the part connecting the gate electrode and the gate wiring formed of a material different from the gate electrode or the gate wiring may also be called the gate electrode or the gate wiring.

[0049] The gate terminal refers to a part (area, conductive film, wiring, etc.) of the gate electrode or a part (area, conductive film, wiring, etc.) electrically connected to the gate electrode and means a part of it.

[0050] When called the gate wiring, gate line, gate signal line, scanning line, scanning signal line, etc., there may be a case where the gate of the transistor is not connected to the wiring. In this case, the gate wiring, gate line, gate signal line, etc. may not have the gate of the transistor connected. In this case, the gate wiring, gate line, gate The gate signal line, scanning line, and scanning signal line are wiring formed on the same layer as the gate of the transistor, wiring formed of the same material as the gate of the transistor, or wiring formed simultaneously with the gate of the transistor. Examples include wiring for holding capacitors, power supply lines, reference potential supply lines, etc.

[0051] The source refers to the whole including the source region, source electrode, and source wiring (also called source line, source signal line, data line , data signal line, etc.), or a part of them. The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) or N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a small amount of P-type or N-type impurities, so-called LDD (Lightly Doped Drain) region, is not included in the source region. The source electrode refers to a conductive layer of a part formed of a material different from the source region and electrically connected to the source region. However, the source electrode may also be called the source electrode including the source region. The source wiring refers to wiring for connecting between the source electrodes of each pixel or for connecting the source electrode to another wiring. However, there are also parts (regions, conductive films, wirings, etc.) that function as both the source electrode and the source wiring. Such parts (regions, conductive films, wirings, etc.) may be called the source electrode or the source wiring. That is, there are also regions where the source electrode and the source wiring cannot be clearly distinguished.

[0052] For example, when a part of the extended source wiring overlaps with the source region, that part (region, conductive film etc.) can be called the source electrode or the source wiring. That is, there are also regions where the source electrode and the source wiring cannot be clearly distinguished. For example, when a part of the extended source wiring overlaps with the source region, that part (region, conductive film etc.) can be called the source electrode or the source wiring. That is, there are also regions where the source electrode and the source wiring cannot be clearly distinguished. For example, when a part of the extended source wiring overlaps with the source region, that part (region, conductive film , wiring, etc.) functions as a source wiring, but also functions as a source electrode This becomes the case. Therefore, such a part (region, conductive film, wiring, etc.) may be called a source electrode or may be called a source wiring.

[0053] A part (region, conductive film, wiring, etc.) formed of the same material as the source electrode, forming the same island as the source electrode and connected to it, or a part (region, conductive film, wiring, etc.) connecting the source electrode and the source electrode (region, conductive film, wiring, etc.) may also be called a source electrode. Furthermore, a part that overlaps with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and forming the same island as the source wiring and connected may also be called a source wiring. Such a part (region, conductive film, wiring, etc.) may not have the function of connecting to another source electrode in a strict sense. However, there is a part (region, conductive film, wiring, etc.) formed of the same material as the source electrode or the source wiring and connected to the source electrode or the source wiring. Therefore, such a part (region, conductive film, wiring, etc.) may also be called a source electrode or a source wiring. For example, a conductive film of a part connecting the source electrode and the source wiring, which is formed of a material different from the source electrode

[0054] or the source wiring, may also be called a source electrode or may be called a source wiring. The source terminal refers to a part of the region of the source region, the source electrode, or a part (region, conductive film, wiring, etc.) electrically connected to the source electrode.

[0055]

[0056] When referred to as a source wiring, source line, source signal line, data line, data signal line, etc., the wiring may not be connected to the source (drain) of the transistor. In this case, the source wiring line, source line, source signal line, data line, data signal line are the wirings formed in the same layer as the source (drain) of the transistor, the wirings formed of the same material as the source (drain) of the transistor or the wirings formed simultaneously with the source (drain) of the transistor. Examples include the wiring for the holding capacitor, power line, reference potential supply wiring, etc. This may be the case. For the drain, it is the same as the source.

[0057] A semiconductor device refers to a device having a circuit including semiconductor elements (such as transistors, diodes, thyristors, etc.). Furthermore, all devices that can function by utilizing semiconductor characteristics may also be referred to as semiconductor devices.

[0058] A display element refers to an optical modulation element, liquid crystal element, light-emitting element, EL element (organic EL element, inorganic EL element or EL element including organic and inorganic substances), electron-emitting element, electrophoretic element, discharge element, light reflection element, light diffraction element, digital micromirror device (DMD), etc. However, it is not limited to this. A display device refers to a device having a display element. Note that a display device may also refer to a display panel body in which a plurality of pixels including the display element or peripheral drive circuits for driving these pixels are formed on the same substrate. Note that the display device is connected by wire bonding, bumps, etc.

[0059] to the peripheral drive circuits arranged on the substrate, so-called chip-on-glass (COG). That is to say.

[0060] It may include an IC chip thus formed, or an IC chip connected by TAB or the like. Note that the display device may include a flexible printed circuit board (FPC) to which an IC chip, a resistance element, a capacitance element, an inductor, a transistor, etc. are mounted. Note that the display device may be connected via a flexible printed circuit board (FPC) or the like, and may include a printed wiring board (PWB) to which an IC chip, a resistance element, a capacitance element, an inductor, a transistor, etc. are mounted. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate . Note that the display device may include a lighting device, a housing, an audio input / output device, an optical sensor, etc. . Here, a lighting device such as a backlight unit may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. .

[0061] A lighting device refers to a device having a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet , a light source (LED, cold cathode tube, hot cathode tube, etc.), a cooling device, etc. .

[0062] Note that a light-emitting device refers to a device having a light-emitting element or the like.

[0063] A reflection device refers to a device having a light reflection element, a light diffraction element, a light reflection electrode, etc. .

[0064] A liquid crystal display device refers to a display device having a liquid crystal element. Liquid crystal display devices include direct-view type, projection type, transmissive type, reflective type, transflective type, etc.

[0065] A driving device refers to a device having a semiconductor element, an electric circuit, an electronic circuit. For example, a A transistor that controls the input of a signal from a source signal line into a pixel (sometimes referred to as a selection transistor, a switching transistor, etc.), a transistor that supplies a voltage or current to a pixel electrode, a transistor that supplies a voltage or current to a light-emitting element, etc. are examples of a driving device. Further, a circuit that supplies a signal to a gate signal line (sometimes referred to as a gate driver, a gate line driving circuit, etc.), a circuit that supplies a signal to a source signal line (sometimes referred to as a source driver, a source line driving circuit, etc.) are examples of a driving device. A transistor that supplies a voltage or current to a pixel electrode, a transistor that supplies a voltage or current to a light-emitting element, etc. are examples of a driving device. A transistor that supplies a voltage or current to a light-emitting element, etc. are examples of a driving device. Furthermore, a circuit that supplies a signal to a gate signal line (sometimes referred to as a gate driver, a gate line driving circuit, etc.), a circuit that supplies a signal to a source signal line (sometimes referred to as a source driver, a source line driving circuit, etc.) are examples of a driving device. A circuit that supplies a signal to a source signal line (sometimes referred to as a source driver, a source line driving circuit, etc.) are examples of a driving device. A circuit that supplies a signal to a source signal line (sometimes referred to as a source driver, a source line driving circuit, etc.) are examples of a driving device.

[0066] A display device, a semiconductor device, a lighting device, a cooling device, a light-emitting device, a reflection device, a driving device, etc. may have overlapping parts with each other. For example, a display device may have a semiconductor device and a light-emitting device, or a semiconductor device may have a display device and a driving device. For example, a display device may have a semiconductor device and a light-emitting device, or a semiconductor device may have a display device and a driving device. For example, a display device may have a semiconductor device and a light-emitting device, or a semiconductor device may have a display device and a driving device.

[0067] In this specification, when it is explicitly described that B is formed on A, or B is formed on A, it is not limited to B being formed directly in contact with A. When they are not in direct contact, that is, when another object is interposed between A and B, it is also included. Here, A and B are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). When it is explicitly described that B is formed on A, or B is formed on A, it is not limited to B being formed directly in contact with A. When they are not in direct contact, that is, when another object is interposed between A and B, it is also included. Here, A and B are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). Here, A and B are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0068] Therefore, for example, when it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be single When it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. When it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. When it is explicitly described that layer B is formed on (or on) layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. It may be a layer or multiple layers.

[0069] Furthermore, the same applies when it is explicitly stated that B is formed above A. This is not limited to B being directly on A, but includes the case where there is another object between A and B. For example, if a layer B is formed above a layer A, In this case, layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. The case where the other layers (e.g., layers C and D) are single layers is also included. Alternatively, it may be multi-layered.

[0070] If you explicitly state that B is formed directly on A, This includes cases where B is formed by A and B, but does not include cases where another object is interposed between A and B. It shall be so.

[0071] The same is true when B is below A, or when B is below A. Effect of the Invention

[0072] It is possible to suppress the deterioration of the characteristics of all the transistors in the shift register. Therefore, malfunctions of semiconductor devices using the shift register, such as liquid crystal display devices, can be suppressed. It can be controlled. [Brief description of the drawings]

[0073]

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Embodiments for Carrying Out the Invention

[0074] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore it should not be construed as being limited to the description content of the present embodiment.

[0075] (Embodiment 1) In the present embodiment, a flip-flop, a drive circuit having the flip-flop, and the​ The configuration and driving method of a display device having the driving circuit will be described.

[0076] The basic configuration of the flip-flop according to this embodiment will be described with reference to FIG. 1. In FIG. 1 The flip-flop shown has a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, and a seventh transistor 107. In this embodiment, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 are N-channel type transistors, and it is assumed that they become conductive when the voltage between the gate and the source (V gs) exceeds the threshold voltage (Vth).

[0077] The connection relationship of the flip-flop in FIG. 1 will be described. The first electrode (either the source electrode or the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the third wiring 12 3. The first electrode of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. The first electrode of the third transistor 103 is connected to the sixth wiring 126, and the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the gate electrode of the third transistor 1 03 is connected to the seventh wiring 127. The first electrode of the fourth transistor 104 is connected to the ninth wiring 129, and the second electrode of the fourth transistor 104 is connected to the second The gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 102. The first gate electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101. The second electrode of the fifth transistor 105 is connected to the eighth wiring 128. The gate electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101. A first electrode of the sixth transistor 106 is connected to the tenth wiring 121. 30, and a second electrode of the sixth transistor 106 is connected to the first transistor 101 The gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 1 The first electrode of the seventh transistor 107 is connected to the gate electrode of the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the first transistor 101 The gate electrode of the seventh transistor 107 is connected to the second wiring 122. Connected.

[0078] The gate electrode of the first transistor 101 and the gate electrode of the fourth transistor 104 , a second electrode of the fifth transistor 105, a second electrode of the sixth transistor 106, and The connection point of the second electrode of the seventh transistor 107 is a node 141. The gate electrode of the first transistor 102, the second electrode of the third transistor 103, The connection point of the second electrode of the sixth transistor 104 and the gate electrode of the sixth transistor 106 is Let's call it node 142.

[0079] The fourth wiring 124, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 13 1 may be connected to each other or may be the same wiring. The eighth wiring 128 may be connected to each other or may be the same wiring.

[0080] Note that the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 may be referred to as the first signal line, the second signal, the third signal line, the fourth signal line , and the fifth signal line, respectively. Further, the fourth wiring 124, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 may be referred to as the first power supply line, the second power supply line, the third power supply line, the fourth power supply line, the fifth power supply line, and the sixth power supply line, respectively.

[0081] Note that a potential of V1 is supplied to the seventh wiring 127 and the eighth wiring 128, respectively, and a potential of V2 is supplied to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131, respectively. Further, V1 > V2.

[0082] Note that signals are input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126, respectively. The signal input to the first wiring 121 is a start signal, the signal input to the second wiring 122 is a reset signal, the signal input to the fifth wiring 125 is a first clock signal, and the signal input to the sixth wiring 126 is a second clock signal. Further, the signals input to the first wiring 121, the second wiring 122, the fifth wiring 125, and the sixth wiring 126 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as the H level), and the potential of the L signal is V2 (hereinafter also referred to as the L level).

[0083] Note that various signals, potentials, and currents may be input to the first wiring 121, the second wiring 122, and the second wiring 122 to the eleventh wiring 131.

[0084] Note that a signal is output from the third wiring 123. The signal output from the third wiring 123 is the output signal of the flip-flop of each stage and is also the start signal (hereinafter also referred to as the transfer signal) of the flip-flop of the next stage. Furthermore, the signal output from the third wiring 123 is a digital signal in which the potential of the H signal is V1 (hereinafter also referred to as the H level) and the potential of the L signal is V2 (hereinafter also referred to as the L level).

[0085] Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. 2 and FIG. 3. Furthermore, the timing chart of FIG. 2 will be divided into a selection period and a non-selection period and described. Furthermore, the non-selection period will be divided into a first non-selection period, a second non-selection period, a set period, and a reset period and described. Furthermore, in the non-selection period, the operation periods excluding the set period, selection period, and reset period are repeatedly performed in order of the first non-selection period and the second non-selection period.

[0086] Note that in FIG. 2, the signal 221, the signal 225, the signal 226, the potential 241, the potential 242, the signal 222, and the signal 223 are, respectively, the signal input to the first wiring 121, the signal input to the fifth wiring 125, the signal input to the sixth wiring 126, the potential of the node 141, the potential of the node 142, the signal input to the second wiring 122, and the signal output from the third wiring 123.

[0087] First, during the set period shown in FIGS. 2(A) and 3(A), since signal 221 is at the H level, the fifth transistor 105 turns on, and since signal 222 is at the L level, the seventh transistor 107 turns off. At this time, the potential of node 141 is such that the second electrode of the fifth transistor 105 becomes the source electrode, and it is a value obtained by subtracting the threshold voltage of the fifth transistor 105 from the potential of the eighth wiring 128, so it becomes V1 - Vth(105) (Vth(105): the threshold voltage of the fifth transistor 105). Thus, the first transistor 101 and the fourth transistor 104 turn on, and the fifth transistor 105 turns off. At this time, the potential of node 142 (potential 242) is determined by the resistance ratio (L / W and applied voltage) between the third transistor 103 and the fourth transistor 1 04, and becomes V2 + β (β: an arbitrary positive number ). Further, let β < Vth(102) (Vth(102): the threshold voltage of the second transistor 10 ) and β < Vth(106) (the threshold voltage of the sixth transistor 106). That is, the potential difference (V1 - V2) between the potential of the ninth wiring 129 (V2) and the potential of the sixth wiring 126 (V1 ) is divided by the third transistor 103 and the fourth transistor 104. Thus, the second transistor 102 and the sixth transistor 106 turn off. In this way, during the set period, since the third wiring 123 is connected to the fifth wiring 125 to which an L signal is input, the potential of the third wiring 123 becomes V2. Therefore, an L signal is output from the third wiring 123. Further, node 141 remains in a floating state while maintaining the potential at V1 - Vt h(105).

[0088] In the selection period shown in FIGS. 2(B) and 3(B), signal 221 becomes at the L level, and the fifth transistor​​​​ Since transistor 105 is off and signal 222 remains at the L level, the seventh transistor 10 7 remains off. At this time, node 141 maintains the potential at V1 - Vth(105). Therefore, the first transistor 101 and the fourth transistor 104 remain on. At this time, the potential of node 142 becomes V 2 because the sixth wiring 126 is at the L level. Therefore, the second transistor 102 and the sixth transistor 106 remain off. Here, since an H signal is input to the fifth wiring 125, the potential of the third wiring 123 begins to rise. At this time, the potential of node 141 rises from V1 - Vth(105) by the bootstrap operation and becomes V1 + Vth(101) + α (Vth(101): the threshold voltage of the first transistor 101, α: an arbitrary positive number). Therefore, the potential of the third wiring 123 becomes equal to the potential of the fifth wiring 125 and becomes V1. Note that this bootstrap operation is performed by the capacitive coupling of the parasitic capacitance between the gate electrode and the second electrode of the first transistor 101. In this way, during the selection period, since the third wiring 123 is conductive with the fifth wiring 125 to which the H signal is input, the potential of the third wiring 123 becomes V1. Therefore, the H signal is output from the third wiring 123.

[0089] During the reset period shown in FIGS. 2(C) and 3(C), since signal 221 remains at the L level, the fifth transistor 105 remains off and signal 222 becomes the H level, turning on the seventh transistor 10 7. At this time, the potential of node 141 becomes V2 because the potential of the eleventh wiring ( V2) is supplied through the seventh transistor 107. Therefore, the first ​​Transistor 101 and the fourth transistor 104 are turned off. At this time, node 142 has a potential that, since the second electrode of the third transistor 103 serves as the source electrode, is the value obtained by subtracting the threshold voltage of the third transistor 103 from the potential (V1) of the sixth wiring 1 26, so it becomes V1 - Vth(103) (Vth(103): the threshold voltage of the third transistor 103 ). Therefore, the second transistor 102 and the sixth transistor 106 are turned on . Thus, during the reset period, since the third wiring 123 is conducting with the fourth wiring 124 to which V2 is supplied, the potential of the third wiring 123 becomes V2. Therefore, the L signal is output from the third wiring 123 .

[0090] During the first non-selection period shown in FIGS. 2(D) and 3(D), since the signal 221 remains at the L level, the fifth transistor 105 remains off, and since the signal 222 becomes the L level, the seventh transistor 107 is turned off. At this time, the potential of node 142 becomes V2 because the L signal is input to the sixth wiring 126 . Therefore, the second transistor 102 and the sixth transistor 106 are turned off . At this time, node 141 becomes floating and maintains its potential at V2 . Therefore, the first transistor 101 and the fourth transistor 104 remain off . Thus, during the first non-selection period, since the third wiring 123 becomes floating , the potential of the third wiring 123 maintains V2 .

[0091] During the second non-selection period shown in FIGS. 2(E) and 3(E), since the signal 221 remains at the L level, the fifth transistor 105 remains off, and since the signal 222 remains at the L level , The seventh transistor 107 remains off. The potential of node 142 at this time is V1 - Vth (103) because an H signal is input to the sixth wiring 126 and the transistor 104 is off. Thus, the second transistor 102 and the sixth transistor 106 turn on. The potential of node 141 at this time remains V2 because the potential of the tenth wiring 130 (V2) is supplied through the sixth transistor 106. Therefore, the first transistor 101 and the fourth transistor 104 remain off. In this way, during the second non-selection period, since the third wiring 123 is in conduction with the fourth wiring 124 to which V2 is supplied, the potential of the third wiring 123 remains V2. Accordingly, an L signal is output from the third wiring 12 3.

[0092] From the above, the flip-flop of FIG. 1 can set the potential of the third wiring 123 to V1 by making the potential of node 141 higher than V1 + Vth(101) using the bootstrap operation during the selection period. Furthermore, the flip-flop of FIG. 1 can obtain merits such as reduction of the layout area and the number of elements because this bootstrap operation is performed using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 101.

[0093] Moreover, since the second transistor 102 and the sixth transistor 106 turn on only during the second non-selection period in the flip-flop of FIG. 1, the shift of the threshold voltage of the second transistor 102 and the sixth transistor 106 can be suppressed.

[0094] ​​​​​​Note that for the flip - flop in FIG. 1, V1 is supplied to the gate electrode of the third transistor 103 and by inputting the second clock signal to the first electrode, the threshold voltage shift of the third transistor 103 can also be suppressed.

[0095] Furthermore, in the flip - flop of FIG. 1, since the first transistor 101, the fourth transistor 1 04, the fifth transistor 105, and the seventh transistor 107 are not turned on during the first non - selection period and the second non - selection period, the threshold voltage shift of the first transistor 101, the fourth transistor 104, the fifth transistor 105, and the seventh transistor 107 can be suppressed.

[0096] Furthermore, in the flip - flop of FIG. 1, even if the potential of node 141 and the potential of the third wiring 123 vary during the first non - selection period, by supplying V2 to node 141 and the third wiring 123 during the next second non - selection period, the potential of node 141 and the potential of the third wiring 123 can be reset to V2. Therefore, the flip - flop of FIG. 1 can suppress malfunction caused by node 141 and wiring 123 being in a floating state and the potential of node 141 and the third wiring 123 varying.

[0097] Furthermore, since the flip - flop of FIG. 1 can suppress the threshold shift of the transistor, malfunction caused by the threshold voltage shift of the transistor can be suppressed.

[0098] Furthermore, the flip - flop of FIG. 1 is entirely composed of N - channel type transistors from the first transistor 101 to the seventh transistor 107. Therefore, the flip - flop of FIG. 1 The flop can use amorphous silicon as the semiconductor layer of the transistor. This allows for the simplification of the manufacturing process, reducing manufacturing costs and improving yields. Furthermore, it is possible to fabricate a large display device. Even if polysilicon or polycrystalline silicon is used as the semiconductor layer of the MOSFET, the manufacturing process can be simplified. It is possible.

[0099] The flip-flop in Fig. 1 is a transistor semiconductor layer that is subject to degradation in characteristics (threshold voltage Even when using amorphous silicon, where the voltage shift is prominent, the degradation of transistor characteristics is prevented. Since the increase in the emission efficiency can be suppressed, a display device with a long life can be manufactured.

[0100] Here, functions of the first to eighth transistors 101 to 108 will be described. The first transistor 101 supplies the potential of the fifth wiring 125 to the third wiring 123. The potential of the node 141 is increased by a bootstrap operation. The second transistor 10 has a function of blocking the input current and functions as a bootstrap transistor. The function of selecting the timing for supplying the potential of the fourth wiring 124 to the third wiring 123 is shown in FIG. The third transistor 103 has a sixth The potential of the wiring 127 is divided into the potential of the wiring 129 and the potential of the ninth wiring 129. The fourth transistor 104 functions as a transistor having the ninth wiring 129. The switching transistor has a function of selecting the timing at which the potential of the switching transistor is supplied to the node 142. The fifth transistor supplies the potential of the eighth wiring to the node 141. It has a function of selecting the timing to operate and functions as an input transistor. The sixth transistor 106 has a function of selecting the timing to supply the potential of the tenth wiring 130 to the node 141 and functions as a switching transistor. The seventh transistor 10 7 has a function of selecting the timing to supply the potential of the eleventh wiring 131 to the node 141 and functions as a switching transistor. However, as long as the first transistor 101 to the seventh transistor 107 have the functions described above, they are not limited to transistors. For example, the second transistor 102 that functions as a switching transistor , the fourth transistor 104, the sixth transistor 106, and the seventh transistor 107 may be applied with elements having a switching function, such as diodes, CMOS analog switches, or various logic circuits. Further, the fifth transistor 105 that functions as an input transistor only needs to have a function of selecting the timing to turn off by raising the potential of the node 141, and a PN junction diode or a diode-connected transistor may be applied.

[0101] Note that the third transistor 103 and the fourth transistor 104 constitute an AC pulse generation circuit. The AC pulse generation circuit outputs the signal input from the first electrode of the third transistor 103 to the node 142. However, when the gate electrode of the fourth transistor 104 is at the H level, the AC pulse generation circuit outputs an L signal to the node 142 regardless of the signal input from the first electrode of the third transistor 103.

[0102] In the flip-flop of the present embodiment, among the W / L values of the first transistor 101 to the seventh transistor 107, when the W / L value of the first transistor 101 is maximized, the fall time and rise time of the signal 223 can be shortened. As a result, the flip-flop of the present embodiment can output a signal with less distortion and delay even when a large load is connected to the wiring 123. Among the W / L values of the first transistor 101 to the seventh transistor 107 in the flip-flop of the present embodiment, when the W / L value of the first transistor 101 is maximized, the fall time and rise time of the signal 223 can be shortened. As a result, the flip-flop of the present embodiment can output a signal with less distortion and delay even when a large load is connected to the wiring 123. As a result, the flip-flop of the present embodiment can output a signal with less distortion and delay even when a large load is connected to the wiring 123. As a result, the flip-flop of the present embodiment can output a signal with less distortion and delay even when a large load is connected to the wiring 123.

[0103] Furthermore, in the flip-flop of the present embodiment, the W / L value of the first transistor 101 is preferably 2 to 5 times, more preferably 3 to 4 times, the W / L value of the fifth transistor 105. As a result, the flip-flop of Embodiment 1 can output a signal with less distortion and delay even when a large load is connected to the wiring 123. Furthermore, in the flip-flop of the present embodiment, the W / L value of the first transistor 101 is preferably 2 to 5 times, more preferably 3 to 4 times, the W / L value of the fifth transistor 105. As a result, the flip-flop of Embodiment 1 can output a signal with less distortion and delay even when a large load is connected to the wiring 123. As a result, the flip-flop of Embodiment 1 can output a signal with less distortion and delay even when a large load is connected to the wiring 123. As a result, the flip-flop of Embodiment 1 can output a signal with less distortion and delay even when a large load is connected to the wiring 123.

[0104] Furthermore, in the flip-flop of the present embodiment, when the W / L value of the fourth transistor 104 is made larger than the W / L value of the third transistor 103, the potential of the node 142 during the set period can be reduced. As a result, the flip-flop of the present embodiment can surely turn off the sixth transistor 106 during the set period, thus suppressing malfunction. Furthermore, in the flip-flop of the present embodiment, when the W / L value of the fourth transistor 104 is made larger than the W / L value of the third transistor 103, the potential of the node 142 during the set period can be reduced. As a result, the flip-flop of the present embodiment can surely turn off the sixth transistor 106 during the set period, thus suppressing malfunction. As a result, the flip-flop of the present embodiment can surely turn off the sixth transistor 106 during the set period, thus suppressing malfunction. As a result, the flip-flop of the present embodiment can surely turn off the sixth transistor 106 during the set period, thus suppressing malfunction.

[0105] Furthermore, in the flip-flop of the present embodiment, the L value of the third transistor 103 is preferably larger than the L value of the fourth transistor 104, more preferably 2 to 3 times. As a result, the flip-flop of the present embodiment can reduce the W / L value of the third transistor 103, so that the W value of the fourth transistor 104 can be reduced. Furthermore, in the flip-flop of the present embodiment, the L value of the third transistor 103 is preferably larger than the L value of the fourth transistor 104, more preferably 2 to 3 times. As a result, the flip-flop of the present embodiment can reduce the W / L value of the third transistor 103, so that the W value of the fourth transistor 104 can be reduced. As a result, the flip-flop of the present embodiment can reduce the W / L value of the third transistor 103, so that the W value of the fourth transistor 104 can be reduced. It is possible to reduce the layout area.

[0106] As long as it performs the same operation as in FIG. 1, the arrangement and number of each transistor, etc. are not limited to those in FIG. 1. As can be seen from FIG. 3 which explained the operation of the flip-flop in FIG. 1, in this embodiment, during the set period, selection period, reset period, first non-selection period, and second non-selection period, it is only necessary that conduction is established as shown by the solid lines in FIGS. 3(A) to (E), respectively. Therefore, as long as transistors and the like are arranged and operated so as to satisfy this, transistors, other elements (resistance elements, capacitance elements, etc.), diodes, switches, various logic circuits, etc. may be newly arranged.

[0107] For example, in the flip-flop shown in FIG. 4(A), by arranging a capacitance element 401 between the gate electrode of the first transistor 101 and the second electrode, the bootstrap operation during the selection period can be performed more stably. Further, in the flip-flop of FIG. 4(A), since the parasitic capacitance between the gate electrode of the first transistor 101 and the second electrode can be reduced, each transistor can switch at high speed. Alternatively, as shown in FIG. 4(B), a transistor 402 may be used as the capacitance element 401. The transistor 402 has its gate electrode connected to the node 141, and the first electrode and the second electrode are connected to the third wiring 123 so that it can function as a capacitance element having a large capacitance component. However, for the transistor 402, even if either one of the first electrode and the second electrode is floating, it can function as a capacitance element. The parts common to the configuration of FIG. 1 are denoted by common reference numerals and their description is omitted.

[0108] Note that the capacitive element 401 may use a gate insulating film as the insulating layer and a gate electrode layer as the conductive layer and a wiring layer, or may use a gate insulating film as the insulating layer and a gate electrode layer and a semiconductor layer doped with impurities as the conductive layer, or may use an interlayer film (insulating film) as the insulating layer and a wiring layer and a transparent electrode layer as the conductive layer. However, when the capacitive element 401 uses a gate electrode layer and a wiring layer as the conductive film, the gate electrode layer is connected to the gate electrode of the first transistor 101, and the wiring layer may be connected to the second electrode of the first transistor 101 More preferably, when using a gate electrode layer and a wiring layer as the conductive film, the gate electrode layer is directly connected to the gate electrode of the first transistor 101, and the wiring layer is directly connected to the second electrode of the first transistor 101. This is because the increase in the layout area of the flip-flop due to the arrangement of the capacitive element 401 is small .

[0109] As another example, in the flip-flop shown in FIG. 4(C), by connecting the first electrode of the first transistor 101 to the first wiring 121 (by connecting the first transistor 101 in diode connection ), the eighth wiring 128 becomes unnecessary, and one wiring and one power supply (V1) can be reduced . Note that the parts common to the configuration of FIG. 1 are denoted by common reference numerals and their description is omitted .

[0110] As another example, in the flip-flop shown in FIG. 4(D), by using a resistive element 403 instead of the third transistor 103, one wiring and one power supply can be reduced. Further , in the flip-flop of FIG. 4(D), the potential of the node 142 is set to the sixth during the second non-selection period ​Since it can be made equal to the potential (V1) of the wiring 126, the driving ability can be improved. Note that parts common to the configuration of FIG. 1 are denoted by common reference numerals and their description is omitted.

[0111] As another example, in the flip-flop shown in FIG. 7(A), by connecting the gate electrode of the second transistor 102 to a wiring 711 to which an arbitrary signal is input, a reverse bias can be applied to the gate electrode of the second transistor 102. Further, the Vgs of the second transistor 102 can be reduced. Therefore, the threshold shift of the second transistor 102 can be further suppressed. Note that parts common to the configuration of FIG. 1 are denoted by common reference numerals and their description is omitted. 2. omitted.

[0112] As another example, in the flip-flop shown in FIG. 7(B), since the gate electrode of the second transistor 102 is connected to the sixth wiring 126, the second transistor 102 can be turned on even during the set period, so that the driving ability can be improved. Further, the noise of the third wiring 123 can be reduced. Note that parts common to the configuration of FIG. 1 are denoted by common reference numerals and their description is omitted. omitted.

[0113] As another example, in the flip-flop shown in FIG. 7(C), instead of the third transistor 103, a diode-connected transistor 701 and a diode-connected transistor 702 are used, so that one wiring and one power supply can be reduced. The first electrode of the transistor 701, the second electrode of the transistor 702, and the gate electrode of the transistor 701 are connected to the sixth wiring 126, and the second electrode of the transistor 701, the second electrode of the transistor 702, and ​The gate electrode of the bit transistor 702 is connected to the node 141. That is, two reverse diodes are connected in parallel between the sixth wiring 1 26 and the node 141. Note that the parts common to the configuration of FIG. 1 are omitted from the description using common reference numerals.

[0114] As another example, as shown in FIG. 21(A), the sixth transistor 106 is not necessarily required. This is because the sixth transistor 106 is not necessarily required as long as it can maintain the potential of the node 141 at the L level during the non-selection period. Therefore, the flip-flop of FIG. 21(A) can reduce the number of transistors, and thus can obtain advantages such as a reduction in the layout area. Note that the parts common to the configuration of FIG. 1 are omitted from the description using common reference numerals.

[0115] As another example, as shown in FIG. 21(B), instead of the fourth transistor 104, the eighth transistor 2108 may be used. The first electrode of the eighth transistor 2108 is connected to the twelfth wiring 2132, the second electrode of the eighth transistor 2108 is connected to the node 14 2, and the gate electrode of the eighth transistor 2108 is connected to the first wiring 121. Furthermore, V2 is supplied to the twelfth wiring 2132. By doing so, the flip-flop of FIG. 21(B ) can control the on / off of the eighth transistor 2108 by the start signal, so that the fall time of the potential of the node 142 can be shortened during the set period, and the off time of the second transistor 102 and the sixth transistor 106 can also be advanced. Furthermore, the flip-flop of FIG. 21(B) can ​​​​​Since the time when the transistor 106 turns off becomes earlier, the rising time of the potential of the node 141 during the set period can be shortened. Thus, the flip-flop of FIG. 21(B) can improve the driving ability of the flip-flop. The parts common to the configuration of FIG. 1 will be omitted from the description using common reference numerals. The flip-flop of FIG. 21(B) can improve the driving ability of the flip-flop. Note that parts common to the configuration of FIG. 1 will be omitted from the description using common reference numerals.

[0116] Note that the eighth wiring 128 may be connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130 or the eleventh wiring 131.

[0117] As another example, as shown in FIG. 21(C), an eighth transistor 2108 may be added. Since the eighth transistor 2108 only needs to be able to set the potential of the node 142 to the L level when the start signal is at the H level, the transistor size can be made small. Further, in the flip-flop of FIG. 22(C), since the on / off of the eighth transistor 2108 is controlled by the start signal, similar to the flip-flop of FIG. 22(B), the driving ability of the flip-flop can be improved. Note that parts common to the configurations of FIGS. 1 and 21(B) will be omitted from the description using common reference numerals. The flip-flop of FIG. 22(C) can improve the driving ability of the flip-flop. Note that parts common to the configurations of FIGS. 1 and 21(B) will be omitted from the description using common reference numerals.

[0118] Note that as long as it performs the same operation as FIG. 1, the connection relationship of each wiring is not limited to FIG. 1. As can be seen from FIG. 3 that illustrates the operation of the flip-flop of FIG. 1, in the present embodiment, during the set period, the selection period, the reset period, the first non-selection period, and the second non-selection period only need to be conductive as shown by the solid lines in FIGS. 3(A) to (E), respectively. Therefore, each wiring may be arranged or connected so as to satisfy this. As long as it is conductive as shown by the solid lines in FIGS. 3(A) to (E), respectively. Therefore, each wiring may be arranged or connected so as to satisfy this.

[0119] ​​​​​​For example, as shown in FIG. 5(A), the first electrodes of the second transistor 102, the fourth transistor 104, the first electrode of the sixth transistor 106, and the first electrode of the seventh transistor 107 may be connected to the sixth wiring 506. Further, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507. Thus, the flip-flop in FIG. 5(A) can reduce the number of wirings from 11 to 7 compared to the flip-flop in FIG. 1. Further, the flip-flop in FIG. 5(A) can improve the yield of the shift register by reducing the number of wirings. Further, the flip-flop in FIG. 5(A) can reduce the routing area of the wiring, and can reduce the layout area of the shift register. Further, since the flip-flop in FIG. 5(A) can increase the width of each wiring, the voltage drop can be reduced, and the driving ability of the shift register can be improved. Note that the parts common to the configuration of FIG. 1 are denoted by common reference numerals and the description thereof is omitted. The first electrodes of the transistor 104, the first electrode of the sixth transistor 106, and the first electrode of the seventh transistor 107 may be connected to the sixth wiring 506. Further, the first electrode of the third transistor 103 and the first electrode of the fifth transistor 105 may be connected to the seventh wiring 507. Thus, the flip-flop in FIG. 5(A) can reduce the number of wirings from 11 to 7 compared to the flip-flop in FIG. 1. Further, the flip-flop in FIG. 5(A) can improve the yield of the shift register by reducing the number of wirings. Further, the flip-flop in FIG. 5(A) can reduce the routing area of the wiring, and can reduce the layout area of the shift register. Further, since the flip-flop in FIG. 5(A) can increase the width of each wiring, the voltage drop can be reduced, and the driving ability of the shift register can be improved. Note that the parts common to the configuration of FIG. 1 are denoted by common reference numerals and the description thereof is omitted. The sixth wiring 506 shown in FIG. 5(A) corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1. Further, the seventh wiring 127 shown in FIG. 5(A) corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. 1. Further, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 shown in FIG. 5(A) respectively correspond to the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 shown in FIG. 1.

[0120] Note that the sixth wiring 506 shown in FIG. 5(A) corresponds to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 shown in FIG. 1. Further, the seventh wiring 127 shown in FIG. 5(A) corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. 1. Further, the seventh wiring 127 shown in FIG. 5(A) corresponds to the seventh wiring 127 and the eighth wiring 128 shown in FIG. 1. Further, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 shown in FIG. 5(A) respectively correspond to the first wiring 121, the second wiring 122, the third wiring 123, the fifth wiring 125, and the sixth wiring 126 shown in FIG. 1.

[0121] Note that the sixth wiring 506 and the seventh wiring 507 may be referred to as the first power supply line and the second power supply line, respectively. Furthermore, the first wiring 501, the second wiring 502, the third wiring 503, the fourth wiring 504, and the fifth wiring 505 may be referred to as the first signal line, the second signal line, the third signal line, the fourth signal line, and the fifth signal line, respectively.

[0122] As another example, as shown in FIG. 5(B), the first electrode of the fourth transistor 104 may be connected to the eighth wiring 508. The flip-flop in FIG. 5(B) can suppress malfunction due to voltage drop in the sixth wiring 506 by flowing the instantaneous current generated in the fourth transistor 104 during the set period through the eighth wiring 508. Note that components common to the configurations of FIGS. 1 and 5(A) are denoted by common reference numerals and their description is omitted.

[0123] As another example, as shown in FIG. 5(C), the first electrode of the second transistor 102 may be connected to the ninth wiring 509. The flip-flop in FIG. 5(B) can suppress malfunction due to voltage drop in the sixth wiring 506 by flowing the instantaneous current generated in the second transistor 102 during the reset period through the ninth wiring 509. Note that components common to the configurations of FIGS. 1 and 5(A ) are denoted by common reference numerals and their description is omitted.

[0124] As another example, as shown in FIG. 5(D), the gate electrode of the third transistor 103 may be connected to the tenth wiring 510. If a potential lower than V1 is supplied to the tenth wiring 5 10 in the flip-flop of FIG. 5(D), the potentials of the gate electrode of the second transistor 102 and the gate electrode of the sixth transistor 106 decrease during the second non-selection period. (e) suppressing characteristic degradation of the second transistor 102 and the sixth transistor 106 is achievable. Note that components common to those in FIGS. 1 and 5(A) are denoted by common reference numerals, and their description is omitted.

[0125] As long as the operation is the same as that in FIG. 1, the power supply potential, signal amplitude, and signal timing are not limited to the timing chart of FIG. 2. As can be seen from FIG. 3 that illustrates the operation of the flip-flop in FIG. 1, in the present embodiment, the set period, selection period, reset period, first non-selection period, and second non-selection period may be conductive as indicated by the solid lines in FIGS. 3(A) to (E), respectively. Therefore, the power supply potential, signal amplitude, and signal timing may be changed so as to satisfy this condition.

[0126] For example, as shown in the timing chart of FIG. 6, the period during which an H signal is input to the first wiring 121, the fifth wiring 125, and the sixth wiring 126 may be shortened. FIG. 6 shows that, compared with the timing chart of FIG. 2, the timing at which the signal switches from the L level to the H level is delayed by only period Ta 1, and the timing at which the signal switches from the H level to the L level is advanced by only period Ta2. That is, in FIG. 6, compared with FIG. 2, the period during which the signal is at the H level (period Tb ) is shortened by period Ta1 + period Ta2. Therefore, in the flip-flop to which the timing chart of FIG. 6 is applied, the instantaneous current in each wiring becomes small, so that power saving, suppression of malfunction, improvement of driving ability, etc. can be achieved. Further, in the flip-flop to which the timing chart of FIG. 6 is applied, the fall time of the signal output from the third wiring 123 can be shortened during the reset period. This is because the potential of node 141 becomes the L level, ... ... ... Since the timing is delayed by the period Ta1 + the period Ta2, the L signal input to the fifth wiring 125 is supplied to the third wiring 123 through the first transistor 101 having a large current capacity (large channel width). This is because it is supplied through the first transistor 101 having a large current capacity (large channel width). Incidentally, the parts in common with the timing chart of FIG. 2 are denoted by common reference numerals and their description is omitted. Since the timing is delayed by the period Ta1 + the period Ta2, the L signal input to the fifth wiring 125 is supplied to the third wiring 123 through the first transistor 101 having a large current capacity (large channel width). Since the timing is delayed by the period Ta1 + the period Ta2, the L signal input to the fifth wiring 125 is supplied to the third wiring 123 through the first transistor 101 having a large current capacity (large channel width).

[0127] Note that it is desirable that the relationship among the period Ta1, the period Ta2, and the period Tb satisfies ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 10 [%]. More desirably, it is desirable that ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 5 [%]. Note that it is desirable that the relationship among the period Ta1, the period Ta2, and the period Tb satisfies ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 10 [%]. More desirably, it is desirable that ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 5 [%]. Note that it is desirable that the relationship among the period Ta1, the period Ta2, and the period Tb satisfies ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 10 [%]. More desirably, it is desirable that ((Ta1 + Tb) / (Ta1 + Ta2 + Tb)) × 100 < 5 [%]. Furthermore, it is desirable that the period Ta1 ≒ the period Ta2.

[0128] As another example, when Va (V2 < Va < V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va - Vth(103) during the reset period and the second non-selection period, so that the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. As another example, when Va (V2 < Va < V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va - Vth(103) during the reset period and the second non-selection period, so that the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. As another example, when Va (V2 < Va < V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va - Vth(103) during the reset period and the second non-selection period, so that the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. As another example, when Va (V2 < Va < V1) is supplied to the seventh wiring 127, the potential of the node 142 becomes Va - Vth(103) during the reset period and the second non-selection period, so that the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed.

[0129] As another example, when Vb (V1 + Vth(103) < Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 during the reset period and the second non-selection period, so that the second transistor 102 and the sixth transistor 106 can be easily turned on. As another example, when Vb (V1 + Vth(103) < Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 during the reset period and the second non-selection period, so that the second transistor 102 and the sixth transistor 106 can be easily turned on. As another example, when Vb (V1 + Vth(103) < Vb) is supplied to the seventh wiring 127, the potential of the node 142 becomes V1 during the reset period and the second non-selection period, so that the second transistor 102 and the sixth transistor 106 can be easily turned on.

[0130] As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc < V2) and the potential of the H signal to Vd (V1 > Vd > V2), the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. This is because, during the set As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc < V2) and the potential of the H signal to Vd (V1 > Vd > V2), the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. This is because, during the set As another example, by setting the potential of the L signal input to the sixth wiring 126 to Vc (Vc < V2) and the potential of the H signal to Vd (V1 > Vd > V2), the threshold voltage shift of the second transistor 102 and the sixth transistor 106 can be suppressed. This is because, during the set During the period and the first non-selection period, the potential of node 142 becomes Vc, and reverse bias is applied to the second transistor 102 and the sixth transistor 106. This is because. Further, during the reset period and the second non-selection period, the potential of node 142 becomes Vd, and the Vgs of the second transistor 102 and the sixth transistor 106 becomes small. This is because.

[0131] An example of a top view of the flip-flop shown in FIG. 5(A) is shown in FIG. 25. The conductive layer 2501 includes portions that function as the gate electrodes of the second transistor 102 and the sixth transistor 106, and is connected to the conductive layer 2502 via the wiring 2547. The conductive layer 25 02 includes portions that function as the second electrodes of the third transistor 103 and the fourth transistor 104. The conductive layer 2503 includes portions that function as the first electrodes of the second transistor 102, the sixth transistor 106, and the fourth transistor 104, and is connected to the sixth wiring 506. The conductive layer 2504 includes portions that function as the second electrodes of the second transistor 102, and is connected to the third wiring 503 via the wiring 2548. The conductive layer 2505 includes portions that function as the second electrodes of the fifth transistor 105 and the seventh transistor 107, and is connected to the conductive layer 2510 via the wiring 2549. The conductive layer 2506 includes portions that function as the first electrodes of the seventh transistor 107, and is connected to the sixth wiring 506. The conductive layer 2507 includes portions that function as the first electrodes of the first transistor 101, and is connected to the fourth wiring 504 via the wiring 2541. The conductive layer 2508 includes portions that function as the second electrodes of the first transistor 101, and is connected to the conductive layer 2510 via the wiring 2549. The conductive layer 2506 includes portions that function as the first electrodes of the seventh transistor 107, and is connected to the sixth wiring 506. The conductive layer 2507 includes portions that function as the first electrodes of the first transistor 101, and is connected to the fourth wiring 504 via the wiring 2541. The conductive layer 2508 includes portions that function as the second electrodes of the first transistor 101, It includes a portion that functions as an electrode and is connected to a third wiring 503 via a wiring 2548. The conductive layer 2510 includes a portion that functions as a gate electrode of the first transistor 101 and a gate electrode of the fourth transistor 104. The conductive layer 2511 includes a portion that functions as a gate electrode of the seventh transistor 107 and is connected to a second wiring 502 via a wiring 2546. The conductive layer 2512 includes a portion that functions as a gate electrode of the third transistor 103 and is connected to a seventh wiring 507 via a wiring 2544. The conductive layer 2513 includes a portion that functions as a first electrode of the third transistor 103 and is connected to a fifth wiring 505 via a wiring 2543. The conductive layer 2514 includes a portion that functions as a gate electrode of the fifth transistor 105 and is connected to a first wiring 501 via a wiring 2545. The conductive layer 2515 includes a portion that functions as a second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 via a wiring 2547. The conductive layer 2510 includes a portion that functions as a gate electrode of the fifth transistor 105 and is connected to a first wiring 501 via a wiring 2545. The conductive layer 2515 includes a portion that functions as a second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 via a wiring 2547. The conductive layer 2515 includes a portion that functions as a second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 via a wiring 2547. The conductive layer 2515 includes a portion that functions as a second electrode of the sixth transistor 106 and is connected to the conductive layer 2510 via a wiring 2547.

[0132] Note that the portions that function as the gate electrode, the first electrode, and the second electrode of the first transistor 101 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2581. The portions that function as the gate electrode, the first electrode, and the second electrode of the second transistor 102 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2582. The portions that function as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2583. The portions that function as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2584. The portions that function as the gate electrode, the first electrode, and the second electrode of the third transistor 103 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2583. The portions that function as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2584. The portions that function as the gate electrode, the first electrode, and the second electrode of the fourth transistor 104 are portions formed by overlapping the conductive layer containing each of them with the semiconductor layer 2584. It is a portion formed by overlapping a conductive layer each including and a semiconductor layer 2584. The portions functioning as the gate electrode, the first electrode, and the second electrode of the fifth transistor 105 are each a portion formed by overlapping a conductive layer each including and a semiconductor layer 2585. The portions functioning as the gate electrode, the first electrode, and the second electrode of the sixth transistor 106 are each a portion formed by overlapping a conductive layer each including and a semiconductor layer 2586. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are each a portion formed by overlapping a conductive layer each including and a semiconductor layer 2587. The portions functioning as the gate electrode, the first electrode, and the second electrode of the seventh transistor 107 are each a portion formed by overlapping a conductive layer including and a semiconductor layer 2587. a portion formed by overlapping a conductive layer each including and a semiconductor layer 2587. a portion formed by overlapping a conductive layer including and a semiconductor layer 2587.

[0133] The configuration and driving method of the shift register having the flip-flop of the above-described embodiment will be described.

[0134] The configuration of the shift register of this embodiment will be described with reference to FIG. 10. The shift register in FIG. 10 has n flip-flops (flip-flop 1001_1 to flip-flop 1001_n). The shift register in FIG. 10 has n flip-flops (flip-flop 1001_1 to flip-flop 1001_n).

[0135] The connection relationship of the shift register in FIG. 10 will be described. The i-th stage flip-flop 1001_i (any one of flip-flops 1001_1 to 1001_n) of the shift register in FIG. 10 is connected to the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_i - 1, the eighth wiring 1018_i, and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 is connected to the first wiring 1011, the second wiring 1012, the third wiring 1013, the i-th stage flip-flop 1001_i (any one of flip-flops 1001_1 to 1001_n) of the shift register in FIG. 10 is connected to the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_i - 1, the eighth wiring 1018_i, and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 is connected to the first wiring 1011, the second wiring 1012, the third wiring 1013, the fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_i - 1, the eighth wiring 1018_i, and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 is connected to the first wiring 1011, the second wiring 1012, the third wiring 1013, the fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_i - 1, the eighth wiring 1018_i, and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 is connected to the first wiring 1011, the second wiring 1012, the third wiring 1013, the eighth wiring 1018_i, and the eighth wiring 1018_i + 1. However, the first-stage flip-flop 1001_1 is connected to the first wiring 1011, the second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, the sixth wiring 1016, the eighth wiring 1018_1, and the eighth wiring 1018_2. A fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, an eighth wiring 1018, 1 and the eighth wiring 1018_2. Furthermore, the nth flip-flop 100 1_n is a second wiring 1012, a third wiring 1013, a fourth wiring 1014, a fifth wiring 1015, a sixth wiring 1016, a seventh wiring 1017, an eighth wiring 1018_n-1, and It is connected to the eighth wiring 1018_n.

[0136] The first wiring 1011 corresponds to the first wiring 121 of the flip-flop 1001_1 shown in FIG. The second wiring 1012 is connected to the fifth wiring 1013 shown in FIG. In the even-numbered flip-flops, the first and second wirings are connected to the sixth wiring 126 shown in FIG. The third wiring 1013 is connected to the sixth wiring 1014 shown in FIG. In the even-numbered flip-flops, the fifth wiring 125 shown in FIG. The fourth wiring 1014 is connected to the seventh wiring 1014 shown in FIG. 27. The fifth wiring 1015 is connected to the eighth flip-flop shown in FIG. The sixth wiring 1016 is connected to the wiring 128 of all the flip-flops shown in FIG. Connected to the fourth wiring 124, the ninth wiring 129, the tenth wiring 130 and the eleventh wiring 131 The eighth wiring 1018_i is connected to the flip-flop 1001_i-1 shown in FIG. The second wiring 122, the third wiring 123 and the flip-flop 1001_i shown in FIG. The flip-flop 1001_i+1 is connected to the first wiring 121 shown in FIG. The eighth wiring 1018_1 is connected to the third wiring 12 shown in FIG. 3 and the first wiring 121 of the flip-flop 1001_2 shown in FIG. For the eighth wiring 1018_n, it is connected to the second wiring 122 shown in FIG. 1 of the flip-flop 1001_n-1 and the third wiring 123 shown in FIG. 1 of the flip-flop 1001_n.

[0137] Note that a potential of V1 is supplied to the fourth wiring 1014 and the fifth wiring 1015 respectively, and a potential of V2 is supplied to the sixth wiring 1016.

[0138] Note that signals are input to the first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1017 respectively. The signal input to the first wiring 1011 is a start signal, the signal input to the second wiring 1012 is a first clock signal, the signal input to the third wiring 1013 is a second clock signal, and the signal input to the seventh wiring 1017 is a reset signal. Further, the signals input to the first wiring 1011, the second wiring 1012, the third wiring 1013, and the seventh wiring 1017 are digital signals where the potential of the H signal is V1 and the potential of the L signal is V2.

[0139] Note that various signals, power supply potentials, or currents may be input to the first wiring 1011 to the seventh wiring 1017.

[0140] Note that signals are output from the eighth wiring 1018_1 to the eighth wiring 1018_n. For example, the signal output from the eighth wiring 1018_i is the output signal of the flip-flop 1001_i. Further, the signal output from the eighth wiring 1018_i is also the start signal of the flip-flop 1001_i + 1 and the reset signal of the flip-flop 1001_i - 1.

[0141] ​​​​​​​​​​​​​​ In addition, when the signals input to or the voltages supplied to the first wiring 1011 to the seventh wiring 1017 are the same, each of the first wiring 1011 to the seventh wiring 1017 may be connected or may be the same wiring.

[0142] Next, the operation of the shift register shown in FIG. 10 will be described with reference to the timing charts of FIGS. 11 and 12. Here, the timing chart of FIG. 11 is divided into a scanning period and a retrace period. The scanning period is from when the output of the selection signal from the eighth wiring 1018_1 starts to when the output of the selection signal from the eighth wiring 1018_n ends. The retrace period is from when the output of the selection signal from the eighth wiring 1018_n ends to when the output of the selection signal from the eighth wiring 1018_1 starts.

[0143] In addition, in FIG. 11, the signal 1111 input to the first wiring 1011, the signal 1112 input to the second wiring 10 12, the signal 1113 input to the third wiring 1013, the signal 1117 input to the seventh wiring 1017, the signal output to the eighth wiring 1018_1, the signal of the eighth wiring 1018_2, and the signal 1118_n output to the eighth wiring 1018_n are shown. Furthermore, in FIG. 12, the signal 1211 input to the first wiring 1011, the signal 1218_1 output to the eighth wiring 1018_1, the signal 1218_i output to the eighth wiring 1018_i, the signal 1218_i+1 output to the eighth wiring 1018_i+1, and the signal 1218_n output to the eighth wiring 1018_n are shown.

[0144] As shown in FIG. 12, for example, when the flip-flop 1001_i is in the selection period, the first An H signal is output from the wiring 1018_i of 8. At this time, the flip-flop 1001_ i+1 becomes the set period. After that, the flip-flop 1001_i becomes the reset period and an L signal is output from the eighth wiring 1018_i. At this time, the flip-flop 1 001_i+1 becomes the selection period. After that, the flip-flop 1001_i becomes the first non-selection period, and the eighth wiring 1018_i becomes floating and maintains the potential at the L level . At this time, the flip-flop 1001_i+1 becomes the reset period. After that, the flip-flop 1001_i becomes the second non-selection period, and an L signal is output from the eighth wiring 1018_i . At this time, the flip-flop 1001_i+1 becomes the first non-selection period . In this way, the flip-flop 1001_i repeats the first non-selection period and the second non-selection period until the next set period.

[0145] From the above, the shift register in FIG. 10 can output the selection signal sequentially from the eighth wiring 1018_1 to the eighth wiring 1018_n. That is, the shift register in FIG. 10 can scan the eighth wiring 1018_1 to the eighth wiring 1018_n. Therefore, the shift register in FIG. 10 can fully obtain the function as a shift register. .

[0146] Furthermore, the reset signal input to the flip-flop 1001_n at the final stage is characterized by being input via the seventh wiring 1017. By doing so, the shift register in FIG. 10 does not require a dummy flip-flop, so the layout area can be reduced. However, a dummy flip-flop may be arranged.

[0147] Furthermore, the shift register in FIG. 10 is based on the timing of the signal input to the first wiring 1011 Therefore, the retrace period can be freely determined.

[0148] Furthermore, the shift register in FIG. 10 applies the flip-flop shown in this embodiment By doing so, it is possible to suppress the threshold shift of the transistor. Furthermore, the shift register in FIG. 10 can achieve a longer lifespan. Furthermore, the shift register in FIG. 10 can improve the driving ability. Furthermore, malfunction can be suppressed. Furthermore, the shift register in FIG. 10 can simplify the process, etc.

[0149] Note that, as long as it performs the same operation as FIG. 10, it is not limited to the configuration of FIG. 10.

[0150] For example, as shown in FIG. 13, the output signals of each flip-flop may be output via buffers respectively The shift register in FIG. 13 has flip-flops 1001_1 to flip-flops 1001_n connected to the eighth wirings 1018_1 to the eighth wirings 1018_n via buffers 1301_1 to buffers 1301_n respectively Therefore, a wide driving ability can be obtained. Because, if a large load is connected to each of the eighth wirings 1018_1 to the eighth wirings 1018_n respectively, delay and distortion will occur in the signals output from each of the eighth wirings 1018_1 to the eighth wirings 1018_n That is, because the delay and distortion of the signals output from each of the eighth wirings 1018_1 to the eighth wirings 1018_n do not affect the operation of the shift register Note that the parts common to the configuration of FIG. 10 are denoted by common reference numerals and their description is omitted. ​​

[0151] Each of the buffers 1301_1 to 1301_n is a NAND, NOR, etc. A logic circuit, an operational amplifier, or a combination of these can be used. In other words, an inverter or an analog buffer can be used. Each of the buffers 301_1 to 1301_n has an N-channel flip-flop. If the input transistor is an N-channel transistor, it is preferable that the input transistor is an N-channel transistor. Furthermore, each of the buffers 1301_1 to 1301_n is a bootstrap buffer. It is desirable to configure the buffer 1301_1 to the buffer 1301_2 so that the buffer 1301_3 can perform the above-mentioned operations. The driving voltage (the potential difference between the negative and positive power supplies) of each of the 1301_n flip-flops is It is preferable that the driving voltage of each of the flip-flops 001_1 to 1001_n is larger than that of the other. It is nice.

[0152] Here, the buffers 1301_1 to 1301_2 of the shift register shown in FIG. An example of the ._n will be described with reference to FIG. 123(A) and FIG. 123(B). The buffer 8000 shown in A) has an inverter 8001 between a wiring 8011 and a wiring 8012. a, inverter 8001b, and inverter 8001c are connected to wiring 8011. An inverted signal of the input signal is output from the wiring 8012. There is no limit to the number of inverters connected between the wiring 8011 and the wiring 8012. When an even number of inverters are connected between the wiring 8012 and the A signal of the same polarity is output from the wiring 8012. Furthermore, the buffer 810 in FIG. As shown in 0, the inverters 8002a, 8002b, and inverter 8002c connected in series, and the inverters 8003a, 8003b and inverter 8003c arranged in series may be connected in parallel. The buffer 81 00 in FIG. 123(B) can average the variations in the characteristics of the transistors, so that the delay and ripple of the signal output from the wiring 8012 can be reduced. Further, the outputs of the inverter 8002a and the inverter 8 002a, and the outputs of the inverter 8002b and the inverter 8002b may be connected to each other.

[0153] In addition, in FIG. 123(A), it is preferable that the W of the transistor of the inverter 8001a < the W of the transistor of the inverter 8001b < the W of the transistor of the inverter 8001c. This is because, since the W of the inverter 8001a is small, the driving ability of the flip-flop (specifically, the value of W / L of the transistor 101 in FIG. 1) can be made small, so that the shift register of the present embodiment can reduce the layout area. Similarly, in FIG. 123(B), it is preferable that the W of the transistor of the inverter 8002a < the W of the transistor of the inverter 8002b < the W of the transistor of the inverter 8002c. Similarly, in FIG. 123(B), it is preferable that the W of the transistor of the inverter 8003a < the W of the transistor of the inverter 8003b < the W of the transistor of the inverter 8003c. Further, the W of the transistor of the inverter 800 2a = the W of the transistor of the inverter 8003a, and the W of the transistor of the inverter 8002b = the W of the transistor of the inverter 8003b. Since the driving ability of the flip-flop can be reduced, the shift register of the present embodiment can reduce the layout area. Similarly, in FIG. 123(B), it is preferable that the W of the transistor of the inverter 8002a < the W of the transistor of the inverter 8002b < the W of the transistor of the inverter 8002c. Similarly, in FIG. 123(B), it is preferable that the W of the transistor of the inverter 8003a < the W of the transistor of the inverter 8003b < the W of the transistor of the inverter 8003c. Further, it is preferable that the W of the transistor of the inverter 8002a = the W of the transistor of the inverter 8003a, the W of the transistor of the inverter 8002b = the W of the transistor of the inverter 8003b, and the W of the transistor of the inverter 8002c = the W of the transistor of the inverter 8003c. Similarly, in FIG. 123(B), it is preferable that the W of the transistor of the inverter 8003a < the W of the transistor of the inverter 8003b < the W of the transistor of the inverter 8003c. Further, it is preferable that the W of the transistor of the inverter 8002a = the W of the transistor of the inverter 8003a, the W of the transistor of the inverter 8002b = the W of the transistor of the inverter 8003b, and the W of the transistor of the inverter 8002c = the W of the transistor of the inverter 8003c. 8002c = the W of the transistor of the inverter 8003c. Further, it is preferable that the W of the transistor of the inverter 800 2a = the W of the transistor of the inverter 8003a, the W of the transistor of the inverter 8002b = the W of the transistor of the inverter 8003b, and the W of the transistor of the inverter 8002c = the W of the transistor of the inverter 8003c. 8002c = the W of the transistor of the inverter 8003c.​ Let the W of the inverter 8002c be the W of the transistor it has, and the W of the transistor of the inverter 8003c be the W of the transistor it has. It is preferable.

[0154] Note that the inverter shown in FIGS. 123(A) and 123(B) is not particularly limited as long as it can invert the input signal and output it. For example, as shown in FIG. 123(C), the inverter may be configured by the first transistor 8201 and the second transistor 8202. Further, a signal is input to the first wiring, a signal is output from the second wiring 8212, V1 is supplied to the third wiring 8213, and V2 is supplied to the fourth wiring 8214. When an H signal is input to the first wiring 8211 of the inverter in FIG. 123(C), the potential obtained by dividing V1 - V2 by the first transistor 8201 and the second transistor 8202 (W / L of the first transistor 8201 < W / L of the second transistor 8202) is output from the second wiring 8212. Further, when an L signal is input to the first wiring 8211 of the inverter in FIG. 123(C), V1 - Vth(8201) (Vth(8201): the threshold voltage of the first transistor 8201) is output from the second wiring 8212. Further, the first transistor 8201 may be a PN junction diode as long as it is an element having a resistance component, or may simply be a resistance element. Further, as shown in FIG. 123(D), the inverter may be configured by the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, and the second wiring If the first transistor 8201 is an element having a resistance component, it may be a PN junction diode or simply a resistance element.

[0155] Furthermore, as shown in FIG. 123(D), the inverter may be configured by the first transistor 8301, the second transistor 8302, the third transistor 8303, and the fourth transistor 8304. Further, a signal is input to the first wiring 8311, and the second wiring A signal is output from 8312, and V1 is supplied to the third wiring 8313 and the fifth wiring 8315, and V2 is supplied to the fourth wiring 8314 and the sixth wiring 8316. FIG. 123 When the inverter in FIG. 123(D) receives an H signal on the first wiring 8311, it outputs V2 from the second wiring 8 312. At this time, since the potential of node 8341 is at the L level, the first transistor 8301 turns off. Further, when the inverter in FIG. 123(D) receives an L signal on the first wiring 83 11, it outputs V1 from the second wiring 8312. At this time, when the potential of node 8341 becomes V1 - Vth(8303) (Vth(8303): the threshold voltage of the third transistor 8303), node 8341 becomes a floating state, and since the potential of node 8341 becomes higher than V1 + Vth(8301) (Vth(8301): the threshold voltage of the first transistor 8301) by the bootstrap operation, the first transistor 8301 turns on. Further, since the first transistor 8301 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode.

[0156] Furthermore, as shown in FIG. 26(A), an inverter may be configured by the first transistor 8401, the second transistor 8402, the third transistor 8403, and the fourth transistor 8404. The inverter in FIG. 26(A) is a two-input type inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8411, an inverted signal is input to the second wiring 8412, a signal is output from the third wiring 8413, and V1 is supplied to the fourth wiring 8414 and the sixth wiring 8416, and the fifth wiring 8415 and ​​​​​​​and V2 is supplied to the seventh wiring 8417. The inverter in FIG. 26(A) inputs an L signal to the first wiring 8411 and an H signal to the second wiring 8412, and outputs V2 from the third wiring 841 3. At this time, since the potential of the node 8441 becomes V2, the first transistor 8401 turns off. Further, when the inverter in FIG. 26(A) inputs an H signal to the first wiring 8411 and an L signal to the second wiring 8412, it outputs V1 from the third wiring 8413 . At this time, when the potential of the node 8441 becomes V1 - Vth(8403) (Vth(8403) : the threshold voltage of the third transistor 8403), the node 8441 becomes a floating state , and the potential of the node 8441 becomes higher than V1 + Vth(8401) (Vth(8401): the threshold voltage of the first transistor 8401) due to the bootstrap operation , and the first transistor 8401 turns on. Further, since the first transistor 8401 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Further, one of the first wiring 8411 and the second wiring 8412 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG. 1.

[0157] Furthermore, as shown in FIG. 26(B), an inverter may be constituted by the first transistor 8501, the second transistor 8502, and the third transistor 8503. The inverter in FIG. 2 6(B) is a two-input type inverter and can perform a bootstrap operation. Further, a signal is input to the first wiring 8511, an inverted signal is input to the second wiring 8512, a signal is output from the third wiring 8513, and the fourth wiring 8514 and the sixth V2 is supplied to the wiring 8516, and V2 is supplied to the fifth wiring 8515. FIG. 26 When the inverter in (B) inputs an L signal to the first wiring 8511 and an H signal to the second wiring 8512 it outputs V2 from the third wiring 8513. At this time, the potential of the node 8541 becomes V2, so the first transistor 8501 turns off. Further, when the inverter in FIG. 26(B) inputs an H signal to the first wiring 8511 and an L signal to the second wiring 8512, V 1 is output from the third wiring 8513. At this time, when the potential of the node 8541 is V1 - Vth (8503) (Vth(8503): threshold voltage of the third transistor 8503) the node 8541 becomes a floating state, and the potential of the node 8541 becomes higher than V1 + Vth(8501) (Vth(8501): threshold voltage of the first transistor 8501) due to the bootstrap operation, so the first transistor 8501 turns on. Further since the first transistor 8501 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Further, one of the first wiring 85 11 and the second wiring 8512 may be connected to the third wiring 123 shown in FIG. 1, and the other may be connected to the node 142 shown in FIG. 1.

[0158] Furthermore, as shown in FIG. 26(C), an inverter may be constituted by the first transistor 8601, the second transistor 8602, the third transistor 8603, and the fourth transistor 8604. The inverter in FIG. 26(C) is a two-input type inverter and is capable of a bootstrap operation. Further, a signal is input to the first wiring 8611, and the first ​​​An inverted signal is input to the wiring 8612 of 2, and a signal is output from the third wiring 8613. V1 is supplied to the fourth wiring 8614, and V2 is supplied to the fifth wiring 8615 and the sixth wiring 8616. When the inverter in Fig. 26(A) receives an L signal on the first wiring 8611 and an H signal on the second wiring 8612, it outputs V2 from the third wiring 8613. At this time, since the potential of node 8641 becomes V2, the first transistor 8601 turns off. Furthermore, when the inverter in Fig. 26(C) receives an H signal on the first wiring 8611 and an L signal on the second wiring 8612, it outputs V1 from the third wiring 8613. At this time, when the potential of node 8641 becomes V1 - Vth(8603) (Vth(8603): the threshold voltage of the third transistor 8603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. When the potential of node 8641 becomes V2, the first transistor 8601 turns off. Furthermore, when the inverter in Fig. 26(C) receives an H signal on the first wiring 8611 and an L signal on the second wiring 8612, it outputs V1 from the third wiring 8613. At this time, when the potential of node 8641 becomes V1 - Vth(8603) (Vth(8603): the threshold voltage of the third transistor 8603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. Furthermore, when the inverter in Fig. 26(C) receives an H signal on the first wiring 8611 and an L signal on the second wiring 8612, it outputs V1 from the third wiring 8613. At this time, when the potential of node 8641 becomes V1 - Vth(8603) (Vth(8603): the threshold voltage of the third transistor 8603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. 641 becomes V1 - Vth(8603) (Vth(8603): the threshold voltage of the third transistor 8603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. 603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. When the potential of node 8641 becomes V1 - Vth(8603) (Vth(8603): the threshold voltage of the third transistor 8603), node 8641 becomes a floating state, and since the potential of node 8641 becomes higher than V1 + Vth(8601) (Vth(8601): the threshold voltage of the first transistor 8601) by the bootstrap operation, the first transistor 8601 turns on. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Furthermore, since the first transistor 8601 functions as a bootstrap transistor, a capacitive element may be arranged between the second electrode and the gate electrode. Furthermore, one of the first wiring 8611 and the second wiring 8612 may be connected to the third wiring 123 shown in Fig. 1, and the other may be connected to the node 142 shown in Fig. 1. Furthermore, one of the first wiring 8611 and the second wiring 8612 may be connected to the third wiring 123 shown in Fig. 1, and the other may be connected to the node 142 shown in Fig. 1.

[0159] As another example, the reset signal input to the flip - flop 1001_n can use other input signals or output signals of the shift register. That is, by generating the reset signal input to the flip - flop 1001_n inside the shift register, one wiring As another example, the reset signal input to the flip - flop 1001_n can use other input signals or output signals of the shift register. That is, by generating the reset signal input to the flip - flop 1001_n inside the shift register, one wiring As another example, the reset signal input to the flip - flop 1001_n can use other input signals or output signals of the shift register. That is, by generating the reset signal input to the flip - flop 1001_n inside the shift register, one wiring A line and one signal can be reduced. For example, when the flip-flop 1001_n is in the even stage it may be connected to the eighth wiring 1018_1 as shown in FIG. 14. Another example is that when the flip-flop 1001_n is in the even stage, it may be connected to the first wiring 1011 as shown in FIG. 15. As another example, as shown in FIG. 17, a dummy flip-flop 1001_d is used to generate a reset signal input to the flip-flop 1001_n. The dummy flip-flop 1001_d can be the same as the flip-flop 1001_n - 1. However, the second wiring 122 shown in FIG. 1 of the dummy flip-flop 1001_d is connected to the sixth wiring 1016 in FIG. 17. Note that the parts common to the configuration of FIG. 10 are denoted by common reference numerals and their description is omitted.

[0160] Subsequently, the structure and driving method of the display device having the shift register of the above-described embodiment will be described. However, the display device of this embodiment only needs to have at least the flip-flop of this embodiment.

[0161] The configuration of the display device of this embodiment will be described with reference to FIG. 18. The display device in FIG. 18 has a signal line driving circuit 1801, a scanning line driving circuit 1802, and a pixel portion 1804. In the pixel portion 1804, a plurality of signal lines S1~Sm extending in the column direction from the signal line driving circuit 1801, a plurality of scanning lines G1~Gn extending in the row direction from the scanning line driving circuit 1802, and a plurality of any one of m), and is connected to one of the scanning lines Gi (any one of the scanning lines G1 to Gn) Furthermore, the scanning line driving circuit 1802 may be referred to as a driving circuit.

[0162] Note that the shift register of the present embodiment can be applied as the scanning line driving circuit 1802. Of course, the shift register of the present embodiment may also be used for the signal line driving circuit 1801.

[0163] Note that the scanning lines G1 to Gn are connected to the eighth wirings 1808_1 to 1808_n shown in FIGS. 10, 12, 13, 14, 15, and 17.

[0164] Note that the signal lines and the scanning lines may simply be referred to as wirings. Furthermore, the signal line driving circuit 1801 and the scanning line driving circuit 1802 may each be referred to as a driving circuit.

[0165] Note that the pixel 1803 has at least one switching element, one capacitive element, and a pixel electrode. However, the pixel 1803 may have a plurality of switching elements or a plurality of capacitive elements. Furthermore, the capacitive element is not necessarily required. Furthermore, the pixel 1803 may further have a transistor that operates in the saturation region. Furthermore, the pixel 1803 may have a display element such as a liquid crystal element or an EL element. Here, as the switching element a transistor and a PN junction diode can be used. However, when a transistor is used as the switching element it is desirable that the transistor operates in the linear region. Furthermore, when the scanning line driving circuit 1802 is composed only of N-channel transistors it is desirable to use an N-channel transistor as the switching element. ​​Yes. Further, when the scanning line driving circuit 1802 is composed only of P-channel transistors, it is desirable to use a P-channel transistor as the switching element. The scanning line driving circuit 1802 and the pixel section 1804 are formed on the insulating substrate 1805, while the signal line driving circuit 1801 is not formed on the insulating substrate 1805. The signal line driving circuit 1801 is formed on a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805. Then, the signal line driving circuit 1801 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. However, the signal line driving circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the functions of the signal line driving circuit 1801 may be formed on the insulating substrate 1805.

[0166] Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). The scanning line driving circuit 1802 and the pixel section 1804 are formed on the insulating substrate 1805, while the signal line driving circuit 1801 is not formed on the insulating substrate 1805. The signal line driving circuit 1801 is formed on a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805. Then, the signal line driving circuit 1801 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. However, the signal line driving circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the functions of the signal line driving circuit 1801 may be formed on the insulating substrate 1805. on a single crystal substrate, an SOI substrate, or an insulating substrate different from the insulating substrate 1805. The signal line driving circuit 1801 is connected to the signal lines S1 to Sm via a printed circuit board such as an FPC. However, the signal line driving circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the functions of the signal line driving circuit 1801 may be formed on the insulating substrate 1805. However, the signal line driving circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the functions of the signal line driving circuit 1801 may be formed on the insulating substrate 1805. However, the signal line driving circuit 1801 may be formed on the insulating substrate 1805, or a circuit constituting a part of the functions of the signal line driving circuit 1801 may be formed on the insulating substrate 1805.

[0167] Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). Note that wirings, electrodes, conductive layers, conductive films, terminals, etc. are made of one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), oxygen (O), or a compound or alloy material having one or more elements selected from the above group as components (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO)). It is desirable to be formed of aluminum-neodymium (Al-Nd), magnesium-silver (Mg-Ag), molybdenum-niobium ( Mo-Nb), etc.). Or, wiring, electrodes, conductive layers, conductive films , terminals, etc. are desirably formed having substances such as combinations of these compounds. Or, compounds of one or more elements selected from the above group and silicon (silicide) (e.g., aluminum silicide, molybdenum silicide, nickel silicide, etc.), compounds of one or more elements selected from the above group and nitrogen (e.g., titanium nitride, tantalum nitride, molybdenum nitride, etc.) are desirably formed.

[0168] Note that silicon (Si) may contain n-type impurities (such as phosphorus) or p-type impurities (such as boron). By silicon containing impurities, the conductivity can be improved. Or, it becomes possible to have the same behavior as a normal conductor. Therefore, it becomes easier to use for wiring, electrodes, etc.

[0169] Note that for silicon, silicon with various crystallinities such as single crystal, polycrystal (polysilicon), microcrystal (microcrystalline silicon) can be used. Or, amorphous ( amorphous silicon) etc. can also be used. By using single crystal silicon or polycrystalline silicon, the resistance of wiring, electrodes, conductive layers, conductive films, terminals, etc. can be reduced. By using amorphous silicon or microcrystalline silicon, wiring etc. can be formed in a simple process.

[0170] Note that since aluminum or silver has high conductivity, signal delay can be reduced. Furthermore, since it is easy to etch, it is easy to pattern and can be microfabricated. .

[0171] Note that since copper has a high conductivity, signal delay can be reduced. When using copper, it is desirable to form a laminated structure to improve adhesion.

[0172] Note that molybdenum or titanium has advantages such as not causing defects, being easy to etch, and having high heat resistance even when in contact with an oxide semiconductor (such as ITO or IZO) or silicon. Therefore, it is desirable.

[0173] Note that tungsten has advantages such as high heat resistance, so it is desirable.

[0174] Note that neodymium has advantages such as high heat resistance, so it is desirable. In particular, when forming an alloy of neodymium and aluminum, the heat resistance is improved and aluminum is less likely to cause hillocks.

[0175] Note that silicon has advantages such as being able to be formed simultaneously with the semiconductor layer of a transistor and having high heat resistance, so it is desirable.

[0176] Note that ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), and tin oxide (SnO) have light-transmitting properties, so they can be used for parts that transmit light. For example, they can be used as pixel electrodes or common electrodes.

[0177] Note that wiring, electrodes, conductive layers, conductive films, terminals, etc. may have a single-layer structure or a multilayer structure. By using a single-layer structure, the manufacturing of wiring, electrodes, conductive layers, conductive films, terminals, etc. The manufacturing process can be simplified, the number of process days can be reduced, and the cost can be lowered. . Alternatively, by forming a multilayer structure, while taking advantage of the merits of each material, the demerits can be reduced, and wiring, electrodes, etc. with good performance can be formed. For example, by including a low-resistance material (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. Also, by forming a laminated structure in which a material with low heat resistance is sandwiched between materials with high heat resistance, while taking advantage of the merits of the material with low heat resistance, the heat resistance of the wiring, electrodes, etc. can be increased. For example, it is desirable to form a laminated structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, etc.

[0178] Also, when wirings, electrodes, etc. are in direct contact with each other, they may have an adverse effect on each other. For example, one wiring, electrode, etc. may enter the material of the other wiring, electrode, etc. and change its properties, resulting in the inability to achieve the original purpose. Or, a high-resistance portion may be formed. Or, problems may occur during manufacturing, making it impossible to manufacture normally. In such cases, it is advisable to sandwich or cover materials that are prone to reaction with materials that are less prone to reaction with a laminated structure. For example, when connecting ITO and aluminum, it is desirable to sandwich a titanium, molybdenum, neodymium alloy between ITO and aluminum. Also, when connecting silicon and aluminum, it is desirable to sandwich a titanium, molybdenum, neodymium alloy between ITO and aluminum.

[0179] Note that wiring refers to something in which a conductor is arranged. It may extend linearly or not extend. It may be arranged short without [a certain situation]. Therefore, the electrode is included in the wiring.

[0180] Note that the wiring and electrodes described above can also be applied to other display devices, shift registers, and pixels. It can be done.

[0181] Note that the signal line driving circuit 1801 inputs a voltage or current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the video signal may have the positive and negative electrodes inverted every frame (frame inversion driving), or the positive and negative electrodes may be inverted every line (gate line inversion driving), or the positive and negative electrodes may be inverted every column (source line inversion driving), or the positive and negative electrodes may be inverted every line and every column (dot line inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or line sequential driving. Further, the signal line driving circuit 1801 may input not only a video signal but also a constant voltage such as a precharge voltage to the signal lines S1 to Sm. It is desirable to input a constant voltage such as a precharge voltage every one gate selection period or every one frame. Note that the scanning line driving circuit 1802 inputs a signal to the scanning lines G1 to Gn and selects (hereinafter also referred to as scans) the scanning lines G1 to Gn in order from the first row. Then, the scanning line driving circuit 180 2 selects a plurality of pixels 1803 connected to the selected scanning line. Here, the period during which one scanning line is selected is called one gate selection period, and the period during which the scanning line is not selected is called a non-selection period. Further, the signal output by the scanning line driving circuit 1802 to the scanning line is a scan signal. Note that the signal line driving circuit 1801 inputs a voltage or current as a video signal to the signal lines S1 to Sm. However, the video signal may be a digital signal or an analog signal. Further, the video signal may have the positive and negative electrodes inverted every frame (frame inversion driving), or the positive and negative electrodes may be inverted every line (gate line inversion driving), or the positive and negative electrodes may be inverted every column (source line inversion driving), or the positive and negative electrodes may be inverted every line and every column (dot line inversion driving). Further, the video signal may be input to the signal lines S1 to Sm by dot sequential driving or line sequential driving. Further, the signal line driving circuit

[0182] Note that the scanning line driving circuit 1802 inputs a signal to the scanning lines G1 to Gn and selects (hereinafter also referred to as scans) the scanning lines G1 to Gn in order from the first row. Then, the scanning line driving circuit 180 2 selects a plurality of pixels 1803 connected to the selected scanning line. Here, the period during which one scanning line is selected is called one gate selection period, and the period during which the scanning line is not selected is called a non-selection period. Further, the signal output by the scanning line driving circuit 1802 to the scanning line is a scan signal. Here, the period during which one scanning line is selected is called one gate selection period, and the period during which the scanning line is not selected is called a non-selection period. Further, the signal output by the scanning line driving circuit 1802 to the scanning line is a scan signal. is called a signal. Further, the maximum value of the scanning signal is greater than the maximum value of the video signal or the maximum voltage of the signal line, and the minimum value of the scanning signal is smaller than the minimum value of the video signal or the minimum voltage of the signal line. This is characterized by the above.

[0183] When the pixel 1803 is selected, a video signal is input to the pixel 1803 via the signal line from the signal line driving circuit 1801. Further, when the pixel 1803 is not selected, the pixel 1803 holds the video signal (the potential corresponding to the video signal) input during the selection period.

[0184] Although not shown in the figure, a plurality of potentials and a plurality of signals are supplied to the signal line driving circuit 1801 and the scanning line driving circuit 1802.

[0185] Next, the operation of the display device shown in FIG. 18 will be described with reference to the timing chart of FIG. 19. Further, in FIG. 19, a frame period corresponding to the period for displaying an image for one screen is shown. However, the frame period is not particularly limited, but it is preferably at least 1 / 60 second or less so that a person viewing the image does not feel flicker.

[0186] In the timing chart of FIG. 19, the timing at which the scanning line G1 in the first row, the scanning line Gi in the i-th row, the scanning line Gi + 1 in the (i + 1)-th row, and the scanning line Gn in the n-th row are respectively selected is shown.

[0187] In FIG. 19, for example, the scanning line Gi in the i-th row is selected, and a plurality of pixels 1803 connected to the scanning line Gi are selected. And a plurality of pixels 1803 connected to the scanning line Gi are ​​​​​​​​​​​Each inputs a video signal and holds a potential corresponding to the video signal. Then, the scanning line Gi of the i-th row becomes non-selected, the scanning line Gi+1 of the (i + 1)-th row is selected, and a plurality of pixels 1803 connected to the scanning line Gi+1 are selected. And, the plurality of pixels 1803 connected to the scanning line Gi+1 each input a video signal and hold a potential corresponding to the video signal. In this way, within one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1803 connected to each scanning line are also sequentially selected. And, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal. The scanning line Gi becomes non-selected, the scanning line Gi+1 of the (i + 1)-th row is selected, and a plurality of pixels 1803 connected thereto are selected. And, the plurality of pixels 1803 connected to the scanning line Gi+1 each input a video signal and hold a potential corresponding to the video signal. In this way, within one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1803 connected to each scanning line are also sequentially selected. And, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal. As described above, within one frame period, the scanning lines G1 to Gn are sequentially selected, and the pixels 1803 connected to each scanning line are also sequentially selected. And, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal. And, the pixels 1803 connected to each scanning line are also sequentially selected. And, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal. And, the plurality of pixels 1803 connected to each scanning line each input a video signal and hold a potential corresponding to the video signal. do so.

[0188] From the above, the display device in FIG. 18 can input a video signal independently to all pixels, so that the function as an active matrix type display device can be sufficiently obtained. Furthermore, since the display device in FIG. 18 uses the shift register of the present embodiment as the scanning line driving circuit 1802, suppression of the threshold shift of the transistor can be achieved. The display device in FIG. 18 can achieve extended life. The display device in FIG. 18 can achieve improvement in driving ability. The display device in FIG. 18 can suppress malfunction. The display device in FIG. 18 can simplify the process.

[0189] Furthermore, since the display device in FIG. 18 forms the signal line driving circuit 1801 that requires high-speed operation, the scanning line driving circuit 1802, and the pixels 1803 on separate substrates, the semiconductor layer of the transistor included in the scanning line driving circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 Furthermore, since the display device in FIG. 18 forms the signal line driving circuit 1801 that requires high-speed operation, the scanning line driving circuit 1802, and the pixels 1803 on separate substrates, the semiconductor layer of the transistor included in the scanning line driving circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 Furthermore, since the display device in FIG. 18 forms the signal line driving circuit 1801 that requires high-speed operation, the scanning line driving circuit 1802, and the pixels 1803 on separate substrates, the semiconductor layer of the transistor included in the scanning line driving circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 can be simplified.

[0190] Furthermore, since the display device in FIG. 18 forms the signal line driving circuit 1801 that requires high-speed operation, the scanning line driving circuit 1802, and the pixels 1803 on separate substrates, the semiconductor layer of the transistor included in the scanning line driving circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 circuit 1802 and the semiconductor layer of the transistor included in the pixels 1803 Thus, amorphous silicon can be used. Therefore, the manufacturing process can be simplified, and the manufacturing cost can be reduced. Furthermore, the display device in FIG. 18 can achieve an improvement in yield. Additionally, the display device of this embodiment can be made larger. Alternatively, polysilicon or polycrystalline silicon can be used as the semiconductor layer of the transistor to simplify the manufacturing process. When the signal line driving circuit 1801, the scanning line driving circuit 1802, and the pixel 1803 are formed on the same substrate, polysilicon or polycrystalline silicon may be used as the semiconductor layer of the transistors included in the scanning line driving circuit 1802 and the semiconductor layer of the transistors included in the pixel 1803. Note that when the pixel is selected as shown in FIG. 18 and a video signal can be written independently to the pixel, the number and arrangement of each driving circuit are not limited to those in FIG. 18. For example, as shown in FIG. 20, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 1802 shown in FIG. 18 and scan the scanning lines G1 to Gn at the same timing. Further, the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be referred to as the first driving circuit and the second driving circuit, respectively. The display device in FIG. 20 includes the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b.

[0191] When the signal line driving circuit 1801, the scanning line driving circuit 1802, and the pixel 1803 are formed on the same substrate, polysilicon or polycrystalline silicon may be used as the semiconductor layer of the transistors included in the scanning line driving circuit 1802 and the semiconductor layer of the transistors included in the pixel 1803. When the pixel is selected as shown in FIG. 18 and a video signal can be written independently to the pixel, the number and arrangement of each driving circuit are not limited to those in FIG. 18. For example, as shown in FIG. 20, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 1802 shown in FIG. 18 and scan the scanning lines G1 to Gn at the same timing. Further, the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be referred to as the first driving circuit and the second driving circuit, respectively. The display device in FIG. 20 includes the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b.

[0192] Note that when the pixel is selected as shown in FIG. 18 and a video signal can be written independently to the pixel, the number and arrangement of each driving circuit are not limited to those in FIG. 18. For example, as shown in FIG. 20, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 1802 shown in FIG. 18 and scan the scanning lines G1 to Gn at the same timing. Further, the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be referred to as the first driving circuit and the second driving circuit, respectively.

[0193] For example, as shown in FIG. 20, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 1802 shown in FIG. 18 and scan the scanning lines G1 to Gn at the same timing. Further, the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be referred to as the first driving circuit and the second driving circuit, respectively. The display device in FIG. 20 includes the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. Note that when the pixel is selected as shown in FIG. 18 and a video signal can be written independently to the pixel, the number and arrangement of each driving circuit are not limited to those in FIG. 18. For example, as shown in FIG. 20, the scanning lines G1 to Gn may be scanned by the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 1802 shown in FIG. 18 and scan the scanning lines G1 to Gn at the same timing. Further, the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b may be referred to as the first driving circuit and the second driving circuit, respectively.

[0194] The display device in FIG. 20 includes the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. Even if a defect occurs in one of 2b, since the other of the scanning line driving circuit 2002a and the second scanning line driving circuit 2002b can scan the scanning lines G1 to Gn, redundancy can be achieved. Furthermore, the display device in FIG. 20 can reduce the load (wiring resistance of the scanning lines and parasitic capacitance of the scanning lines) of the first scanning line driving circuit 2002a and the load of the second scanning line driving circuit 2002b to about half compared to FIG. 18. Therefore, the delay and droop of the signals (output signals of the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b) input to the scanning lines G1 to Gn can be reduced. Furthermore, since the load of the first scanning line driving circuit 2002a and the load of the second scanning line driving circuit 2002b of the display device in FIG. 20 are reduced, the scanning lines G1 to Gn can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed, enlargement or high definition of the panel can be enabled. Furthermore, the advantage of the display device in FIG. 20 is more effective when amorphous silicon is used for the semiconductor layer of the transistors included in the first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b. Note that the parts common to the configuration of FIG. 18 are denoted by common reference numerals and their description is omitted. As another example, FIG. 8 shows a display device capable of writing a video signal to pixels at high speed. In the display device of FIG. 8, the pixels 1803 in the odd-numbered rows receive the video signal from the signal lines in the odd-numbered columns, and the pixels 1803 in the even-numbered rows receive the video signal from the signal lines in the even-numbered columns. Furthermore, in the display device of FIG. 8, the scanning lines in the odd-numbered stages among the scanning lines G1 to Gn are scanned by the first scanning line driving circuit 802a, and the scanning lines in the even-numbered stages among the scanning lines G1 to Gn are the second

[0195] circuit 802a, and the scanning lines in the even-numbered stages among the scanning lines G1 to Gn are the second It is scanned by the scanning line driving circuit 802b of 2. Further, the start signal input to the first scanning line driving circuit 802 b is input with a delay of 1 / 4 cycle of the clock signal compared to the start signal input to the first scanning line driving circuit 802a .

[0196] Note that the display device in FIG. 8 can perform dot inversion driving by simply inputting a positive video signal and a negative video signal to each signal line for each column in one frame period. Furthermore, the display device in FIG. 8 can perform frame inversion driving by inverting the polarity of the video signal input to each signal line every one frame period. The operation of the display device in FIG. 8 will be described with reference to the timing chart in FIG. 9. In the timing chart of FIG. 9, the scanning line G1 in the first row, the scanning line Gi-1 in the (i-1)-th row, the scanning line Gi in the i-th row, the scanning line Gi+1 in the (i+1)-th row, and the scanning line Gn in the n-th row are each selected.

[0197] The timing for this is shown. Further, in the timing chart of FIG. 9, one selection period is divided into a selection period a and a selection period b. Further, in the timing chart of FIG. 9, the case where the display device in FIG. 8 performs dot inversion driving and frame inversion driving will be described. In FIG. 9, for example, the selection period a of the scanning line Gi in the i-th row overlaps with the selection period b of the scanning line Gi-1 in the (i-1)-th row, and the selection period Tb of the scanning line Gi in the i-th row overlaps with the selection period a of the scanning line Gi+1 in the (i+1)-th row. Therefore, in the selection period a, the same video signal as that input to the pixel 1803 at the (i-1)-th row and the (j+1)-th column is input to the pixel 1 803 at the i-th row and the j-th column. Further, in the selection period b, the video signal input to the pixel 1803 at the i-th row and the j-th column is input . . .

[0198] In FIG. 9, for example, the selection period a of the scanning line Gi in the i-th row overlaps with the selection period b of the scanning line Gi-1 in the (i-1)-th row, and the selection period Tb of the scanning line Gi in the i-th row overlaps with the selection period a of the scanning line Gi+1 in the (i+1)-th row. Therefore, in the selection period a, the same video signal as that input to the pixel 1803 at the (i-1)-th row and the (j+1)-th column is input to the pixel 1 803 at the i-th row and the j-th column. Further, in the selection period b, the video signal input to the pixel 1803 at the i-th row and the j-th column is input . to the pixel 1803 at the i-th row and the j-th column. Further, in the selection period b, the video signal input to the pixel 1803 at the i-th row and the j-th column is input to the pixel 1803 at the i-th row and the j-th column. Further, in the selection period b, the video signal input to the pixel 1803 at the i-th row and the j-th column is input A video signal similar to the one to be output is input to the pixel 1803 at the (i + 1)-th row and (j + 1)-th column. Also, the video signal input to the pixel 1803 during the selection period b is the original video signal, and the video signal input to the pixel 1803 during the selection period a is the video signal for the precharge of the pixel 1803. Therefore, each pixel 1803 is precharged by the video signal input to the pixel 1803 at the (i - 1)-th row and (j + 1)-th column during the selection period a, and then the original (i-th row and j-th column) video signal is input during the selection period b.

[0199] From the above, the display device in FIG. 8 can write a video signal to the pixel 1803 at high speed, so that enlargement or high definition can be easily achieved. Furthermore, in the display device in FIG. 8, since the same-polarity video signal is input to each signal line during one frame period, the charge and discharge of each signal line are small, and low power consumption can be achieved. Furthermore, in the display device in FIG. 8, since the load of the IC for supplying the video signal is significantly reduced, heat generation of the IC and power consumption of the IC can be reduced. Furthermore, in the display device in FIG. 8, the driving frequencies of the first scanning line driving circuit 802a and the second scanning line driving circuit 802b can be reduced to about half.

[0200] Note that the display device of the present embodiment can perform various driving methods depending on the configuration and driving method of the pixel 1803. For example, during one frame period, the scanning line driving circuit may scan the scanning line a plurality of times.

[0201] Note that the display devices in FIGS. 8, 18, and 20 may have additional wiring or the like depending on the configuration of the pixel 1803. For example, a power supply line, a capacitance line, and a new scanning line that are maintained at a constant potential ​​You may also add etc. However, when newly adding a scanning line, you may newly add a scanning line driving circuit to which the shift register of this embodiment is applied. As another example, dummy scanning lines, signal lines, power supply lines, or capacitor lines may be arranged in the pixel portion. In addition, although various figures have been used in this embodiment to describe, the content or part of the content described in each figure can also be applied to the content or part of the content described in another figure. Or they can be combined. Furthermore, in the figures described so far, for each part, by combining with another part, more figures can be constructed. Similarly, the content or part of the content described in each figure of this embodiment can also be applied to the content or part of the content described in the figures of another embodiment. Or they can be combined. Furthermore, in the figures of this embodiment, for each part, by combining with the parts of another embodiment, more figures can be constructed.

[0202] Note that this embodiment shows an example when implementing, slightly modifying, partially changing, improving, describing in detail, applying, or an example of related parts of the content described in other embodiments. Therefore, the content described in other embodiments can also be applied to this embodiment. Or they can be combined. In this embodiment, a flip - flop different from that in Embodiment 1 and having the flip - flop are used.

[0203]

[0204]

[0205] (Embodiment 2) The configuration and driving method of a driving circuit and a display device having the driving circuit will be described. For components similar to those in Embodiment 1, the same reference numerals are used, and detailed descriptions of the same parts or parts having similar functions are omitted. For components similar to those in Embodiment 1, the same reference numerals are used, and detailed descriptions of the same parts or parts having similar functions are omitted. For components similar to those in Embodiment 1, the same reference numerals are used, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0206] The configuration of the flip - flop in this embodiment can use the same flip - flop configuration as in Embodiment 1. However, the timing for driving the flip - flop is different from that in Embodiment 1. Therefore, in this embodiment, the description of the flip - flop configuration is omitted. The configuration of the flip - flop in this embodiment can use the same flip - flop configuration as in Embodiment 1. However, the timing for driving the flip - flop is different from that in Embodiment 1. Therefore, in this embodiment, the description of the flip - flop configuration is omitted. The configuration of the flip - flop in this embodiment can use the same flip - flop configuration as in Embodiment 1. However, the timing for driving the flip - flop is different from that in Embodiment 1. Therefore, in this embodiment, the description of the flip - flop configuration is omitted.

[0207] The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented. The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented. The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented. The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented. The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented. The case where the driving timing of this embodiment is applied to the flip - flop in FIG. 1 will be described. However, the driving timing of this embodiment can also be freely combined with the flip - flops in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), or 21(C) and implemented. Furthermore, the driving timing of this embodiment can also be freely combined with the driving timing described in Embodiment 1 and implemented.

[0208] Next, the operation of the flip - flop in this embodiment will be described with reference to the flip - flop in FIG. 1 and the timing chart in FIG. 31. Furthermore, the timing chart in FIG. 31 will be divided into a selection period and a non - selection period for description. Furthermore, the non - selection period will be divided into a first non - selection period, a second non - selection period, a set period a, a set period b, and a reset period for description. Next, the operation of the flip - flop in this embodiment will be described with reference to the flip - flop in FIG. 1 and the timing chart in FIG. 31. Furthermore, the timing chart in FIG. 31 will be divided into a selection period and a non - selection period for description. Furthermore, the non - selection period will be divided into a first non - selection period, a second non - selection period, a set period a, a set period b, and a reset period for description. Next, the operation of the flip - flop in this embodiment will be described with reference to the flip - flop in FIG. 1 and the timing chart in FIG. 31. Furthermore, the timing chart in FIG. 31 will be divided into a selection period and a non - selection period for description. Furthermore, the non - selection period will be divided into a first non - selection period, a second non - selection period, a set period a, a set period b, and a reset period for description. Next, the operation of the flip - flop in this embodiment will be described with reference to the flip - flop in FIG. 1 and the timing chart in FIG. 31. Furthermore, the timing chart in FIG. 31 will be divided into a selection period and a non - selection period for description. Furthermore, the non - selection period will be divided into a first non - selection period, a second non - selection period, a set period a, a set period b, and a reset period for description. Furthermore, the selection period will be divided into a selection period a and a selection period b for description. Furthermore, during the non - selection period, the set period a, the set period b, the selection period a, the selection period b, and the reset period will be Furthermore, the selection period will be divided into a selection period a and a selection period b for description. Furthermore, during the non - selection period, the set period a, the set period b, the selection period a, the selection period b, and the reset period will be During the except operation period, the first non-selection period and the second non-selection period are repeated.

[0209] In addition, in FIG. 31, signal 3121, signal 3125, signal 3126, potential 3141, elec trical potential 3142, signal 3122, and signal 3123 are respectively the signals input to the first wiring 121, the signal input to the fifth wiring 125, the signal input to the sixth wiring 126, the potential of node 141, the potential of node 142, the signal input to the second wiring 122, and the signal output from the third wiring 123.

[0210] In addition, signal 3121, signal 3125, signal 3126, potential 3141, potential 3142, signal 3122, and signal 3123 correspond to signal 221, signal 225, signal 226, potential 241, potential 242, signal 222, and signal 223 shown in FIG. 2 and have similar characteristics.

[0211] In addition, the flip-flop of this embodiment basically performs the same operation as the flip-flop described in Embodiment 1. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that the timing at which the H signal is input to the first wiring 121 is delayed by 1 / 4 cycle of the clock signal.

[0212] In addition, the flip-flop of this embodiment performs the same operation as the first non-selection period and the second non-selection period of the flip-flop described in Embodiment 1 during the first non-selection period and the second non-selection period. Furthermore, the flip-flop of this embodiment performs the same operation as the second non-selection period during the set period a. Furthermore, the flip-flop of this embodiment ​​​​​​During the reset period, it performs the same operation as the reset period of the flip-flop described in Embodiment 1 and performs a similar operation. Furthermore, the flip-flop of this embodiment performs the same operation as the selection period of the flip-flop described in Embodiment 1 during the selection period a and the selection period b. However, the flip-flop of this embodiment is different from the flip-flop of Embodiment 1 in that an H signal is input to the first wiring 121 during the selection period a. However, even if an H signal is input to the first wiring 121 during the selection period a, since the fifth transistor 105 is off, it has little effect on the operation of this embodiment. Therefore, a detailed description of the flip-flop of this embodiment during the set period a, the set period b, the selection period a, the selection period b, the reset period, the first non-selection period, and the second non-selection period is omitted. It should be noted that the flip-flop of this embodiment can reduce the layout area in the same manner as the flip-flop shown in Embodiment 1. Furthermore, the flip-flop of this embodiment can suppress the threshold shift of the transistor. Furthermore, the flip-flop of this embodiment can simplify the process.

[0213] It should be noted that by applying the timing chart shown in FIG. 32 to the flip-flop of this embodiment, the flip-flop of this embodiment can significantly shorten the fall time of the output signal. This is because by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101. It should be noted that by applying the timing chart shown in FIG. 32 to the flip-flop of this embodiment, the flip-flop of this embodiment can significantly shorten the fall time of the output signal. This is because by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101. Furthermore, the flip-flop of this embodiment can suppress the threshold shift of the transistor. Furthermore, the flip-flop of this embodiment can simplify the process.

[0214] It should be noted that by applying the timing chart shown in FIG. 32 to the flip-flop of this embodiment, the flip-flop of this embodiment can significantly shorten the fall time of the output signal. This is because by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101. This is because an L signal can be input to the third wiring 123 via the first transistor 101 by shifting the timing at which the signal 3122 (reset signal) becomes the H level. That is, by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101. That is, by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101. That is, by shifting the timing at which the signal 3122 (reset signal) becomes the H level, an L signal can be input to the third wiring 123 via the first transistor 101.

[0215] Next, the configuration and driving method of the shift register having the flip-flop according to the above-described embodiment will be described.

[0216] The configuration of the shift register according to the present embodiment will be described with reference to FIG. 33. The shift register in FIG. 33 has n flip-flops (flip-flop 3301_1 to flip-flop 3301_n).

[0217] The connection relationship of the shift register in FIG. 33 will be described. In the shift register of FIG. 33, among the flip-flops 3301_i at the i-th stage (any one of the flip-flops 3301_1 to 3301_n), the flip-flop 3301_4N-3 at the (4N-3)-th stage (where N is a natural number of 1 or more) and the flip-flop 3301_4N-1 at the (4N-1)-th stage are connected to the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the eleventh wiring 3321_i-1, the eleventh wiring 3321_i, and the eleventh wiring 3321_i+2. Further, the flip-flop 3301_4N-2 at the (4N-2)-th stage and the flip-flop 3301_4N at the 4N-th stage are connected to the third wiring 3313, the fifth wiring 3315, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the eleventh wiring 3321_i-1, the eleventh wiring 3321_i, and the eleventh wiring 3321_i+2. However, the flip-flop 3301_1 at the first stage is connected to the first wiring 3111, the second wiring 3312, the fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the eleventh wiring 3321_1, and the eleventh wiring 3321_3. Further, the flip-flop 3101_n-1 at the (n-1)-th stage is connected to the second wiring 3312. ​​​​​​​​​​​​​​​​ The fourth wiring 3314, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318, the tenth wiring 3320, the eleventh wiring 3321_n - 2, the eleventh wiring 3321_n - 1 are connected. Further, the flip - flop 3301_n in the n - th stage is connected to the third wiring 3313 the fifth wiring 3315, the sixth wiring 3316, the seventh wiring 3317, the eighth wiring 3318 the ninth wiring 3319, the eleventh wiring 3321_n - 1, the eleventh wiring 3321_n. It continues.

[0218] The first wiring 3311 is connected to the first wiring 121 shown in FIG. 1 of the flip - flop 3301_1. The second wiring 3312 is connected to the fifth wiring 125 shown in FIG. 1 in the flip - flop 3301_4N - 3, and is connected to the sixth wiring 126 shown in FIG. 1 in the flip - flop 3301_4N - 1. The third wiring 3313 is connected to the fifth wiring 125 shown in FIG. 1 in the flip - flop 3301_4N - 2, and is connected to the sixth wiring 126 shown in FIG. 1 in the flip - flop 3301_4N. The fourth wiring 3314 is connected to the sixth wiring 126 shown in FIG. 1 in the flip - flop 3301_4N - 3, and is connected to the fifth wiring 125 shown in FIG. 1 in the flip - flop 3301_4N - 1. The fifth wiring 3315 is connected to the sixth wiring 126 shown in FIG. 1 in the flip - flop 3301_4N - 2, and is connected to the fifth wiring 125 shown in FIG. 1 in the flip - flop 3301_4N. The sixth wiring 3306 is connected to the seventh wiring 127 shown in FIG. 1 in all - stage flip - flops. The seventh wiring 3317 is connected to the eighth wiring 128 shown in FIG. 1 in all - stage flip - flops. The eighth wiring 3318, the fourth wiring 124 shown in FIG. 1 in all - stage flip - flops, the ninth wiring in all - stage flip - flops, the fourth wiring 124 shown in FIG. 1, the ninth wiring in all - stage flip - flops, the fourth wiring 124 shown in FIG. 1, the ninth wiring in all - stage flip - flops, the fourth wiring 124 shown in FIG. 1, the ninth wiring in all - stage flip - flops, the fourth wiring 124 shown in FIG. 1, the ninth wiring in all - stage flip - flops, the fourth wiring 124 shown in FIG. 1, the ninth wiring 3318, the fourth wiring 124 shown in FIG. 1 in all - stage flip - flops, the ninth wiring is connected to the 129th wire, the 10th wiring 130, and the 11th wiring 131. The 9th wiring 331 9 is connected to the 2nd wiring 122 shown in FIG. 1 of the flip-flop 3301_n. The 1st wiring 3120 is connected to the 2nd wiring 122 shown in FIG. 1 of the flip-flop 3301_n-1 is connected to. The 11th wiring 3321_i is connected to the 2nd wiring 122 shown in FIG. 1 of the flip-flop 3301_i-2 and the 3rd wiring 123 shown in FIG. 1 of the flip-flop 3301_i, and the 1st wiring 121 shown in FIG. 1 of the flip-flop 3301_i+1 is connected to. However, the 11th wiring 3321_1 is the 3rd shown in FIG. 1 of the flip-flop 3301_1 is connected to the wiring 123 and the 1st wiring 121 shown in FIG. 1 of the flip-flop 3301_2 is connected. Furthermore, the 11th wiring 3321_2 is shown in FIG. 1 of the flip-flop 3301_2 is connected to the 3rd wiring 123 shown and the 1st wiring 12 shown in FIG. 1 of the flip-flop 3301_3 1 is connected. Furthermore, the 11th wiring 3321_n is connected to the 3rd wiring 123 shown in FIG. 1 of the flip-flop 3301_n is connected.

[0219] Note that the potential of V1 is supplied to the 6th wiring 3316 and the 7th wiring 3317, respectively, and the potential of V2 is supplied to the 8th wiring 3318.

[0220] Note that signals are input to the 1st wiring 3311, the 2nd wiring 3312, the 3rd wiring 3314, the 5th wiring 33 15, the 9th wiring 3319, and the 10th wiring 3320, respectively. The signal input to the 1st wiring 3311 is a start signal, the signal input to the 2nd wiring 3312 is the 1st clock signal, and the signal input to the 3rd wiring 3313 is the 2nd clock signal signal, and the signal input to the 4th wiring 3314 is the 2nd clock signal It is a lock signal, and the signal input to the fourth wiring 3314 is the third clock signal. The signal input to the fifth wiring 3315 is the fourth clock signal, and the ninth wiring 3319 The signal input to is the first reset signal, and the signal input to the tenth wiring 3320 Is the second reset signal. Further, the first wiring 3311, the second wiring 3312, and the third Of the wiring 3314, the fifth wiring 3315, the ninth wiring 3319, and the tenth wiring 3320 The signals input to each are digital signals with the potential of the H signal being V1 and the potential of the L signal being V2. There is.

[0221] Note that various signals, currents, or Voltages may be input to the first wiring 3311 to the tenth wiring 3320, respectively.

[0222] Note that signals are output from the eleventh wiring 3321_1 to the eleventh wiring 3321_n. For example, the signal output from the eleventh wiring 3321_i is the output signal of the flip-flop 3301_ i. Further, the signal output from the eleventh wiring 3321_i is the input signal of the flip Of the flop 3301_i + 1 and the reset Signal of the flip-flop 3301_i - 2.

[0223] Next, the operation of the shift register shown in FIG. 33 will be described with reference to the timing chart of FIG. 35 and The timing chart of FIG. 36. Here, the timing chart of FIG. 35 Is divided into a scanning period and a retrace period. The scanning period is from the output of the selection signal from the eleventh wiring 3311_1 To the end of the output of the selection signal from the eleventh wiring 3311_n. The retrace period is from the end of the output of the selection signal from the eleventh wiring 3311_n This is the period until the output of the selection signal from the 11th wiring 3311_1 starts.

[0224] In addition, in FIG. 35, the signal 3511 input to the first wiring 3311, the second wiring 33 the signal 3512 input to 12, the signal 3513 input to the third wiring 3313, the fourth the signal 3514 input to the wiring 3314, the signal 3515 input to the fifth wiring 3315 , the signal 3519 input to the ninth wiring 3319, the signal input to the tenth wiring 3320 3520, the signal 3521_1 output to the 11th wiring 3321_1 and the 11th wiring the signal 3521_n output to 3321_n are shown. Further, in FIG. 36, the first the signal 3611 input to the wiring 3311, the signal output to the 11th wiring 3321_1 3621_1, the signal 3621_i-1 output to the 11th wiring 3321_i-1, the the signal 3621_i output to the 11th wiring 3321_i, the 11th wiring 3321_i+1 the signal 3621_i+1 output to and the signal 36 output to the 11th wiring 3321_n 21_n are shown.

[0225] As shown in FIG. 36, for example, when the flip-flop 3301_i-1 enters the selection period a an H signal is output from the 11th wiring 3321_i-1. At this time, the flip-flop 3 301_i enters the set period a. After that, when the flip-flop 3301_i-1 enters the selection period b and the H signal continues to be output from the 11th wiring 3321_i-1. At this time the flip-flop 3301_i enters the selection period a. After that, when the flip-flop 33 01_i-1 enters the reset period and the H signal is output from the 11th wiring 3321_i-1 This occurs, and the flip-flop 3301_i enters the selection period b. That is, in the shift register of this embodiment, H signals are output sequentially from the flip-flop 3301_i-1. However, there is a period during which the selection period b of the flip-flop 3301_i-1 overlaps with the selection period a of the flip-flop 3301_i.

[0226] When the timing chart of FIG. 32 is applied to the flip-flop in this specification, the configuration of the shift register may be as shown in FIG. 34. For example, in the shift register of FIG. 34, the wiring 122 shown in FIG. 1 of the flip-flop 3301_i in the i-th stage is connected to the 11th wiring 3321_i + 3. Further, the second wiring 122 shown in FIG. 1 of the flip-flop 3301_n-2 is connected to the 12th wiring 3322 to which the third reset signal is input. Note that parts common to FIG. 33 are denoted by common reference numerals and their description is omitted.

[0227] Since the shift register of this embodiment applies the flip-flop of this embodiment, it is possible to achieve suppression of transistor threshold shift, extended lifespan, improved driving ability, suppression of malfunction, and simplification of the process.

[0228] The shift register of this embodiment can be implemented in any combination with the shift register described in Embodiment 1. For example, the shift register of this embodiment can be implemented in any combination with the shift registers of FIGS. 13, 14, 15, and 17. Specifically, for the shift register of this embodiment, buffers may be connected to the 11th wirings 3321_1 to 3321_n, a reset signal may be generated internally, or dummy flip-flops may be provided. The flip-flop may be arranged. As already described, the parts common to Embodiment 1 are denoted by the same reference numerals and their description is omitted.

[0229] Subsequently, the configuration and driving method of the display device having the shift register according to the present embodiment described above will be described. However, the display device according to the present embodiment only needs to have at least the flip-flop of the present embodiment.

[0230] The configuration of the display device according to the present embodiment will be described with reference to FIG. 16. In the display device of FIG. 16 , the scanning lines G1 to Gn are scanned by the scanning line driving circuit 1602. Further, in the display device of FIG. 1 6, the video signal is input to the pixels 1803 in the odd rows from the signal lines for the odd rows, and the video signal is input to the pixels 1803 in the even rows from the signal lines for the even rows. The parts common to the configuration of FIG. 1 8 are denoted by the same reference numerals and their description is omitted.

[0231] Note that, in the display device of FIG. 16, by applying the shift register of the present embodiment to the scanning line driving circuit 1602 , the same operation as that of the display device of FIG. 8 can be performed by one scanning line driving circuit. Therefore, the display device of FIG. 16 can write the video signal to the pixels at high speed. Furthermore, the display device of FIG. 16 can be made larger or have higher definition. . Furthermore, the display device of FIG. 16 can further reduce power consumption. Furthermore, the display device of FIG. 16 can suppress the heat generation of the IC. Furthermore, the display device of FIG. 16 can achieve power saving of the IC.

[0232] Note that, as shown in FIG. 22, the scanning lines G1 to Gn are connected to the first scanning line driving circuit 2202a and may be scanned by the second scanning line driving circuit 2202b. The first scanning line driving circuit 2002a and the second scanning line driving circuit 2002b have the same configuration as the scanning line driving circuit 16 02 shown in FIG. 16, and scan the scanning lines G1 to Gn at the same timing. Furthermore , the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b may be referred to as the first driving circuit and the second driving circuit, respectively.

[0233] The display device of FIG. 22 can have redundancy because even if one of the first scanning line driving circuit 2202a and the second scanning line driving circuit 220 2b has a defect, the other of the scanning line driving circuit 2202a and the second scanning line driving circuit 2202b can scan the scanning lines G1 to Gn. Furthermore, since the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b of the display device of FIG. 22 scan the scanning lines G1 to Gn, the load (wiring resistance of the scanning line and parasitic capacitance of the scanning line) of the first scanning line driving circuit 2202a and the load of the second scanning line driving circuit 2202b can be halved compared to FIG. 18. Therefore, the display device of FIG. 22 can reduce the load of the first scanning line driving circuit 2202a and the load of the second scanning line driving circuit 2202b, so that the delay and sag of the signal input to the scanning lines G1 to Gn (the output signals of the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b) can be reduced. Furthermore, since the load of the first scanning line driving circuit 2202a and the load of the second scanning line driving circuit 2202b of the display device of FIG. 22 are reduced, the scanning lines G1 to Gn can be scanned at high speed. Furthermore, since the scanning lines G1 to Gn can be scanned at high speed ​​​​​Therefore, it is possible to increase the size or the definition of the panel. Further, in the merit of the display device is more effective when amorphous silicon is used for the semiconductor layer of the transistor included in the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b. Note that components common to the configuration of FIG. 16 are denoted by the same reference numerals and their description is omitted. When amorphous silicon is used for the semiconductor layer of the transistor included in the first scanning line driving circuit 2202a and the second scanning line driving circuit 2202b, it is more effective. Note that components common to the configuration of FIG. 16 are denoted by the same reference numerals and their description is omitted. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured.

[0234] Similarly, the content described in each figure of this embodiment or a part of the content can be applied to the content described in the figure of another embodiment or a part of the content. Alternatively, they can be combined. Further, in the figures of this embodiment, by combining different parts of another embodiment with respect to each part, more figures can be configured. Similarly, the content described in each figure of this embodiment or a part of the content can be applied to the content described in the figure of another embodiment or a part of the content. Alternatively, they can be combined. Further, in the figures of this embodiment, by combining different parts of another embodiment with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured.

[0235] In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured. In addition, although various figures have been used in this embodiment, the content described in each figure or a part of the content can be applied to the content described in another figure or a part of the content. Alternatively, they can be combined. Further, in the figures described so far, by combining different parts with respect to each part, more figures can be configured.

[0236] Note that this embodiment shows an example when the content described in another embodiment is embodied, an example when it is slightly modified, an example when a part is changed, an example when it is improved, an example when it is described in detail, an example when it is applied, and an example of related parts. Therefore, the content described in another embodiment can also be applied to this embodiment. Alternatively, they can be combined. Note that this embodiment shows an example when the content described in another embodiment is embodied, an example when it is slightly modified, an example when a part is changed, an example when it is improved, an example when it is described in detail, an example when it is applied, and an example of related parts. Therefore, the content described in another embodiment can also be applied to this embodiment. Alternatively, they can be combined. Note that this embodiment shows an example when the content described in another embodiment is embodied, an example when it is slightly modified, an example when a part is changed, an example when it is improved, an example when it is described in detail, an example when it is applied, and an example of related parts. Therefore, the content described in another embodiment can also be applied to this embodiment. Alternatively, they can be combined. Note that this embodiment shows an example when the content described in another embodiment is embodied, an example when it is slightly modified, an example when a part is changed, an example when it is improved, an example when it is described in detail, an example when it is applied, and an example of related parts. Therefore, the content described in another embodiment can also be applied to this embodiment. Alternatively, they can be combined. Note that this embodiment shows an example when the content described in another embodiment is embodied, an example when it is slightly modified, an example when a part is changed, an example when it is improved, an example when it is described in detail, an example when it is applied, and an example of related parts. Therefore, the content described in another embodiment can also be applied to this embodiment. Alternatively, they can be combined.

[0237] (Embodiment 3) In this embodiment, a flip-flop different from those in Embodiment 1 and Embodiment 2, a drive circuit having the flip-flop, and the configuration and driving method of a display device having the drive circuit will be described. The flip-flop of this embodiment is characterized in that the output signal of the flip-flop and the transfer signal of the flip-flop are output from different wirings by different transistors. Regarding those similar to Embodiment 1 and Embodiment 2, the same reference numerals are used, and detailed descriptions of the same parts or parts having the same functions are omitted. The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 27. The flip-flop shown in FIG. 27 has a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, a seventh transistor 107, an eighth transistor 108, and a ninth transistor 109. In this embodiment, the eighth transistor 108 and the ninth transistor 109 are N-channel type transistors, and are assumed to be in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). Note that the flip-flop in FIG. 27 is the same as that obtained by adding the eighth transistor 108 and the ninth transistor 109 to the flip-flop in FIG. 1. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 can be the same as those in FIG. 1. That is, the flip-flop of this embodiment outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors. For those similar to Embodiment 1 and Embodiment 2, the same reference numerals are used, and detailed descriptions of the same parts or parts having the same functions are omitted.

[0238] The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 27. The flip-flop shown in FIG. 27 has a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a fifth transistor 105, a sixth transistor 106, a seventh transistor 107, an eighth transistor 108, and a ninth transistor 109. In this embodiment, the eighth transistor 108 and the ninth transistor 109 are N-channel type transistors, and are assumed to be in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). Note that the flip-flop in FIG. 27 is the same as that obtained by adding the eighth transistor 108 and the ninth transistor 109 to the flip-flop in FIG. 1. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 can be the same as those in FIG. 1. That is, the flip-flop of this embodiment outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors.

[0239] Note that the flip-flop in FIG. 27 is the same as that obtained by adding the eighth transistor 108 and the ninth transistor 109 to the flip-flop in FIG. 1. Therefore, the first transistor 101, the second transistor 102, the third transistor 103, the fourth transistor 104, the fifth transistor 105, the sixth transistor 106, and the seventh transistor 107 can be the same as those in FIG. 1. That is, the flip-flop of this embodiment outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors. For those similar to Embodiment 1 and Embodiment 2, the same reference numerals are used, and detailed descriptions of the same parts or parts having the same functions are omitted. That is, the flip-flop of this embodiment outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors.

[0240] The connection relationship of the flip-flop in FIG. 27 will be described. One of the first electrodes (either the source electrode or the drain electrode) of the first transistor 101 is connected to the fifth wiring 125, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 101 is connected to the third wiring 1 23. One of the first electrodes of the second transistor 102 is connected to the fourth wiring 124, and the second electrode of the second transistor 102 is connected to the third wiring 123. One of the first electrodes of the third transistor 103 is connected to the sixth wiring 126, and the second electrode of the third transistor 103 is connected to the gate electrode of the second transistor 102, and the gate electrode of the third transistor 103 is connected to the seventh wiring 127. One of the first electrodes of the fourth transistor 104 is connected to the ninth wiring 129, and the second electrode of the fourth transistor 104 is connected to the gate electrode of the second transistor 102, and the gate electrode of the fourth transistor 104 is connected to the gate electrode of the first transistor 101. One of the first electrodes of the fifth transistor 105 is connected to the eighth wiring 128, and the second electrode of the fifth transistor 105 is connected to the gate electrode of the first transistor 101, and the gate electrode of the fifth transistor 105 is connected to the first wiring 121. One of the first electrodes of the sixth transistor 106 is connected to the tenth wiring 130, and the second electrode of the sixth transistor 106 is connected to the gate electrode of the first transistor 101, and the gate electrode of the sixth transistor 106 is connected to the gate electrode of the second transistor 102. One of the first electrodes of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 10 1, and the gate electrode of the seventh transistor 107 is connected to the second transistor 102. One of the first electrodes of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 10 1, and the gate electrode of the seventh transistor 107 is connected to the gate electrode of the second transistor 102. One of the first electrodes of the seventh transistor 107 is connected to the eleventh wiring 131, and the second electrode of the seventh transistor 107 is connected to the gate electrode of the first transistor 10 1, and the gate electrode of the seventh transistor 107 is connected to the gate electrode of the second transistor is connected to the gate electrode of 1, and the gate electrode of the seventh transistor 107 is connected to the second wiring 122 is connected. The first electrode of the eighth transistor 108 is connected to the thirteenth wiring 133 , the second electrode of the eighth transistor 108 is connected to the twelfth wiring, and the gate electrode of the eighth transistor 108 is connected to the gate electrode of the first transistor 101. The first electrode of the ninth transistor 109 is connected to the fourteenth wiring 134, and the second electrode of the ninth transistor 109 is connected to the twelfth wiring 132, and the gate electrode of the ninth transistor 109 is connected to the gate electrode of the second transistor 102.

[0241] Note that the twelfth wiring 132 and the third wiring 133 may be referred to as the sixth signal line and the seventh signal line respectively. Further, the fourteenth wiring may be referred to as the seventh power supply line.

[0242] Note that V2 is supplied to the fourteenth wiring 134.

[0243] Note that a signal is input to the thirteenth wiring 133. The signal input to the third wiring can be the same as the signal input to the fifth wiring 125.

[0244] Note that a signal is output from the twelfth wiring 132. Further, as described in Embodiment 1, a signal is also output from the third wiring 123.

[0245] Note that the signals or potentials input to the first wiring 121, the second wiring 122, the fourth wiring 124, the fifth wiring 125, the sixth wiring 126, the seventh wiring 127, the eighth wiring 128, the ninth wiring 129, the tenth wiring 130, and the eleventh wiring 131 are the same as those in FIG. 1 .

[0246] The flip-flop shown in FIG. 27 shows the case where an eighth transistor 10 8 and a ninth transistor 109 are added to the flip-flop shown in FIG. 1. However, FIGS. 4(A), 4( B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), FIG 7(A), 7(B), 7(C), 21(A), 21(B), and 21(C) show that an eighth transistor 108 and a ninth transistor 109 may be added to the flip-flop shown. to the flip-flop shown. It is also possible.

[0247] Next, the operation of the flip-flop shown in FIG. 1 will be described with reference to the timing chart of FIG. 28. Furthermore, parts common to the timing chart of FIG. 2 will be denoted by common reference numerals and their description will be omitted. Furthermore, parts common to the timing chart of FIG. 2 will be denoted by common reference numerals and their description will be omitted. and its description will be omitted.

[0248] Note that the signal 232 indicates the signal output from the twelfth wiring 132. Furthermore, the signals 221, 225, 226, the potentials 241, 242, the signal 222, and the signal 22 3 are the same as those in FIG. 2. However, as the signals 221, 225, 226, the potentials 241, 242, the signal 222, and the signal 223, those similar to FIGS. 6, 31, or 32 may be used. used. It is also possible to use.

[0249] In the present embodiment, as already described, the output signal of the flip-flop and the transfer signal of the flip-flop are output from separate wirings by separate transistors, which is a characteristic. That is, the flip-flop shown in FIG. 27 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and outputs a signal from the twelfth wiring 132 by the eighth transistor 108 and the ninth transistor. Furthermore, the eighth transistor 108 outputs a signal from the third wiring 123 by the first transistor 101 and the second transistor 102, and outputs a signal from the twelfth wiring 132 by the eighth transistor 108 and the ninth transistor. Furthermore, the eighth The eighth transistor 108 and the ninth transistor are connected in the same manner as the first transistor 101 and the second transistor 102. Therefore, as shown in FIG. 28, the signal (signal 232) output from the twelfth wiring 132 has substantially the same waveform as the signal (signal 223 ) output from the third wiring 123. Here, signal 232 is used as the output signal of the flip-flop , and signal 223 is used as the transfer signal of the flip-flop. However, signal 223 may be used as the output signal of the flip-flop , and signal 232 may be used as the transfer signal of the flip-flop.

[0250] Note that the eighth transistor 108 and the ninth transistor 109 each have the same function as the first transistor 101 and the second transistor 102. Further, the eighth transistor 108 and the ninth transistor 109 may be referred to as a buffer section.

[0251] From the above, the flip-flop in FIG. 27 can prevent malfunction even when a large load is connected to the third wiring 132 and delay, distortion, etc. occur in signal 232. This is because the flip-flop in FIG. 27 outputs the output signal of the flip-flop and the transfer signal of the flip-flop from different wirings by different transistors, so that delay, distortion, etc. of the output signal do not affect the operation of the flip-flop. Furthermore, the flip-flop in FIG. 27, similar to the flip-flops shown in Embodiment 1 and Embodiment 2, can obtain advantages such as reduction of layout area, suppression of threshold shift of transistors, simplification of processes,

[0252] fabrication of semiconductor devices such as large display devices, and fabrication of semiconductor devices such as long-life display panels. ​

[0253] Note that the operation timing described in Embodiment 2 can also be applied to the flip-flop of this embodiment. This is also possible.

[0254] The configuration and driving method of the shift register having the flip-flop of this embodiment described above will be described. This will be described.

[0255] The configuration of the shift register of this embodiment will be described with reference to FIG. 29. The shift register in FIG. 29 has n flip-flops (flip-flop 2901_1 to flip-flop 2901_n). The flip-flop in FIG. 29 has n flip-flops (flip-flop 2901_1 to flip-flop 2901_n). One of them has n flip-flops (flip-flop 2901_1 to flip-flop 2901_n).

[0256] The connection relationship of the flip-flops in FIG. 29 will be described. The flip-flop in FIG. 29 is connected to the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_i-1, the eighth wiring 2918_i, the eighth wiring 2918_i+1, and the ninth wiring 2919_i. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1. However, the first-stage flip-flop 2901_1 is connected to the first wiring 2911, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 2915, the sixth wiring 2916, the eighth wiring 2918_1, the eighth wiring 2918_2, and the ninth wiring 2919_1.

[0257] The first wiring 2911 is connected to the first wiring 121 shown in FIG. 27 of the flip-flop 2901_1. The second wiring 2912 is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27 in the flip-flops of odd-numbered stages, and is connected to the sixth wiring 126 shown in FIG. 27 in the flip-flops of even-numbered stages. The third wiring 2913 is connected to the sixth wiring 126 shown in FIG. 27 in the flip-flops of odd-numbered stages, and in the flip-flops of even-numbered stages is connected to the fifth wiring 125 and the third wiring 133 shown in FIG. 27. The fourth wiring 2914 is connected to the seventh wiring 127 shown in FIG. 27 in all stages of flip-flops. The fifth wiring 29 15 is connected to the eighth wiring 128 shown in FIG. 27 in all stages of flip-flops. The sixth wiring 2916 is connected to the fourth wiring 124, the ninth wiring 129, the twenty-ninth wiring 130 and the eleventh wiring 131 shown in FIG. 27 in all stages of flip-flops. The eighth wiring 2918 _i is connected to the second wiring 122 shown in FIG. 27 of the flip-flop 2901_i - 1, the third wiring 123 shown in FIG. 27 of the flip-flop 2901_i and the first wiring 121 shown in FIG. 27 of the flip-flop 2901i +1. However, the eighth wiring 2918_1 is connected to the third wiring 123 shown in FIG. 27 of the flip-flop 2901_1 and the first wiring 121 shown in FIG. 27 of the flip-flop 2901_2. Further, the eighth wiring 291 8_n is connected to the second wiring 122 shown in FIG. 27 of the flip-flop 2901_n - 1 and the third wiring 123 shown in FIG. 27 of the flip-flop 2901_n. The ninth wiring 2 919_1 to the ninth wiring 2919_n are respectively connected to the flip-flops 2901_1 to the flip flops 2901_n. The twelfth wiring 132 shown in FIG. 27 of the flip-flop 2901_n is connected to the twelfth wiring 132 shown in FIG.

[0258] In addition, the flip-flops 2901_1 to 2901_n and the first wiring 29 11, the second wiring 2912, the third wiring 2913, the fourth wiring 2914, the fifth wiring 29 15, the fifth wiring 2916, and the seventh wiring 2907 are the flip-flops shown in FIG. Flip-flop 1001_1 to flip-flop 1001_n, a first wiring 1011, a second wiring 1012, the third wiring 1013, the fourth wiring 1014, the fifth wiring 1015, The seventh wiring 1016 corresponds to the seventh wiring 1007, and a similar signal or potential is supplied to the seventh wiring 1016.

[0259] Next, the operation of the shift register shown in FIG. 29 will be described with reference to the timing chart in FIG. 30. This will be explained in light of the above.

[0260] In FIG. 30, a signal 3011 is input to the first wiring 2911, and A signal 3018_1 output to the eighth wiring 2918_i. i, a signal 3018_i+1 output to the eighth wiring 2918_i+1, 8_n, and a signal 3018_n output to a ninth wiring 2919_1. 9_1, a signal 3019_i output to the ninth wiring 2918_i, i+1 and a signal 3019_i+1 output to the ninth wiring 2919_n It shows 3018_n.

[0261] As shown in FIG. 30, for example, when the flip-flop 2901_i is in the selected period, the eighth An H signal is output from the first wiring 2918_i and the ninth wiring 2919_i. Flip-flop 2901_i+1 enters the set period. Subsequently, flip-flop 290 1_i enters the reset period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 2919_i. At this time, flip-flop 2901_i+1 enters the selection period . Subsequently, flip-flop 2901_i enters the first non-selection period, and the eighth wiring 29 18_i and the ninth wiring 2919_i become floating and maintain the potential at the L level. At this time, flip-flop 2901_i+1 enters the reset period. Subsequently, flip-flop 2901_i enters the second non-selection period, and an L signal is output from the eighth wiring 2918_i and the ninth wiring 29 19_i. At this time, flip-flop 2901_i+1 enters the first non-selection period. In this way, flip-flop 2901_i repeats the first non-selection period and the second non-selection period until the next set period . From the above, the shift register in FIG. 29 can output the transfer signal sequentially from the eighth wiring 2918_1 to the eighth wiring 2918_n. Furthermore, the shift register in FIG. 29 can output the selection signal sequentially from the ninth wiring 2919_1 to the ninth wiring 2919_n . That is, the shift register in FIG. 29 can scan the ninth wiring 2919_1 to the ninth wiring

[0262] 2919_n. Therefore, the shift register in FIG. 29 can fully obtain the function as a shift register . Furthermore, even if a large load (such as resistance and capacitance) is connected to the ninth wiring 2919_1 to the ninth wiring 2919_n, the shift register in FIG. 29 can operate without being affected by the load . Therefore, the shift register in FIG. 29 can fully obtain the function as a shift register .

[0263] Furthermore, even if a large load (such as resistance and capacitance) is connected to the ninth wiring 2919_1 to the ninth wiring 2919_n , the shift register in FIG. 29 can operate without being affected by the load Further, the shift register of FIG. 29 includes a ninth wiring 2919_1 to a ninth wiring 29 Even if any of 19_n is shorted to the power line or signal line, normal operation can continue. Therefore, the shift register in FIG. 29 can improve the driving capability. Then, the shift register in Figure 29 has the transfer signal of each flip-flop and This is because the output signal from the amplifier is divided into two parts.

[0264] Furthermore, the shift register in FIG. 29 uses the flip-flop shown in this embodiment. This reduces the layout area, suppresses the threshold shift of transistors, simplifies the process, Manufacturing of semiconductor devices such as large display devices, manufacturing of semiconductor devices such as long-life display panels, etc. The benefits of this system can be obtained.

[0265] Note that the configuration is not limited to that of FIG. 29 as long as it performs the same operation as that of FIG. 29. For example, By freely combining the shift registers in Figures 13, 14, 15, and 17, , the same advantages as those shown in FIGS. 13, 14, 15, and 17 can be obtained.

[0266] The structure and driving method of a display device having the shift register of the above-mentioned embodiment will be described. However, the display device of this embodiment mode is at least the flip-flop of this embodiment mode. It is sufficient for the user to have a

[0267] As the display device of this embodiment, the display devices shown in FIG. 8, FIG. 18, FIG. 16, FIG. 20, and FIG. 22 are used. Therefore, the display device of this embodiment can be realized as a scanning line driving circuit. By applying the shift register of the embodiment, it is possible to reduce the layout area. In addition, the display device of the present embodiment can suppress the threshold shift of the transistor. Further , the display device of the present embodiment can simplify the process. Further, the display device of the present embodiment can be enlarged or made higher definition. Further, the display device of the present embodiment can achieve a longer lifespan. In particular, if the shift register of the present embodiment is applied as the scanning line driving circuit to the display devices of FIGS. 8, 16, and 22, enlargement or higher definition can be achieved. Further, the display devices of FIGS. 8, 16, or 22 to which the shift register of the present embodiment is applied can achieve power saving. Further, the display devices of FIGS. 8, 16, or 22 to which the shift register of the present embodiment is applied can suppress the heat generation of the IC. Further, the display devices of FIGS. 8, 16, or 22 to which the shift register of the present embodiment is applied can achieve power saving of the IC.

[0268] Note that, in the present embodiment, although described using various figures, the content described in each figure or a part of the content can also be applied to the content described in another figure or a part of the content. Or, they can be combined. Further, in the figures described so far, for each part, by combining with another part, more figures can be formed. Similarly, the content described in each figure of the present embodiment or a part of the content

[0269] can also be applied to the content described in the figures of another embodiment or a part of the content. Or, they can be combined. Further, in the figures of the present embodiment, for each part, by combining with a part of another embodiment, more figures can be formed.

[0270] Note that this embodiment shows an example of implementing the content described in other embodiments, an example of making a slight modification, an example of changing a part, an example of improvement, an example of detailed description, an example of application, an example of related parts, etc. Therefore, the content described in other embodiments can also be applied to this embodiment or combined with it. (Embodiment 4) In this embodiment, the case where a P-channel transistor is applied to the transistors constituting the flip-flop of this specification will be described. Furthermore, the configuration and driving method of a driving circuit having the flip-flop and a display device having the driving circuit will be described. The flip-flop of this embodiment will be described when the polarities of the transistors included in the flip-flop of FIG. 1 are made P-channel type. However, the polarities of the transistors included in the flip-flop shown in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), 21(C), or 27 can also be made P-channel type. Furthermore, the flip-flop of this embodiment can also be implemented in any combination with the descriptions of Embodiments 1 to 3. The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 23. The flip-flop shown in FIG. 23 includes a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, and a fifth transistor 2

[0271] (Embodiment 4) In this embodiment, the case where a P-channel transistor is applied to the transistors constituting the flip-flop of this specification will be described. Furthermore, the configuration and driving method of a driving circuit having the flip-flop and a display device having the driving circuit will be described. The flip-flop of this embodiment will be described when the polarities of the transistors included in the flip-flop of FIG. 1 are made P-channel type. However, the polarities of the transistors included in the flip-flop shown in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), 21(C), or 27 can also be made P-channel type. Furthermore, the flip-flop of this embodiment can also be implemented in any combination with the descriptions of Embodiments 1 to 3. The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 23. The flip-flop shown in FIG. 23 includes a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, and a fifth transistor 2

[0272] The flip-flop of this embodiment will be described when the polarities of the transistors included in the flip-flop of FIG. 1 are made P-channel type. However, the polarities of the transistors included in the flip-flop shown in FIGS. 4(A), 4(B), 4(C), 4(D), 5(A), 5(B), 5(C), 5(D), 7(A), 7(B), 7(C), 21(A), 21(B), 21(C), or 27 can also be made P-channel type. Furthermore, the flip-flop of this embodiment can also be implemented in any combination with the descriptions of Embodiments 1 to 3. Moreover, the flip-flop of this embodiment can be implemented in any combination with the descriptions of Embodiments 1 to 3. (C), FIG. 4(D), FIG. 5(A), FIG. 5(B), FIG. 5(C), FIG. 5(D), FIG. 7(A), FIG. 7(B), FIG. 7(C), FIG. 21(A), FIG. 21(B), FIG. 21(C) or FIG. 27 shown can also have the polarities of the transistors included in the flip-flop made P-channel type. Furthermore, the flip-flop of this embodiment can be implemented in any combination with the descriptions of Embodiments 1 to 3. The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 23. The flip-flop shown in FIG. 23 includes a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, and a fifth transistor 2

[0273] The basic configuration of the flip-flop of this embodiment will be described with reference to FIG. 23. The flip-flop shown in FIG. 23 includes a first transistor 2301, a second transistor 2302, a third transistor 2303, a fourth transistor 2304, and a fifth transistor 2 3, a fourth transistor 2304, and a fifth transistor 2 3 It has the 305th, the sixth transistor 2306, and the seventh transistor 2307. In this implementation form, the first transistor 2301, the second transistor 2302, the third transistor 2303, the fourth transistor 2304, the fifth transistor 2305, the sixth transistor 2306, and the seventh transistor 2307 are P-channel transistors and are assumed to be in the conducting state when the absolute value of the voltage between the gate and the source (|Vgs|) exceeds the absolute value of the threshold voltage (|Vt h|) (when Vgs is lower than Vth).

[0274] The connection relationship of the flip-flop in FIG. 23 will be described. One of the first electrodes (either the source electrode or the drain electrode) of the first transistor 2301 is connected to the fifth wiring 2325, and the second electrode (the other of the source electrode and the drain electrode) of the first transistor 2301 is connected to the third wiring 2323. One of the first electrodes of the second transistor 2302 is connected to the fourth wiring 23 24, and the second electrode of the second transistor 2302 is connected to the third wiring 2323 connected. One of the first electrodes of the third transistor 2303 is connected to the sixth wiring 2326, and the second electrode of the third transistor 2303 is connected to the gate electrode of the second transistor 2302 connected, and the gate electrode of the third transistor 2303 is connected to the seventh wiring 2327. One of the first electrodes of the fourth transistor 2304 is connected to the ninth wiring 2329, and the second electrode of the fourth transistor 2304 is connected to the gate electrode of the second transistor 2302, and the gate electrode of the fourth transistor 2304 is connected to the gate electrode of the first transistor 2301. One of the first electrodes of the fifth transistor 2305 is connected to the eighth wiring 2328, and the second electrode of the fifth transistor 2305 is connected to the gate electrode of the second transistor 2302, and the gate electrode of the fifth transistor 2305 is connected to the gate electrode of the first transistor 2301. The second electrode of the fifth transistor 2305 is connected to the gate electrode of the first transistor 2301 and the gate electrode of the fifth transistor 2305 is connected to the first wiring 2321 . The first electrode of the sixth transistor 2306 is connected to the tenth wiring 2330, and the sixth transistor 2306's second electrode is connected to the gate electrode of the first transistor 2301 , and the gate electrode of the sixth transistor 2306 is connected to the gate electrode of the second transistor 2302. The first electrode of the seventh transistor 2307 is connected to the eleventh wiring 2331 , and the second electrode of the seventh transistor 2307 is connected to the gate electrode of the first transistor 2301, and the gate electrode of the seventh transistor 2307 is connected to the second wiring 2322 .

[0275] Note that the connection points of the gate electrode of the first transistor 2301, the gate electrode of the fourth transistor 2304, the second electrode of the fifth transistor 2305, the second electrode of the sixth transistor 2306, and the second electrode of the seventh transistor 2307 are defined as node 2341 . Furthermore, the connection points of the gate electrode of the second transistor 2302, the second electrode of the third transistor 2303, the second electrode of the fourth transistor 2304, and the gate electrode of the sixth transistor 2306 are defined as node 2342

[0276] The fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330, and the eleventh wiring 23 31 may be connected to each other or may be the same wiring. Furthermore, the seventh wiring 23 27 and the eighth wiring 2328 may be connected to each other or may be the same wiring

[0277] Note that the first transistor 2301 to the seventh transistor 2307 respectively correspond to the first transistor 101 to the seventh transistor 107 in FIG. 1 and have the same functions.

[0278] Note that the first wiring 2321 to the eleventh wiring 2331 respectively correspond to the first wiring 121 to the eleventh wiring 131 in FIG. 1. However, the signals input to, the potentials supplied to, or the signals output from the first wiring 2321 to the eleventh wiring 2331 are inverted in terms of H level and L level compared with the signals input to, the potentials supplied to, or the signals output from the first wiring 121 to the eleventh wiring 131 in FIG. 1.

[0279] Note that the potential of V2 is supplied to the seventh wiring 2327 and the eighth wiring 2328 respectively, and the potential of V1 is supplied to the fourth wiring 2324, the ninth wiring 2329, the tenth wiring 2330, and the eleventh wiring 2331 respectively.

[0280] Note that signals are input to the first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2326 respectively. The signal input to the first wiring 2321 is a start signal, the signal input to the second wiring 2322 is a reset signal, the signal input to the fifth wiring 2325 is a first clock signal, and the signal input to the sixth wiring 2326 is a second clock signal. Further, the signals input to the first wiring 2321, the second wiring 2322, the fifth wiring 2325, and the sixth wiring 2326 are digital signals in which the potential of the H signal is V1 (hereinafter also referred to as the H level) and the potential of the L signal is V2 (hereinafter also referred to as the L level).

[0281] Note that various signals, currents, or voltages may be input to the first wiring 2321, the second wiring 2322, and the second wiring 2322 to the eleventh wiring 2 331, respectively.

[0282] Note that a signal is output from the third wiring 2323. The signal output from the third wiring 2323 is the output signal of the flip-flop of each stage and is also the start signal (hereinafter also referred to as the transfer signal) of the flip-flop of the next stage. Further, the signal output from the third wiring 2323 is a digital signal in which the potential of the H signal is V1 (hereinafter also referred to as the H level) and the potential of the L signal is V2 (hereinafter also referred to as the L level).

[0283] Next, the operation of the flip-flop shown in FIG. 23 will be described with reference to the timing chart of FIG. 24. Further, the timing chart of FIG. 24 will be divided into a selection period and a non-selection period and described. Further, the non-selection period will be divided into a first non-selection period, a second non-selection period, a set period and a reset period and described. Here, as shown in the timing chart of FIG. 24 , each period is arranged in the order of a set period, a selection period, a reset period, a first non-selection period, a second non-selection period, a first non-selection period, and a second non-selection period. That is, the operation periods excluding the set period, the selection period, and the reset period are the first non-selection period and the second non-selection period in order. Further, the period before the set period is the second non-selection period. Note that the timing chart of FIG. 24 is the same as that obtained by inverting the H level and L level of the timing chart of FIG. 2.

[0284] Note that the flip-flop of the present embodiment has the H level and L level of FIG. 2 inverted

[0285] ​ Moreover, the H level and L level of the timing charts of FIGS. 6, 28, 31, and 32 may be inverted and used.

[0286] In FIG. 24, signals 2421, 2425, 2426, potential 2441, potential 2442, signal 2422, and signal 2423 are, respectively, the signal input to the first wiring 2321, the signal input to the fifth wiring 2325, the signal input to the sixth wiring 2326, the potential of node 2341, the potential of node 2342, the signal input to the second wiring 2322, and the signal output from the third wiring 2323.

[0287] Signals 2421, 2425, 2426, potential 2441, potential 2442, signal 2422, and signal 223 respectively correspond to signals 221, 225, 226, potential 241, potential 242, signal 222, and signal 223 in FIG. 2. However, as already described, the H level and L level are inverted.

[0288] First, in the set period shown in FIG. 24(A), since signal 2421 is at the L level, the fifth transistor 2305 is on, and since signal 2422 is at the H level, the seventh transistor 2307 is off. At this time, the potential of node 2341 is such that the second electrode of the fifth transistor 2305 becomes the source electrode, and it is the sum of the potential of the eighth wiring 2328 and the absolute value of the threshold voltage of the fifth transistor 2305, so it becomes V2 + |Vth(2305)| (Vth(2305): the threshold voltage of the fifth transistor 2305). Therefore, the first transistor 2301 and the fourth transistor 2304 are on, and the fifth transistor 2305 is ​​​​​​​​​​​Turn off. At this time, the potential of node 2342 (potential 2442) is the third transistor 2 It is determined by the resistance ratio (L / W and applied voltage) between 303 and the fourth transistor 2304 and becomes V1 - θ (θ: any positive number). Furthermore, θ < |Vth(2302)| (Vt h(2302): threshold voltage of the second transistor 2302) and θ < |Vth(23 06)| (threshold voltage of the sixth transistor 2306). That is, the potential difference (V1 - V2) between the potential (V1) of the ninth wiring 2 329 and the potential (V2) of the sixth wiring 2326 is Divided by the third transistor 2303 and the fourth transistor 2304. Therefore The second transistor 2302 and the sixth transistor 2306 turn off. In this way During the set period, since the third wiring 2323 is connected to the fifth wiring 2325 to which an H signal is input, the potential of the third wiring 2323 becomes V1. Therefore, an H signal is output from the third Wiring 2323. Furthermore, node 2341 becomes a floating state while maintaining the potential at V2 + |Vth(23 05)|.

[0289] In the selection period shown in Fig. 24B), signal 2421 becomes H level and the fifth transistor 2 305 turns off, and since signal 2422 remains at H level, the seventh transistor 2307 remains Off. At this time, node 2341 maintains the potential at V2 + |Vth(2305)| . Therefore, the first transistor 2301 and the fourth transistor 2304 remain Off. At this time, the potential of node 2342 becomes V1 because the sixth wiring 2326 becomes H level . Therefore, the second transistor 2302 and the sixth transistor 23 06 remain off. Here, since an L signal is input to the fifth wiring 2325, the third The potential of the wiring 2323 starts to decrease. Then, the potential of the node 2341 increases due to the bootstrap The voltage drops from V2+|Vth(2305)| to V2-|Vth(230 1) |-γ(Vth(2301): threshold voltage of the first transistor 2301, γ: arbitrary Therefore, the potential of the third wiring 2323 is The potential becomes equal to V2. This bootstrap operation is This is achieved by capacitive coupling of the parasitic capacitance between the gate electrode and the second electrode of the transistor 2301. In this way, during the selection period, the third wiring 2323 is connected to the fifth wiring 2323 to which the L signal is input. 325, the potential of the third wiring 2323 becomes V2. It is output from the third wiring 2323.

[0290] During the reset period shown in FIG. 24(C), the signal 2421 remains at H level, so the fifth transistor The transistor 2305 remains off, and the signal 2422 goes low to turn on the seventh transistor. At this time, the potential of the node 2341 is equal to the potential of the 11th wiring (V 1) is supplied through the seventh transistor 2307, so it becomes V1. The transistor 2301 and the fourth transistor 2304 are turned off. At this time, the node 2 The potential of the sixth transistor 342 is supplied to the sixth transistor 2303 through the second electrode of the sixth transistor 2303, which serves as the source electrode of the sixth transistor 2303. The threshold voltage of the third transistor 2303 is subtracted from the potential (V2) of the wiring 2326. Therefore, V2+|Vth(2303)|(Vth(2303): the third transistor Therefore, the second transistor 2302 and the sixth transistor Transistor 2306 turns on. Thus, during the reset period, the third wiring 2323 conducts with the fourth wiring 2324 to which V 1 is supplied, so that the potential of the third wiring 2323 becomes V 1. Therefore, an H signal is output from the third wiring 2323.

[0291] In the first non-selection period shown in FIG. 24(D), since the signal 2421 remains at the H level, the fifth transistor 2305 remains off, and the signal 2422 becomes the H level and the seventh transistor 2307 turns off. The potential of the node 2342 at this time becomes V1 because an H signal is input to the sixth wiring 2326. Therefore, the second transistor 2302 and the sixth transistor 2306 turn off. The node 2341 at this time becomes in a floating state, so the potential is maintained at V1. Therefore, the first transistor 2301 and the fourth transistor 23 04 remain off. Thus, in the first non-selection period, since the third wiring 2323 becomes in a floating state, the potential of the third wiring 2323 maintains V1.

[0292] In the second non-selection period shown in FIG. 24(E), since the signal 2421 remains at the H level, the fifth transistor 2305 remains off, and since the signal 2422 remains at the H level, the seventh transistor 2307 remains off. The potential of the node 2342 at this time is such that an L signal is input to the sixth wiring 2326 and the transistor 2304 is off, so it becomes V2 + |V th(2303)|. Therefore, the second transistor 2302 and the sixth transistor 2306 turn on. The potential of the node 2341 at this time remains at V1 because the potential (V1) of the tenth wiring 2330 is supplied through the sixth transistor 2306. Thus That is, the first transistor 2301 and the fourth transistor 2304 remain off. . Thus, during the second non-selection period, since the third wiring 2323 conducts with the fourth wiring 2324 to which V1 is supplied, the potential of the third wiring 2323 remains at V1. Therefore, an H signal is output from the third wiring 2323.

[0293] From the above, the flip-flop in FIG. 23 uses a bootstrap operation during the selection period to lower the potential of the node 2341 below V2 - |Vth(2301)|, and thereby the potential of the third wiring 2323 can be set to V2. Furthermore, the flip-flop in FIG. 23 performs this bootstrap operation by using the capacitive coupling of the parasitic capacitance between the second electrode and the gate electrode of the first transistor 2301, and thus merits such as reduction of the layout area and reduction of the number of elements can be obtained.

[0294] Furthermore, in the flip-flop of FIG. 23, since the second transistor 2302 and the sixth transistor 2306 are turned on only during the second non-selection period, the shift of the threshold voltages of the second transistor 2302 and the sixth transistor 2306 can be suppressed.

[0295] Note that in the flip-flop of FIG. 23, by supplying V2 to the gate electrode of the third transistor 2303 and inputting the second clock signal to the first electrode, the shift of the threshold voltage of the third transistor 2303 can also be suppressed.

[0296] Furthermore, the flip-flop in FIG. 23 includes the first transistor 2301 and the fourth transistor 2304. ​​​​Since the second transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 are not turned on during the first non-selection period and the second non-selection period, the shift of the threshold voltages of the first transistor 2301, the fourth transistor 2304, the fifth transistor 2305, and the seventh transistor 2307 can be suppressed. Further, even if the potential of the node 2341 and the potential of the third wiring 2323 vary during the first non-selection period, by supplying V1 to the node 2341 and the third wiring 2323 during the next second non-selection period, the potential of the node 2341 and the potential of the third wiring 2323 can be reset to V1. Therefore, the flip-flop in FIG. 23 can suppress malfunction caused by the node 2341 and the wiring 2323 being in a floating state and the potential of the node 2341 and the third wiring 2323 varying.

[0297]

[0298]

[0299]

[0300] Furthermore, since the flip-flop in FIG. 23 can suppress the threshold shift of the transistor, it can suppress malfunction caused by the threshold voltage shift of the transistor.

[0299] Furthermore, the flip-flop in FIG. 23 is characterized in that all of the first transistor 2301 to the seventh transistor 2307 are composed of P-channel transistors. Therefore, the flip-flop in FIG. 23 can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

[0300]

[0300] Note that as long as it performs the same operation as in FIG. 24, the arrangement and number of each transistor, etc. are as shown in FIG. 2. It is not limited to 4. Therefore, transistors, other elements (such as resistive elements and capacitive elements), diodes, switches, various logic circuits, etc. can be newly arranged in the flip-flop of FIG. 24.

[0301] Note that the shift register of the present embodiment can be implemented by freely combining the flip-flop of the present embodiment with the shift registers described in Embodiments 1 to 3. For example, the shift register of the present embodiment can be implemented by freely combining the flip-flop of the present embodiment with the shift registers of FIGS. 10 , 13, 14, 15, 17, 29, 33, and 34. However, compared with the shift registers described in Embodiments 1 to 3, the H level and L level of the shift register of the present embodiment are inverted.

[0302] Note that the display device of the present embodiment can be implemented by freely combining the shift register of the present embodiment with the display devices described in Embodiments 1 to 3. For example, the display device of the present embodiment can be implemented by freely combining with the display devices of FIGS. 8, 18, 16, 20, and 22. However, compared with the display devices described in Embodiments 1 to 3, the H level and L level of the display device of the present embodiment are inverted.

[0303] Note that in the present embodiment, various figures have been used for description. However, the content or part of the content described in each figure can also be applied to the content or part of the content described in another figure. Alternatively, they can be combined. Furthermore, regarding each part in the figures described so far, ​​​​​​By combining other parts, even more figures can be constructed.

[0304] Similarly, the content or part of the content described in each figure of this embodiment can also be applied to the content or part of the content described in the figures of another embodiment. Or, they can be combined. Or, they can be combined. Furthermore, in the figures of this embodiment, for each part, by combining the parts of another embodiment, even more figures can be constructed. By combining the parts of another embodiment, even more figures can be constructed.

[0305] Note that this embodiment shows an example of implementing the content described in other embodiments, an example of slight modification, an example of partial change, an example of improvement, an example of detailed description, an example of application, an example of related parts, etc. Therefore, the content described in other embodiments can also be applied to this embodiment. Or, they can be combined. Or, they can be combined. Or, they can be combined. Therefore, the content described in other embodiments can also be applied to this embodiment. Or, they can be combined. Or, they can be combined.

[0306] (Embodiment 5) In this embodiment, the signal line driving circuit of the display device shown in Embodiments 1 to 4 will be described. The signal line driving circui...

Claims

[Claim 1] The semiconductor device includes first to seventh transistors, one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; one of a source and a drain of the third transistor is electrically connected to a gate of the second transistor; one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor; a gate of the fourth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor; one of a source and a drain of the sixth transistor is electrically connected to a gate of the first transistor; a gate of the sixth transistor is electrically connected to a gate of the second transistor; a flip-flop in which one of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor.

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