Semiconductor device

Abstract

To provide a semiconductor device with a compact footprint.SOLUTION: A unit logic circuit LG_A include:s an N-type MOS transistor N2 having a first terminal T1, a second terminal T2, and a gate terminal G, where a first signal from a first input circuit is supplied to the first terminal T1 and a second signal from the first input circuit is supplied to the gate terminal G; an N-type MOS transistor N1 having a first terminal T1, a second terminal T2, and a gate terminal G, where the second signal is supplied to the first terminal T1 and the first signal is supplied to the gate terminal G; an N-type MOS transistor N1 having a first terminal T1, a second terminals T2, and a gate terminal G, where the second signal is supplied to the first terminal T1 and the first signal is supplied to the gate terminal G; an inverter circuit IV1 including an input terminal connected to the second terminals T2 of the N-type MOS transistor N2 and the N-type MOS transistor N1; and a P-type MOS transistor P1 that is connected between the input terminal of the inverter circuit IV1 and a power source voltage VDD and pre-charges the input terminal of the inverter circuit IV1 with the voltage based on the power source voltage VDD in response to a trigger signal TRG supplied to the gate terminal.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an exclusive OR circuit (hereinafter also referred to as an XOR circuit).

Background Art

[0002] Semiconductor devices are becoming increasingly highly integrated. As the degree of integration increases, the probability of occurrence of soft errors caused by radiation such as alpha rays increases. For example, when a semiconductor device includes a memory, there is a concern that the data stored in the memory may change (be destroyed) due to a soft error, resulting in a decrease in the reliability of the stored data.

[0003] In order to improve the reliability of the stored data, an ECC (Error Correcting Code) circuit is provided in the semiconductor device. In this case, the ECC circuit can detect the destruction of the stored data and further correct the destroyed data, thereby improving the reliability of the stored data.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] An ECC circuit is composed of many XOR circuits. An example of an XOR circuit is shown in FIG. 7 of Patent Document 1. In Patent Document 1, a 2-input XOR circuit (for example, logic unit 20 in FIG. 7) is composed of two P-channel type series circuits connected in parallel between an output terminal (node N0) and a power supply voltage (VCC), and two N-channel type series circuits connected in parallel between the output terminal (N0) and a ground voltage (GND).

[0006] Here, each of the two P-channel series circuits is composed of two P-channel field-effect transistors (hereinafter also referred to as PMOSFETs or P-type MOS transistors) to which an input signal is supplied to the gate electrode and the source-drain paths are connected in series. Similarly, each of the two N-channel series circuits is composed of two N-channel field-effect transistors (hereinafter also referred to as NMOSFETs or N-type MOS transistors) to which an input signal is supplied to the gate electrode and the source-drain paths are connected in series. In this specification, when the P-type MOS transistor and the N-type MOS transistor are collectively described, they are simply also referred to as MOSFETs or MOS transistors.

[0007] When the logic values of the two inputs of the XOR circuit match, either one of the two N-channel series circuits becomes conductive, and when they do not match, either one of the two P-channel series circuits becomes conductive. As a result, the exclusive OR of the two inputs is realized.

[0008] However, eight MOS transistors are required to realize a two-input XOR circuit. Also, as shown in FIG. 7 of Patent Document 1, two inverter circuits are required to generate the inputs of the XOR circuit (20). Since one inverter circuit can be realized by, for example, two MOS transistors, four more MOS transistors are required. As a result, twelve MOS transistors are required to realize a two-input XOR circuit, and there is a problem that the occupied area of the ECC circuit becomes large.

Means for Solving the Problem

[0009] The outline of typical ones among the embodiments disclosed in the present application will be briefly described as follows.

[0010] That is, a semiconductor device according to an embodiment includes a semiconductor chip on which a plurality of circuit blocks are formed.

[0011] Here, the plurality of circuit blocks include a memory, a first input circuit that outputs a signal, a plurality of logic circuits, a first processing circuit that processes the signal from the first input circuit, and a first output circuit that supplies the output of the first processing circuit to the memory.

[0012] Furthermore, each of the plurality of logic circuits includes a first terminal, a second terminal, and a first gate terminal that controls conduction between the first terminal and the second terminal. A first N-type MOS transistor to which a first signal from the first input circuit is supplied to the first terminal and a second signal from the first input circuit is supplied to the first gate terminal, a third terminal, a fourth terminal, and a second gate terminal that controls conduction between the third terminal and the fourth terminal. A second N-type MOS transistor to which the second signal is supplied to the third terminal and the first signal is supplied to the second gate terminal, and an output driver including an input terminal to which the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor are connected, and a first P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a first trigger signal supplied to the gate terminal. After being precharged by the first trigger signal, the output driver outputs a signal according to the logical operation result of the first signal and the second signal.

[0013] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Effect of the Invention

[0014] According to one embodiment, a semiconductor device capable of suppressing an increase in occupied area can be provided.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Best Mode for Carrying Out the Invention

[0016] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention.

[0017] Also, in this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0018] (Embodiment 1) <Configuration of the Semiconductor Device> FIG. 1 is a block diagram showing the configuration of a semiconductor device according to Embodiment 1. The semiconductor device according to Embodiment 1 includes one semiconductor chip in which a plurality of circuit blocks are formed by a well-known semiconductor manufacturing technology. In FIG. 1, CHP indicated by a one-dot chain line represents a semiconductor chip in which a plurality of circuit blocks are formed. Although various circuit blocks are formed as a plurality of circuit blocks in the semiconductor chip CHP, only the circuit blocks necessary for the description are drawn in FIG. 1 to avoid complicating the drawing.

[0019] In FIG. 1, CBT represents a memory having an ECC circuit. Also, CBP represents a pre-stage circuit that supplies a signal (data Din) to the memory CBT, and CBA represents a post-stage circuit to which a signal (data Dout) is supplied from the memory CBT. The pre-stage circuit CBP is constituted by, for example, a processor, and the data Din generated by the processor is supplied to and written into the memory CBT. The data Dout read from the memory CBT is supplied to a post-stage circuit CBA such as a peripheral circuit and processed.

[0020] The memory CBT is not particularly limited, but includes one memory RM and an ECC circuit EC. The single memory RM according to Embodiment 1 includes two storage areas DBA and RBA. The storage area DBA is a data bit area into which the data Din generated by the preceding circuit CBP is written. The storage area RBA is a code bit area into which a code (error correction code) generated by the ECC circuit EC described later is written.

[0021] During the read and write operations of the memory RM, for example, the preceding circuit CBP generates an address signal for accessing the memory RM. By the generated address signal, a predetermined area (address area specified by the address signal) in each of the two storage areas DBA and RBA is accessed. During writing, the data Din is written into a predetermined area of the storage area DBA, and the code R generated by the ECC circuit EC is written into a predetermined area of the storage area RBA.

[0022] During reading, the data (bits) stored in a predetermined area of the storage area DBA is read out as Din_E and supplied to the ECC circuit EC. Also, during reading, the data (code) stored in a predetermined area of the storage area RBA is read out as code R and supplied to the ECC circuit EC. The ECC circuit EC uses the supplied data Din_E and code R to detect whether there is an error in the data Din_E read from the storage area DBA, and outputs the detection result as an error flag EFG. If a correctable error is detected in this detection, the ECC circuit EC corrects the error in the data Din_E and outputs it as data Dout to the subsequent circuit CBA.

[0023] Although not particularly limited, the error flag EFG is supplied to the processor which is the preceding circuit CBP. Thereby, the processor can detect the occurrence of, for example, an uncorrectable error by the ECC circuit EC based on the error flag EFG.

[0024] In the following description, the case where a static random access memory (SRAM) is used as the memory RM will be described as an example, but it is not limited thereto. For example, the memory RM may be a dynamic random access memory (DRAM), an electrically rewritable non-volatile memory (e.g., flash memory), or MRAM, etc.

[0025] <<Overview of ECC Circuit>> Next, the overview of the ECC circuit EC will be described with reference to FIG. 1. As shown in FIG. 1, the ECC circuit EC includes an encoder EC_E, a decoder EC_D, and a correction processing circuit (hereinafter also referred to as a correction circuit) EC_C.

[0026] Although an example will be shown later with reference to the drawings, data Din to be written into the memory RM is supplied to the encoder EC_E. The encoder EC_E encodes the supplied data Din to generate a code R, and writes the generated code R into the storage area RBA.

[0027] The decoder EC_D is supplied with the code R read from the storage area RBA and the data Din_E read from the storage area DBA. The decoder EC_D decodes the supplied data, detects whether an error has occurred, and if an error has occurred, notifies it with an error flag EFG. Also, when a correctable error has occurred, the decoder EC_D identifies the position where the error has occurred in the data Din_E.

[0028] The correction circuit EC_C is supplied with the data Din_E read from the storage area DBA and the data DD identifying the position where the error has occurred. When a correctable error has occurred, the correction circuit EC_C corrects the error and outputs it as data Dout.

[0029] Next, an example of the configurations of the encoder EC_E, decoder EC_D, and correction circuit EC_C will be described with reference to the drawings. Here, for ease of explanation, a case where the data Din supplied from the preceding-stage circuit CBP to the memory RM is composed of 4 bits IN[0] to IN[3] (parallel 4 bits) will be described as an example. Of course, the number of bits of the data Din is not limited to this.

[0030] <<<Overview of Encoding EC_E>>> FIG. 2 is a block diagram showing an example of an encoder according to Embodiment 1. The encoder EC_E includes three 3-input XOR circuits XR_E0 to XR_E2. Among the 4 bits IN[0] to IN[3] constituting the data Din, as shown in FIG. 2, the data Din is supplied to the corresponding 3-input XOR circuits XR_E0 to XR_E2 in combinations of 3 different bits. For example, the data Din is input to the XOR circuit XR_E0 in a combination of the bits IN[0], IN[1], and IN[2]. Similarly, 3 bits of the data Din are also input to the XOR circuits XR_E1 and XR_E2. The outputs of these three 3-input XOR circuits XR_E0 to XR_E2 are output as bits R[0] to R[2] constituting the code R from the decoder EC_D to the storage area RBA of the memory RM.

[0031] Although not particularly limited, in the encoder EC_E according to Embodiment 1, a buffer circuit BF_E is provided in front of the encoder, and the data Din is supplied from the preceding-stage circuit CBP (FIG. 1) via the buffer circuit BF_E. Of course, the buffer circuit BF_E may not be provided.

[0032] The encoder EC_E generates a code R composed of bits R[0] to R[2] having logical values according to the combination of the logical values of the bits IN[0] to IN[3] constituting the data Din, and the generated code is written into the storage area RBA of the memory RM.

[0033] <<<Overview of Decoder EC_D and Correction Circuit EC_C>>> FIG. 3 is a block diagram showing an example of a decoder and a correction circuit according to Embodiment 1. As shown in FIG. 3, the decoder EC_D includes three 4-input XOR circuits XR_D0 to XR_D2, and five 3-input AND circuits AD_D0 to AD_D3 and AD_EF.

[0034] Four bits IN[0] to IN[3] constituting the data Din_E read from the storage area DBA of the memory RM shown in FIG. 1, and three bits R[0] to R[2] constituting the code R read from the storage area RBA, as shown in FIG. 3, are supplied to the 4-input XOR circuits XR_D0 to XR_D2 in different combinations. For example, bits IN[0] to IN[2] and bit R[0] are input to the 4-input XOR circuit XR_D0, and bits IN[0], IN[1], IN[3] and bit R[2] are input to the 4-input XOR circuit XR_D2.

[0035] The outputs of the XOR circuits XR_D0 to XR_D2 are supplied to the 3-input AND circuits AD_D0 to AD_D3 and AD_EF. The circles drawn on the input sides of the 3-input AND circuits AD_D1 to AD_D3 and AD_EF mean inversion. That is, at the circled part, the supplied data is inverted and input to the AND circuit. As shown in FIG. 3, in the 3-input AND circuits AD_D1 to AD_D3, the outputs of different XOR circuits are inverted (circled) and input.

[0036] For example, in the 3-input AND circuit AD_D1 corresponding to the first bit of the data Din, the output from the XOR circuit XR_D1 is inverted and input. On the other hand, in the 3-input AND circuit AD_D2 corresponding to the second bit of the data Din, the output from the XOR circuit XR_D2 is inverted and input.

[0037] In the 3-input AND circuit AD_D0 corresponding to the 0th bit of the data Din, all the outputs from the XOR circuits XR_D0 to XR_D2 are input without being inverted. Also, in the 3-input AND circuit AD_EF corresponding to the error flag, all the outputs from the XOR circuits XR_D0 to XR_D2 are input after being inverted.

[0038] The correction circuit EC_C includes 2-input XOR circuits XR_C0 to XR_C3 corresponding to the bits IN[0] to IN[3] of the data Din. The XOR circuit XR_C0 corresponding to the 0th bit of the data Din is supplied with the bit IN[0] and the output of the 3-input AND circuit AD_D0 corresponding to the 0th bit. Also, the XOR circuit XR_C1 corresponding to the 1st bit of the data Din is supplied with the bit IN[1] and the output of the 3-input AND circuit AD_D1 corresponding to the 1st bit. Further, the XOR circuit XR_C2 corresponding to the 2nd bit of the data Din is supplied with the bit IN[2] and the output of the 3-input AND circuit AD_D2 corresponding to the 2nd bit. Similarly, the XOR circuit XR_C3 corresponding to the 3rd bit of the data Din is supplied with the bit IN[3] and the output of the 3-input AND circuit AD_D3 corresponding to the 3rd bit. The outputs of the XOR circuits XR_C0 to XR_C3 are output as the data Dout from the correction circuit EC_C. Also, the output of the 3-input AND circuit AD_EF becomes the error flag EFG.

[0039] In the data Din_E read from the memory RM, for example, if one bit (e.g., the bit IN[1] in FIG. 3) has its logical value inverted due to a soft error, using the read data Din_E and the code R, the decoder EC_D identifies the position of the bit whose logical value is inverted in the data Din_E (the 1st bit corresponding to the bit IN[1]). The correction circuit EC_C corrects (corrects by inversion) the logical value of the bit at the position identified by the decoder EC_D. At this time, the decoder EC_D notifies the occurrence of the error by the error flag EFG.

[0040] Incidentally, although not particularly limited, in Embodiment 1, each bit of the data Din_E and each bit of the code R are supplied to the decoder EC_D and the correction circuit EC_C via the buffer circuit BF_D, in the same manner as the encoder EC_E shown in FIG. 2. Of course, this buffer circuit BF_D may not be provided.

[0041] As shown in FIGS. 2 and 3, in the ECC circuit EC, many XOR circuits are used. Therefore, if the number of elements constituting the XOR circuit is large, the occupied area of the ECC circuit EC increases. In Embodiment 1, an XOR circuit that can be configured with a small number of elements is provided. As a result, it is possible to suppress an increase in the occupied area of the ECC circuit.

[0042] <<Specific Example of ECC Circuit>> Next, an example of a specific configuration of the ECC circuit according to Embodiment 1 will be described with reference to the drawings. In the following description, the description will be divided into a portion corresponding to the encoder EC_E and a portion corresponding to the decoder EC_D and the correction circuit EC_C.

[0043] <<Portion Corresponding to Encoder EC_E>> FIG. 4 is a block diagram showing an example of the ECC circuit according to Embodiment 1. In the figure, mainly, the portion corresponding to the encoder EC_E described in FIG. 1 is shown. In FIG. 4, CBP and RBA correspond to the front-stage circuit CBP and the storage area of the memory RM shown in FIG. 1. The encoder EC_E includes an input circuit (first input circuit) E_IN, a processing circuit (first processing circuit) E_PR, an output circuit (first output circuit) E_OT, and a control circuit (first control circuit) E_CTE.

[0044] The bits IN[0] to IN[K-1] constituting the data Din output from the front-stage circuit CBP are input to the input circuit E_IN, and the input circuit E_IN outputs data (signal) corresponding to the input data to the processing circuit E_PR.

[0045] The processing circuit E_PR includes a plurality of logic circuits (hereinafter also referred to as unit logic circuits) LG_A. The plurality of logic circuits LG_A have the same configuration as each other without particular limitation. In Embodiment 1, an example of the unit logic circuit LG_A will be described later with reference to FIG. 5 and the like, so detailed description is omitted here. By connecting the plurality of unit logic circuits LG_A, a plurality of multi-input logic circuits with three or more inputs (for example, the XOR circuits XR_E0 to XR_E2 shown in FIG. 2) are realized. A logic operation is performed on the data (signal) from the input circuit E_IN by the logic circuit realized by the plurality of unit logic circuits LG_A in the processing circuit E_PR. The result of the logic operation performed in the processing circuit E_PR is output from the processing circuit E_PR to the output circuit E_OT as bits XQ[0] to XQ[N-1] that constitute a code. The output circuit E_OT supplies the input code to the storage area RBA of the memory RM as bits R[0] to R[N-1] of the code R, and the supplied code is written into the storage area RBA.

[0046] The control circuit E_CTE receives an external clock signal ECLK and generates a timing signal for controlling the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT. That is, the control circuit E_CTE generates a trigger signal TRG synchronized with the external clock signal ECLK and an inverted trigger signal TRGB that is phase-inverted with respect to the trigger signal TRG, supplies them to the input circuit IN_U, and supplies the trigger signal TRG to the processing circuit E_PR. Further, the control circuit E_CTE supplies a clock signal CLK synchronized with the external clock signal ECLK and an inverted clock signal CLKB that is phase-inverted with respect to the clock signal CLK to the output circuit E_OT. The input circuit IN_U, the processing circuit E_PR, and the output circuit E_OT operate according to the timing signals (TRG, TRGB, CLK, CLKB) supplied from the control circuit E_CTE. The external clock signal ECLK supplied to the control circuit E_CTE is not particularly limited, but is generated by a circuit block (not shown) such as a control circuit formed in the semiconductor chip CHP (FIG. 1).

[0047] Note that the timing signal CCONT indicated by the dashed line will be described in Modification Example 1 later, so it is omitted here.

[0048] <<<An example of the logic circuit LG_A>>> FIG. 5 is a circuit diagram showing the configuration of the unit logic circuit according to Embodiment 1. The unit logic circuit LG_A includes two N-type MOS transistors (first N-type MOS transistor, second N-type MOS transistor) N1, N2, one P-type MOS transistor (first P-type MOS transistor) P1, and an inverter circuit (output driver) IV1. Each MOS transistor includes a first terminal T1 and a second terminal T2, and a gate terminal G for controlling conduction between the first terminal T1 and the second terminal T2. Note that the first terminal T1 and the second terminal T2 correspond to the source terminal and the drain terminal of the MOS transistor. However, since the source terminal and the drain terminal are determined by the voltage at the terminal, in this specification, when it is not necessary to specifically indicate the source terminal and the drain terminal, they will be described as the first terminal and the second terminal. Also, in order to avoid complicating the drawings, in the following drawings, in principle, the reference numerals T1, T2, and G will be omitted.

[0049] The first terminal T1 of the N-type MOS transistor N1 is connected to the input terminal A of the unit logic circuit LG_A and the gate terminal G of the N-type MOS transistor N2. The first terminal T1 of the N-type MOS transistor N2 is connected to the input terminal B of the unit logic circuit LG_A and the gate terminal G of the N-type MOS transistor N1. Also, the second terminals T2 of the N-type MOS transistors N1 and N2 are connected to the synthesis node CB, and the input terminal of the inverter circuit IV1 and the second terminal T2 of the P-type MOS transistor P1 are also connected to the synthesis node CB. Further, the first terminal T1 of the P-type MOS transistor P1 is connected to the power supply voltage (predetermined voltage) VDD, a trigger signal (first trigger signal) TRG is supplied to the gate terminal G of the P-type MOS transistor P1, and the output terminal of the inverter circuit IV1 is connected to the output terminal C of the unit logic circuit LG_A.

[0050] When the P-type MOS transistor P1 is turned on (conducting state) by the trigger signal TRG, the composite node CB is connected to the power supply voltage VDD via the P-type MOS transistor P1. As a result, the composite node CB including the input terminal of the inverter circuit IV1 is pre-charged to a voltage based on the power supply voltage VDD. Binary logic signals (first signal and second signal) are supplied to the input terminals A and B. During the processing period (logical operation period) after the pre-charge period, the unit logic circuit LG_A performs a logical operation (exclusive OR operation in FIG. 5) between the first signal and the second signal, and outputs an output signal corresponding to the logical operation result from the output terminal C.

[0051] <<<Operation example of logic circuit LG_A>>> FIG. 6 is a timing diagram for explaining the operation of the unit logic circuit according to the first embodiment. Using FIGS. 5 and 6, the operation of the unit logic circuit LG_A, that is, the exclusive OR operation, will be explained.

[0052] The period during which the trigger signal TRG is at the low level is the pre-charge period Tpr, and the period during which the trigger signal TRG is at the high level is the processing period Tlc. The control circuit E_CTE shown in FIG. 4 outputs a trigger signal TRG whose voltage periodically changes between high level and low level in synchronization with the external clock signal ECLK.

[0053] During the precharge period Tpr before the calculation start time TC_1, the trigger signal TRG becomes a low level. Also, during the precharge period Tpr, an input signal (first signal) with a logic value of 0 is supplied to the input terminal A, and an input signal (second signal) with a logic value of 0 is also supplied to the input terminal B. As a result, the P-type MOS transistor P1 is turned on, the N-type MOS transistors N1 and N2 are turned off, and the composite node CB is precharged to a voltage (high level) based on the power supply voltage VDD. Since the composite node CB is precharged to a high level, a low-level output signal is output from the output terminal C. This precharge period Tpr can be regarded as the initialization period of the logic circuit LG_A. When regarded as the initialization period, the logic circuit LG_A is supplied with the first signal and the second signal with a logic value of 0 at the time of initialization, and the logic circuit LG_A outputs an output signal with a logic value of 0.

[0054] During the calculation start time TC_1 and the subsequent processing period Tlc_1, the trigger signal TRG becomes a high level, and the first signal and the second signal for performing a logical operation are supplied to the input terminals A and B. In response to the high level of the trigger signal TRG, the P-type MOS transistor P1 is turned off. In the example of FIG. 6, the first signal and the second signal are at a low level during the calculation start time TC_1 and the processing period Tlc_1. Since the low level is supplied to the gate terminals G of the N-type MOS transistors N1 and N2, both of the N-type MOS transistors N1 and N2 maintain an off state. As a result, during the processing period Tlc_1, the composite node CB maintains the precharged voltage, and a low-level output signal continues to be output from the output terminal C.

[0055] During the precharge period Tpr following the processing period Tlc_1, the trigger signal TRG becomes low level again, and the synthetic node CB is precharged. At this time, the first signal and the second signal at initialization (logical value 0) are supplied to the input terminals A and B. At the operation start time TC_2 and during the processing period Tlc_2, the first signal with a logical value of 0 and the second signal with a logical value of 1 are supplied to the input terminals A and B. As a result, the voltage at the input terminal B becomes high level, and the voltage at the input terminal A becomes low level. Consequently, the N-type MOS transistor N1 changes to the on state, and the charge precharged to the synthetic node CB is discharged to the ground voltage VSS via the N-type MOS transistor N1, and a high-level output signal is output from the output terminal C. At this time, the N-type MOS transistor N2 maintains the off state.

[0056] During the precharge period Tpr following the processing period Tlc_2, the trigger signal TRG becomes low level again, and the synthetic node CB is precharged. Also at this time, the first signal and the second signal at initialization are supplied to the input terminals A and B. At the operation start time TC_3 and during the processing period Tlc_3, the first signal with a logical value of 1 and the second signal with a logical value of 0 are supplied to the input terminals A and B. As a result, the voltage at the input terminal A becomes high level, and the voltage at the input terminal B becomes low level. Consequently, the N-type MOS transistor N2 changes to the on state, and the charge precharged to the synthetic node CB is discharged to the ground voltage VSS via the N-type MOS transistor N2, and a high-level output signal is output from the output terminal C. At this time, the N-type MOS transistor N1 maintains the off state.

[0057] During the precharge period Tpr following the processing period Tlc_3, the trigger signal TRG becomes low level again, and the synthesis node CB is precharged. Also, at this time, the first signal and the second signal at the time of initialization are supplied to the input terminals A and B. At the operation start time TC_4 and the processing period Tlc_4, the first signal and the second signal with a logical value of 1 are supplied to the input terminals A and B. As a result, the voltages at the input terminals A and B become high level. Since the voltages of the gate terminals G, the first terminals T1, and the second terminals T2 of the N-type MOS transistors N1 and N2 become high level, the N-type MOS transistors N1 and N2 maintain the off state. As a result, the charge precharged to the synthesis node CB is not discharged to the ground voltage VSS via the N-type MOS transistors N1 and N2, the voltage of the synthesis node CB maintains the high level, and a low-level output signal is output from the output terminal C.

[0058] In this way, during the processing period Tlc, the exclusive OR operation based on the first signal and the second signal supplied to the input terminals A and B is performed and output in the unit logic circuit LG_A. This processing period Tlc can also be regarded as a logical operation period.

[0059] <<<An example of the input circuit E_IN and the processing circuit E_PR>>> <<<<Input circuit E_IN>>>> FIG. 7 is a circuit diagram showing an example of the input circuit and the processing circuit according to the first embodiment. The input circuit E_IN shown in FIG. 4 is composed of a plurality of unit input circuits IN_U corresponding to the bits IN[0] to IN[K - 1] that constitute the data Din from the preceding-stage circuit CBP. In FIG. 7, as an example, four unit input circuits IN_U0 to IN_U3 corresponding to the bits IN[0] to IN[3] among the bits IN[0] to IN[K - 1] are shown. Since the configurations of the four unit input circuits are the same, the unit input circuit IN_U0 will be described as an example.

[0060] The unit input circuit IN_U0 includes N-type MOS transistors N3 to N6 and P-type MOS transistors P2 and P3. The first terminal of the N-type MOS transistor N3 is connected to the first terminal of the P-type MOS transistor P2, the second terminal of the N-type MOS transistor N3 is connected to the second terminal of the P-type MOS transistor P2, a trigger signal TRG is supplied to the gate terminal of the N-type MOS transistor N3, and an inverted trigger signal TRGB is supplied to the gate terminal of the P-type MOS transistor P2. Also, the first terminals of the MOS transistors N3 and P2 are connected to the input terminal D of the unit input circuit IN_U0, and the second terminals of the MOS transistors N3 and P2 are connected to the output terminal F of the unit input circuit IN_U0. Thus, a CMOS pass (transfer) gate is formed, which is composed of the MOS transistors N3 and P2, connected between the input terminal D and the output terminal F, and controlled by the trigger signal TRG (inverted trigger signal TRGB).

[0061] Similarly, a CMOS pass gate is formed, which is composed of the MOS transistors N4 and P3, connected between the input terminal E and the output terminal G, and controlled by the trigger signal TRG (inverted trigger signal TRGB).

[0062] The first terminals of the N-type MOS transistors N5 and N6 are connected to the ground voltage VSS (GND), the second terminals are connected to the output terminals F and G of the unit input circuit IN_U0, and an inverted trigger signal TRGB is supplied to the gate terminals.

[0063] During the precharge period when the trigger signal TRG is at a low level (the inverted trigger signal TRGB is at a high level), the N-type MOS transistors N5 and N6 are turned on, and the N-type MOS transistors N3 and N4 are turned off. At this time, the P-type MOS transistors P2 and P3 are also turned off. That is, during the precharge period, the CMOS pass gate is in a non-conducting state, and the input terminals D and E are electrically separated from the output terminals F and G. At this time, the output terminals F and G are precharged to the ground voltage VSS. That is, the voltages at the output terminals F and G become a low level corresponding to the logical value 0.

[0064] During the processing (logical operation) period when the trigger signal TRG is at a high level (the inverted trigger signal TRGB is at a low level), the N-type MOS transistors N5 and N6 are in the off state, and the N-type MOS transistors N3 and N4 and the P-type MOS transistors P2 and P3 are in the on state. That is, the output terminals F and G are electrically separated from the ground voltage VSS and are electrically connected to the input terminals D and E via a CMOS pass gate.

[0065] That is, the unit input circuit IN_U0 outputs the logical value 0, which is the initial value, regardless of the logical value of the supplied bit during the precharge period, and outputs the logical value of the supplied bit during the processing period.

[0066] <<<<Processing circuit E_PR>>>> In the processing circuit E_PR according to the first embodiment, a plurality of 2-input unit logic circuits LG_A are connected in a tree shape to form one multi-input logic circuit. Specifically, an 8-input exclusive OR circuit is formed by connecting 7 unit logic circuits LG_A in a tree shape in three stages.

[0067] The input terminals A and B of the unit logic circuits LG_A10 to LG_A13 arranged in the first stage of the tree are electrically connected to the output terminals F and G of the corresponding unit input circuits IN_U0 to IN_U3 as shown in FIG. 7. Also, the input terminals A and B of the unit logic circuits LG_A20 and LG_A21 arranged in the second stage are connected to the output terminal C of the unit logic circuits LG_A10 to LG_A13 arranged in the first stage as shown in FIG. 7. Further, the input terminals A and B of the unit logic circuit LG_A30 arranged in the third stage are connected to the output terminal C of the unit logic circuits LG_A20 and LG_A21 arranged in the second stage as shown in FIG. 7.

[0068] For example, taking the unit logic circuit LG_A20 (the first logic circuit) as an example, the input terminals A and B of the second-stage unit logic circuit LG_A20 are electrically connected to the output terminal C of the first-stage unit logic circuits LG_A10 and LG_A11 (the second logic circuit and the third logic circuit), and the output terminal C of the second-stage unit logic circuit LG_A20 is electrically connected to the input terminal A of the third-stage unit logic circuit LG_A30.

[0069] During the precharge period, the output terminals F and G of the unit input circuit IN_U0 are precharged to the ground voltage VSS, so that the logical value 0 of the initial value is supplied to the first-stage unit logic circuit group LG_A1. Also, in the unit logic circuit group LG_A1, during the precharge period, the composite node CB is precharged with a voltage based on the power supply voltage VDD instead of the ground voltage VSS. As a result, during the precharge period, the logical value 0 of the initial value is supplied to the unit logic circuit groups LG_A2 and LG_A3 after the second stage.

[0070] During the processing period, the exclusive OR of the data Din (bits IN[0] to IN[7]) is sequentially obtained for the first stage, the second stage, and the third stage, and the operation result of the exclusive OR is output from the output terminal C of the third-stage unit logic circuit LG_A30.

[0071] In FIG. 7, one 8-input logic circuit configured using seven unit logic circuits was described as an example, but it is not limited to 8 inputs. Also, in the processing circuit E_PR, a plurality of multi-input logic circuits as shown in FIG. 7 are provided so as to realize the encoder as described in FIG. 2, and they are electrically connected to each other.

[0072] <<<An example of the output circuit E_OT>>> The data generated in the processing circuit E_PR, for example, the operation result from the 8-input logic circuit shown in FIG. 7, is output from the processing circuit E_PR to the output circuit E_OT as the bits XQ[0] to XQ[N - 1] constituting the code.

[0073] As shown in FIG. 4, the output circuit E_OT includes a plurality of unit output circuits OU_U corresponding to bits XQ[0] to XQ[N - 1]. Since the unit output circuits OU_U corresponding to bits XQ[0] to XQ[N - 1] have the same configuration, here, the unit output circuit OU_U0 corresponding to bit XQ[0] will be described as an example. FIG. 8 is a circuit diagram showing the configuration of an example of the unit output circuit according to the first embodiment.

[0074] The unit output circuit OU_U0 includes N-type MOS transistors N7 to N9, P-type MOS transistors P4 to P6, and an inverter circuit IV2.

[0075] The first terminals of the N-type MOS transistor N7 and the P-type MOS transistor P4 are connected to each other, and the second terminals of the two are connected to each other. Also, a clock signal CLK is supplied to the gate terminal of the P-type MOS transistor P4, and an inverted clock signal CLKB is supplied to the gate terminal of the N-type MOS transistor N7. Thus, a CMOS pass gate is formed by the P-type MOS transistor P4 and the N-type MOS transistor N7. The corresponding bit XQ[0] is supplied to the input terminal of the CMOS pass gate, and the output terminal of the CMOS pass gate is connected to the input terminal of the inverter circuit IV2 and the output terminal of the clocked inverter circuit CIV1 described below.

[0076] As shown in FIG. 8, the clocked inverter circuit CIV1 is composed of P-type MOS transistors P5 and P6 and N-type MOS transistors N8 and N9 connected in series between the power supply voltage VDD and the ground voltage VSS. Here, the gate terminal of the P-type MOS transistor P5 and the gate terminal of the N-type MOS transistor N9 are connected to the output terminal of the inverter circuit IV2. The inverted clock signal CLKB is supplied to the gate terminal of the P-type MOS transistor P6, and the clock signal CLK is supplied to the gate terminal of the N-type MOS transistor N8. The connection node between the P-type MOS transistor P6 and the N-type MOS transistor N8 becomes the output terminal of the clocked inverter circuit CIV1, and the gate terminals of the P-type MOS transistor P5 and the N-type MOS transistor N9 become the input terminals of the clocked inverter circuit CIV1. The output terminal of the inverter circuit IV2 becomes the output terminal of the unit output circuit OU_U0, and the code R[0] corresponding to the bit XQ[0] is output from the unit output circuit OU_U0 to the storage area RBA (FIG. 4) of the memory RM.

[0077] The CMOS pass gate in the unit output circuit OU_U0 is in a conductive state when the clock signal CLK is at a low level (the inverted clock signal CLKB is at a high level), supplies the bit XQ[0] to the inverter circuit IV2, and is in a non-conductive state when the clock signal CLK is at a high level, stopping the supply of the bit XQ[0] to the inverter circuit IV2. That is, during the period when the clock signal CLK is at a low level, the unit output circuit OU_U0 takes in the bit XQ[0].

[0078] The input terminal of the inverter circuit IV2 is connected to the output terminal of the clocked inverter circuit CIV1, and the output terminal of the inverter circuit IV2 is connected to the input terminal of the clocked inverter circuit CIV1. Therefore, a latch circuit FF that operates in synchronization with the clock signal CLK (inverted clock signal CLKB) is constituted by the inverter circuit IV2 and the clocked inverter circuit CIV1. The latch circuit FF latches the logical value of the bit XQ[0] supplied via the CMOS pass gate when the clock signal CLK is at a high level (inverted clock signal CLKB is at a low level).

[0079] Therefore, the unit output circuit OU_U0 captures the logical value of the bit XQ[0] during the period when the clock signal CLK is at a low level, and then holds the logical value of the captured bit XQ[0] when the clock signal CLK becomes high. Note that the unit output circuit OU_U0 inverts (logical inversion) the logical value of the captured bit XQ[0] and outputs it as the code R[0].

[0080] <<Operation of the Encoder>> Next, the operation of the encoder EC_E shown in FIG. 4 will be described with reference to the drawings. FIG. 9 is a timing chart for explaining the operation of the encoder according to the first embodiment.

[0081] The control circuit E_CTE shown in FIG. 4 generates the clock signal CLK and the trigger signal TRG shown in FIG. 9 based on the external clock signal ECLK. Although not shown in FIG. 9, the control circuit E_CTE also generates the inverted clock signal CLKB and the inverted trigger signal TRGB. In the first embodiment, the control circuit E_CTE generates a trigger signal that rises in synchronization with the falling edge of the clock signal CLK as the trigger signal TRG.

[0082] In Embodiment 1, the memory RM (Fig. 1) starts writing and reading operations in synchronization with the rising edge of an external clock signal ECLK (in Fig. 9, a clock signal CLK in phase with ECLK). In Fig. 9, WTT indicates a period (writing period) during which writing is performed to the storage area RBA of the memory RM. Also, the symbols TW0 to TW3 indicate writing cycles. In Embodiment 1, for a predetermined writing cycle in which code R is written to the memory RM, the code R to be written in the predetermined writing cycle is generated in the immediately preceding writing cycle in terms of time.

[0083] Bits IN[0] to IN[K - 1] constituting the data Din are input to the input circuit E_IN during times t0 to t1 of the first writing cycle TW0. In Fig. 9, only bit IN[0] among bits IN[0] to IN[K - 1] is shown as an example. In the input circuit E_IN and the processing circuit E_PR, as described in Figs. 5 to 7, precharge is executed during the period when the trigger signal TRG is at the low level (the inverted trigger signal TRGB is at the high level). Therefore, during the period from time t0 to t1 of the first writing cycle TW0, precharge is being performed in the input circuit E_IN and the processing circuit E_PR. Since precharge is being performed, the data (data composed of bits XQ[0] to XQ[N - 1]) supplied from the processing circuit E_PR to the output circuit E_OT becomes the precharge level. In Fig. 9, only bit XQ[0] is shown as a representative, and the precharge level is at the high level (for example, the power supply voltage VDD).

[0084] Also, as described in Fig. 8, the output circuit E_OT has a CMOS passgate composed of an N-type MOS transistor N7 and a P-type MOS transistor P4 in a non-conductive state during the period when the clock signal CLK is at the high level. Therefore, during the period from time t0 to t1 of the writing cycle TW0, the data supplied to the output circuit E_OT is not output as code R.

[0085] At time t1 of write cycle TW0, when the trigger signal TRG changes to a high level (the inverted trigger signal TRGB is at a low level), as shown in FIGS. 5 to 7, the precharge in the input circuit E_IN and the processing circuit E_PR is completed, and the unit logic circuits arranged in a tree shape in the processing circuit E_PR sequentially perform logical operations on the data Din, and during the period from time t1 to t2 of cycle TW0, a code R (a bit string including bit R[0]) is generated.

[0086] At times t1 to t3 of cycle TW0, since the clock signal CLK is at a low level (the inverted clock signal CLKB is at a high level), during this period, as described in FIG. 8, the CMOS pass gate composed of the N-type MOS transistor N7 and the P-type MOS transistor P4 is in a conductive state, and the code R generated during the period from time t1 to t2 of write cycle TW0 is held in the latch circuit FF of the output circuit E_OT, and the code R will be supplied to the memory RM.

[0087] At times t2 to t3 of write cycle TW0, the code R supplied to the memory RM is written into the storage area RBA of the memory RM during the write period WTT starting from time t0 (the same as time t3 of the previous write cycle TW0) of write cycle TW1 following cycle TW0.

[0088] Also at times t0 to t3 of write cycle TW1, the same operations as those at times t0 to t3 of write cycle TW0 are performed. The same applies to subsequent write cycles such as TW3.

[0089] In the bits IN[0] to IN[K - 1] that make up the data Din, when the number of bits with a logical value of 1 is even, the processing circuit E_PR generates the bit R[0] of the code R with a logical value of 0, as shown at times t2 to t3 of the write cycle TW0. On the other hand, in the bits IN[0] to IN[K - 1] of the data Din, when the number of bits with a logical value of 1 is odd, the processing circuit E_PR generates the bit R[0] of the code R with a logical value of 1, as shown at times t2 to t3 of the write cycle TW1. Although the bit R[0] is described as an example, the same applies to other bits.

[0090] The unit logic circuit LG_A and the processing circuit E_PR including a plurality of unit logic circuits LG_A according to Embodiment 1 are dynamic circuits that require a precharge operation. That is, it is necessary to secure a period (time) for performing the precharge operation. There is a concern that this period of the precharge operation may slow down the operation of the semiconductor device. However, according to Embodiment 1, as shown in FIG. 9, the period of the precharge operation partially overlaps with the write period WTT during which writing is being performed to the memory RM. That is, by hiding the period of the precharge operation within the write period WTT, it is possible to suppress the operation of the semiconductor device from being slowed down.

[0091] <<Portion Corresponding to Decoder EC_D and Correction Circuit EC_C>> FIG. 10 is a block diagram showing an example of the ECC circuit according to Embodiment 1. In the figure, mainly, the portions corresponding to the decoder EC_D and the correction circuit EC_C described in FIG. 1 are shown. In FIG. 10, RM (storage area DBA + RBA) corresponds to the memory shown in FIG. 1, and CBA corresponds to the subsequent circuit CBA shown in FIG. 1. The decoder EC_D includes an input circuit (second input circuit) E_IN, a processing circuit (second processing circuit) E_PR, an output circuit (second output circuit) E_OT, and a control circuit (second control circuit) E_CTD.

[0092] Memory RM starts a read operation in synchronization with the rising edge of the external clock signal ECLK. The code R and the data Din_E read from the storage areas RBA and DBA of memory RM are input to the input circuit E_IN. The data and code output from the input circuit E_IN are input to the processing circuit E_PR. The data (bits XQ[0] to XQ[N-1]) of the processing result obtained by the processing circuit E_PR is input to the output circuit E_OT. The output circuit E_OT outputs the input data as data DD (bits DD[0] to DD[N-1]) to the correction circuit EC_C.

[0093] The memory RM according to Embodiment 1 is not particularly limited, but as shown in FIG. 10, it includes a plurality of inverter circuits, and an output completion signal QSET indicating the timing at which the read operation is completed is generated based on the external clock signal ECLK using this inverter circuit or the like.

[0094] The control circuit E_CTD is supplied with the external clock signal ECLK and the output completion signal QSET from the memory RM, and the control circuit E_CTD generates a trigger signal TRG, an inverted trigger signal TRGB, a clock signal CLK, and an inverted clock signal CLKB based on the external clock signal ECLK and the output completion signal QSET.

[0095] The input circuit E_IN is similar to the input circuit E_IN shown in FIG. 4. The main difference is that the input circuit E_IN shown in FIG. 10 is supplied with the code R (R[0] to R[N-1]) and the data Din_E from the memory RM. The output circuit E_OT is also similar to the output circuit E_OT shown in FIG. 4. The main difference is that the output circuit E_OT shown in FIG. 10 outputs the data (bits XQ[0] to XQ[N-1]) as the data DD (bits DD[0] to DD[N-1]) to the correction circuit EC_C. Also, the processing circuit E_PR is similar to the processing circuit E_PR shown in FIG. 4. The main difference is that in the processing circuit E_PR shown in FIG. 10, by connecting a plurality of unit logic circuits LG_A, logic circuits such as the XOR circuits XR_D0 to XR_D2 as described in FIG. 3 are configured, and further, the AND circuits AD_D0 to AD_D3 and AD_EF as described in FIG. 3 are provided in the processing circuit E_PR.

[0096] The operations of the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT shown in FIG. 10 are similar to the operations described with reference to FIGS. 4 to 8, and thus are omitted here.

[0097] The correction circuit EC_C is supplied with the data DD (bits DD[0] to DD[N-1]) and the data Din_E from the storage area DBA. The correction circuit EC_C includes logic circuits such as the XOR circuits XR_C0 to XR_C3 described in FIG. 3, and corrects, for example, the bits where an error has occurred, and supplies the corrected data to the subsequent-stage circuit CBA.

[0098] <<Operation of the decoder>> Next, the operation of the decoder shown in FIG. 10 will be described with reference to the drawings. FIG. 11 is a timing chart for explaining the operation of the decoder according to Embodiment 1.

[0099] In FIG. 11, ROT indicates a period (read period) of an operation of reading data Din_E and code R from memory RM. Note that the starting point of the read period ROT is the rising timing of the clock signal CLK as shown in FIG. 11. Also, the symbols TR0 to TR3 indicate read cycles of data Din and code R.

[0100] In Embodiment 1, the trigger signal TRG and the inverted trigger signal TRGB are generated by the control circuit E_CTD based on the rising timing of the output completion signal QSET. Also, the pulse widths (widths in the time axis direction) of the trigger signal TRG and the inverted trigger signal TRGB are set by, for example, a delay circuit provided in the control circuit E_CTD.

[0101] At times t0 to t2 of the read cycle TR0, the trigger signal TRG becomes low level. As a result, precharge is performed in the input circuit E_IN and the processing circuit E_PR in the same manner as described with reference to FIG. 9. Since precharge is being performed, the bits XQ[0] to XQ[N - 1] output from the processing circuit E_PR become high level. Note that only bit XQ[0] is shown in FIG. 11. Also, an example in which precharge is performed during the period from time t0 to t1 is shown in FIG. 11.

[0102] When the reading is completed at time t2 of the read cycle TR0 and the output completion signal QSET rises, in response to this, the trigger signal TRG rises. As a result, the input circuit E_IN captures the bits R[0] to R[N - 1] of the data Din_E and code R read from the memory RM and supplies them to the processing circuit E_PR. Also, in the processing circuit E_PR, a logical operation is performed. The bits XQ[0] to XQ[N - 1] of the operation result are generated between times t2 and t3 of the read cycle TR0 and supplied to the output circuit E_OT.

[0103] As shown in FIG. 8, the output circuit E_OT captures the operation result during the period when the clock signal CLK is at the low level, and when the clock signal CLK changes to the high level, the captured operation result is held by the latch circuit FF. Therefore, at times t0 to t1 of the next read cycle TR1, the bits DD[0] to DD[N - 1] corresponding to the bits XQ[0] to XQ[N - 1] of the operation result in the processing circuit E_PR are supplied from the output circuit E_OT to the correction circuit EC_C.

[0104] Also in the decoder according to the first embodiment, the precharge operation period partially overlaps with the read period ROT during which reading is performed on the memory RM. That is, by hiding the precharge operation period within the read period ROT, it is possible to suppress a slowdown in the operation of the semiconductor device.

[0105] Similar to the processing circuit E_PR of the encoder EC_E shown in FIG. 4, in the decoder EC_D, when the number of bits whose logical value is 1 in the data input from the input circuit E_IN is even, the processing circuit E_PR generates a bit DD[0] with a logical value of 0 as shown at times t3 to t4 of the read cycle TR0. On the other hand, when the number of bits whose logical value is 1 in the data input from the input circuit E_IN is odd, the processing circuit E_PR generates a bit DD[0] with a logical value of 1 as shown at times t3 to t4 of the read cycle TR1.

[0106] The unit logic circuit LG_A according to Embodiment 1 and the processing circuit E_PR including a plurality of unit logic circuits LG_A are dynamic circuits that require a precharge operation. That is, it is necessary to secure a period (time) for performing the precharge operation, and there is a concern that the operation of the semiconductor device may be slowed down. However, according to Embodiment 1, as shown in FIG. 11, the period of the precharge operation partially overlaps with the read period ROT during which the memory RM is being read. That is, since the period of the precharge operation can be hidden by the read period ROT, it is possible to suppress the slowdown of the operation of the semiconductor device.

[0107] In FIGS. 9 and 11, it was explained that the bits XQ[0] to XQ[N - 1], which are the outputs from the processing circuit E_PR, become high level by precharge. On the other hand, in the configuration of the processing circuit shown in FIG. 7, the output terminal C of the third-stage unit logic circuit LG_A30 becomes low level by precharge. This is because a logic circuit (not shown) that causes a logic inversion is provided between the third-stage unit logic circuit LG_A30 shown in FIG. 7 and the output of the processing circuit E_PR. In order to cancel the logic inversion by the logic circuit not shown, the unit output circuit OU_U0 is configured to output after logic inversion as described with reference to FIG. 8. Of course, the bits XQ[0] to XQ[N - 1] from the processing circuit E_PR may be set to low level by precharge.

[0108] <Modification Example 1> In Modification Example 1, the front-end circuit CBP and the control circuit E_CTE shown in FIG. 4 are changed. That is, the front-end circuit CBP is changed to generate a timing signal CCONT and supply it to the control circuit E_CTE. Similar to the output completion signal QSET described with reference to FIGS. 10 and 11, when the processing in the front-end circuit CBP is completed, the front-end circuit CBP generates a timing signal CCONT indicating completion. The control circuit E_CTE according to Modification Example 1 generates a trigger signal TRG, an inverted trigger signal TRGB, a clock signal CLK, and an inverted clock signal CLKB, which are timing signals according to the processing of the front-end circuit CBP, based on the timing signal CCONT. Note that the remaining circuit blocks shown in FIG. 4 are not changed.

[0109] In Modification Example 1, when the processing in the front-end circuit CBP is completed, starting from this completion of the processing, the input circuit E_IN, the processing circuit E_PR, and the output circuit E_OT start operating. Thereby, delay loss in the context can be eliminated, and high speed operation can be achieved.

[0110] <Modification Example 2> In FIGS. 1 to 11, the exclusive OR circuit has been described as the unit logic circuit LG_A, but in Modification Example 2, a negative exclusive OR circuit (hereinafter also referred to as an XNOR circuit) will be described.

[0111] FIG. 12 is a diagram for explaining the unit logic circuit according to Modification Example 2 of Embodiment 1. Here, FIG. 12(A) shows a circuit diagram of the XNOR circuit constituting the unit logic circuit LG_AN, and FIG. 12(B) is a truth table showing the operation of the XNOR circuit of FIG. 12(A).

[0112] As shown in FIG. 12(A), the XNOR circuit includes P-type MOS transistors P7 and P8, an N-type MOS transistor N10, and an inverter circuit IV3. A 2-input XNOR circuit is configured by these MOS transistors and the inverter circuit.

[0113] The first terminal of P-type MOS transistor P7 is connected to the input terminal A of the XNOR circuit and the gate terminal of P-type MOS transistor P8. The first terminal of P-type MOS transistor P8 is connected to the input terminal B of the XNOR circuit and the gate terminal of P-type MOS transistor P7. Also, the second terminals of P-type MOS transistors P7 and P8 are connected to the combined node CB to which the input terminal of inverter circuit IV3 is connected. An N-type MOS transistor N10 is connected between the combined node CB and the ground voltage VSS (GND). That is, the first terminal of N-type MOS transistor N10 is connected to the ground voltage VSS, the second terminal is connected to the combined node CB, and the trigger signal TRG is supplied to the gate terminal. The output terminal of inverter circuit IV3 is connected to the output terminal C of the XNOR circuit.

[0114] The XNOR circuit according to Modification 2 also operates in the order of the precharge period and the processing period, similar to the XOR circuit described with reference to FIGS. 5 and 6. That is, in the precharge period, the trigger signal TRG is at a high level (logical value 1), and the N-type MOS transistor N10 is in an on state. As a result, the combined node CB is precharged (discharged) to a voltage based on the ground voltage VSS. Thereafter, the trigger signal TRG becomes a low level (logical value 0), and the process proceeds to the processing period.

[0115] For example, in the processing period, as shown in FIG. 12(B), when signals (first signal, second signal) having the same logical value (0, 0 or 1, 1) are supplied to the input terminals A and B, a logical value 1 is output from the output terminal C. On the other hand, when signals having different logical values are supplied to the input terminals A and B, a logical value 0 is output from the output terminal C. That is, a 2-input XNOR circuit can be realized with a small number of elements.

[0116] In the XOR circuit shown in FIG. 5 and the XNOR circuit shown in FIG. 12, the P-type MOS transistor and the N-type MOS transistor may be changed to MOS transistors of the opposite conductivity type. For example, in FIG. 5, the MOS transistors N1 and N2 may be changed to P-type MOS transistors, and the MOS transistor P1 may be changed to an N-type MOS transistor. In this case, the inverter circuit IV1 will be changed to a buffer circuit that does not perform an inversion operation. Such a buffer circuit that does not perform an inversion operation can be realized, for example, by connecting an even number of inverter circuits in series, but the number of MOS transistors will increase, leading to an increase in the occupied area. In order to suppress the increase in the occupied area, it is desirable to adopt the configuration shown in FIG. 5. Although the XOR circuit has been described as an example, similarly for the XNOR circuit, in order to suppress the increase in the occupied area, it is desirable to adopt the configuration shown in FIG. 12.

[0117] (Embodiment 2) In Embodiment 1, a semiconductor device including an ECC circuit configured using a plurality of unit logic circuits was described. The circuit configured using a plurality of unit logic circuits is not limited to the ECC circuit. In Embodiment 2, examples other than the ECC circuit will be described. Specifically, a multi-input parallel multiplier (hereinafter also simply referred to as a multiplier) configured using a plurality of unit logic circuits will be described.

[0118] FIG. 13 is a block diagram showing the configuration of a multiplier according to Embodiment 2. In FIG. 13, MUP indicates a multiplier formed on a semiconductor chip. As shown in FIG. 13, the multiplier MUP is composed of a plurality of full adder circuits (full adders) FA, a plurality of half adder circuits (half adders) HA, and a plurality of AND circuits. The multiplier MUP shown in FIG. 13 multiplies the first input data composed of bits X0 to X4 and the second input data composed of bits Y0 to Y4, and calculates the multiplication result composed of bits Z0 to Z8 and the carry C.

[0119] FIG. 14 is a block diagram showing the configuration of the addition circuit according to Embodiment 2. Here, FIG. 14(A) shows the configuration of the full adder circuit FA, and FIG. 14(B) shows the configuration of the half adder circuit HA. As shown in FIG. 14(A), the full adder circuit FA is composed of three XOR circuits FA_1 to FA_3 and two AND circuits FA_4 to FA_5. As shown in FIG. 14(B), the half adder circuit HA is composed of one XOR circuit HA_1 and one AND circuit HA_2.

[0120] In Embodiment 2, each of the three XOR circuits FA_1 to FA_3 constituting the full adder circuit FA shown in FIG. 14(A) is constituted by the XOR circuit shown in FIG. 5. Also, the XOR circuit HA_1 constituting the half adder circuit HA shown in FIG. 14(B) is constituted by the XOR circuit shown in FIG. 5. Thereby, it is possible to reduce the occupied area of the XOR circuit and suppress an increase in the occupied area of the multiplier MUP. Of course, it is not necessary to configure all the XOR circuits in the full adder circuit FA and the half adder circuit FA constituting the multiplier MUP to have the configuration shown in FIG. 5.

[0121] (Embodiment 3) FIG. 15 is a block diagram showing an example of the ECC circuit according to Embodiment 3. In the figure, mainly, the part corresponding to the encoder EC_E described in FIG. 1 is shown. FIG. 15 is similar to FIG. 4. The main difference is that in FIG. 15, the input circuit E_IN shown in FIG. 4 is not provided, and the bits IN[0] to IN[K - 1], which are the data from the preceding stage circuit CBP, are input to the processing circuit E_PR, and the processing circuit E_PR includes two types of unit logic circuits (first unit logic circuit, second unit logic circuit) LG_A and LG_B. A plurality of each of the two types of unit logic circuits LG_A and LG_B are provided in the processing circuit E_PR.

[0122] The unit logic circuit (second unit logic circuit) LG_A has the configuration shown in FIG. 5 and operates as described with reference to FIG. 6 and the like. On the other hand, the unit logic circuit (first unit logic circuit) LG_B has the functions of the unit logic circuit LG_A and the function corresponding to the unit input circuit IN_U. In other words, the unit logic circuit LG_B is obtained by adding the function of the unit input circuit IN_U to the unit logic circuit LG_A.

[0123] FIG. 16 is a circuit diagram showing the configuration of the unit logic circuit according to Embodiment 3. The unit logic circuit LG_B includes N-type MOS transistors N11 to N14, P-type MOS transistors P9 to P11, and an inverter circuit IV4.

[0124] The N-type MOS transistor (first MOS transistor) N11 has its first terminal T1 connected to the input terminal A of the unit logic circuit LG_B, and its gate terminal G connected to the input terminal B of the unit logic circuit LG_B via the source-drain (first terminal-second terminal) path of the P-type MOS transistor (seventh MOS transistor) P11. Also, the N-type MOS transistor (second MOS transistor) N12 has its first terminal T1 connected to the input terminal B of the unit logic circuit LG_B, and its gate terminal G connected to the input terminal A of the unit logic circuit LG_B via the source-drain path of the P-type MOS transistor (eighth MOS transistor) P10. The second terminals T2 of the N-type MOS transistors N11 and N12 are connected to a composite node CB to which the input terminal of the inverter circuit IV4 is connected. The composite node CB is connected to the power supply voltage VDD via the source-drain path of the P-type MOS transistor (third MOS transistor) P9. Further, the output terminal of the inverter circuit IV4 is connected to the output terminal C of the unit logic circuit LG_B.

[0125] The gate terminals G of the N-type MOS transistors N11 and N12 are connected to the ground voltage VSS via the source-drain paths of the N-type MOS transistors N14 and N13.

[0126] A trigger signal TRG is supplied to the gate terminal G of the P-type MOS transistor P9. On the other hand, an inverted trigger signal TRGB is supplied to the gates of the N-type MOS transistors N13, N14 and the P-type MOS transistors P10, P11.

[0127] The N-type MOS transistors N11, N12 and the P-type MOS transistor P9 shown in FIG. 16 correspond to the N-type MOS transistors N1, N2 and the P-type MOS transistor P1 shown in FIG. 4.

[0128] During the precharge period, the P-type MOS transistor P9 is turned on, and the composite node CB is precharged to a voltage based on the power supply voltage VDD. Also, during the precharge period, the inverted trigger signal TRGB turns on the N-type MOS transistors N13, N14 and turns off the P-type MOS transistors P10, P11. As a result, the N-type MOS transistors N11 and N12 are turned off, and the gate terminals G of the N-type MOS transistors N11, N12 are electrically separated from the input terminals B, A. As a result, during the precharge period, a low-level logic value is output as the initial value from the output terminal C.

[0129] When the precharge period ends and during the processing period, the trigger signal TRG becomes high level and the inverted trigger signal TRGB becomes low level. As a result, the N-type MOS transistors N13, N14 are turned off and the P-type MOS transistors P10, P11 are turned on. As a result, the input terminal A is electrically connected to the gate terminal G of the N-type MOS transistor N12 via the P-type MOS transistor P10. Similarly, the input terminal B is electrically connected to the gate terminal G of the N-type MOS transistor N11 via the P-type MOS transistor P11. As a result, during the processing period, the N-type MOS transistors N11, N12 operate in the same manner as the N-type MOS transistors N1, N2 in FIG. 4, obtain the exclusive OR of the signals supplied to the input terminals A, B, and output the result from the output terminal C.

[0130] The unit logic circuit LG_B is used as the first-stage unit logic circuit group (LG_A10 to LG_A13) in, for example, FIG. 7. To explain the case where the unit logic circuit LG_B shown in FIG. 16 is used as the unit logic circuit LG_A10 shown in FIG. 7, the unit input circuit IN_U0 is omitted, and the bits IN[0] and IN[1] are supplied to the input terminals A and B of the unit logic circuit LG_B shown in FIG. 16, and the output terminal C of the unit logic circuit LG_B is connected to the input terminal A of the second-stage unit logic circuit LG_A20. Of course, in this case, the second-stage unit logic circuit LG_A20 is composed of the unit logic circuit LG_A.

[0131] Here, an example in which the processing circuit in the encoder EC_E is composed of two types of unit logic circuits LG_A and LG_B is shown, but it is not limited to this. That is, the processing circuit in the decoder EC_D may be composed of two types of unit logic circuits LG_A and LG_B. Of course, the processing circuits of both the encoder EC_E and the decoder EC_D may be composed of two types of unit logic circuits LG_A and LG_B.

[0132] According to the third embodiment, since the input circuit E_IN can be omitted, the number of elements can be further reduced, and an increase in the occupied area can be further suppressed.

[0133] FIGS. 17 and 18 are diagrams for explaining the effects of the ECC circuit according to the first embodiment. Here, FIG. 17 is a diagram showing the effect of suppressing an increase in the occupied area, and FIG. 18 is a diagram showing the speeding up of the operation.

[0134] In FIG. 17, the horizontal axis indicates the number of gates constituted by XOR circuits, and the vertical axis indicates the number of MOS transistors (Tr) required to constitute the gates. In the figure, P = XOR(12Tr) indicates the case where a gate is constituted by the XOR circuit shown in Patent Document 1. In contrast, A = XOR(5Tr) indicates the case where a gate is constituted by the XOR circuit shown in FIG. 5. Further, in FIG. 17, AR = XOR(5Tr) + peripheral circuit indicates the case where MOS transistors constituting the peripheral circuit are added to A = XOR(5Tr). In FIG. 17, as indicated by the downward arrow, according to Embodiment 1, compared with the case of using the XOR circuit shown in Patent Document 1, for example, it is possible to reduce about 2000 MOS transistors, and it is possible to suppress an increase in the occupied area.

[0135] FIG. 18 shows the speed of a semiconductor device provided with an ECC circuit. In FIG. 18, P = ECC(XOT(12Tr)) indicates the operation when the ECC circuit is constituted by using the XOR circuit shown in Patent Document 1. Further, A = ECC(XOR(5Tr)) indicates the case where the ECC circuit is constituted by the XOR circuit shown in FIG. 5 as described in Embodiment 1. In FIG. 18, SRAM indicates the time of the read cycle required to read data from the memory, and ECC indicates the time during which error detection and correction are performed on the data read from the memory by the ECC circuit.

[0136] As high integration progresses, for example, memory cells constituting a memory become smaller, and a decrease in reliability due to soft errors becomes a problem. Therefore, it is considered essential to provide an ECC circuit in a semiconductor device.

[0137] However, error detection and correction by the ECC circuit takes time and the speed increase is limited. That is, for example, in the XOR circuit shown in Patent Document 1, since a plurality of MOS transistors are connected in series between the power supply voltage VDD (or the ground voltage VSS) and the output terminal, the change in voltage at the output terminal becomes slow, and the operation of the ECC circuit becomes slow. On the other hand, in the XOR circuit according to Embodiment 1, it is possible to prevent the change in voltage at the output terminal from becoming slow, and it is possible to speed up the operation of the ECC circuit. As a result, the sum of the time of the memory read cycle and the time by the operation cycle of the ECC circuit can be shortened from Tcyc1 to Tcyc2, and the speed can be increased.

[0138] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0139] CBA post-stage circuit CBP pre-stage circuit CLK clock signal CLKB inverted clock signal CHP semiconductor chip E_IN input circuit E_OT output circuit E_PR processing circuit EC ECC circuit EC_C correction circuit EC_D decoder EC_E encoder IV1~IV4 inverter circuit LG_A, LG_AN, LG_B unit logic circuit N1~N14 N-type MOS transistor P1~P11 P-type MOS transistor RM memory TRG trigger signal TRGB inverted trigger signal

Claims

1. A semiconductor device including a semiconductor chip on which a plurality of circuit blocks are formed, wherein the plurality of circuit blocks include, a memory, a first input circuit that outputs a signal, a first processing circuit including a plurality of logic circuits that processes the signal from the first input circuit, a first output circuit that supplies the output of the first processing circuit to the memory, and, each of the plurality of logic circuits includes, a first N-type MOS transistor including a first terminal, a second terminal, and a first gate terminal that controls conduction between the first terminal and the second terminal, wherein a first signal from the first input circuit is supplied to the first terminal and a second signal from the first input circuit is supplied to the first gate terminal, a second N-type MOS transistor including a third terminal, a fourth terminal, and a second gate terminal that controls conduction between the third terminal and the fourth terminal, wherein the second signal is supplied to the third terminal and the first signal is supplied to the second gate terminal, an output driver including an input terminal to which the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor are connected, a first P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a first trigger signal supplied to a gate terminal, and, after being precharged by the first trigger signal, the output driver of the logic circuit outputs a signal according to a result of a logical operation between the first signal and the second signal. A semiconductor device.

2. In the semiconductor device according to claim 1, the plurality of logic circuits include a first logic circuit, a second logic circuit, and a third logic circuit, The output of the second logic circuit is supplied as the first signal to the first terminal of the first logic circuit and the second gate terminal of the first logic circuit, and the output of the third logic circuit is supplied as the second signal to the third terminal of the first logic circuit and the first gate terminal of the first logic circuit. Semiconductor device.

3. In the semiconductor device according to claim 2, During the period when the signal from the first output circuit is written to the memory, the output drivers in the first logic circuit, the second logic circuit, and the third logic circuit are precharged by the first trigger signal. Semiconductor device.

4. In the semiconductor device according to claim 3, The plurality of circuit blocks include: A pre-stage circuit that supplies signals to the memory and the first input circuit; A first control circuit that is connected to the pre-stage circuit and the first processing circuit and outputs a timing signal according to the processing of the pre-stage circuit; and further includes: The timing signal output from the first control circuit is supplied as the first trigger signal to the gate terminal of the first P-type MOS transistor in the first logic circuit. Semiconductor device.

5. In the semiconductor device according to claim 4, The timing signal output from the first control circuit is supplied as the first trigger signal to the gate terminals of the first P-type MOS transistors in the second logic circuit and the third logic circuit. Semiconductor device.

6. In the semiconductor device according to claim 5, The timing signal output from the first control circuit is supplied to the first input circuit and the first output circuit, and the first input circuit and the first output circuit operate according to the timing signal. Semiconductor device.

7. In the semiconductor device according to claim 3, the plurality of circuit blocks include a second input circuit to which a signal is supplied from the memory, a second processing circuit including a plurality of logic circuits and processing a signal from the second input circuit, a second output circuit to which a signal from the second processing circuit is supplied, and are provided with each of the plurality of logic circuits in the second processing circuit includes a fifth terminal, a sixth terminal, and a third gate terminal for controlling conduction between the fifth terminal and the sixth terminal, a first signal from the second input circuit is supplied to the fifth terminal, and a third N-type MOS transistor to which a second signal from the second input circuit is supplied to the third gate terminal; a seventh terminal, an eighth terminal, and a fourth gate terminal for controlling conduction between the seventh terminal and the eighth terminal, a second signal from the second input circuit is supplied to the seventh terminal, and a fourth N-type MOS transistor to which a first signal from the second input circuit is supplied to the fourth gate terminal; an output driver including an input terminal to which the sixth terminal of the third N-type MOS transistor and the eighth terminal of the fourth N-type MOS transistor are connected; a second P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage, and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a second trigger signal supplied to the gate terminal; and are provided with after the output driver of the logic circuit in the second processing circuit is precharged by the second trigger signal, outputs a signal according to the result of the logical operation of the first signal and the second signal. Semiconductor device.

8. In the semiconductor device according to claim 7, The plurality of circuit blocks are connected to the memory and further include a second control circuit that outputs a timing signal according to a read operation in the memory. The timing signal output from the second control circuit is supplied as the second trigger signal to the gate terminal of a second P-type MOS transistor in the logic circuit of the second processing circuit. Semiconductor device.

9. A semiconductor device including a semiconductor chip on which a plurality of circuit blocks are formed, The plurality of circuit blocks include: a memory, an input circuit to which a signal is supplied from the memory, a processing circuit including a plurality of logic circuits that processes a signal from the input circuit, an output circuit to which a signal from the processing circuit is supplied, and each of the plurality of logic circuits includes: a first N-type MOS transistor including a first terminal, a second terminal, and a first gate terminal that controls conduction between the first terminal and the second terminal, wherein a first signal from the input circuit is supplied to the first terminal and a second signal from the input circuit is supplied to the first gate terminal; a second N-type MOS transistor including a third terminal, a fourth terminal, and a second gate terminal that controls conduction between the third terminal and the fourth terminal, wherein the second signal is supplied to the third terminal and the first signal is supplied to the second gate terminal; an output driver including an input terminal to which the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor are connected; a P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage, and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a trigger signal supplied to a gate terminal; and After being pre-charged by the trigger signal, the output driver of the logic circuit outputs a signal according to the result of the logical operation between the first signal and the second signal. Semiconductor device.

10. In the semiconductor device according to claim 9, The plurality of logic circuits include a first logic circuit, a second logic circuit, and a third logic circuit. The output of the second logic circuit is supplied as the first signal to the first terminal of the first logic circuit and the second gate terminal of the first logic circuit, and the output of the third logic circuit is supplied as the second signal to the third terminal of the first logic circuit and the first gate terminal of the first logic circuit. Semiconductor device.

11. In the semiconductor device according to claim 10, During the period when a signal is being read from the memory, the output drivers in the first logic circuit, the second logic circuit, and the third logic circuit are pre-charged by the trigger signal. Semiconductor device.

12. In the semiconductor device according to claim 11, The plurality of circuit blocks are connected to the memory and further include a control circuit that outputs a timing signal according to the read operation in the memory. The timing signal output from the control circuit is supplied as the trigger signal to the gate terminal of the P-type MOS transistor in the first logic circuit. Semiconductor device.

13. In the semiconductor device according to claim 12, The timing signal output from the control circuit is supplied as the trigger signal to the gate terminals of the P-type MOS transistors in the second logic circuit and the third logic circuit. Semiconductor device.

14. In the semiconductor device according to claim 13, The timing signal output from the control circuit is supplied to the input circuit and the output circuit, and the input circuit and the output circuit operate according to the timing signal. Semiconductor device.

15. A pre-stage circuit that generates a signal to be written to the memory, A processing circuit that processes the signal generated by the pre-stage circuit, A memory in which the signal generated by the processing in the processing circuit and the signal generated by the pre-stage circuit are written, Comprising: The processing circuit is A plurality of first logic circuits to which the signal generated by the pre-stage circuit is supplied, A plurality of second logic circuits to which the signals from the plurality of first logic circuits are supplied, Comprising: Each of the plurality of first logic circuits Comprises a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal. During the processing period, a first signal is supplied from the pre-stage circuit to the first terminal, and a second signal is supplied from the pre-stage circuit to the first gate terminal. A first MOS transistor, Comprises a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal. During the processing period, the second signal is supplied to the third terminal, and the first signal is supplied to the second gate terminal. A second MOS transistor, A first output driver having an input terminal to which the second terminal of the first MOS transistor and the fourth terminal of the second MOS transistor are connected, A third MOS transistor connected between the input terminal of the first output driver and a predetermined first voltage, and pre-charging the input terminal of the first output driver with a voltage based on the predetermined first voltage during a pre-charge period before the processing period, Comprising: Each of the plurality of second logic circuits A fourth MOS transistor including a fifth terminal, a sixth terminal, and a third gate terminal for controlling conduction between the fifth terminal and the sixth terminal, wherein the fifth terminal is connected to an output terminal of an output driver of one of the plurality of first logic circuits, and the third gate terminal is connected to an output terminal of an output driver of another one of the plurality of first logic circuits. A fifth MOS transistor including a seventh terminal, an eighth terminal, and a fourth gate terminal for controlling conduction between the seventh terminal and the eighth terminal, wherein the seventh terminal is connected to an output terminal of an output driver of the other first logic circuit, and the fourth gate terminal is connected to an output terminal of an output driver of the one first logic circuit. A second output driver including an input terminal to which a sixth terminal of the fourth MOS transistor and an eighth terminal of the fifth MOS transistor are connected. A sixth MOS transistor connected between the input terminal of the second output driver and the predetermined first voltage, and for precharging the input terminal of the second output driver with a voltage based on the predetermined first voltage during the precharge period. Comprising: A semiconductor device.

16. In the semiconductor device according to claim 15, The first logic circuit Comprises a seventh MOS transistor connected between the previous-stage circuit and the first gate terminal of the first MOS transistor, and An eighth MOS transistor connected between the previous-stage circuit and the second gate terminal of the second MOS transistor. Comprising: During the precharge period, the first gate terminal of the first MOS transistor and the second gate terminal of the second MOS transistor are precharged with a voltage based on a predetermined second voltage. During the processing period, the second signal is supplied to the first gate terminal of the first MOS transistor via the seventh MOS transistor, and the first signal is supplied to the second gate terminal of the second MOS transistor via the eighth MOS transistor. Semiconductor device.

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