Semiconductor device and semiconductor system including the same

Abstract

To provide a semiconductor device and a semiconductor system including the same that can achieve low power consumption.SOLUTION: A semiconductor device according to the present disclosure includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, and a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line for performing a predetermined processing on an input signal, and a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor which are provided in series between the second power supply voltage line and the second reference voltage line, each having a gate connected to a drain.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a semiconductor system including the same, and more particularly, to a semiconductor device suitable for achieving low power consumption and a semiconductor system including the same.

Background Art

[0002] There is a demand for reducing the power consumption of semiconductor systems. In recent years in particular, there is a demand for reducing the power consumption during standby in, for example, keyless entry systems mounted on vehicles and alarm systems mounted on vehicles. That is, in recent years, there has been a demand for reducing the power consumption during standby of semiconductor systems and semiconductor devices mounted thereon. Technologies related to keyless entry systems are disclosed in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As described above, there is a demand for reducing the power consumption during standby in semiconductor devices and semiconductor systems including the same. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0005] The semiconductor device according to the present disclosure includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined process on an input signal, a first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor, the first transistor and the second transistor being provided in series between the second power supply voltage line and the second reference voltage line and having their gates connected to their drains, respectively.

Effect of the Invention

[0006] The present disclosure can provide a semiconductor device capable of achieving low power consumption and a semiconductor system including the same.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description of these drawings. Also, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] In the following embodiments, when necessary for convenience, they will be described by being divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a modification example, application example, detailed description, supplementary description, etc. of a part or all of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, amount, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0010] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential, except in cases where they are specifically stated or are considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it shall include those that are substantially approximated or similar to the shape, etc., except in cases where it is specifically stated and in cases where it is clearly not so in principle. This also applies to the above numbers (including the number, numerical value, quantity, range, etc.).

[0011] <Pre-examination by the inventors, etc.> First, a semiconductor device pre-examined by the inventors, etc. will be described. FIG. 13 is a diagram showing a configuration example of the pre-examined semiconductor device 50.

[0012] As shown in FIG. 13, the semiconductor device 50 includes a power supply voltage terminal to which a power supply voltage VDD is supplied from the outside, a reference voltage terminal to which a reference voltage GND is supplied from the outside, an input terminal to which an input signal IN is supplied from the outside, and a logic circuit (electronic circuit) 51.

[0013] The power supply voltage VDD indicates, for example, 3.3V. Also, the reference voltage GND indicates, for example, 0V. Hereinafter, the line to which the power supply voltage VDD is supplied is referred to as the first power supply voltage line VDD, and the line to which the reference voltage GND is supplied is referred to as the first reference voltage line GND. The logic circuit 51 is provided between the first power supply voltage line VDD and the first reference voltage line GND, and performs a predetermined process on the input signal IN. In other words, the logic circuit 51 is driven by the power supply voltage VDD and the reference voltage GND, and performs a predetermined process on the input signal IN.

[0014] Here, the smaller the average current consumption (dark current) of the logic circuit 51, the more the power consumption of the semiconductor device 50 is suppressed. For example, when the semiconductor device 50 is mounted on a vehicle as part of a keyless entry system or the like, the smaller the dark current of the logic circuit 51, the more the consumption of the power stored in the vehicle battery is suppressed.

[0015] FIG. 14 is a waveform diagram showing the operation of the semiconductor device 50. In the example of FIG. 14, assume that the scale of the logic circuit 51 is 2K gates in terms of NAND gates, the frequency of the main clock signal supplied to the logic circuit 51 is 16 MHz, and the operating rate of the logic circuit 51 is 50%. In this case, the peak current of the logic circuit 51 indicates 225 mA, and the average power consumption current (dark current) of the logic circuit 51 indicates 4.8 mA. In recent years, further reduction of the average power consumption current of the logic circuit 51 has been demanded.

[0016] Therefore, a semiconductor device 1 capable of realizing low power consumption has been found.

[0017] <Embodiment 1> FIG. 1 is a diagram showing a configuration example of the semiconductor device 1 according to Embodiment 1. The semiconductor device 1 is applied to, for example, a keyless entry system mounted on a vehicle or an alarm system mounted on a vehicle.

[0018] As shown in FIG. 1, the semiconductor device 1 includes a power supply voltage terminal to which a power supply voltage VDD is supplied from the outside, a reference voltage terminal to which a reference voltage GND is supplied from the outside, an input terminal to which an input signal IN is supplied from the outside, a resistance element (first impedance element) R1, a resistance element (second impedance element) R2, a transistor (first transistor) MP1 which is a P-channel MOS transistor, a transistor (second transistor) MN1 which is an N-channel MOS transistor, and a logic circuit (electronic circuit) 10.

[0019] The power supply voltage VDD indicates, for example, 3.3 V. Also, the reference voltage GND indicates, for example, 0 V. Hereinafter, the line to which the power supply voltage VDD is supplied is referred to as the first power supply voltage line VDD, and the line to which the reference voltage GND is supplied is referred to as the first reference voltage line GND. The resistance element R1 is provided between the first power supply voltage line VDD and the second power supply voltage line VDD2. The resistance element R2 is provided between the first reference voltage line GND and the second reference voltage line GND2.

[0020] The logic circuit 10 is provided between a second power supply voltage line VDD2 and a second reference voltage line GND2, and performs a predetermined process on the input signal IN. In other words, the logic circuit 10 is driven by the power supply voltage of the second power supply voltage line VDD2 (hereinafter referred to as the power supply voltage VDD2) and the reference voltage of the second reference voltage line GND2 (hereinafter referred to as the reference voltage GND2), and performs a predetermined process on the input signal IN. The source and back gate of each P-channel MOS transistor provided in the logic circuit 10 are connected to the second power supply voltage line VDD2. Also, the source and back gate of each N-channel MOS transistor provided in the logic circuit 10 are connected to the second reference voltage line GND2.

[0021] The transistors MP1 and MN1 are provided in series between the second power supply voltage line VDD2 and the second reference voltage line GND2. Specifically, in the transistor MP1, the source and back gate are connected to the second power supply voltage line VDD2, and the gate and drain are connected to the gate and drain of the transistor MN1. In the transistor MN1, the source and back gate are connected to the second reference voltage line GND2. By providing the transistors MP1 and MN1, the power supply voltage of the second power supply voltage line VDD2 and the reference voltage of the second reference voltage line GND2 are stabilized.

[0022] Here, the smaller the dark current of the logic circuit 10, the more the power consumption of the semiconductor device 1 is suppressed. For example, when the semiconductor device 1 is mounted on a vehicle, the smaller the dark current of the logic circuit 10, the more the consumption of the power stored in the vehicle battery is suppressed.

[0023] FIG. 2 is a waveform diagram showing the operation of the semiconductor device 1. In the example of FIG. 2, it is assumed that the scale of the logic circuit 10 is 2K gates in terms of NAND gates, the frequency of the main clock signal supplied to the logic circuit 10 is 16 MHz, and the operation rate of the logic circuit 10 is 50%. In this case, the average current consumption of the logic circuit 10 is 1.4 mA, which is improved compared to the case of the logic circuit 51.

[0024] Specifically, assuming that the gate charging and discharging current of the operating transistor provided in the logic circuit 10 is I_sw and the through-current of the operating transistor provided in the logic circuit 10 is I_leak, the average power consumption current of the logic circuit 10, that is, the dark current I_dark of the logic circuit 10, is expressed as the following formula (1).

[0025] I_dark = I_sw + I_leak ···(1)

[0026] Also, assuming that the frequency of the main clock signal supplied to the logic circuit 10 is f, the gate capacitance of the operating transistor provided in the logic circuit 10 is C, and the amplitude of the clock signal is Vf, the gate charging and discharging current I_sw is expressed as the following formula (2).

[0027] I_sw = f·C·Vf ···(2)

[0028] Here, assuming that the power supply voltage VDD is VDD and the resistance values of the resistance elements R1 and R2 are R1 and R2, the amplitude Vf of the clock signal is expressed as the following formula (3).

[0029] Vf = VDD - {I_dark·(R1 + R2)} ···(3)

[0030] Assuming that the threshold voltage of each transistor is Vt, from formula (3), formula (4) holds.

[0031] I_leak ∝ (Vf - Vt)^2 ···(4)

[0032] That is, the through-current I_leak is proportional to (Vf - Vt)^2.

[0033] For example, in the logic circuit 51 provided in the semiconductor device 50 shown in FIG. 13, the amplitude Vf of the clock signal is VDD = 3.3V, while in the logic circuit 10 provided in the semiconductor device 1 shown in FIG. 1, the amplitude Vf of the clock signal is VDD - {I_dark·(R1 + R2)} < 3.3V. That is, in the logic circuit 10 provided in the semiconductor device 1, compared with the case of the logic circuit 51 provided in the semiconductor device 50, the amplitude Vf of the clock signal becomes smaller, so the gate charge and discharge current I_sw and the through current I_leak become smaller, and as a result, the dark current I_dark becomes smaller. Designers, etc., grasp the maximum value of the dark current I_dark in advance, and for example, by adjusting the resistance values of the resistance elements R1 and R2 so that the amplitude Vf of the clock signal becomes smaller within the operable range of the logic circuit 10, the dark current I_dark of the logic circuit 10 provided in the semiconductor device 1 can be effectively suppressed.

[0034] Thus, the semiconductor device 1 according to the present embodiment includes a second power supply voltage line VDD2 connected to the first power supply voltage line VDD via a resistance element R1, and a second reference voltage line GND2 connected to the first reference voltage line GND via a resistance element R2, and between them, a logic circuit 10, and transistors MP1 and MN1 connected in series. Thereby, the semiconductor device 1 according to the present embodiment can reduce the amplitude Vf of the clock signal supplied to the logic circuit 10 within the operable range of the logic circuit 10, so that the dark current of the logic circuit 10 can be reduced. That is, the semiconductor device 1 according to the present embodiment can achieve low power consumption.

[0035] <Embodiment 2> FIG. 3 is a diagram showing a configuration example of the semiconductor device 2 according to Embodiment 2.

[0036] As shown in FIG. 3, the semiconductor device 2 includes a logic circuit 20 instead of the logic circuit 10 as compared with the semiconductor device 1. The back gate of each P-channel MOS transistor provided in the logic circuit 20 is connected to the first power supply voltage line VDD instead of the second power supply voltage line VDD2. The back gate of each N-channel MOS transistor provided in the logic circuit 20 is connected to the first reference voltage line GND instead of the second reference voltage line GND2. Since the other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1, the description thereof is omitted.

[0037] In the semiconductor device 2, when a simulation is performed under the same conditions as those of the semiconductor device 1, the average current consumption (dark current) of the logic circuit 20 is 679 μA, which is improved compared with the case of the logic circuit 10. This is because, as shown in the above formula (4), the threshold voltage Vt of each transistor is increased by the back gate effect, so that the through current I_leak is decreased.

[0038] Thus, the semiconductor device 2 can achieve effects equivalent to or better than those of the semiconductor device 1.

[0039] In the present embodiment, in the logic circuit 20, the case where the back gates of all the P-channel MOS transistors are connected to the first power supply voltage line VDD and the back gates of all the N-channel MOS transistors are connected to the first reference voltage line GND has been described as an example, but the present invention is not limited thereto. In the logic circuit 20, it is sufficient that the back gates of at least some of the P-channel MOS transistors are connected to the first power supply voltage line VDD and the back gates of at least some of the N-channel MOS transistors are connected to the first reference voltage line GND.

[0040] <Embodiment 3> FIG. 4 is a diagram showing a configuration example of a semiconductor system 3 according to Embodiment 3. The configuration of the semiconductor device 1 is applied to the semiconductor system 3. The semiconductor system 3 is used, for example, in a keyless entry system mounted on a vehicle.

[0041] Specifically, the semiconductor system 3 includes a semiconductor device 1a, a crystal oscillator 13, a capacitive element (first capacitive element) Cxi, and a capacitive element (second capacitive element) Cxo. Further, the semiconductor device 1a further includes a feedback resistor Rf, a buffer 11, and an inverter 12 in addition to the components of the semiconductor device 1.

[0042] In the semiconductor device 1a, the gates of the transistors MP1 and MN1 are connected to the external terminal XI, and the drains of the transistors MP1 and MN1 are connected to the external terminal XO. The crystal oscillator 13 is provided outside the semiconductor device 1a between the external terminal XI and the external terminal XO of the semiconductor device 1a. That is, the crystal oscillator 13 is provided between the gates of the transistors MP1 and MN1 and the drains of the transistors MP1 and MN1 via the external terminals XI and XO of the semiconductor device 1a.

[0043] The capacitive element Cxi is provided outside the semiconductor device 1a between the external terminal XI of the semiconductor device 1a and the reference voltage terminal GND. The capacitive element Cxo is provided outside the semiconductor device 1a between the external terminal XO of the semiconductor device 1a and the reference voltage terminal GND.

[0044] In the semiconductor device 1a, the feedback resistor Rf is provided between the gates of the transistors MP1 and MN1 and the drains of the transistors MP1 and MN1. The buffer 11 is a so-called Schmitt buffer that drives and outputs the output signal of the drains of the transistors MP1 and MN1. The inverter 12 outputs an inverted signal of the output signal of the buffer 11. The output signal of the inverter 12 is supplied to the logic circuit 10 as a clock signal.

[0045] FIG. 5 is a diagram showing the simulation results of the EYE opening (EYE pattern) in the semiconductor system of the comparative example. In the semiconductor system of the comparative example, the resistance values of the resistance elements R1 and R2 are set to 0 Ω as compared with the semiconductor system 3. Therefore, the power supply voltage VDD2 of the second power supply voltage line VDD2 shows the same 3.3 V as the power supply voltage VDD. Also, the power supply voltage GND2 of the second reference voltage line GND2 shows the same 0 V as the reference voltage GND.

[0046] Also, in the example of FIG. 5, the oscillation frequency of the crystal oscillator 13 is 16 MHz, the scale of the logic circuit 10 is 40K gates in terms of NAND gates, the frequency of the main clock signal supplied to the logic circuit 10 is 16 MHz, and the operating rate of the logic circuit 10 is 50%. Further, in the example of FIG. 5, it is assumed that the amplitude of the external noise is 3.3 V ± 100 mV and the frequency of the external noise is 40 MHz.

[0047] In this case, in the semiconductor system of the comparative example, the jitter showed 6.52 nsec / 100 mV.

[0048] FIG. 6 is a diagram showing the simulation results of the EYE opening in the semiconductor system 3. In the example of FIG. 6, while the power supply voltage VDD of the first power supply voltage line VDD shows 3.3 V, the power supply voltage VDD2 of the second power supply voltage line VDD2 shows 2.7 V due to the voltage drop of I_dark × R1. Also, in the example of FIG. 6, while the reference voltage GND of the first reference voltage line GND shows 0 V, the reference voltage GND2 of the second reference voltage line GND2 shows 0.5 V due to the voltage rise of I_dark × R2.

[0049] When the simulation was performed in the semiconductor system 3 under the same conditions as the semiconductor system of the comparative example except for the resistance values of the resistance elements R1 and R2, the jitter showed 2.74 nsec / 100 mV. That is, in the semiconductor system 3, the jitter was suppressed to about 42% as compared with the case of the semiconductor system of the comparative example.

[0050] In recent years, in the automotive industry, IEC62132-4 (DPI method) has attracted attention as an EMC test for ICs (Integrated Circuits) standardized by IEC (International Electrotechnical Commission) standards. In this DPI method, it is required that the IC does not malfunction even when noise of about ±600 mV in terms of 50 Ω is superimposed on the 3.3 V power supply voltage VDD supplied to the local pins. A local pin is a pin that is not connected to the outside of the ECU and is connected to components including other ICs within the ECU.

[0051] Here, the amount of noise superimposed on the power supply voltage VDD is in a proportional relationship with jitter. Therefore, in order to examine whether the semiconductor system of the comparative example satisfies the requirements of the DPI method, when the amount of noise superimposed on the power supply voltage VDD, that is, the amplitude of external noise, is set to 3.3 V ± 600 mV among the simulation conditions in FIG. 5, the jitter shows 39.12 nsec / 100 mV (= 6.52 × 6 nsec / 100 mV), and the EYE opening becomes narrow.

[0052] On the other hand, in order to examine whether the semiconductor system 3 satisfies the requirements of the DPI method, when the amount of noise superimposed on the power supply voltage VDD, that is, the amplitude of external noise, is set to 3.3 V ± 600 mV among the simulation conditions in FIG. 6, the jitter shows 16.44 nsec / 100 mV (= 2.74 × 6 nsec / 100 mV), and the EYE opening is maintained in a wide state. That is, the semiconductor system 3 can maintain the EYE opening in a wide state without using external components such as an external low-pass filter. In other words, the semiconductor system 3 can achieve low jitter.

[0053] The low jitter realized by the semiconductor system 3 will be described in more detail. For example, when noise of +100 mV is superimposed on the power supply voltage VDD, the power supply voltage VDD2 also instantaneously increases by ΔVDD. At this time, the gate-source voltage of each of the transistors MP1 and MN1 instantaneously increases, and current flows through the transistors MP1 and MN1 and the resistance element R2, so the reference voltage GND2 also instantaneously increases by ΔGND. Thereby, the potential difference between the power supply voltage VDD2 and the reference voltage GND2 is kept almost constant even when noise occurs. That is, since the semiconductor system 3 is hardly affected by noise, low jitter can be realized.

[0054] As described above, the semiconductor system 3 having an oscillation circuit to which the configuration of the semiconductor device 1 is applied can not only achieve low power consumption as in the case of the semiconductor device 1, but also maintain the EYE opening in a wide state without using external components such as an external low-pass filter, and can achieve low jitter.

[0055] <Embodiment 4> FIG. 7 is a diagram showing a configuration example of a semiconductor system 4 according to Embodiment 4. The semiconductor system 4 includes a semiconductor device 1b instead of the semiconductor device 1a as compared with the semiconductor system 3. The semiconductor device 1b includes pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2. The pseudo-inductance circuits L1 and L2 constitute a pseudo-inductance circuit by using transistors or the like instead of using coils. Thereby, the semiconductor device 1b can suppress an increase in circuit scale compared to the case of using a coil. Since the other configurations of the semiconductor system 4 are the same as those of the semiconductor system 3, the description thereof will be omitted.

[0056] FIG. 8 is a diagram showing a specific configuration example of the pseudo-inductance circuit L1. As shown in FIG. 8, the pseudo-inductance circuit L1 includes transistors MU1 to MU4, a capacitive element CU1, and a resistive element RU1. The transistor MU1 is a P-channel MOS transistor, and the transistors MU2 to MU4 are all N-channel MOS transistors.

[0057] In the transistor MU1, the source is connected to the first power supply voltage line VDD, and the drain is connected to the second power supply voltage line VDD2. The capacitive element CU1 is provided between the gate of the transistor MU1 and the first reference voltage line GND. In the transistor MU2, the source is connected to the gate of the transistor MU1, the drain is connected to the first power supply voltage line VDD, and the gate is connected to the second power supply voltage line VDD2. In the transistor MU3, the source is connected to the first reference voltage line GND, and the drain is connected to the source of the transistor MU2. The resistive element RU1 is provided between the first power supply voltage line VDD and the gate of the transistor MU3. In the transistor MU4, the source is connected to the first reference voltage line GND, and the drain and the gate are connected to the gate of the transistor MU3.

[0058] FIG. 9 is a diagram showing a specific configuration example of the pseudo-inductance circuit L2. As shown in FIG. 9, the pseudo-inductance circuit L2 includes transistors ML1 to ML4, a capacitive element CL1, and a resistive element RL1. The transistor ML1 was an N-channel MOS transistor, and the transistors ML2 to ML4 are all P-channel MOS transistors.

[0059] In transistor ML1, the source is connected to the first reference voltage line GND, and the drain is connected to the second reference voltage line GND2. The capacitive element CL1 is provided between the gate of transistor ML1 and the first power supply voltage line VDD. In transistor ML2, the source is connected to the gate of transistor ML1, the drain is connected to the first reference voltage line GND, and the gate is connected to the second reference voltage line GND2. In transistor ML3, the source is connected to the first power supply voltage line VDD, and the drain is connected to the source of transistor ML2. The resistive element RL1 is provided between the first reference voltage line GND and the gate of transistor ML3. In transistor ML4, the source is connected to the first power supply voltage line VDD, and the drain and gate are connected to the gate of transistor ML3.

[0060] FIG. 10 is a diagram showing the simulation result of the EYE opening in the semiconductor system 4. In the semiconductor system 4, when the simulation was performed under the same conditions as in the semiconductor system 3, the jitter showed 1.03 nsec / 100 mV. That is, in the semiconductor system 4, the jitter is further suppressed compared to the case of the semiconductor system 3.

[0061] Also, in order to examine whether the semiconductor system 4 satisfies the requirements of the DPI method, when the noise superposition amount of the power supply voltage VDD, that is, the amplitude of the external noise, was set to 3.3 V ± 600 mV among the simulation conditions in FIG. 10, the jitter showed 6.18 nsec / 100 mV (= 1.03 × 6 nsec / 100 mV), and the EYE opening was maintained in a wide state. That is, the semiconductor system 4 can maintain the EYE opening in a wider state compared to the case of the semiconductor system 3. In other words, the semiconductor system 4 can further reduce the jitter compared to the case of the semiconductor system 3.

[0062] FIG. 11 is a diagram showing the AC analysis result of the semiconductor system 4 when noise is applied to the power supply voltage VDD. In FIG. 11, the vertical axis represents 20Log(GND2 / VDD2), and the horizontal axis represents the logarithmically expressed frequency. As shown in FIG. 11, in the semiconductor system 4, since the pseudo-inductance circuits L1 and L2 are provided instead of the resistance elements R1 and R2, the followability of the reference voltage GND2 with respect to the power supply voltage VDD2 is improved when the frequency is 10 MHz or higher. Therefore, the semiconductor system 4 can further reduce jitter as compared with the case of the semiconductor system 3.

[0063] In this embodiment, the case where the semiconductor system 4 includes the pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2 has been described as an example, but it is not limited thereto. As shown in FIG. 12, the semiconductor system 4 may include impedance elements Z1 and Z2 that can realize functions equivalent to those of the resistance elements R1 and R2, the pseudo-inductance circuits L1 and L2, and the like.

[0064] FIG. 12 is a diagram showing a modified example of the semiconductor system 4 as the semiconductor system 4a. The semiconductor system 4a includes a semiconductor device 1c instead of the semiconductor device 1b as compared with the semiconductor system 4. The semiconductor device 1c includes impedance elements Z1 and Z2 instead of the resistance elements R1 and R2. Since the other configurations of the semiconductor system 4a are the same as those of the semiconductor system 4, the description thereof is omitted.

[0065] As described above, the semiconductor device according to the present disclosure includes a second power supply voltage line VDD2 connected to the first power supply voltage line VDD via a resistance element R1, and a second reference voltage line GND2 connected to the first reference voltage line GND via a resistance element R2, and includes a logic circuit and transistors MP1 and MN1 connected in series therebetween. Thereby, the semiconductor device according to the present disclosure can reduce the amplitude Vf of the clock signal supplied to the logic circuit within the operable range of the logic circuit, and thus can reduce the dark current of the logic circuit. That is, the semiconductor device according to the present disclosure can achieve low power consumption.

[0066] Furthermore, a semiconductor system having an oscillation circuit to which the configuration of the semiconductor device according to the present disclosure is applied can not only achieve low power consumption, but also maintain a wide EYE opening without using external components such as an external low-pass filter, thereby achieving low jitter.

[0067] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and it goes without saying that various modifications are possible without departing from the gist thereof.

[0068] For example, in the present disclosure, the case where the semiconductor device 1 includes the resistance elements R1 and R2 has been described as an example, but it is not limited thereto. The semiconductor device 1 can be appropriately changed to a configuration including impedance elements Z1 and Z2 such as pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2. Similarly, in the present disclosure, the case where the semiconductor device 2 includes the resistance elements R1 and R2 has been described as an example, but it is not limited thereto. The semiconductor device 2 can be appropriately changed to a configuration including impedance elements Z1 and Z2 such as pseudo-inductance circuits L1 and L2 instead of the resistance elements R1 and R2.

[0069] Also, in the present disclosure, the case where the semiconductor system 3 includes the semiconductor device 1 has been described as an example, but it is not limited thereto. The semiconductor system 3 can be appropriately changed to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 3 can be appropriately changed to a configuration including the logic circuit 20 instead of the logic circuit 10. Similarly, in the present disclosure, the case where the semiconductor system 4 includes the semiconductor device 1 has been described as an example, but it is not limited thereto. The semiconductor system 4 can be appropriately changed to a configuration including the semiconductor device 2 instead of the semiconductor device 1. In other words, the semiconductor system 4 can be appropriately changed to a configuration including the logic circuit 20 instead of the logic circuit 10.

[0070] Furthermore, the present disclosure can be realized by causing a CPU to execute a computer program for part or all of the processing of the semiconductor device 1, the semiconductor device 2, or a semiconductor system including any of them.

[0071] When the above-described program is loaded into a computer, it includes a set of instructions (or software code) for causing the computer to perform one or more functions described in the embodiments. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or tangible storage medium includes RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive) or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray (registered trademark) disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or communication medium includes electrical, optical, acoustic, or other forms of propagated signals.

Explanation of Reference Numerals

[0072] 1, 1a, 1b, 1c Semiconductor device 2 Semiconductor device 3 Semiconductor system 4 Semiconductor system 4a Semiconductor system 10 Logic circuit 11 Buffer 12 Inverter 13 Crystal oscillator 20 Logic circuit CL1 Capacitor element CU1 Capacitor element Cxi Capacitor element Cxo Capacitor element GND First reference voltage line GND2 Second reference voltage line L1 Pseudo-inductance circuit L2 Pseudo-inductance circuit ML1~ML4 Transistor MN1 Transistor MP1 Transistor MU1~MU4 Transistor R1 Resistive element R2 Resistive element Rf Feedback resistor RL1 Resistive element RU1 Resistive element VDD First power supply voltage line VDD2 Second power supply voltage line Z1 Impedance element Z2 Impedance element

Claims

1. A first power supply voltage line to which a power supply voltage is supplied, A second power supply voltage line, A first impedance element provided between the first power supply voltage line and the second power supply voltage line, A first reference voltage line to which a reference voltage is supplied, A second reference voltage line, A second impedance element provided between the first reference voltage line and the second reference voltage line, An electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined process on an input signal, A first transistor which is a P-channel MOS transistor and a second transistor which is an N-channel MOS transistor, which are provided in series between the second power supply voltage line and the second reference voltage line and each have a gate connected to a drain, comprising A semiconductor device.

2. Both the first impedance element and the second impedance element are resistance elements, The semiconductor device according to claim 1.

3. The first impedance element is constituted by a first pseudo-inductance circuit, The first pseudo-inductance circuit A first upper transistor which is a P-channel MOS transistor provided between the first power supply voltage line and the second power supply voltage line, A first upper capacitance element provided between the gate of the first upper transistor and the first reference voltage line, A second upper transistor which is an N-channel MOS transistor provided between the first power supply voltage line and the gate of the first upper transistor and has a gate connected to the second power supply voltage line, A third upper transistor, which is an N-channel MOS transistor provided between the source of the second upper transistor and the first reference voltage line, A first upper resistor element provided between the first power supply voltage line and the gate of the third upper transistor, A fourth upper transistor, which is an N-channel MOS transistor provided between the gate of the third upper transistor and the first reference voltage line and has a gate connected to the gate of the third upper transistor, and has The second impedance element is constituted by a second pseudo-inductance circuit, The second pseudo-inductance circuit A first lower transistor, which is an N-channel MOS transistor provided between the first reference voltage line and the second reference voltage line, A first lower capacitor element provided between the gate of the first lower transistor and the first power supply voltage line, A second lower transistor, which is a P-channel MOS transistor provided between the first reference voltage line and the gate of the first lower transistor and has a gate connected to the second reference voltage line, A third lower transistor, which is a P-channel MOS transistor provided between the source of the second lower transistor and the first power supply voltage line, A first lower resistor element provided between the first reference voltage line and the gate of the third lower transistor, A fourth lower transistor, which is a P-channel MOS transistor provided between the gate of the third lower transistor and the first power supply voltage line and has a gate connected to the gate of the third lower transistor, and has The semiconductor device according to claim 1.

4. In the first transistor, the source and the back gate are connected to the second power supply voltage line, and the gate and the drain are connected to the gate and the drain of the second transistor. In the second transistor, the source and the back gate are connected to the second reference voltage line. The semiconductor device according to claim 1.

5. The back gate of each P-channel MOS transistor provided in the electronic circuit is connected to the second power supply voltage line. The back gate of each N-channel MOS transistor provided in the electronic circuit is connected to the second reference voltage line. The semiconductor device according to claim 1.

6. The back gates of some of the plurality of P-channel MOS transistors provided in the electronic circuit are connected to the first power supply voltage line. The back gates of some of the plurality of N-channel MOS transistors provided in the electronic circuit are connected to the first reference voltage line. The semiconductor device according to claim 1.

7. The back gates of all of the plurality of P-channel MOS transistors provided in the electronic circuit are connected to the first power supply voltage line. The back gates of all of the plurality of N-channel MOS transistors provided in the electronic circuit are connected to the first reference voltage line. The semiconductor device according to claim 1.

8. The semiconductor device according to claim 1, A crystal oscillator provided between each gate of the first and second transistors and each drain of the first and second transistors, First and second capacitor elements provided between each of one end and the other end of the crystal oscillator and a reference voltage terminal, A semiconductor system comprising: The semiconductor device is A feedback resistor provided in parallel with the crystal oscillator, A buffer that drives and outputs the output signals of the drains of the first and second transistors respectively. An inverter that outputs the inverted signal of the output signal of the buffer as a clock signal supplied to the electronic circuit; A semiconductor system further comprising the same.

9. The buffer is a Schmitt buffer. The semiconductor system according to claim 8.

10. Applied to a keyless entry system mounted on a vehicle. The semiconductor system according to claim 8.

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