Semiconductor device and display device

Abstract

To provide a semiconductor device common for two different circuits to drive the circuits.SOLUTION: A semiconductor device can sequentially output a plurality of signal potentials to the outside by switching the signal potentials, and can operate all of the rows in one of two different circuits arranged in a matrix and operate all of the rows or a specific row alone in the other circuit. For example, in a case where the semiconductor device is applied as a low driver which operates pixels of a display device with a sensor element built therein, it is possible to switch operations of a display element in the pixels of all the rows and operations of a sensor element in pixels of all the rows or a specific row.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a display device including the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an imaging device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. The semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics.

Background Art

[0003] For the purpose of miniaturizing an electronic device or improving the degree of freedom in design, it is required to narrow the bezel of a display device. For narrowing the bezel of a display device, it is effective to provide a pixel portion and part or all of a driving circuit portion monolithically on the same substrate.

[0004] In addition, since the driving circuit portion can be manufactured in the same process as the pixel portion, mounting of an IC chip or the like becomes unnecessary, and the manufacturing cost can be reduced. For example, Patent Document 1 discloses a technique of configuring a circuit such as a shift register with unipolar transistors.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In a display device, high functionality can be achieved by incorporating sensor elements or the like into pixels. For example, by incorporating a capacitance sensor into the display device, it can function as a touch panel. Also, by incorporating an optical sensor into the display device, an imaging function or a non-contact input function can be imparted.

[0007] However, since a driving circuit is required for driving the sensor element as in the case of a display element, it becomes an obstacle to making the bezel narrower.

[0008] Therefore, one object of one aspect of the present invention is to provide a semiconductor device for driving two different circuits. Or, one object is to provide a semiconductor device having a pixel having a first circuit and a second circuit. Or, one object is to provide a display device having the above semiconductor device. Or, one object is to provide the above semiconductor device, a driving method of the above display device, etc. Or, one object is to provide a novel semiconductor device, a display device, etc.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not have to solve all of these problems. Note that other problems can be extracted from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention relates to a common semiconductor device for driving two different circuits. Or, it relates to a display device having the semiconductor device.

[0011] One aspect of the present invention has a first block, a second block, a third block, and a first switch circuit. Each of the first block to the third block has a plurality of flip-flop circuits and a plurality of output circuits. For each flip-flop circuit, a pair of output circuits is electrically connected thereto. In each of the first block to the third block, the plurality of flip-flop circuits are connected in series. The last-stage flip-flop circuit of the first block, the first-stage flip-flop circuit of the second block, the last-stage flip-flop circuit of the second block, and the first-stage flip-flop circuit of the third block are electrically connected to the first switch circuit. The output circuit has a second switch circuit, a first circuit, and a second circuit. The second switch circuit is a semiconductor device electrically connected to the flip-flop circuit, the first circuit, and the second circuit.

[0012] The first switch circuit can have a function of selecting either an output operation of signal potentials from the first block, the second block, and the third block, or an output operation of signal potentials from the first block and the third block.

[0013] The second switch circuit can have a function of selecting either conduction between the flip-flop circuit and the first circuit or conduction between the flip-flop circuit and the second circuit.

[0014] The flip-flop circuit outputs a first signal potential to the second switch circuit. The second switch circuit outputs a second signal potential based on the first signal potential to the first circuit, and the second switch circuit outputs a third signal potential based on the first signal potential to the second circuit. The first circuit outputs a fourth signal potential based on the second signal potential, and the second circuit can output a fifth signal potential based on the third signal potential.

[0015] The first switch circuit and the second switch circuit can input a sixth signal potential, a seventh signal potential, or an eighth signal potential. When the sixth signal potential is input to the first switch circuit and the second switch circuit, the first circuit included in the first block to the third block outputs a signal potential. When the seventh signal potential is input to the first switch circuit and the second switch circuit, the second circuit included in the first block to the third block outputs a signal potential. When the eighth signal potential is input to the first switch circuit and the second switch circuit, the second circuit included in the first block and the third block can output a signal potential.

[0016] When the last stage of the flip-flop circuit included in the first block is the fourth stage, the last stage of the flip-flop circuit included in the second block can be the 4n-th stage (n is an integer of 2 or more), and the last stage of the flip-flop circuit included in the third block can be the (4n + 4)-th stage.

[0017] Another aspect of the present invention is a display device including the semiconductor device and a pixel. The pixel includes a third circuit having a display element and a fourth circuit having a light receiving element. The first circuit is electrically connected to the third circuit, and the second circuit is electrically connected to the fourth circuit.

[0018] The display element is a light emitting element, and the light receiving element can have an electrode common to the light emitting element.

[0019] The third circuit and the fourth circuit each include a transistor having a metal oxide in a channel formation region. The metal oxide preferably contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Advantages of the Invention

[0020] According to one aspect of the present invention, a semiconductor device for driving two different circuits can be provided. Or, a semiconductor device having a pixel having a first circuit and a second circuit can be provided. Or, a display device having the semiconductor device can be provided. Or, a driving method of the semiconductor device, the display device, etc. can be provided. Or, a novel semiconductor device, display device, etc. can be provided.

[0021] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0022]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same part or parts having the same or similar functions, and the repeated description thereof may be omitted. Note that the hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

[0024] Even if an element is illustrated as a single element on a circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, transistors operating as switches may be connected in series or in parallel. Also, there may be cases where a capacitor is divided and arranged at a plurality of positions.

[0025] In addition, a single conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if it is illustrated on a circuit diagram that elements are directly connected to each other, actually, the elements may be connected via one or a plurality of conductors, and such a configuration is also included in the category of direct connection in this specification.

[0026] (Embodiment 1) In this embodiment, a semiconductor device which is an aspect of the present invention will be described with reference to the drawings.

[0027] One aspect of the present invention is a semiconductor device capable of switching a plurality of signal potentials and sequentially outputting them to the outside. The semiconductor device can, for example, operate all rows of one of two different circuits arranged in a matrix form, and operate all rows or only specific rows of the other circuit.

[0028] For example, when the semiconductor device is applied as a load driver for driving pixels of a display device in which a sensor element is incorporated, it is possible to switch between the operation of the display elements in all pixels and the operation of the sensor elements in all pixels or specific pixels.

[0029] Note that the two different circuits operated by the semiconductor device are not limited to a combination of a circuit having a display element and a circuit having a sensor element, and may be a combination of a circuit having a first display element and a circuit having a second display element. For example, a light-emitting device such as an organic EL element and a non-light-emitting device such as a liquid crystal element can be operated by the semiconductor device.

[0030] Alternatively, it may be a combination of a circuit having a first sensor element and a circuit having a second sensor element. For example, an imaging element for image capture and an imaging element for distance measurement (such as a TOF (Time Of Flight) sensor) can be operated in the semiconductor device. Alternatively, it may be a combination of one of a display element and a sensor element and a memory circuit.

[0031] FIGS. 2A and 2B are examples of the prior art, showing an example in which two drive circuits are used to drive the pixel 24 included in the pixel array 23. Conventionally, when the pixel 24 has a circuit 25 having a display element and a circuit 26 having a sensor element, different drive circuits (load drivers 21 and 22) are required to drive the circuit 25 and the circuit 26, respectively. This is because the control of the signal output timing and the like are different between the circuit 25 and the circuit 26, or because the rows to be driven may be different between the circuit 25 and the circuit 26, such as when the circuit 26 is not arranged in all rows as shown in FIG. 2B.

[0032] By using the semiconductor device 20 according to one aspect of the present invention as a load driver, it is possible to switch between the operation of the circuit 25 in all rows shown in FIG. 2C or the operation of the circuit 26 in all rows and the operation of the circuit 26 in a specific row shown in FIG. 2D.

[0033] That is, since two different load drivers can be made into one load driver, the number of wirings and the occupied area of transistors and the like constituting the load driver can be reduced. Therefore, the bezel can be narrowed and the display device and the like can be miniaturized.

[0034] FIG. 1 is a block diagram for explaining a semiconductor device according to one aspect of the present invention. The semiconductor device 20 is a sequential circuit that sequentially outputs signal potentials to the outside, and is also called a shift register. Note that FIG. 1 is a schematic diagram, and details such as the signal potentials input to each element, the power supply potential, and the connection form between the elements are omitted.

[0035] The semiconductor device 20 has blocks 31, 32, and 33. Each of blocks 31, 32, and 33 has a plurality of flip-flop circuits 10 and output circuits 11. The plurality of flip-flop circuits 10 included in each of blocks 31, 32, and 33 are connected in series. Also, a pair of output circuits 11 are electrically connected to each of the flip-flop circuits 10.

[0036] The flip-flop circuit 10 at the last stage of block 31, the flip-flop circuit 10 at the first stage of block 32, the flip-flop circuit 10 at the last stage of block 32, and the flip-flop circuit 10 at the last stage of block 32 are electrically connected to the switch circuit 15.

[0037] The switch circuit 15 can switch between a first mode in which the output operation of the signal potential in blocks 31, 32, and 33 is enabled and a second mode in which the output operation of the signal potential in blocks 31 and 33 is enabled. In the first mode, the signal potential can be sequentially output from all the blocks to the outside. In the second mode, since block 32 becomes non-operational, the signal potential can be sequentially output from blocks 31 and 33 to the outside.

[0038] As shown in FIG. 1, when a start pulse SP enters the flip-flop circuit 10 at the first stage of block 31 and the flip-flop circuit 10 at the fourth stage is taken as the last stage of block 31, block 32 can have flip-flop circuits 10 from the fifth stage to the 4n-th stage (n is an integer of 2 or more). Also, block 33 can have flip-flop circuits 10 from the (4n + 1)-th stage to the (4n + 4)-th stage.

[0039] For example, when n = 2 in the second mode, the flip-flop circuits in the first to fourth stages and the ninth to twelfth stages can output a signal potential, and the flip-flop circuits in the fifth to eighth stages can perform an operation of not outputting a signal potential. Also, when n = 9, the flip-flop circuits in the first to fourth stages and the thirty-seventh to fortieth stages can output a signal potential, and the flip-flop circuits in the fifth to thirty-sixth stages can perform an operation of not outputting a signal potential.

[0040] Specifically, when the semiconductor device 20 is applied to a display device having a sensor element and a display element in a pixel, etc., the first mode is used when writing image data and performing a sensing function (such as fingerprint authentication) that requires high resolution. On the other hand, since a high resolution is not required for a panel operation function by contact or non-contact, etc., the second mode is used. In the second mode, since the number of operating rows can be reduced, it can be operated at high speed.

[0041] Note that circuits having the same configuration as the switch circuit 15, the block 32, and the block 33 can be repeatedly connected after the block 33.

[0042] Next, the output circuit 11 electrically connected to the flip-flop circuit 10 will be described. The output circuit 11 includes a switch circuit 12, a circuit 13, and a circuit 14. The switch circuit 12 is electrically connected to the flip-flop circuit 10. Also, the switch circuit 12 is electrically connected to the circuit 13 and the circuit 14.

[0043] Based on the first signal potential input from the flip-flop circuit 10, the switch circuit 12 can output a second signal potential to one of the circuit 13 or the circuit 14. Also, a pulse width control signal PWC is input to one of the circuit 13 or the circuit 14 via the switch circuit 12. Based on the pulse width control signal PWC and the second signal potential, the circuit 13 or the circuit 14 can output a third signal potential to the outside.

[0044] For example, circuit 13 can be electrically connected to a circuit that drives a display element included in a pixel of the display device. Circuit 14 can be electrically connected to a circuit that drives a sensor element included in a pixel of the display device. Note that in FIG. 1, the output paths from circuit 13 and circuit 14 are each shown as one, but two or more may be provided. By increasing the pulse width control signal PWC input to switch circuit 12, circuit 13, and circuit 14, signal potentials can be output from two or more paths at different timings.

[0045] FIGS. 3 and 4 are detailed block diagrams of semiconductor device 20a applicable as semiconductor device 20 when n = 9. The flip-flop circuit 10, output circuit 11 (switch circuit 12, circuit 13, and circuit 14) shown in FIGS. 3 and 4 correspond to the block diagram shown in FIG. 1. The switch circuit 15 shown in FIG. 1 includes, as components, the switch circuit 16, switch circuit 17, switch circuit 18 shown in FIG. 3, and the switch circuit 19 shown in FIG. 4, etc.

[0046] As described above, output circuit 11 can output a signal potential from circuit 13 or circuit 14. FIGS. 3 and 4 illustrate a form in which a signal potential GLA (GLA[1] to GLA

[40] ) is output from circuit 13 and a signal potential GLB (GLB[1] to GLB

[40] ) is output from circuit 14.

[0047] Also, FIG. 3 shows an example in which a switch circuit 18 is provided between the fourth-stage flip-flop circuit 10 and the fifth-stage flip-flop circuit, and FIG. 4 shows an example in which a switch circuit 19 is provided between the 36th-stage flip-flop circuit 10 and the 37th-stage flip-flop circuit 10.

[0048] That is, the flip-flop circuits 10 and output circuits 11 of the first to fourth stages shown in FIG. 3 correspond to block 31 shown in FIG. 1. Also, the flip-flop circuits 10 and output circuits 11 of the fifth to thirty-sixth stages shown in FIGS. 3 and 4 correspond to block 32 shown in FIG. 1. Further, the flip-flop circuits 10 and output circuits 11 of the thirty-seventh to fortieth stages shown in FIG. 4 correspond to block 33 shown in FIG. 1.

[0049] Note that the number of stages of each block can be changed within the scope of the description of FIG. 1. Also, in the configurations shown in FIGS. 3 and 4, since the output signal of the subsequent flip-flop circuit 10 is input to the previous flip-flop circuit 10, a necessary number of dummy flip-flop circuits 10 are provided in the final block (not shown) of the entire semiconductor device 20a.

[0050] As input signals of the semiconductor device 20a, clock signals CLK1 to CLK4, pulse width control signals PWC1 to PWC4, reset signal RES, start pulse signal SP, selection signal SEL_A, selection signal SEL_B1, and selection signal SEL_B2 can be used.

[0051] FIG. 5A shows a block diagram of the flip-flop circuit 10, and FIG. 5B shows an example of a circuit diagram of the flip-flop circuit 10. The connection forms of the transistors and capacitors constituting the flip-flop circuit 10 are referred to FIG. 5B, and the description thereof is omitted. Note that VDD represents a high-potential power supply, and VSS represents a low-potential power supply. Also, the transistors constituting the semiconductor device 20a are n-channel type transistors.

[0052] The input signals are two systems of clock signals, reset signal RES, reset signal RIN input from the subsequent flip-flop circuit 10, and shift signal LIN input from the previous flip-flop circuit 10. Note that in the first-stage flip-flop circuit 10, clock signals CLK1 and CLK2 are used, and the start pulse signal SP is used instead of the shift signal LIN.

[0053] The output signals are signal potential 01, signal potential SROUT, and signal potential FN. Signal potential 01 is used for generating the signal potential output to the outside in circuit 13 or circuit 14, and signal potential FN is used for controlling the transistor serving as a pull-down resistor in circuit 13 or circuit 14. Signal potential SROUT is used as the shift signal LIN for the subsequent flip-flop circuit 10 and the reset signal RIN for the preceding flip-flop circuit 10.

[0054] Fig. 6A shows a block diagram of the switch circuit 12, and Fig. 6B shows an example of the circuit diagram of the switch circuit 12. The connection forms of the transistors and capacitors constituting the switch circuit 12 are referred to Fig. 6B, and the description thereof is omitted.

[0055] The input signals are the pulse width control signal PWC, the selection signal SEL_A, the selection signal SEL_B, the signal potential 01 input from the flip-flop circuit 10, and the signal potential FN. The selection signal SEL_A and the selection signal SEL_B are signals for selecting from which of circuit 13 and circuit 14 to output the signal potential to the outside. The selection signal SEL_B is the signal potential generated by the switch circuit 16 described later.

[0056] The output signals are signal potential 01_A, signal potential 01_B, signal potential FN_A, signal potential FN_B, pulse width control signal A_PWC, and pulse width control signal B_PWC. By inputting the selection signal SEL_A, signal potential 01_A, signal potential FN_A, and pulse width control signal A_PWC are generated. By inputting the selection signal SEL_B, signal potential 01_B, signal potential FN_B, and pulse width control signal B_PWC are generated.

[0057] Signal potential 01_A and signal potential 01_B are used for generating the signal potential output by circuit 13 or circuit 14. Signal potential FN_A and signal potential FN_B are used for controlling the transistors serving as pull-down resistors in circuit 13 or circuit 14. Pulse width control signal A_PWC and pulse width control signal B_PWC are used for controlling the pulse width of the signal potential output by circuit 13 or circuit 14.

[0058] That is, since the switch circuit 12 generates two pulse width control signals from one pulse width control signal, the number of input signals to the semiconductor device 20 can be reduced.

[0059] FIG. 7A shows a block diagram of the circuit 13, and FIG. 7B shows an example of a circuit diagram of the circuit 13. The connection forms of the transistors and capacitors constituting the circuit 13 are referred to FIG. 7B, and the description thereof is omitted.

[0060] The input signals are a signal potential 01_A, a signal potential FN_A, and a pulse width control signal A_PWC input from the switch circuit 12. The signal potential GLA generated by the input of the signal potential 01_A and the pulse width control signal A_PWC can be output to a wiring to which an external circuit is connected. Further, by the input of the signal potential FN_A, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring at VSS.

[0061] FIG. 7C shows a block diagram of the circuit 14, and FIG. 7D shows an example of a circuit diagram of the circuit 14. The connection forms of the transistors and capacitors constituting the circuit 14 are referred to FIG. 7D, and the description thereof is omitted.

[0062] The input signals are a signal potential 01_B, a signal potential FN_B, and a pulse width control signal B_PWC input from the switch circuit 12. The signal potential GLB generated by the input of the signal potential 01_B and the pulse width control signal B_PWC can be output to a wiring to which an external circuit is connected. Further, by the input of the signal potential FN_B, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring at VSS.

[0063] FIG. 8A shows a block diagram of the switch circuit 16, and FIG. 8B shows an example of a circuit diagram of the switch circuit 16. The connection form of the transistors constituting the switch circuit 16 is referred to FIG. 8B, and the description thereof is omitted.

[0064] The input signals are selection signal SEL_B1 and selection signal SEL_B2. Regardless of which selection signal is input, a signal potential SEL_B is generated. The signal potential SEL_B is input to the switch circuit 12 described above. By inputting the selection signal SEL_B to the switch circuit 12, the output of the signal potential from the circuit 14 to the outside can be enabled.

[0065] Fig. 8C shows a block diagram of the switch circuit 17, and Fig. 8D shows an example of a circuit diagram of the switch circuit 17. The connection form of the transistors constituting the switch circuit 17 is referred to Fig. 8D, and the description thereof is omitted.

[0066] The input signals are selection signal SEL_A and selection signal SEL_B1. Regardless of which selection signal is input, a signal potential SEL_C is generated. The signal potential SEL_C is input to the switch circuit 18 and the switch circuit 19 described later.

[0067] Fig. 9A shows a block diagram of the switch circuit 18, and Fig. 9B shows an example of a circuit diagram of the switch circuit 18. The connection form of the transistors constituting the switch circuit 18 is referred to Fig. 9B, and the description thereof is omitted.

[0068] The input signals are selection signal SEL_C and selection signal SEL_B2. Also, the switch circuit 18 has a terminal SWIN1, a terminal RIN1, a terminal LIN1, a terminal LIN2, and a terminal SWIN2. In Fig. 3, the terminal SWIN1 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the fourth-stage flip-flop circuit 10. The terminal RIN1 is electrically connected to the input terminal (the terminal to which the reset signal RIN is input) of the fourth-stage flip-flop circuit 10. The terminal LIN1 is electrically connected to the input terminal (the terminal to which the shift signal LIN is applied) of the fifth-stage flip-flop circuit 10. In Figs. 3 and 4, the terminal LIN2 is electrically connected to the input terminal (the terminal to which the shift signal LIN is input) of the 37th-stage flip-flop circuit 10 and the switch circuit 19 described later. The terminal SWIN2 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the fifth-stage flip-flop circuit 10.

[0069] FIG. 10A shows a block diagram of the switch circuit 19, and FIG. 10B shows an example of a circuit diagram of the switch circuit 19. The connection form of the transistors constituting the switch circuit 19 is referred to FIG. 10B, and the description thereof is omitted.

[0070] The input signals are the selection signal SEL_C and the selection signal SEL_B2. Also, it has terminals SWIN1, RIN1, RIN2, LIN1, and SWIN2. In FIG. 4, the terminal SWIN1 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the 36th flip-flop circuit 10. The terminal RIN1 is electrically connected to the input terminal (the terminal to which the reset signal RIN is input) of the 36th flip-flop circuit 10. In FIGS. 3 and 4, the terminal RIN2 is electrically connected to the input terminal (the terminal to which the reset signal RIN is input) of the 4th flip-flop circuit 10. In FIG. 4, the terminal LIN1 is electrically connected to the input terminal (the terminal to which the shift signal LIN is input) of the 37th flip-flop circuit 10. The terminal SWIN2 is electrically connected to the output terminal (the terminal that outputs the signal potential SROUT) of the 37th flip-flop circuit 10.

[0071] Here, when the selection signal SEL_C is input to the switch circuit 18 and the switch circuit 19, in the switch circuit 18, the terminal SWIN1 and the terminal LIN1 are conducted, and the terminal RIN1 and the terminal SWIN2 are conducted. Also, in the switch circuit 19, the terminal SWIN1 and the terminal LIN1 are conducted, and the terminal RIN1 and the terminal SWIN2 are conducted.

[0072] Therefore, the signal potential SROUT output by the 4th flip-flop circuit 10 is input to the 5th flip-flop circuit 10 as the shift signal LIN. The signal potential SROUT output by the 5th flip-flop circuit 10 is input to the 4th flip-flop circuit 10 as the reset signal RIN. Therefore, by inputting the selection signal SEL_C, the output operation of the signal potential in the blocks 31 and 32 shown in FIG. 1 is selected.

[0073] Also, the signal potential SROUT output by the flip-flop circuit 10 at the 36th stage is input to the flip-flop circuit 10 at the 37th stage as the shift signal LIN. The signal potential SROUT output by the flip-flop circuit 10 at the 37th stage is input to the flip-flop circuit 10 at the 36th stage as the reset signal RIN. Therefore, by inputting the selection signal SEL_C, the output operation of the signal potential in the block 33 shown in FIG. 1 is further selected.

[0074] That is, by inputting the selection signal SEL_C, the operations of the blocks 31, 32, and 33 shown in FIG. 1 are selected, and the signal potentials GLA[1] to GLA

[40] or the signal potentials GLB[1] to GLB

[40] can be output.

[0075] On the other hand, when the selection signal SEL_B2 is input to the switch circuit 18 and the switch circuit 19, in the switch circuit 18, the terminal SWIN1 and the terminal LIN2 are electrically connected. Also, in the switch circuit 19, the terminal RIN2 and the terminal SWIN2 are electrically connected.

[0076] Therefore, the signal potential SROUT output by the flip-flop circuit 10 at the 4th stage is input to the flip-flop circuit 10 at the 37th stage as the shift signal LIN. The signal potential SROUT output by the flip-flop circuit 10 at the 37th stage is input to the flip-flop circuit 10 at the 4th stage as the reset signal RIN.

[0077] That is, by inputting the selection signal SEL_B2, the output operations of the signal potentials in the blocks 31 and 33 shown in FIG. 1 are selected, and the signal potentials GLA[1] to GLA[4] and GLA

[37] to GLA

[40] , or the signal potentials GLB[1] to GLB[4] and GLB

[37] to GLB

[40] can be output.

[0078] The selection signals input to the semiconductor device 20a in the description so far and the circuits that output signal potentials are summarized in Table 1.

[0079]

Table 1

[0080] In the above, an example in which the paths of the signal potentials output from the circuits 13 and 14 are each one has been shown. However, by increasing the control signal PWC input to the switch circuit 12, the circuits 13, and 14, signal potentials can be output from two or more paths at different timings.

[0081] FIG. 11 is a block diagram of a semiconductor device 20b showing an example in which the signal potentials output from the circuits 13 and 14 are each two. From the circuit 13, the signal potential GLA1 and the signal potential GLA2 can be output at different timings. Also, from the circuit 14, the signal potential GLB1 and the signal potential GLB2 can be output at different timings.

[0082] In the input signal, the point that the pulse width control signal PWC increases to the pulse width control signal PWCA (PWCA1 to PWCA4) and the pulse width control signal PWCB (PWCB1 to PWCB4) is different from the semiconductor device 20a shown in FIGS. 3 and 4. Also, the configurations of the switch circuit 12, the circuits 13, and 14 are different from those of the semiconductor device 20a. Note that the configurations of the flip-flop circuit 10, the switch circuits 16, 17, the switch circuits 18, 19 (not shown), and the connection configurations of these elements in the semiconductor device 20b can be the same as those of the semiconductor device 20a.

[0083] FIG. 12A shows a block diagram of the switch circuit 12 included in the semiconductor device 20b, and FIG. 12B shows an example of a circuit diagram of the switch circuit 12. The connection forms of the transistors and capacitors constituting the switch circuit 12 are referred to FIG. 12B, and the description thereof is omitted.

[0084] The input signals are the pulse width control signal PWCA, the pulse width control signal PWCB, the selection signal SEL_A, the selection signal SEL_B, the signal potential 01 and the signal potential FN input from the flip-flop circuit 10. The selection signal SEL_A and the selection signal SEL_B are signals for selecting whether to output the signal potential externally from either the circuit 13 or the circuit 14.

[0085] The output signals are the signal potential 01_A, the signal potential 01_B, the signal potential FN_A, the signal potential FN_B, the pulse width control signal A_PWCA, the pulse width control signal B_PWCA, the pulse width control signal A_PWCB, and the pulse width control signal B_PWCB. By inputting the selection signal SEL_A, the signal potential 01_A, the signal potential FN_A, the pulse width control signal A_PWCA, and the pulse width control signal A_PWCB are generated. By inputting the selection signal SEL_B, the signal potential 01_B, the signal potential FN_B, the pulse width control signal B_PWCA, and the pulse width control signal B_PWCB are generated.

[0086] The signal potential 01_A and the signal potential 01_B are used for generating the signal potential output by the circuit 13 or the circuit 14. The signal potential FN_A and the signal potential FN_B are used for controlling the transistors that serve as pull-down resistors in the circuit 13 or the circuit 14. The pulse width control signals A_PWCA, A_PWCB, B_PWCA, and B_PWCB are used for controlling the pulse width and timing of the signal potential output by the circuit 13 or the circuit 14.

[0087] Fig. 13A shows a block diagram of the circuit 13 included in the semiconductor device 20b, and Fig. 13B shows an example of the circuit diagram of the circuit 13. The connection forms of the transistors and capacitors constituting the circuit 13 are referred to Fig. 13B, and the description thereof is omitted.

[0088] The input signals are the signal potential 01_A, the signal potential FN_A, and the pulse width control signals A_PWCA, A_PWCB input from the switch circuit 12.

[0089] By inputting the signal potential 01_A and the pulse width control signal A_PWCA, the signal potential GLA1 can be output to the wiring to which an external circuit is connected. Also, by inputting the signal potential FN_A and the pulse width control signal A_PWCA, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring at VSS.

[0090] Also, by inputting the signal potential 01_A and the pulse width control signal A_PWCB, the signal potential GLA2 can be output to the wiring to which an external circuit is connected. Also, by inputting the signal potential FN_A and the pulse width control signal A_PWCB, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring at VSS.

[0091] Therefore, each of the signal potential GLA1 and the signal potential GLA2 can be output externally at different timings.

[0092] FIG. 14A shows a block diagram of a circuit 14 included in the semiconductor device 20b, and FIG. 14B shows an example of a circuit diagram of the circuit 14. The connection forms of the transistors and capacitors constituting the circuit 14 are referred to FIG. 14B, and the description thereof is omitted.

[0093] The input signals are the signal potential 01_B, the signal potential FN_B, and the pulse width control signals B_PWCA and B_PWCB input from the switch circuit 12.

[0094] By inputting the signal potential 01_B and the pulse width control signal B_PWCA, the signal potential GLB1 can be output to the wiring to which an external circuit is connected. Also, by inputting the signal potential FN_B and the pulse width control signal B_PWCA, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring at VSS.

[0095] Also, by inputting the signal potential 01_B and the pulse width control signal B_PWCB, the signal potential GLB2 can be output to the wiring to which an external circuit is connected. Also, by inputting the signal potential FN_B and the pulse width control signal B_PWCB, a transistor corresponding to a pull-down resistor can be operated, and the potential of the wiring can be stabilized to VSS.

[0096] Therefore, each of the signal potential GLB1 and the signal potential GLB2 can be output externally at different timings.

[0097] The semiconductor devices 20a and 20b described above can use an n-channel type transistor as a component. As a semiconductor material that can be used for the channel formation region of the n-channel type transistor, silicon or a metal oxide is preferable.

[0098] In a transistor (hereinafter, Si transistor) using silicon for the channel formation region of the transistor, amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. can be used. When a transistor is provided on an insulating surface such as on a glass substrate, it is preferable to use amorphous silicon or polycrystalline silicon.

[0099] Since the technology for forming amorphous silicon on a large-area glass substrate by plasma CVD (chemical vapor deposition) method has been established, it is preferably used for large-sized devices. Also, since polycrystalline silicon can form a transistor with high mobility, the transistor size can be reduced, and it is preferably used for high-definition medium and small-sized devices. Also, since a transistor using polycrystalline silicon can operate at high speed, a drive circuit can also be formed. Specific examples of the device include a display device.

[0100] High-quality polycrystalline silicon can be easily obtained by using a laser crystallization process or the like. Further, high-quality polycrystalline silicon can also be obtained by a solid-phase growth method in which a metal catalyst such as nickel or palladium is added to amorphous silicon and heated. Further, laser irradiation may be performed on the polycrystalline silicon formed by the solid-phase growth method using a metal catalyst to further enhance the crystallinity. Note that since the metal catalyst remains in the polycrystalline silicon and deteriorates the electrical characteristics of the transistor, it is preferable to provide a region doped with phosphorus or a noble gas or the like outside the channel formation region and capture the metal catalyst in the region.

[0101] On the other hand, a transistor using a metal oxide in the channel formation region (hereinafter, an OS transistor) has a higher mobility than a transistor using amorphous silicon in the channel formation region. Further, since it can be formed on an insulating surface such as a glass substrate by a sputtering method or the like, it is also easy to apply to large-area devices. Therefore, the OS transistor can be widely applied from small and medium-sized devices to large-sized devices.

[0102] Since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit an extremely low off-current characteristic of several yA / μm (current value per 1 μm channel width). Therefore, when the OS transistor is used in a pixel circuit of a display device, the pixel circuit can hold a data potential for a long time.

[0103] Therefore, appropriate image display can be performed even when the frame frequency is lowered. For example, in the case of moving image display, the first frame frequency (for example, 60 Hz or more) is set, and in the case of still image display, the frame frequency is switched to a second frame frequency lower than the first frame frequency (for example, about 1 to 10 Hz), so that the display device can be made to consume less power.

[0104] The semiconductor device according to one aspect of the present invention can be used for a driving circuit (e.g., a load driver) of the display device. By forming the driving circuit using the same process as the pixel circuit, mounting of an IC chip etc. becomes unnecessary, and thus a display device with a narrow border can be formed. That is, forming the semiconductor device according to one aspect of the present invention together with the pixel circuit using an OS transistor is effective for making the display device have a narrow border.

[0105] Note that the configuration is not limited to a case where all transistors included in the pixel circuit and the driving circuit are formed of Si transistors or OS transistors. One of the pixel circuit and the driving circuit may be formed of Si transistors and the other may be formed of OS transistors. Alternatively, some transistors included in the pixel circuit and the driving circuit may be formed of one of Si transistors or OS transistors, and the other transistors may be formed of the other of Si transistors or OS transistors. The above configuration may be appropriately determined according to functions required for the display device etc.

[0106] As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS described later can be used. In CAAC-OS, atoms constituting the crystal are stable, and it is suitable for transistors etc. that emphasize reliability. Also, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors etc. that perform high-speed driving.

[0107] The OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effect, and a highly reliable circuit can be formed. Also, variations in electrical characteristics due to non-uniformity of crystallinity, which are problems in Si transistors, are less likely to occur in OS transistors.

[0108] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using the ALD (Atomic Layer Deposition) method.

[0109] For the sputtering target used to form the In-M-Zn-based oxide by the sputtering method, it is preferable that the atomic ratio of the metal elements satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements in the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0110] As the semiconductor layer, an oxide semiconductor with a low carrier concentration is used. For example, the semiconductor layer has a carrier concentration of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, even more preferably 1×10 11 / cm 3 or less, still more preferably 1×10 10 / cm 3 or less, and an oxide semiconductor with a carrier concentration of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low defect level density and stable characteristics.

[0111] Note that the present invention is not limited to these, and a material having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistors. Further, in order to obtain the semiconductor characteristics of the required transistors, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate values.

[0112] In the oxide semiconductor constituting the semiconductor layer, when silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and the semiconductor becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0113] In addition, when an alkali metal or an alkaline earth metal binds to an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0114] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, carriers in the form of electrons are generated, the carrier concentration increases, and the semiconductor easily becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. For this reason, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably set to 5×10 18 atoms / cm 3 or less.

[0115] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to form water, so oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, defects with hydrogen incorporated into oxygen vacancies may function as donors, and electrons, which are carriers, may be generated. Also, a part of hydrogen may bind to oxygen that binds to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to exhibit normally-on characteristics.

[0116] Defects with hydrogen incorporated into oxygen vacancies may function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may sometimes be paraphrased as "donor concentration".

[0117] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0118] Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0119] The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0120] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0121] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0122] CAC-OS is, for example, a configuration of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Hereinafter, in the oxide semiconductor, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0123] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

[0124] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (where X3 is a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0).) and other materials are separated to form a mosaic shape, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 is distributed uniformly in the film (hereinafter, also referred to as a cloud-like state).

[0125] That is, CAC-OS is a composite oxide semiconductor having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are mixed. In this specification, for example, when the atomic ratio of indium to element M in the first region is greater than the atomic ratio of indium to element M in the second region, it is considered that the concentration of indium in the first region is higher than that in the second region when compared with the second region.

[0126] Note that IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. As a representative example, InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number). Examples of crystalline compounds represented by this formula include those with a single crystal structure, a polycrystalline structure, or a CAAC structure.

[0127] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0128] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which regions observed as nanoparticle-like regions mainly composed of Ga and regions observed as nanoparticle-like regions mainly composed of In are randomly dispersed in a mosaic pattern in a material composition containing In, Ga, Zn, and O. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0129] Note that CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure composed of two layers, a film mainly composed of In and a film mainly composed of Ga, is not included.

[0130] Note that GaO X3 in the region where it is the main component and In X2 Zn Y2 O Z2 , or InO X1 in the region where it is the main component may not have a clear boundary.

[0131] In addition, when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are included instead of gallium, CAC-OS refers to a structure in which a region observed as nanoparticles mainly composed of the metal element and a region observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern, respectively.

[0132] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0133] CAC-OS has the characteristic that no distinct peak is observed when measured using θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0134] Also, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high brightness in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0135] Also, for example, in CAC-OS in In-Ga-Zn oxide, regions where GaO X3 is the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are unevenly distributed and mixed, and it can be confirmed that they have a structure.

[0136] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of an IGZO compound. That is, CAC-OS has regions where components such as GaO X3 are the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, and they are phase-separated from each other, and the regions with each element as the main component have a mosaic-like structure.

[0137] Here, regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are regions with higher conductivity compared to regions where components such as GaO X3 are the main component. That is, when carriers flow through regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, conductivity as an oxide semiconductor is exhibited. Therefore, when regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are distributed in a cloud-like manner in the oxide semiconductor, high field-effect mobility (μ) can be realized.

[0138] On the other hand, regions where components such as GaO X3 are the main component are In X2 Zn Y2 O Z2 , or InOX1 is a region with high insulation compared to the region where it is the main component. That is, GaO X3 and the like being the main component are distributed in the oxide semiconductor, suppressing the leakage current and enabling a good switching operation.

[0139] Therefore, when CAC-OS is used in a semiconductor device, the insulation due to GaO X3 and the like, and the conductivity due to In X2 Zn Y2 O Z2 or InO X1 act complementarily to realize a high on-current (I on ) and a high field-effect mobility (μ).

[0140] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0141] Also, the semiconductor device 20a and the semiconductor device 20b described above use an n-channel type transistor as a constituent element, but a p-channel type transistor may be used as a constituent element.

[0142] FIG. 15 is a block diagram of a semiconductor device 20c using a p-channel type transistor as a constituent element of a circuit. The connection configuration of each element circuit is the same as that of the semiconductor device 20a shown in FIGS. 3 and 4, and only a part is shown in FIG. 15. In the semiconductor device 20c, in addition to using a p-channel type transistor as a constituent element of the circuit, the configurations of the switch circuit 16 and the switch circuit 17 and the signals input thereto are different from those of the semiconductor device 20a.

[0143] FIG. 16A shows a block diagram of the flip-flop circuit 10, and FIG. 16B shows an example of a circuit diagram of the flip-flop circuit 10 composed of p-channel transistors. The connection forms of the transistors and capacitors constituting the flip-flop circuit 10 are referred to FIG. 16B, and the description thereof is omitted. Also, the description of the input signals and output signals can be referred to the description of FIG. 5B. Note that the flip-flop circuit 10 shown in FIG. 16B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 5B.

[0144] FIG. 17A shows a block diagram of the switch circuit 12, and FIG. 17B shows an example of a circuit diagram of the switch circuit 12 composed of p-channel transistors. The connection forms of the transistors and capacitors constituting the switch circuit 12 are referred to FIG. 6B, and the description thereof is omitted. Also, the description of the input signals and output signals can be referred to the description of FIG. 6B. Note that the switch circuit 12 shown in FIG. 17B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 6B.

[0145] FIG. 18A shows a block diagram of the circuit 13, and FIG. 18B shows an example of a circuit diagram of the circuit 13 composed of p-channel transistors. The connection forms of the transistors and capacitors constituting the circuit 13 are referred to FIG. 7B, and the description thereof is omitted. Also, the description of the input signals and output signals can be referred to the description of FIG. 7B. Note that the circuit 13 shown in FIG. 18B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 7B.

[0146] FIG. 18C shows a block diagram of the circuit 14, and FIG. 18D shows an example of a circuit diagram of the circuit 14 composed of p-channel transistors. The connection forms of the transistors and capacitors constituting the circuit 14 are referred to FIG. 18D, and the description thereof is omitted. Also, the description of the input signals and output signals can be referred to the description of FIG. 7D. Note that the circuit 14 shown in FIG. 18D is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 7D.

[0147] FIG. 19A shows a block diagram of the switch circuit 16, and FIG. 19B shows an example of a circuit diagram of the switch circuit 16 composed of p-channel transistors. The connection form of the transistors constituting the switch circuit 16 is referred to FIG. 19B, and the description thereof is omitted.

[0148] The input signals are the selection signal SEL_A, the selection signal SEL_B1, and the selection signal SEL_B2. When the selection signal SEL_B1 or the selection signal SEL_B2 is input, a signal potential SEL_B is generated. The signal potential SEL_B is input to the switch circuit 12 described above. By inputting the selection signal SEL_B to the switch circuit 12, the output of the signal potential from the circuit 14 to the outside can be enabled. When the selection signal SEL_A is input, a valid signal potential SEL_B is not generated.

[0149] FIG. 19C shows a block diagram of the switch circuit 17, and FIG. 19D shows an example of a circuit diagram of the switch circuit 17 composed of p-channel transistors. The connection form of the transistors constituting the switch circuit 17 is referred to FIG. 19D, and the description thereof is omitted.

[0150] The input signals are the selection signal SEL_A, the selection signal SEL_B1, and the selection signal SEL_B2. When the selection signal SEL_B1 or the selection signal SEL_B2 is input, a signal potential SEL_C is generated. The signal potential SEL_C is input to the switch circuits 18 and 19 described later. When the selection signal SEL_A is input, a valid signal potential SEL_B is not generated.

[0151] FIG. 20A shows a block diagram of the switch circuit 18, and FIG. 20B shows an example of a circuit diagram of the switch circuit 18 composed of p-channel transistors. The connection form of the transistors constituting the switch circuit 18 is referred to FIG. 20B, and the description thereof is omitted. Also, the description of the input signals and output signals can refer to the description of FIG. 9B. Note that the circuit 14 shown in FIG. 20B is supplied with power potentials obtained by inverting the power potentials (VDD, VSS) shown in FIG. 9B.

[0152] FIG. 21A shows a block diagram of the switch circuit 19, and FIG. 21B shows an example of a circuit diagram of the switch circuit 19 composed of p-channel transistors. The connection form of the transistors constituting the switch circuit 19 can be referred to FIG. 21B, and the description thereof is omitted. Also, the description of the input signal and the output signal can refer to the description of FIG. 10B. Note that the circuit 14 shown in FIG. 21B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 10B.

[0153] Note that, in the above, an example in which the path of the signal potential output from the circuit 13 and the circuit 14 is one each has been shown. However, by increasing the control signal PWC input to the switch circuit 12, the circuit 13, and the circuit 14, the signal potential can be output from two or more paths at different timings.

[0154] FIG. 22 is a block diagram of a semiconductor device 20d showing an example in which the path of the signal potential output from the circuit 13 and the circuit 14 is two each. From the circuit 13, the signal potential GLA1 and the signal potential GLA2 can be output at different timings. Also, from the circuit 14, the signal potential GLB1 and the signal potential GLB2 can be output at different timings.

[0155] In the input signal, the point that the pulse width control signal PWC increases to the pulse width control signal PWCA (PWCA1 to PWCA4) and the pulse width control signal PWCB (PWCB1 to PWCB4) is different from the semiconductor device 20c shown in FIG. 5. Also, the configurations of the switch circuit 12, the circuit 13, and the circuit 14 are different from those of the semiconductor device 20c. Note that the configurations of the flip-flop circuit 10, the switch circuits 16 and 17, the switch circuits 18 and 19 (not shown) included in the semiconductor device 20d, and the connection configurations of these elements with each other can be the same as those of the semiconductor device 20c.

[0156] FIG. 23A shows a block diagram of a switch circuit 12 included in the semiconductor device 20d, and FIG. 23B shows an example of a circuit diagram of the switch circuit 12 constituted by p-channel transistors. The connection forms of the transistors and capacitors constituting the switch circuit 12 are referred to FIG. 23B, and the description thereof is omitted. Also, the description of the input signal and the output signal can refer to the description of FIG. 12B. Note that the switch circuit 12 shown in FIG. 23B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 12B.

[0157] FIG. 24A shows a block diagram of a circuit 13 included in the semiconductor device 20d, and FIG. 24B shows an example of a circuit diagram of the circuit 13 constituted by p-channel transistors. The connection forms of the transistors and capacitors constituting the circuit 13 are referred to FIG. 24B, and the description thereof is omitted. Also, the description of the input signal and the output signal can refer to the description of FIG. 13B. Note that the circuit 13 shown in FIG. 23B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 13B.

[0158] FIG. 25A shows a block diagram of a circuit 14 included in the semiconductor device 20d, and FIG. 25B shows an example of a circuit diagram of the circuit 14 constituted by p-channel transistors. The connection forms of the transistors and capacitors constituting the circuit 14 are referred to FIG. 25B, and the description thereof is omitted. Also, the description of the input signal and the output signal can refer to the description of FIG. 14B. Note that the circuit 14 shown in FIG. 23B is supplied with power supply potentials obtained by inverting the power supply potentials (VDD, VSS) shown in FIG. 14B.

[0159] Note that it is preferable to use Si transistors for the p-channel transistors. In particular, it is preferable to use polycrystalline silicon or single crystal silicon capable of forming transistors with high mobility even for p-channel transistors.

[0160] Note that the configuration is not limited to forming all the transistors included in the pixel circuit and the driving circuit using Si transistors. The driving circuit may be formed using Si transistors, and the pixel circuit may be formed using OS transistors. Alternatively, some of the transistors included in the pixel circuit and the driving circuit may be formed using one of Si transistors or OS transistors, and the other transistors may be formed using the other of Si transistors or OS transistors. The above configuration may be appropriately determined according to the functions required for the display device and the like.

[0161] This embodiment can be implemented in appropriate combination with at least some parts of other embodiments described in this specification.

[0162] (Embodiment 2) In this embodiment, a display device to which the semiconductor device described in Embodiment 1 can be applied will be described.

[0163] FIG. 26 is a diagram for explaining a display device according to an aspect of the present invention. The display device includes a pixel array 23 having pixels 24 arranged in a column direction and a row direction, a circuit 40, a circuit 41, and a circuit 42. Note that the wirings connecting the respective blocks shown in FIG. 26 are simplified and may differ from the actual number of wirings.

[0164] The pixel 24 includes a circuit 25 and a circuit 26. The circuit 25 has a function of emitting light for display. The circuit 26 has a function of detecting light. Note that the circuits 25 and 26 may also be referred to as sub-pixels.

[0165] Circuit 25 has a light-emitting device (also referred to as a light-emitting element) that emits visible light. As the light-emitting device, it is preferable to use an EL element such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode). Examples of the light-emitting substance of the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), an inorganic compound (such as a quantum dot material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material). Further, as the light-emitting device, an LED such as a micro LED (Light Emitting Diode) can also be used.

[0166] Circuit 26 has a light-receiving device (also referred to as a light-receiving element). As the light-receiving device, for example, a pn-type or pin-type photodiode can be used. For the light-receiving device, a photoelectric conversion element that detects incident light and generates electric charges can be used. In the light-receiving device, the amount of generated electric charges is determined based on the amount of incident light.

[0167] As the light-receiving device, it is preferable to use an organic photodiode having an organic compound in the photoelectric conversion layer. The organic photodiode is easy to be thinned, lightened, and enlarged in area. Further, since the degree of freedom in shape and design is high, it can be applied to various display devices. Alternatively, a photodiode using amorphous silicon, crystalline silicon (single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, etc.), metal oxide, etc. can also be used as the light-receiving device.

[0168] When an organic compound is used for the photoelectric conversion layer of a photodiode, by appropriately selecting the material, it can have sensitivity from ultraviolet light to infrared light. When amorphous silicon is used for the photoelectric conversion layer, it mainly has sensitivity to visible light, and when crystalline silicon is used, it has sensitivity from visible light to infrared light. Since metal oxides have a large energy gap, when a metal oxide is used for the photoelectric conversion layer, it mainly has high sensitivity to light with higher energy than visible light. Note that as the metal oxide, for example, the In-M-Zn-based oxide described in Embodiment 1 can be used.

[0169] In one aspect of the present invention, an organic EL element is used as a light-emitting device, and an organic photodiode is used as a light-receiving device. The organic photodiode can have many layers in common with the organic EL element. Therefore, a light-receiving device can be incorporated into a display device without significantly increasing the manufacturing process. For example, the photoelectric conversion layer of the light-receiving device and the light-emitting layer of the light-emitting device can be separately formed, and the other layers may have the same configuration for both the light-emitting device and the light-receiving device.

[0170] Circuit 40 is a load driver (gate driver) for driving Circuit 25 and Circuit 26. For Circuit 40, the semiconductor device 20a, semiconductor device 20b, semiconductor device 20c, or semiconductor device 20d described in Embodiment 1 can be used.

[0171] Circuit 41 is a column driver (source driver) for supplying image data and the like to Circuit 25. For Circuit 41, for example, a shift register circuit or a decoder circuit can be used.

[0172] Circuit 42 is a read circuit for the data output by circuit 26. Circuit 42 has, for example, an A / D conversion circuit and has the function of converting the analog data output from circuit 26 into digital data. Further, circuit 42 may have a CDS circuit that performs correlated double sampling processing on the output data of circuit 26. Also, a selection circuit (multiplexer circuit) may be provided between the CDS circuit and the A / D conversion circuit. Further, it may have a column driver that outputs digital data to the outside.

[0173] Circuit 26 can have the function as an input interface. Circuit 26 has a light receiving device and can read position information of an object close to the display device and the like from the change in the amount of light reaching the pixel array 23. Therefore, operations equivalent to those of a touch panel can be performed non-contact. Also, operations such as those of a pointer can be performed non-contact.

[0174] Further, the object may be brought into contact with the display device, and circuit 26 may acquire imaging data. By bringing the object into contact with the display device, imaging data such as fingerprints or palm prints can be acquired with high resolution. That is, a biometric authentication function can be added to the display device. In the display device according to one aspect of the present invention, the imaging data can be obtained by circuit 26 receiving the light emitted by circuit 25 and reflected by the object. At this time, the light emitted by circuit 25 is preferably green light or white light.

[0175] FIG. 27A shows an example of a pixel circuit PIX1 applicable to circuit 25. Pixel circuit PIX1 has a light emitting device EL, transistors M1, M2, M3, and a capacitor C1. Here, an example using a light emitting diode as the light emitting device EL is shown. It is preferable to use an organic EL element that emits visible light as the light emitting device EL.

[0176] Transistor M1 has its gate electrically connected to wiring G1, one of its source or drain electrically connected to wiring S1, and the other of its source or drain electrically connected to one electrode of capacitor C1 and the gate of transistor M2. One of the source or drain of transistor M2 is electrically connected to wiring V2, and the other is electrically connected to the anode of light-emitting device EL and one of the source or drain of transistor M3. Transistor M3 has its gate electrically connected to wiring G2, and the other of its source or drain electrically connected to wiring V0. The cathode of light-emitting device EL is electrically connected to wiring V1.

[0177] A fixed potential is supplied to wiring V1 and wiring V2 respectively. Light emission can be achieved by setting the anode side of light-emitting device EL to a high potential and the cathode side to a low potential. Transistor M1 is controlled by the signal supplied to wiring G1 and functions as a selection transistor for controlling the selection state of pixel circuit PIX1. Also, transistor M2 functions as a driving transistor for controlling the current flowing through light-emitting device EL according to the potential supplied to its gate.

[0178] When transistor M1 is in the conductive state, the potential supplied to wiring S1 is supplied to the gate of transistor M2, and the emission luminance of light-emitting device EL can be controlled according to that potential. Transistor M3 is controlled by the signal supplied to wiring G2. The potential between transistor M3 and light-emitting device EL can be reset to the fixed potential supplied from wiring V0, and the potential writing to the gate of transistor M2 can be performed with the source potential of transistor M2 stabilized.

[0179] Fig. 27B shows an example of pixel circuit PIX2 applicable to circuit 25. Pixel circuit PIX2 has a boosting function. Pixel circuit PIX2 has light-emitting device EL, transistor M4, transistor M5, transistor M6, transistor M7, capacitor C2 and capacitor C3.

[0180] Transistor M4 has its gate electrically connected to wiring G1, one of its source or drain electrically connected to wiring S1, and the other of its source or drain electrically connected to one electrode of capacitor C2, one electrode of capacitor C3, and the gate of transistor M7. Transistor M5 has its gate electrically connected to wiring G2, one of its source or drain electrically connected to wiring VRW, and the other of its source or drain electrically connected to the other electrode of capacitor C2 and one of the source or drain of transistor M6.

[0181] The gate of transistor M6 is electrically connected to wiring G1, and the other of its source or drain is electrically connected to the other electrode of capacitor C3, one of the source or drain of transistor M7, and the anode of light-emitting device EL. The other of the source or drain of transistor M7 is electrically connected to wiring V2.

[0182] Transistors M4 and M6 are controlled by the signal supplied to wiring G1, and transistor M5 is controlled by the signal supplied to wiring G2. Transistor M7 functions as a driving transistor that controls the current flowing through light-emitting device EL according to the potential supplied to its gate.

[0183] By turning on transistors M5 and M6, the potential between transistor M7 and light-emitting device EL can be reset to a constant potential (e.g., reset potential VRES) supplied from wiring VRW. Therefore, the potential of wiring S1 can be written to the gate of transistor M7 with the source potential of transistor M7 stabilized. Also, by setting the reset potential VRES to the same potential as wiring V1 or a potential lower than wiring V1, the light emission of light-emitting device EL can be suppressed.

[0184] In pixel circuit PIX2, the light emission intensity of light emitting device EL can be increased. The boosting function of pixel circuit PIX2 will be described using the timing chart shown in Fig. 27C. Note that the node to which the gate of transistor M7 is connected is defined as node ND.

[0185] First, when the potentials of wiring G1 and wiring G2 are set to “H” (high potential), transistor M4 conducts, and the potential D1 of wiring S1 is supplied to node ND. Also, transistors M5 and M6 conduct, and the reset potential VRES is supplied to the other electrode of capacitor C2.

[0186] Next, when the potential of wiring G1 is set to “L” (low potential), transistors M4 and M6 become non - conductive, and node ND becomes a floating state. At this time, the potential D1 - VRES is held in capacitor C2.

[0187] Then, when the potential of wiring VRW is changed from the reset potential VRES to the boosting potential VW, due to capacitive coupling, the change in potential (VW - VRES) of the other electrode of capacitor C2 is added to the potential of node ND.

[0188] Note that the actual increase in the potential of node ND is (C2 / (C ND +C2))×(VW - VRES) according to the capacitance ratio between the capacitance of node ND and the capacitance of capacitor C2. Here, C ND is the capacitance of node ND, C2 is the capacitance of capacitor C2, and if C2 is sufficiently large, (C2 / (C ND +C2)) approximates to 1. Also, when the reset potential VRES = 0, the increase in the potential of node ND is VW. Therefore, node ND is boosted from potential D1 to potential D1+VW.

[0189] By boosting the potential of node ND, a larger current can be passed through the light-emitting device EL, and the emission luminance can be increased. When the object to be imaged is brought into contact with the display device, increasing the emission luminance reduces the dark areas, so that more detailed imaging data can be obtained. Also, by having the function of boosting the voltage in the pixel, it becomes unnecessary to supply a high voltage from the source driver, so that the power consumption can also be reduced. Further, since a high-output source driver is also unnecessary, the manufacturing cost can be reduced.

[0190] FIG. 27D shows an example of the pixel circuit PIX3 applicable to the circuit 26. The pixel circuit PIX3 includes a light-receiving device PD, transistors M9, M10, M11, M12, and a capacitor C4. Here, an example using a photodiode is shown as the light-receiving device PD.

[0191] The cathode of the light-receiving device PD is electrically connected to the wiring V1, and the anode is electrically connected to either the source or the drain of the transistor M9. The gate of the transistor M9 is electrically connected to the wiring G4, and the other of the source or the drain is electrically connected to one electrode of the capacitor C4, one of the source or the drain of the transistor M10, and the gate of the transistor M11. The gate of the transistor M10 is electrically connected to the wiring G5, and the other of the source or the drain is electrically connected to the wiring V4. One of the source or the drain of the transistor M11 is electrically connected to the wiring V3, and the other of the source or the drain is electrically connected to one of the source or the drain of the transistor M12. The gate of the transistor M12 is electrically connected to the wiring G6, and the other of the source or the drain is electrically connected to the wiring OUT.

[0192] A constant potential is supplied to wiring V1, wiring V3, and wiring V4, respectively. When driving the light receiving device PD in reverse bias, a potential lower than the potential of wiring V1 is supplied to wiring V4. The transistor M10 is controlled by a signal supplied to wiring G5 and has a function of resetting the potential of a node (charge readout section) connected to the gate of the transistor M11 to the potential supplied to wiring V4. The transistor M9 is controlled by a signal supplied to wiring G4 and has a function of controlling the timing at which the potential of the above node changes according to the amount of charge accumulated in the light receiving device PD. The transistor M11 functions as an amplification transistor that outputs according to the potential of the above node. The transistor M12 is controlled by a signal supplied to wiring G6 and functions as a selection transistor for reading an output according to the potential of the above node to an external circuit connected to wiring OUT.

[0193] Here, it is preferable to apply an OS transistor to the transistors included in the pixel circuits PIX1 to PIX3. The OS transistor can achieve an extremely small off-current. Due to the small off-current characteristic of the OS transistor, it becomes possible to hold the charge accumulated in the capacitor connected in series with the transistor for a long period of time.

[0194] In particular, it is preferable to use an OS transistor for the transistors M1, M4, M5, M6, M9, and M10 in which a current path is connected in series to the capacitor C1, capacitor C2, or capacitor C3. By using an OS transistor in circuit 26, it becomes possible to hold the charge for a long period of time. Therefore, a global shutter method in which the charge accumulation operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method. Also, by using an OS transistor for the other transistors as well, the manufacturing cost can be reduced.

[0195] In addition, Si transistors can also be used for the transistors included in pixel circuits PIX1 to PIX3. In particular, by using highly crystalline silicon such as single-crystalline silicon or polycrystalline silicon, high field-effect mobility can be achieved, enabling faster operation, which is preferable.

[0196] Moreover, among the transistors included in pixel circuits PIX1 to PIX3, an OS transistor may be used for one or more of them, and an Si transistor may be used for the rest.

[0197] Note that when an OS transistor is used, as shown in FIG. 27E, a back gate may be provided for each transistor. By supplying the front gate with the same potential as the back gate, the on-current can be increased. Also, by supplying a fixed potential to the back gate, the threshold voltage of the transistor can be adjusted. Note that the configuration in which a back gate is provided for the transistor can also be applied to FIGS. 27A to 27D. Moreover, it can also be applied to the semiconductor device in which the OS transistor shown in Embodiment 1 can be used.

[0198] Note that in FIGS. 27A to 27E, an example in which an n-channel type transistor is used is illustrated, but a p-channel type transistor can also be used.

[0199] Next, the connection form between circuit 40 and pixel 24 (circuits 25 and 26) and their operations will be described. As described above, semiconductor devices 20a to 20d described in Embodiment 1 can be used for circuit 40. Here, an example in which semiconductor device 20b is used for circuit 40 will be described.

[0200] FIG. 28 is a diagram showing the connection form between a part of circuit 40 (one-stage flip-flop circuit 10 and output circuit 11 (switching circuit 12, circuits 13, 14)) and circuits 25 and 26 included in pixel 24. Note that as circuit 25, pixel circuit PIX2 shown in FIG. 27B is used, and as circuit 26, pixel circuit PIX3 shown in FIG. 27C is used.

[0201] In FIG. 28, a configuration is illustrated in which one circuit 25 and one circuit 26 are provided for each pixel 24. When the display and imaging data conform to grayscale, this configuration can be used. When performing color display, at least a circuit 25 that emits each of the three primary colors of light is required. Therefore, as shown in FIG. 29A, the pixel 24 can use a configuration in which a circuit 25(R) that emits red light, a circuit 25(G) that emits green light, and a circuit 25(B) that emits blue light are provided.

[0202] In the configuration shown in FIG. 29A, the light-emitting device EL included in the circuit 25 can be formed by using a light-emitting device that emits red, green, or blue light. Alternatively, a light-emitting device that emits white light can be used for the light-emitting device EL included in the circuit 25, and a color filter for red, green, or blue can be provided on the light-emitting device.

[0203] Furthermore, when acquiring color imaging data, as shown in FIG. 29B, the pixel 24 can use a configuration having a circuit 26(R) for red light imaging, a circuit 26(G) for green light imaging, and a circuit 26(B) for blue light imaging. These can be formed by using a light-emitting device having a photoelectric conversion layer that strongly absorbs light of one color among red, green, and blue light more than light of other colors as the light-receiving device PD included in the circuit 26. Alternatively, a light-emitting device having a photoelectric conversion layer that has absorption in the wavelength bands of red, green, and blue can be used for the light-receiving device PD included in the circuit 26, and a color filter for red, green, or blue can be provided on the light-receiving device.

[0204] As shown in FIG. 28, the circuit 13 is electrically output to the wiring G1 and the wiring G2. The signal potential GLA1 output by the circuit 13 can be supplied to the wiring G1. The signal potential GLA2 output by the circuit 13 can be supplied to the wiring G2.

[0205] Circuit 14 is electrically output to wiring G5 and wiring G6. Wiring G5 can supply the signal potential GLB1 output by circuit 14. Wiring G6 can supply the signal potential GLB2 output by circuit 14.

[0206] Note that wiring G5 is electrically connected to the gate of transistor M10 included in circuit 26. Transistor M10 is a transistor for a reset operation that resets the potential of the gate of transistor M11 to the potential of wiring V4. As described above, by using OS transistors such as transistor M9 and transistor M10, a global shutter method in which charge accumulation operations are performed simultaneously in all pixels can be applied.

[0207] In the global shutter method, in order to perform a reset operation simultaneously in all pixels, a signal potential for turning on transistor M10 simultaneously must be supplied from circuit 40 to all circuits 26. In such a case, it is preferable that circuit 14 has the configuration shown in FIGS. 30A and 30B.

[0208] In this configuration, when signal potential FN_B is input and the reset power supply potential RSVSS is inverted from a low potential to a high potential, a high potential can be output as signal potential GLB1. This operation is effective only when the power supply potential RSVSS is inverted from a low potential to a high potential, and a signal potential for turning on transistor M10 simultaneously can be supplied from circuit 40 to all circuits 26.

[0209] Also, selection circuit 50 is electrically connected to wiring VRW. Selection circuit 50 can supply either the aforementioned reset potential VRES or the boosting potential VW to wiring VRW.

[0210] Next, the operations of the circuit 40 and the pixel 24 shown in FIGS. 26 and 28 will be described using the timing charts shown in FIGS. 31 to 34. Note that the operations will be described separately for writing of image data to all the circuits 25 (normal light emission, mode A), writing of boosting data to all the circuits 25 (high-brightness light emission, mode B), reading of imaging data from all the circuits 26 (mode C), and reading of imaging data from a specific circuit 26 (mode D). Also, the number of rows of the pixel 24 is assumed to be 2340, and the circuit 40 is assumed to be capable of outputting a signal potential for driving the pixel 24 of that number of rows.

[0211] First, the writing of image data (normal light emission, mode A) will be described using the timing chart shown in FIG. 31. The input signals described in the timing chart are the clock signals CLK1 to CLK4, pulse width control signals PWCA1 to PWCA4, pulse width control signals PWCB1 to PWCB4, and start pulse signal SP input to the circuit 40. Note that in modes A and B, the reset power supply potential RSVSS is always at a low potential.

[0212] The output signals described in the timing chart are the signal potentials GLA1[1] to GLA1

[2340] , signal potentials GLA2[1] to GLA2

[2340] , signal potential GLA1[DUM] of the dummy stage, and signal potential GLA2[DUM] of the dummy stage output from the circuit 13 of the circuit 40.

[0213] Also, the timing chart describes the signal potentials GLB1[1] to GLB1

[2340] , signal potentials GLB2[1] to GLB2

[2340] , signal potential GLB1[DUM] of the dummy stage, and signal potential GLB2[DUM] of the dummy stage output from the circuit 14 of the circuit 40. However, at the operation timings of modes A and B, the signal potential for turning on the transistors of the circuit 26 from the circuit 14 is not output.

[0214] The operation in Mode A utilizes the first mode, which is the operation of the semiconductor device 20 described in FIG. 1. First, a start pulse signal is input, and subsequently, clock signals CLK1 to CLK4 are sequentially input. Also, pulse width control signals PWCA1 to PWCA4 and pulse width control signals PWCB1 to PWCB4 are sequentially input in parallel with the clock signals CLK1 to CLK4.

[0215] In accordance with the input signal, pulses of signal potential GLA1 and pulses of signal potential GLA2 are sequentially output from the first stage to the dummy stage with the same pulse width and the same timing. The signal potential GLA1 is supplied to the wiring G1 to turn on the transistors M4 and M6 in the circuit 25. Also, the signal potential GLA2 is supplied to the wiring G2 to turn on the transistor M5 in the circuit 25. Further, the selection circuit 50 supplies a reset potential VRES (for example, a low potential such as 0V) to the wiring VRW (see FIG. 28).

[0216] At this time, the reset potential VRES is supplied to the source of the transistor M7 in the circuit 25, and the gate (node ND) of the transistor M7 becomes the data potential supplied from the wiring S1. That is, the data potential can be written to the node ND while the source potential of the transistor M7 is in a stable state. In accordance with the data potential, the light-emitting device EL emits light.

[0217] The above is the description of Mode A.

[0218] Next, the writing of the boosted data (high-brightness light emission, Mode B) will be described using the timing chart shown in FIG. 32.

[0219] The operation of Mode B utilizes the first mode, which is the operation of the semiconductor device 20 described with reference to FIG. 1. First, a start pulse signal is input, and subsequently, clock signals CLK1 to CLK4 are sequentially input. Also, pulse width control signals PWCA1 to PWCA4 and pulse width control signals PWCB1 to PWCB4 are sequentially input in parallel with the clock signals CLK1 to CLK4. The difference from the writing of image data (normal light emission) is that the pulse width of the pulse width control signal PWCA is smaller than the pulse width of the pulse width control signal PWCB.

[0220] In accordance with the input signal, pulses of signal potential GLA1 and pulses of signal potential GLA2 start to be output at the same timing, but the pulses of signal potential GLA1 finish outputting first. Using this operation, the boosting operation described with reference to FIG. 27C can be performed. In this operation, the selection circuit 50 performs an operation of switching the potential supplied to the wiring VRW from the reset potential VRES to the potential VW (see FIG. 28).

[0221] The above is the description of the writing of boosted data (high-brightness light emission).

[0222] Next, using the timing chart shown in FIG. 33, the reading (Mode C) of imaging data from all the circuits 26 will be described. In Mode C, since imaging data is read from the circuits 26 of the pixels 24 in all rows, high-resolution imaging data can be obtained.

[0223] The operation of Mode C utilizes the first mode, which is the operation of the semiconductor device 20 described with reference to FIG. 1. The operation of Mode C performs an imaging operation using the light emission in the operation of Mode A or Mode B. Therefore, it is performed following the operation of Mode A or Mode B.

[0224] In the operation of Mode C, first, the imaging operation by circuit 26 is performed. In this operation, by inverting the reset power potential RSVSS, which was described in FIG. 30, to a high potential, a high potential is output as the signal potential GLB1 from circuit 14. By this operation, the reset operation of the charge readout section can be performed simultaneously for all circuits 26. Subsequently, after the exposure period, the charge accumulated in the light-receiving device is transferred to the charge readout section, and the potential of the charge readout section is held. This is the imaging operation up to this point.

[0225] Next, the readout operation of the potential of the charge readout section held by the imaging operation is performed. In the readout operation, first, a start pulse signal is input, and subsequently, clock signals CLK1 to CLK4 are sequentially input. Also, pulse width control signals PWCA1 to PWCA4 are sequentially input in parallel with the clock signals CLK1 to CLK4. Also, pulse width control signals PWCB1 to PWCB4 having waveforms with pulse widths smaller than that of the pulse width control signal PWCA are input with a delay with respect to the pulses of the pulse width control signals PWCA1 to PWCA4.

[0226] According to the input signal, the pulse of the signal potential GLB2 is output first, and the pulse of the signal potential GLB1 is output with a delay, and both finish outputting at the same timing. By using this operation, it is possible to read the potential of the charge readout section when data is acquired and the potential of the charge readout section when the charge readout section is reset. Using these two pieces of data, the difference can be read by the CDS circuit included in circuit 42 shown in FIG. 26. The difference is the potential obtained by subtracting the reset potential from the data potential (including the reset potential), and corresponds to the data with the noise component removed.

[0227] Next, the reading of imaging data from a specific circuit 26 (Mode D) will be described using the timing chart shown in FIG. 34. In Mode D, since imaging data is read from the circuits 26 of a specific row, imaging data can be acquired at high speed.

[0228] The operation of mode D utilizes the second mode, which is the operation of the semiconductor device 20 described with reference to FIG. 1. In the operation of mode D, first, an imaging operation by the circuit 26 is performed in the same manner as in mode C.

[0229] Next, a reading operation of the potential of the charge reading unit is performed. The input signal is the same as in mode C, and the signal potentials GLB1[1:4] and GLB2[1:4] are sequentially output, but the signal potentials GLB1[5:36] and GLB2[5:36] are not output. Also, the signal potentials GLB1[37:40] and GLB2[37:40] are sequentially output.

[0230] Therefore, the reading is sequentially performed from the circuit 26 in the first row (the circuit 26 to which the signal potentials GLB1[1] and GLB2[1] are input) to the circuit 26 in the fourth row, the circuits 26 in the fifth row to the 36th row are not read, and the circuits 26 in the 37th row to the 40th row are read.

[0231] Note that the operations of mode A, mode B, mode C, and mode D are sequentially switched without overlap. For example, operations such as switching from mode A to mode B, from mode A to mode D, from mode B to mode C, and from mode C to mode A can be performed. Here, in the display operation of mode B, since a boosting operation is involved, the number of operation steps is more than that in mode A. Also, since mode C performs a reading operation from all the pixels in a row, the number of operation steps is more than that in the reading operation from the pixels in a specific row in mode D.

[0232] Therefore, it may be operated at frame frequencies suitable for mode A, mode B, mode C, and mode D, respectively. For example, it may be operated at 60 Hz in mode A and switched to 30 Hz to perform the operation of mode B. Or, it may be operated at 30 Hz in mode B and switched to 10 Hz to perform the operation of mode C. Or, it may be operated at 60 Hz in mode A and perform the operation of mode D without changing the frame frequency.

[0233] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0234] (Embodiment 3) In this embodiment, the pixel configuration of the display device described in Embodiment 2 will be described.

[0235] FIG. 35 shows an example of a cross-section of a region including a part of circuit 40, a part of circuit 25, and a part of circuit 26 in pixel 24 of the display device shown in FIG. 26.

[0236] The display device shown in FIG. 35 has a transistor 201, a transistor 205, a transistor 206, a light-emitting device 190, a light-receiving device 110, etc. between a substrate 151 and a substrate 152.

[0237] The substrate 152 and the insulating layer 214 are adhered via an adhesive layer 142. For the encapsulation of the light-emitting device 190 and the light-receiving device 110, a solid encapsulation structure, a hollow encapsulation structure, or the like can be applied. The space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 is filled with an inert gas (such as nitrogen, argon), and a hollow encapsulation structure is applied. The adhesive layer 142 may be provided overlapping the light-emitting device 190. Also, the region surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 may be filled with a resin different from the adhesive layer 142.

[0238] The light-emitting device 190 has a stacked structure in which a pixel electrode 191, a common layer 112, a light-emitting layer 193, a common layer 114, and a common electrode 115 are stacked in this order from the insulating layer 214 side. The pixel electrode 191 is connected to a conductive layer 222b included in the transistor 206 through an opening provided in the insulating layer 214. The transistor 206 has a function of controlling the driving of the light-emitting device 190. The end of the pixel electrode 191 is covered by a partition wall 216.

[0239] The light-receiving device 110 has a stacked structure in which a pixel electrode 111, a common layer 112, a photoelectric conversion layer 113, a common layer 114, and a common electrode 115 are stacked in this order from the side of the insulating layer 214. The pixel electrode 111 is electrically connected to a conductive layer 222b included in the transistor 205 through an opening provided in the insulating layer 214. An end portion of the pixel electrode 111 is covered by a partition wall 216.

[0240] The light emitted from the light-emitting device 190 is emitted toward the substrate 152 side. Further, light enters the light-receiving device 110 through the substrate 152 and the space 143. It is preferable to use a material having high transmittance for visible light for the substrate 152.

[0241] The pixel electrode 111 and the pixel electrode 191 can be manufactured using the same material and the same process. The common layer 112, the common layer 114, and the common electrode 115 are used for both the light-receiving device 110 and the light-emitting device 190. The light-receiving device 110 and the light-emitting device 190 can have all the same configurations except that the configurations of the photoelectric conversion layer 113 and the light-emitting layer 193 are different. Thereby, the light-receiving device 110 can be incorporated into the display device without significantly increasing the manufacturing process.

[0242] A light-shielding layer 148 is provided on the surface of the substrate 152 on the substrate 151 side. The light-shielding layer 148 has openings at positions overlapping the light-receiving device 110 and at positions overlapping the light-emitting device 190. Further, an optical filter 149 such as a color filter is provided at a position overlapping the light-receiving device 110. Note that a configuration in which the optical filter 149 is not provided is also possible.

[0243] The transistor 201, the transistor 205, and the transistor 206 are all formed on the substrate 151. These transistors can be manufactured using the same material and the same process.

[0244] On the substrate 151, an insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided in this order. A part of the insulating layer 211 functions as a gate insulating layer of each transistor. A part of the insulating layer 213 functions as a gate insulating layer of each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and has a function as a planarization layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistor are not limited, and each may be a single layer or two or more layers.

[0245] It is preferable to use a material in which impurities such as water and hydrogen hardly diffuse in at least one of the insulating layers covering the transistor. Thereby, the insulating layer can function as a barrier layer. With such a configuration, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0246] As the insulating layer 211, the insulating layer 213, and the insulating layer 215, it is preferable to use an inorganic insulating film. As the inorganic insulating film, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum nitride film can be used. Note that the silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition. Alternatively, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, or a neodymium oxide film may be used. Further, two or more of the above-described insulating films may be laminated and used.

[0247] An organic insulating film is suitable for the insulating layer 214 that functions as a planarization layer. Examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene-based resin, phenol resin, and precursors of these resins.

[0248] Here, the organic insulating film often has a lower barrier property against impurities compared to the inorganic insulating film. Therefore, it is preferable that the organic insulating film has an opening near the end of the display device. Thereby, it is possible to suppress the diffusion of impurities from the end of the display device through the organic insulating film. Or, the organic insulating film may be formed such that the end of the organic insulating film is located inside the end of the display device so that the organic insulating film is not exposed at the end of the display device.

[0249] In the region 228 shown in FIG. 35, an opening is formed in the insulating layer 214. Thereby, even when an organic insulating film is used for the insulating layer 214, it is possible to suppress the diffusion of impurities from the outside to the circuit 25 or the circuit 26 through the insulating layer 214. Therefore, the reliability of the display device can be improved.

[0250] The transistor 201, the transistor 205, and the transistor 206 include a conductive layer 221 that functions as a gate, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as a source and a drain, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate. Here, the same hatching pattern is given to a plurality of layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0251] The structure of the transistor included in the display device of the present embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverse staggered transistor, or the like can be used. Also, either a top gate type or a bottom gate type transistor structure may be used. Or, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0252] For transistors 201, 205, and 206, a configuration is applied in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The transistors may be driven by connecting the two gates and supplying the same signal thereto. Alternatively, a potential for controlling the threshold voltage of the transistor may be applied to one of the two gates, and a potential for driving may be applied to the other.

[0253] The crystallinity of the semiconductor material used for the transistor is not particularly limited either, and any of an amorphous semiconductor, a single-crystalline semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystal region in part) may be used. Using a single-crystalline semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0254] The semiconductor layer of the transistor preferably has a metal oxide (also referred to as an oxide semiconductor). Alternatively, the semiconductor layer of the transistor may have silicon. Examples of silicon include amorphous silicon, crystalline silicon (such as low-temperature polysilicon, single-crystalline silicon, etc.).

[0255] The transistors included in circuit 40, the transistors included in circuit 25, and the transistors included in circuit 26 may have the same structure or different structures.

[0256] A connection portion 204 is provided in a region on substrate 151 where substrate 152 does not overlap. In connection portion 204, wiring 165 is electrically connected to FPC 172a via conductive layer 166 and connection layer 242. On the upper surface of connection portion 204, conductive layer 166 obtained by processing the same conductive film as pixel electrode 191 is exposed. Thereby, connection portion 204 and FPC 172a can be electrically connected via connection layer 242.

[0257] Various optical members can be arranged on the outside of the substrate 152. Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an antireflection layer, and a condensing film. Further, on the outside of the substrate 152, an antistatic film for suppressing the adhesion of dust, a water-repellent film for making it difficult for dirt to adhere, a hard coat film for suppressing the generation of scratches during use, a shock absorption layer, etc. may be arranged.

[0258] For the substrates 151 and 152, glass, quartz, ceramic, sapphire, resin, etc. can be used.

[0259] As the adhesive layer, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Examples of these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc. In particular, a material with low moisture permeability such as epoxy resin is preferable. Also, a two-component mixed resin may be used. Further, an adhesive sheet or the like may be used.

[0260] As the connection layer 242, an anisotropic conductive film (ACF: Anisotropic Conductive Film), an anisotropic conductive paste (ACP: Anisotropic Conductive Paste), etc. can be used.

[0261] The light-emitting device 190 includes a top emission type, a bottom emission type, a dual emission type, etc. In one aspect of the present invention, it is preferably a top emission type, but by making the light emission surface of the light-emitting device 190 and the light incident surface of the light-receiving device 110 face the same direction, other configurations can also be applied.

[0262] The light-emitting device 190 has at least a light-emitting layer 193. The light-emitting device 190 may further have, as layers other than the light-emitting layer 193, a layer containing a substance with high hole-injecting property, a substance with high hole-transporting property, a hole-blocking material, a substance with high electron-transporting property, a substance with high electron-injecting property, or a bipolar substance (a substance with high electron-transporting and hole-transporting properties), etc. For example, the common layer 112 preferably has one or both of a hole-injecting layer and a hole-transporting layer. For example, the common layer 114 preferably has one or both of an electron-transporting layer and an electron-injecting layer.

[0263] Either a low-molecular compound or a high-molecular compound can be used for the common layer 112, the light-emitting layer 193, and the common layer 114, and they may contain an inorganic compound. The layers constituting the common layer 112, the light-emitting layer 193, and the common layer 114 can be formed by methods such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, etc.

[0264] The light-emitting layer 193 may have an inorganic compound such as a quantum dot as a light-emitting material.

[0265] The photoelectric conversion layer 113 of the light-receiving device 110 contains a semiconductor. As the semiconductor, an inorganic semiconductor such as silicon or an organic semiconductor containing an organic compound can be used. In this embodiment, an example of using an organic semiconductor as the semiconductor included in the photoelectric conversion layer 113 is shown. By using an organic semiconductor, the light-emitting layer 193 of the light-emitting device 190 and the photoelectric conversion layer 113 of the light-receiving device 110 can be formed by the same method (for example, a vacuum vapor deposition method), and the manufacturing apparatus can be shared, which is preferable.

[0266] As the material of the n-type semiconductor included in the photoelectric conversion layer 113, fullerene (for example, C 60 , C 70Examples of the electron-accepting organic semiconductor material include quinones or derivatives thereof. Examples of the material of the p-type semiconductor included in the photoelectric conversion layer 113 include electron-donating organic semiconductor materials such as copper (II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), and zinc phthalocyanine (ZnPc).

[0267] For example, the photoelectric conversion layer 113 can be formed by co-evaporating an n-type semiconductor and a p-type semiconductor.

[0268] Examples of the material that can be used for conductive layers such as the gate, source, and drain of the transistor, and various wirings and electrodes constituting the display device include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys mainly composed of the metals. A film containing these materials can be used as a single-layer structure or a laminated structure.

[0269] As the conductive material having translucency, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide containing gallium, or graphene can be used. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, and alloy materials containing the metal materials can be used. Alternatively, nitrides of the metal materials (for example, titanium nitride) may be used. When using metal materials, alloy materials (or their nitrides), it is preferable to make them thin enough to have translucency. In addition, a laminated film of the above materials can be used as the conductive layer. For example, using a laminated film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting the display device, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of the display elements.

[0270] Examples of the insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0271] The display device of the present embodiment has a light-receiving device and a light-emitting device in the display unit, and the display unit has both a function of displaying an image and a function of detecting light. Thereby, compared with the case where a sensor is provided outside the display unit or outside the display device, miniaturization and weight reduction of the electronic device can be achieved. In addition, in combination with a sensor provided outside the display unit or outside the display device, a more multifunctional electronic device can also be realized.

[0272] The light-receiving device can have at least one layer other than the photoelectric conversion layer with the same configuration as that of the light-emitting device (EL element). Further, the light-receiving device may have all layers other than the photoelectric conversion layer with the same configuration as that of the light-emitting device (EL element). For example, by simply adding a step of forming a photoelectric conversion layer to the manufacturing process of the light-emitting device, the light-emitting device and the light-receiving device can be formed on the same substrate. Also, the pixel electrode and the common electrode of the light-receiving device and the light-emitting device can be formed of the same material and in the same process. Further, by manufacturing the circuit electrically connected to the light-receiving device and the circuit electrically connected to the light-emitting device of the same material and in the same process, the manufacturing process of the display device can be simplified. Thus, a display device with a built-in light-receiving device and high convenience can be manufactured without complicated processes.

[0273] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0274] (Embodiment 4) In this embodiment, examples of electronic devices to which the display device according to one aspect of the present invention can be applied will be described.

[0275] An electronic device 6500 shown in FIG. 36A is a portable information terminal that can be used as a smartphone.

[0276] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0277] The display device according to one aspect of the present invention can be applied to the display unit 6502.

[0278] FIG. 36B is a schematic cross-sectional view including an end portion on the microphone 6506 side of the housing 6501.

[0279] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0280] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0281] Also, in a region outside the display unit 6502, a part of the display panel 6511 is folded back. An FPC 6515 is connected to the folded-back portion. An IC 6516 is mounted on the FPC 6515. Also, the FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0282] The display panel 6511 can be applied with the display device according to one aspect of the present invention. By using the narrow bezel display device according to one aspect of the present invention, a small and lightweight electronic device can be realized.

[0283] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0284] (Embodiment 5) In this embodiment, an electronic device including the display device according to one aspect of the present invention will be described.

[0285] The electronic device exemplified below includes the display device according to one aspect of the present invention in the display unit. Therefore, it is an electronic device with a high resolution realized. Also, it can be an electronic device that achieves both a high resolution and a large screen.

[0286] In the display unit of the electronic device according to one aspect of the present invention, for example, a video having a resolution of full high vision, 4K2K, 8K4K, 16K8K, or higher can be displayed.

[0287] Examples of electronic devices include, in addition to electronic devices with relatively large screens such as television sets, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, and the like.

[0288] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of a house, the inner or outer wall of a building, the interior or exterior of an automobile, or the like.

[0289] The electronic device shown in FIGS. 37A to 37G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, and the like.

[0290] The electronic device shown in FIGS. 37A to 37G has various functions. For example, it can have a function of displaying various information (such as still images, moving images, and text images) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. Further, the electronic device may be provided with a camera or the like and have a function of taking a still image or a moving image and storing it in a recording medium (external or built into the camera), a function of displaying the taken image on the display unit, and the like.

[0291] Details of the electronic device shown in FIGS. 37A to 37G will be described below.

[0292] FIG. 37A is a perspective view showing a television apparatus 9100. The television apparatus 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0293] FIG. 37B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as, for example, a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Further, the portable information terminal 9101 can display character and image information on a plurality of its surfaces. FIG. 37B shows an example in which three icons 9050 are displayed. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming calls such as e-mail, SNS, and telephone, titles such as e-mail or SNS, sender names, dates and times, battery remaining amounts, antenna reception strengths, etc. Alternatively, an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0294] FIG. 37C is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different surfaces. For example, the user can also confirm the information 9053 displayed at a position that can be observed from above the portable information terminal 9102 in a state where the portable information terminal 9102 is stored in the breast pocket of the clothes. The user can check the display without taking the portable information terminal 9102 out of the pocket and can determine, for example, whether to answer a call.

[0295] FIG. 37D is a perspective view showing a wristwatch-type portable information terminal 9200. Also, the display unit 9001 is provided with a curved display surface, and can perform display along the curved display surface. Further, the portable information terminal 9200 can also make a hands-free call by mutually communicating with, for example, a wirelessly communicable headset. Further, the portable information terminal 9200 can also perform data transmission and charging mutually with other information terminals via the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0296] FIGS. 37E, 37F, and 37G are perspective views showing a foldable portable information terminal 9201. Also, FIG. 37E shows the portable information terminal 9201 in an unfolded state, FIG. 37G shows the folded state, and FIG. 37F is a perspective view of a state in the process of changing from one of FIGS. 37E and 37G to the other. The portable information terminal 9201 has excellent portability in the folded state, and excellent display comprehensibility due to a seamless wide display area in the unfolded state. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0297] FIG. 38A shows an example of a television apparatus. In the television apparatus 7100, a display unit 7500 is incorporated in a housing 7101. Here, a configuration in which the housing 7101 is supported by a stand 7103 is shown.

[0298] The operation of the television apparatus 7100 shown in FIG. 38A can be performed by an operation switch provided in the housing 7101 or a separate remote control operation unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television apparatus 7100 may be operated by touching this. The remote control operation unit 7111 may have a display unit in addition to operation buttons.

[0299] Note that the television apparatus 7100 may have a television broadcast receiver or a communication device for network connection.

[0300] Figure 38B shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated in the housing 7211.

[0301] Figures 38C and 38D show an example of digital signage.

[0302] The digital signage 7300 shown in Figure 38C has a housing 7301, a display unit 7500, a speaker 7303, etc. Further, it can have an LED lamp, operation keys (including a power switch or operation switches), connection terminals, various sensors, a microphone, etc.

[0303] Also, Figure 38D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0304] The larger the display unit 7500, the more information can be provided at once, and it is also easier to catch people's eyes. For example, it has the effect of enhancing the advertising effect.

[0305] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. Thereby, it can be used not only for advertising purposes but also for purposes of providing information required by the user, such as route information, traffic information, and guidance information of commercial facilities.

[0306] Also, as shown in Figures 38C and 38D, it is preferable that the digital signage 7300 or the digital signage 7400 can communicate wirelessly with an information terminal device 7311 such as a smartphone held by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal device 7311, or the display of the display unit 7500 can be switched by operating the information terminal device 7311.

[0307] Also, a game can be executed on the digital signage 7300 or the digital signage 7400, with the information terminal 7311 as the operation means (controller). As a result, an unspecified number of users can participate in and enjoy the game simultaneously.

[0308] The display device according to one aspect of the present invention can be applied to the display unit 7500 in FIGS. 38A to 38D.

[0309] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Explanation of Reference Numerals

[0310] C1: Capacitor, C2: Capacitor, C3: Capacitor, C4: Capacitor, EL: Light-emitting device, G1: Wiring, G2: Wiring, G4: Wiring, G5: Wiring, G6: Wiring, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M5: Transistor, M6: Transistor, M7: Transistor, M9: Transistor, M10: Transistor, M11: Transistor, M12: Transistor, PD: Light-receiving device, PIX1: Pixel circuit, PIX2: Pixel circuit, PIX3: Pixel circuit, S1: Wiring, V0: Wiring, V1: Wiring, V2: Wiring, V3: Wiring, V4: Wiring, VRW: Wiring, 10: Flip-flop circuit, 11: Output circuit, 12: Switch circuit, 13: Circuit, 14: Circuit, 15: Switch circuit, 16: Switch circuit, 17: Switch circuit, 18: Switch circuit, 19: Switch circuit, 20: Semiconductor device, 20a: Semiconductor device, 20b: Semiconductor device, 20c: Semiconductor device, 20d: Semiconductor device, 21: Load driver, 22: Load driver, 23: Pixel array, 24: Pixel, 25: Circuit, 26: Circuit, 31: Block, 32: Block, 33: Block, 40: Circuit, 41: Circuit, 42: Circuit, 50: Selection circuit, 110: Light-receiving device, 111: Pixel electrode, 112: Common layer, 113: Photoelectric conversion layer, 114: Common layer, 115: Common electrode, 142: Adhesive layer, 143: Space, 148: Light-shielding layer, 149: Optical filter, 151: Substrate, 152: Substrate, 165: Wiring, 166: Conductive layer, 172a: FPC, 190: Light-emitting device, 191: Pixel electrode, 193: Light-emitting layer, 201: Transistor, 204: Connection part, 205: Transistor, 206: Transistor, 211: Insulating layer, 213: Insulating layer, 214: Insulating layer, 215: Insulating layer, 216: Partition wall, 221: Conductive layer, 222a: Conductive layer, 222b: Conductive layer, 223: Conductive layer, 228: Region, 231: Semiconductor layer, 242: Connection layer, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7100: Television device, 7101: Housing,7103: Stand, 7111: Remote control unit, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal device, 7400: Digital signage, 7401: Column, 7500: Display unit, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television device, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

1. A first block, a second block, and a third block, each of the first block to the third block includes a plurality of flip-flop circuits and a plurality of output circuits; the flip-flop circuits are electrically connected to the output circuits in pairs, In each of the first block to the third block, the plurality of flip-flop circuits are cascade-connected; a last-stage flip-flop circuit of the first block is electrically connected to a first-stage flip-flop circuit of the second block via a first switch; a last-stage flip-flop circuit of the first block is electrically connected to a first-stage flip-flop circuit of the third block via a second switch; The semiconductor device, wherein the last-stage flip-flop circuit of the second block is electrically connected to the first-stage flip-flop circuit of the third block via a third switch.

2. A semiconductor device comprising: the semiconductor device according to claim 1; and a pixel; the pixel comprises a first circuit having a display element; The display device, wherein the output circuit is electrically connected to the first circuit.

Images