Semiconductor device and method of manufacturing the same

Abstract

To improve reliability of a semiconductor device.SOLUTION: A resistance element Rg and a trench TR form a closed path in plan view. A semiconductor device includes: first and second contact members CM1, CM2 each electrically connecting a gate pad GP and the resistance element Rg; third and fourth contact members CM3, CM4 each electrically connecting gate wiring GW and the resistance element Rg; and fifth to eighth contact members CM5 to CM8 each electrically connecting a first conductive member CE1 and the resistance element Rg. A current path passing from the gate pad GP to the gate wiring GW through the first conductive member CE1 is made of the plurality of contact members CM1 to CM8 and the resistance element Rg. The first conductive member CE1 forms, together with the fifth to eighth contact members CM5 to CM8, a bypass path for reducing the current that flows through some sections of the closed path made of the resistance element Rg.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a resistance element for electrically connecting a gate pad and a gate wiring, and a method for manufacturing the same.

Background Art

[0002] In an IGBT (Insulated Gate Bipolar Transistor) or the like, by interposing a resistance element between a gate wiring connected to a gate electrode and a gate pad, the switching speed of the IGBT or the like can be adjusted or limited, or oscillation when a plurality of IGBTs are connected in parallel can be prevented.

[0003] Patent Document 1 describes an IGBT including a built-in resistance element connected in series between a gate pad and a trench gate electrode. The built-in resistance element is formed via an insulating film directly above a P-type semiconductor region and is electrically connected to the gate electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As the layout of the resistance element, various layouts can be adopted. For example, by adopting a layout in which a (loop-shaped) trench structure having a loop shape in plan view is interposed between the gate pad and the gate wiring, the switching speed can be adjusted or limited, or oscillation when a plurality of IGBTs are connected in parallel can be prevented. In one example, a resistance element is formed by forming a trench and embedding polysilicon in the trench. However, mainly from the viewpoint of the embeddability of polysilicon, the trench may be formed such that the trench width in plan view becomes narrower at the folded-back portion of the loop shape.

[0006] In this case, particularly in the portion where the trench width is narrow, due to electromigration caused by the continuous flow of current, the risk of the resistance element breaking is relatively large. In other words, in the portion where the trench width is narrow, the electromigration resistance is low. Therefore, from the viewpoint of the requirement for miniaturization of the device structure or the embeddability of polysilicon into the trench, when adopting a resistance element having a trench structure with a narrow portion, it is required to suppress the influence of electromigration by reducing the current flowing through the narrow portion.

[0007] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0008] Among the embodiments disclosed in the present application, the outline of representative ones will be briefly described as follows.

[0009] In a semiconductor device according to an embodiment, a resistor element that electrically connects a gate pad and a gate wiring, and a trench that houses the resistor element form a closed path in a plan view. First and second contact members that electrically connect the gate pad and the resistor element, third and fourth contact members that electrically connect the gate wiring and the resistor element, and fifth to eighth contact members that electrically connect a first conductive member and the resistor element are provided, and a current path from the gate pad to the gate wiring via the first conductive member is formed by a plurality of contact members and the resistor element. The first conductive member, together with the fifth to eighth contact members, forms a detour path for reducing a current flowing through a part of an area in a closed path formed by the resistor element.

[0010] A method of manufacturing a semiconductor device according to an embodiment includes a step of forming a well region on a first main surface of a semiconductor substrate, a step of forming a trench that forms a closed path in a plan view in the well region, a step of forming an insulating film inside the trench, a step of forming a resistor element inside the trench via the insulating film, a step of forming an interlayer insulating film on the first main surface, a step of forming first to eighth contact members that penetrate the interlayer insulating film and reach the resistor element, and a step of forming a gate pad, a gate wiring, and a first conductive member on the interlayer insulating film. The first and second contact members electrically connect the gate pad and the resistor element, respectively, the third and fourth contact members electrically connect the gate wiring and the resistor element, respectively, and the fifth to eighth contact members electrically connect the first conductive member and the resistor element, respectively. The first conductive member, together with the fifth to eighth contact members, forms a detour path for reducing a current flowing through a part of an area in a closed path formed by the resistor element.

Advantages of the Invention

[0011] According to an embodiment, the reliability of the semiconductor device can be improved.

Brief Description of the Drawings

[0012]

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DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary. Also, in FIGS. 3 to 5, FIGS. 10 to 19, there are some places where the vertical relationship of each element is not accurately represented in order to facilitate the understanding of the shape of each element. The vertical relationship of each element is as shown in FIGS. 6 to 9, FIGS. 20 to 35 which are cross-sectional views.

[0014] (Embodiment 1) <Structure of Semiconductor Device> FIG. 1 is a plan view showing a semiconductor device 100 configured as a semiconductor chip. The semiconductor device 100 includes a cell region 1A including cells configured as IGBTs, and a peripheral region 1B located around the cell region 1A and including gate wiring and the like. The cell region 1A includes a plurality of IGBT cells. In the example of FIG. 1, the cell region 1A is divided into three sub-regions along the Y direction (at the boundaries between the sub-regions, the gate wiring GW extends in the X direction orthogonal to the Y direction), and the three sub-regions are covered by the emitter electrode EE.

[0015] The peripheral region 1B includes a gate pad GP for applying a voltage to the gate electrode GE1, a gate wiring GW for electrically connecting the gate pad GP and the gate electrode GE1, and a resistor element region RGA. Although the detailed shapes of the gate pad GP, the gate wiring GW, and the resistor element region RGA are omitted in FIG. 1, as shown in FIG. 3 and the like described later, the gate pad GP and the gate wiring GW are electrically connected via a resistor element Rg formed in the resistor element region RGA, and the gate wiring GW is electrically connected to the gate electrode GE1 of the IGBT via a contact member (plug) PG formed in a contact hole CH3 described later (see the cross-sectional view taken along line B-B in FIG. 7).

[0016] Note that the emitter electrode EE, the gate pad GP, the gate wiring GW, and the resistor element region RGA are covered with a protective film such as a polyimide film. However, an opening OPE and an opening OPG are formed in the protective film covering the emitter electrode EE and the protective film covering the gate pad GP, respectively. External connection terminals are connected to the portion of the emitter electrode EE exposed from the opening OPE and the portion of the gate pad GP exposed from the opening OPG, respectively. Through the external connection terminals, the semiconductor device 100 is electrically connected to a lead frame, another semiconductor chip, a wiring board, or the like. The external connection terminals are, for example, bonding wires made of gold, copper, or aluminum, or clips made of copper plates.

[0017] Also, on the first main surface SUBa of the semiconductor substrate SUB, a plurality of annular field plates are formed so as to surround the outer shape of the gate wiring GW. The innermost field plate among the field plates is integrated with the end portion of the emitter electrode EE on the side opposite to the gate pad GP side and is separated from the gate wiring GW without overlapping each other.

[0018] FIG. 2 shows a conceptual equivalent circuit diagram of the semiconductor device 100. The IGBT includes a gate electrode GE1, a collector region PC, and an emitter region NE. A collector electrode CE is electrically connected to the collector region PC, and an emitter electrode EE is electrically connected to the emitter region NE. As described above, the gate pad GP and the gate electrode GE1 are electrically connected via a resistor element. More specifically, as shown in FIG. 2, first, the gate pad GP and a first conductive member CE1 (see FIG. 3 described later. In one example, it is a flat conductive pad.) are electrically connected via a resistor element portion Rg1, and then the first conductive member CE1 and the gate electrode GE1 are electrically connected via a resistor element portion Rg2. In the example of FIG. 3, the portion between the first contact member CM1 and the fifth contact member CM5 in the first extending portion P1, and the portion between the second contact member CM2 and the eighth contact member CM8 in the second extending portion P2 correspond to the resistor element portion Rg1, and the portion between the third contact member CM3 and the sixth contact member CM6 in the third extending portion P3, and the portion between the fourth contact member CM4 and the seventh contact member CM7 in the fourth extending portion P4 correspond to the resistor element portion Rg2.

[0019] <Structure of IGBT> FIGS. 3 to 5 are principal part plan views near the resistor element region RGA in the semiconductor device 100. FIG. 6 is a cross-sectional view taken along line A-A in FIG. 3. FIG. 7 is a cross-sectional view taken along line B-B in FIG. 3.

[0020] As shown in FIG. 6, the cell region 1A of the semiconductor device 100 includes an active cell AC for performing the main operation of the IGBT and an inactive cell IAC other than the active cell AC. The IGBT shown in FIG. 6 is an IE-type IGBT that utilizes the IE (Injection Enhancement) effect of increasing the concentration of charges accumulated in the drift region NV by making it difficult for holes to be discharged from the emitter electrode EE side when the IGBT is in the on state. The gate electrode GE1 of the active cell AC is electrically connected to the gate wiring GW through the contact member PG filled in the contact hole CH3 (FIGS. 3 and 7), and the gate potential is supplied during the operation of the IGBT. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE through the contact member PG filled in the contact hole CH2 (FIGS. 3 and 6), and the emitter potential is supplied during the operation of the IGBT.

[0021] As shown in FIG. 3, in the cell region 1A, the trench TR (inside the active cell AC) in which the gate electrode GE1 is formed and the trench TR (inside the inactive cell IAC) in which the gate electrode GE2 is formed are alternately formed along the X direction while extending in the Y direction. The trench TR formed in the active cell AC and the gate electrode GE1 formed therein constitute a gate trench. The trench TR formed in the inactive cell IAC and the gate electrode GE2 formed therein constitute an emitter trench. A contact hole CH1 is formed in the active cell AC, and the contact hole CH1 is filled with a contact member PG. A contact hole CH2 is formed in the inactive cell IAC, and the contact hole CH2 is filled with a contact member PG. The contact member PG in the contact hole CH1 and the contact member PG in the contact hole CH2 are both electrically connected to the emitter electrode EE (FIG. 6). Further, an emitter region NE is formed in the active cell AC.

[0022] As shown in FIG. 6, the semiconductor device 100 includes an n-type semiconductor substrate SUB having a first main surface (upper surface) SUBa and a second main surface (lower surface) SUBb. The semiconductor substrate SUB is made of n-type silicon and has a low-concentration n-type semiconductor layer (drift region) NV. On the second main surface SUBb side of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS having an impurity concentration higher than that of the drift region NV, a p-type collector region (impurity region) PC, and a collector electrode CE made of a metal film are formed. The field stop region NS is provided to suppress the depletion layer extending from the pn junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off. During the operation of the IGBT, a collector potential is supplied to the collector region PC via the collector electrode CE. The collector electrode CE is a single-layer metal film such as an Au film, a Ni film, a Ti film, or an AlSi film, or a laminated metal film in which these are laminated as appropriate.

[0023] On the first main surface SUBa side of the semiconductor substrate SUB, a trench TR is formed in the semiconductor substrate SUB. The trench TR penetrates the emitter region NE and / or the base region PB and reaches the inside of the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 μm or more and 5 μm or less. A gate insulating film GI is formed inside the trench TR. The gate electrodes GE1 and GE2 are formed on the gate insulating film GI so as to fill the inside of the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE1 and GE2 are, for example, polycrystalline silicon films (polysilicon films) into which n-type impurities are introduced. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0024] In the active cell AC, a hole barrier region (impurity region) NHB having an impurity concentration higher than that of the drift region NV is formed in the semiconductor substrate SUB between a pair of gate electrodes GE1. A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE having an impurity concentration higher than that of the drift region NV is formed in the p-type base region PB. The base region PB is formed to be shallower than the depth of the trench TR, and the emitter region NE is formed to be shallower than the depth of the base region PB. The base region PB located below the emitter region NE is used as a channel region.

[0025] In the inactive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between a pair of gate electrodes GE2. Also, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the gate electrode GE1 and the gate electrode GE2. A p-type base region PB having an impurity concentration higher than that of the floating region PF is formed in the hole barrier region NHB and in the floating region PF. The floating region PF is preferably formed to a position deeper than the bottom of the trench TR in order to enhance the high breakdown voltage characteristics, and more preferably formed to cover the bottom of the trench TR. Also, in the inactive cell IAC, a floating region PF is formed in the semiconductor substrate SUB of the cell region 1A other than between a pair of trenches TR. The floating region PF and the base region PB formed in the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE and are in an electrically floating state.

[0026] On the first main surface SUBa of the semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600 nm or more and 1500 nm or less. Further, the interlayer insulating film IL is subjected to a planarization process for planarizing the upper surface of the interlayer insulating film IL. In the active cell AC, the contact hole CH1 penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH1 is formed so as to be in contact with the emitter region NE and the base region PB. A contact member PG is embedded inside the contact hole CH1, and the contact member PG is electrically connected to the emitter region NE and the base region PB. In the inactive cell IAC, the contact hole CH2 penetrates the interlayer insulating film IL and reaches the inside of the base region PB. Further, the contact hole CH2 is formed so as to overlap the gate electrode GE2 in a plan view. A contact member PG is embedded inside the contact hole CH2, and the contact member PG is electrically connected to the gate electrode GE2 and the base region PB. The contact member PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0027] Around the bottoms of the contact holes CH1 and CH2, a p-type high-concentration diffusion region (impurity region) PR having an impurity concentration higher than that of the base region PB is formed. The high-concentration diffusion region PR is provided to reduce the contact resistance with the contact member PG and to prevent latch-up.

[0028] On the interlayer insulating film IL, an emitter electrode EE is formed. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, and the high-concentration diffusion region PR via a contact member PG, and supplies an emitter potential to these regions. Although not shown in FIG. 6, on the interlayer insulating film IL, a gate pad GP (including a gate pad wiring GPW), a gate wiring GW, and a first conductive member CE1, which are formed in the same process as the emitter electrode EE, are also formed (FIGS. 3, 7 to 9).

[0029] Such an emitter electrode EE, gate pad GP, gate wiring GW, and first conductive member CE1 include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film added with copper or silicon. The aluminum alloy film is the main conductor film of the emitter electrode EE and the gate wiring GW, and is sufficiently thicker than the TiW film.

[0030] Also, as shown in FIG. 3, a pair of gate electrodes GE1 are connected to each other and are electrically connected to the gate wiring GW via a contact member PG formed in a contact hole CH3 in the peripheral region 1B. As shown in FIG. 7, in the peripheral region 1B, a well region PW, which is a p-type semiconductor region, is provided. The gate electrode GE1 formed in a trench TR provided in the well region PW is electrically connected to the gate wiring GW via a contact member PG formed in a contact hole CH3. Since the well region PW is formed in the same process as the floating region PF of the cell region 1A, it has the same depth as the floating region PF. However, in plan view, the well region and the floating region PF are physically separated.

[0031] <Resistance element and its surrounding structure> FIGS. 4 and 5 are plan views of the resistance element region RGA region shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line C-C of FIG. 4. FIG. 9 is a cross-sectional view taken along line D-D of FIG. 4.

[0032] As shown in FIG. 1, in the semiconductor device 100, in the Y direction, two resistor element regions RGA are formed so as to sandwich the gate pad GP. FIGS. 3 and 4 show the structure of the resistor element region RGA located below the gate pad GP. The structure of the resistor element region RGA located above the gate pad GP has the same structure as that in FIGS. 3 and 4, and the two resistor element regions RGA are in a line-symmetric relationship with respect to the X axis passing through the center of the gate pad GP in the Y direction.

[0033] As shown in FIG. 3, the semiconductor device 100 includes, in the X direction, the aforementioned cell region 1A and a peripheral region 1B adjacent to the cell region 1A. The peripheral region 1B is formed within the well region PW in a plan view.

[0034] As shown in FIG. 3, the peripheral region 1B has a gate pad GP and a resistor element region RGA disposed below (negative direction of Y) the gate pad GP. The gate pad GP has a quadrangle (such as a square or a rectangle) in a plan view and has an opening OPG in its central portion.

[0035] A gate pad wiring GPW (which is a part of the gate pad GP) is connected to the gate pad GP, and the gate pad wiring GPW extends to the resistor element region RGA. The gate pad wiring GPW is a wiring extending from the gate pad GP, and the wiring width of the gate pad wiring GPW is smaller than the length of the side of the gate pad GP (for example, the side from which the gate pad wiring GPW protrudes). The gate wiring GW is disposed around the gate pad GP and the resistor element region RGA and extends to the resistor element region RGA.

[0036] The resistive element region RGA is formed within the well region PW in a plan view. A resistive element Rg exists in the resistive element region RGA. In the positive Z direction as viewed from the resistive element Rg, there are a gate pad wiring GPW, a gate wiring GW (connected to a gate inspection pad GIP), and a first conductive member CE1. Also, a part of the emitter electrode EE extends into the gaps between the respective elements of the gate pad GP, the gate wiring GW, and the first conductive member CE1 within the resistive element region RGA. As already described, the plan view such as FIG. 3 does not accurately represent the vertical positional relationship of each element. Refer to the cross-sectional views of FIGS. 8 and 9 for the vertical positional relationship of each element within the resistive element region RGA. The resistive element Rg, the gate pad GP (gate pad wiring GPW), the gate wiring GW, and the first conductive member CE1 are electrically connected to each other by a contact member PG formed within the contact hole CH3.

[0037] The resistance element Rg shown in FIG. 3 is an integrated resistance element formed via an insulating film inside a trench that forms a closed path (has an endless loop shape) in plan view. For convenience, it will be described separately as the first to seventh extending portions P1 to P7 and the first connection portion CP1 as shown in FIG. 4. The first and second extending portions P1 and P2 extend in the Y direction and are arranged spaced apart from each other in the X direction. The first connection portion CP1 electrically connects one end of the first extending portion P1 and one end of the second extending portion P2. The third and fourth extending portions P3 and P4 extend in the Y direction, are spaced apart from each other in the X direction, and are arranged between the first and second extending portions in plan view. The fifth extending portion P5 extends in the X direction and electrically connects one end of the third extending portion P3 and one end of the fourth extending portion P4. The sixth extending portion P6 extends in the X direction and electrically connects the other end of the first extending portion P1 and the other end of the third extending portion P3. The seventh extending portion P7 extends in the X direction and electrically connects the other end of the second extending portion P2 and the other end of the fourth extending portion P4. Since the other end of the first extending portion P1 and the other end of the second extending portion P2 are electrically connected by the third to seventh extending portions P3 to P7, the third to seventh extending portions P3 to P7 may be collectively referred to as the second connection portion CP2. As already described, mainly from the perspective of the embedding property of polysilicon, the trench may be formed such that the trench width in plan view becomes narrow at the folded portion of the loop shape. In Embodiment 1, the width (width in the X direction in plan view) of the first to fourth extending portions P1 to P4 extending in the Y direction is 0.8 μm (micrometer), and the width (width in the Y direction in plan view) of the fifth to seventh extending portions P5 to P7 extending in the X direction and the first connection portion CP1 is 0.4 μm (micrometer).

[0038] As shown in FIG. 5, the resistance element Rg formed inside the trench is electrically connected to the first contact member CM1 to the eighth contact member CM8. As shown in FIGS. 3 to 5, the first and second contact members CM1, CM2 electrically connect the gate pad GP to the first and second extending portions P1, P2, and the third and fourth contact members CM3, CM4 electrically connect the gate wiring GW to the third and fourth extending portions P3, P4, respectively. The fifth contact member CM5 electrically connects the first conductive member CE1 to the first extending portion P1, the sixth contact member CM6 electrically connects the first conductive member CE1 to the third extending portion P3, the seventh contact member CM7 electrically connects the first conductive member CE1 to the fourth extending portion P4, and the eighth contact member CM8 electrically connects the first conductive member CE1 to the second extending portion P2. As shown in FIGS. 8 and 9, each contact member electrically connects either the gate pad GP, the gate wiring GW, or the first conductive member CE1 formed on the interlayer insulating film IL to the resistance element Rg formed in the p-type well region PW through the interlayer insulating film IL.

[0039] <Features of Embodiment 1> By providing the resistance element Rg having the configuration shown in FIGS. 3 to 5, FIGS. 8, and 9, the resistance to electromigration of the resistance element Rg can be improved. Specifically, when the first conductive member CE1 and the fifth to eighth contact members CM5 to CM8 are not provided, at least a part of the current flowing through the narrow sixth and seventh extending portions P6, P7 is diverted to flow through the first conductive member CE1, thereby reducing the current flowing through the sixth and seventh extending portions P6, P7 and reducing the influence of electromigration in the sixth and seventh extending portions P6, P7. Hereinafter, the current path when current flows from the gate pad GP to the gate wiring GW will be described in detail.

[0040] First, the current path when the first conductive member CE1 and the fifth to eighth contact members CM5 to CM8 are not provided in the resistor element region RGA shown in FIG. 3 and the like will be described. The current from the gate pad GP flows through the contact member CM1 to the first extending portion P1 of the resistor element Rg, and reaches the gate wiring GW through the sixth extending portion P6, the third extending portion P3, and the third contact member CM3. In parallel with this, the current from the gate pad GP flows through the contact member CM2 to the second extending portion P2 of the resistor element Rg, and reaches the gate wiring GW through the seventh extending portion P7, the fourth extending portion P4, and the fourth contact member CM4. Since both paths pass through the narrow sixth or seventh extending portion and there is no detour path for detouring the current flowing through the sixth and seventh extending portions P6 and P7, the resistor element Rg may deteriorate over time particularly due to the influence of electromigration in the narrow sixth and seventh extending portions P6 and P7.

[0041] Next, as shown in FIG. 3 and the like, as Embodiment 1, the current path in the case where the first conductive member CE1 and the fifth to eighth contact members CM5 to CM8 are provided in the resistor element region RGA will be described. The current from the gate pad GP flows through the first contact member CM1 to the first extending portion P1 of the resistor Rg, and from the first extending portion P1, it flows into the first conductive member CE1 through the fifth contact member CM5 and then into the third extending portion through the sixth contact member CM6. The current from the first extending portion P1 branches into a current that flows into the third extending portion through the sixth extending portion P6. That is, when the first conductive member CE1 and the fifth to eighth contact members CM5 to CM8 are not provided, at least a part of the current that was flowing to the sixth extending portion P6 detours to the first conductive member CE1. In parallel with this, the current from the gate pad GP flows through the contact member CM2 to the second extending portion P2 of the resistor Rg, and from the second extending portion P2, it flows into the first conductive member CE1 through the eighth contact member CM8 and then into the fourth extending portion through the seventh contact member CM7. The current from the second extending portion P2 branches into a current that flows into the fourth extending portion through the seventh extending portion P7. That is, when the first conductive member CE1 and the fifth to eighth contact members CM5 to CM8 are not provided, at least a part of the current that was flowing to the seventh extending portion P7 detours to the first conductive member CE1. The current flowing into the third extending portion P3 and the current flowing into the fourth extending portion P4 each reach the gate wiring GW through the third contact member CM3 and the fourth contact member CM4. As described above, by using the resistor Rg, the first to eighth contact members CM1 to CM8, and the first conductive member CE1 of Embodiment 1, at least a part of the current flowing into the narrow sixth and seventh extending portions P6 and P7 can be detoured. Thereby, the resistance of the resistor Rg to electromigration can be improved.In a preferred embodiment, by adjusting the distances D1 (see FIG. 5) between the fifth to eighth contact members CM5 to CM8 and the sixth and seventh extending portions P6 and P7 such that the ratio of the electrical resistance values of the detour path and the non-detour path becomes 1:1, the magnitude of the current flowing into the narrow sixth and seventh extending portions P6 and P7 can be made half of the magnitude of the current flowing into the sixth and seventh extending portions P6 and P7 when there is no detour path.

[0042] In the configuration of Embodiment 1, the ratio of the magnitude of the current flowing through the detour path that reaches the third extending portion P3 from the first extending portion P1 through the fifth contact member CM5, the first conductive member CE1, and the sixth contact member CM6, and the current flowing through the non-detour path that reaches the third extending portion P3 from the first extending portion P1 through the sixth extending portion P6 is related to the ratio of the electrical resistances of the two paths. Similarly, the ratio of the magnitude of the current flowing through the detour path that reaches the fourth extending portion P4 from the second extending portion P2 through the eighth contact member CM8, the first conductive member CE1, and the seventh contact member CM7, and the current flowing through the non-detour path that reaches the fourth extending portion P4 from the second extending portion P2 through the seventh extending portion P7 is related to the ratio of the electrical resistances of the two paths. That is, if the path length of the non-detour path is extremely short and the electrical resistance of the non-detour path is very small compared to the electrical resistance of the detour path, most of the current will flow through the non-detour path, and the effect of improving electromigration resistance cannot be sufficiently obtained. As one aspect of adjusting the path length of the non-detour path, by adjusting the above-described distance D1 shown in FIG. 5, that is, the distance D1 from the fifth to eighth contact members CM5 to CM8 to the sixth and seventh extending portions P6, P7 to be equal to or greater than a predetermined distance, the electrical resistance of the non-detour path can be adjusted to be equal to or greater than a predetermined value to adjust the current flowing into the detour path. Further, if the length of the first to eighth contact members CM1 to CM8 in the Y direction is extremely short, the current density in the first to eighth contact members CM1 to CM8 increases, and the influence of electromigration in the first to eighth contact members CM1 to CM8 becomes large. On the other hand, since the current flowing through the first to eighth contact members CM1 to CM8 concentrates on the central side end portions in the loop shape of the trench TR in which the resistance element Rg is present, if the length of the first to eighth contact members CM1 to CM8 in the Y direction is configured to be extremely long, the region where no current flows in the first to eighth contact members CM1 to CM8 becomes large and the first to eighth contact members CM1 to CM8 cannot be efficiently utilized. In view of the above, it is preferable to configure the length of the first to eighth contact members CM1 to CM8 in the Y direction within a predetermined range.In one example, the length of the first to eighth contact members CM1 to CM8 in the Y direction can be 20 μm (micrometers).

[0043] <Modification Example of Embodiment 1> FIG. 10 is a partial plan view showing a modification example of the semiconductor device in Embodiment 1. The resistance elements Rg and the first to eighth contact members CM1 to CM8 described with reference to FIG. 3 and the like are formed in two sets spaced apart in the X direction. The configuration of each of the two sets is the same as the configuration described so far as Embodiment 1. The configuration of FIG. 10 corresponds to a configuration in which two sets of current paths from the gate pad GP to the gate wiring GW described with reference to FIG. 3 and the like are provided in parallel. By reducing the current flowing into the narrow sixth and seventh extending portions P6 and P7 in each of the two sets of resistance elements RgA and RgB, based on the same principle as the principle described with reference to FIG. 3 and the like, the resistance to electromigration in each of the two sets of resistance elements Rg can be improved. Note that the sets of the resistance element Rg and the first to eighth contact members CM1 to CM8 may be formed in any number of three or more. That is, a plurality of sets of the resistance element Rg formed via the insulating film GI in the trench TR and the first to eighth contact members CM1 to CM8 are formed, and each set is arranged to be spaced apart from each other in the X direction in a plan view. The gate pad wiring GPW included in the gate pad GP is formed to overlap the first and second contact members CM1 and CM2 in each of the plurality of sets in a plan view, the gate wiring GW is arranged to overlap the third and fourth contact members CM3 and CM4 in each of the plurality of sets in a plan view, and the first conductive member CE1 is arranged to overlap the fifth to eighth contact members CM5 to CM8 in each of the plurality of sets in a plan view.

[0044] (Embodiment 2) FIG. 11 and FIG. 12 are principal part plan views showing the semiconductor device 100 in Embodiment 2. In Embodiment 2, the shape of the resistance element Rg is different from that in Embodiment 1, and the arrangement and number of the contact members CM are also different from those in Embodiment 1. Further, in Embodiment 2, a second conductive member CE2 (in one example, a flat conductive pad) is provided. Similar to the first conductive member CE1, the second conductive member CE2 is also arranged on the interlayer insulating film IL and includes a barrier metal film and a conductive film formed on the barrier metal film, which is the same as the first conductive member CE1. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points common to Embodiment 1 will be omitted as appropriate.

[0045] As shown in FIG. 11, the first and second extending portions P1 and P2 extend in the Y direction and are arranged to be spaced apart from each other in the X direction. The third and fourth extending portions P3 and P4 extend in the Y direction, are spaced apart from each other in the X direction, and are arranged between the first extending portion and the second extending portion in a plan view. The fifth extending portion P5 extends in the X direction and electrically connects one end of the third extending portion P3 and one end of the fourth extending portion P4. The sixth extending portion P6 extends in the X direction and electrically connects the other end of the first extending portion P1 and the other end of the third extending portion P3. The seventh extending portion P7 extends in the X direction and electrically connects the other end of the second extending portion P2 and the other end of the fourth extending portion P4. The eighth and ninth extending portions P8 and P9 extend in the Y direction, are spaced apart from each other in the X direction, and are arranged between the first extending portion P1 and the second extending portion P2 in a plan view. The tenth extending portion P10 extends in the X direction and electrically connects one end of the first extending portion P1 and one end of the eighth extending portion P8. The eleventh extending portion P11 extends in the X direction and electrically connects one end of the second extending portion P2 and one end of the ninth extending portion P9. The twelfth extending portion P12 extends in the X direction and electrically connects the other end of the eighth extending portion P8 and the other end of the ninth extending portion P9. Since the eighth to twelfth extending portions P8 to P12 electrically connect one end of the first extending portion P1 and one end of the second extending portion P2, the eighth to twelfth extending portions P8 to P12 are collectively referred to as the first connection portion CP1. Since the third to seventh extending portions P3 to P7 electrically connect the other end of the first extending portion P1 and the other end of the second extending portion P2, the third to seventh extending portions P3 to P7 are collectively referred to as the second connection portion CP2. In Embodiment 2, the widths (widths in the X direction in a plan view) of the first to fourth, eighth, and ninth extending portions P1 to P4, P8, and P9 extending in the Y direction are set to 0.8 μm (micrometers), and the widths (widths in the Y direction in a plan view) of the fifth to seventh, tenth to twelfth extending portions P5 to P7, P10 to P12 extending in the X direction are set to 0.4 μm (micrometers).

[0046] As shown in FIG. 12, the resistor element Rg formed inside the trench is electrically connected to the first contact member CM1 to the twelfth contact member CM12. The first and second contact members CM1 and CM2 electrically connect the gate pad GP to the eighth and ninth extending portions P8 and P9, respectively. The third and fourth contact members CM3 and CM4 electrically connect the gate wiring GW to the third and fourth extending portions P3 and P4, respectively. The fifth contact member CM5 electrically connects the first conductive member CE1 to the first extending portion P1. The sixth contact member CM6 electrically connects the first conductive member CE1 to the third extending portion P3. The seventh contact member CM7 electrically connects the first conductive member CE1 to the fourth extending portion P4. The eighth contact member CM8 electrically connects the first conductive member CE1 to the second extending portion P2. The ninth contact member CM9 electrically connects the second conductive member CE2 to the first extending portion P1. The tenth contact member CM10 electrically connects the second conductive member CE2 to the eighth extending portion P8. The eleventh contact member CM11 electrically connects the second conductive member CE2 to the ninth extending portion P9. The twelfth contact member CM12 electrically connects the second conductive member CE2 to the second extending portion P2.

[0047] In the semiconductor device 100 shown in FIGS. 11 and 12, as a detour path for the current path passing through the sixth extending portion P6, a current path passing through the fifth contact member CM5, the first conductive member CE1, and the sixth contact member CM6 is formed. Also, as a detour path for the current path passing through the seventh extending portion P7, a current path passing through the seventh contact member CM7, the first conductive member CE1, and the eighth contact member CM8 is formed. Also, as a detour path for the current path passing through the tenth extending portion P10, a current path passing through the ninth contact member CM9, the second conductive member CE2, and the tenth contact member CM10 is formed. Also, as a detour path for the current path passing through the eleventh extending portion P11, a current path passing through the eleventh contact member CM11, the second conductive member CE2, and the twelfth contact member CM12 is formed. Therefore, the current flowing through the narrow sixth, seventh, tenth, and eleventh extending portions P6, P7, P10, and P11 is reduced, thereby reducing the influence of electromigration on these extending portions.

[0048] Note that the shape of the resistance element Rg in Embodiment 2 is also characterized in that while ensuring electromigration resistance, the electrical resistance value of the current path from the gate pad GP to the gate wiring GW can be adjusted by changing the position of the contact member CM. Hereinafter, an example in which the electrical resistance value of the resistance element Rg is changed from the electrical resistance value of the resistance element Rg in FIGS. 11 and 12 by changing the position of the contact member CM will be described with reference to FIGS. 13 to 15.

[0049] <Modification Example 1 of Embodiment 2> FIG. 13 is a main part plan view showing a modification example 1 of the semiconductor device in Embodiment 2. Compared with the configurations of FIGS. 11 and 12, the positions of the first and second contact members CM1 and CM2 are different, and the first and second contact members CM1 and CM2 electrically connect the gate pad GP to the first and second extending portions P1 and P2, respectively.

[0050] The path of the current flowing from the gate pad GP to the gate wiring GW (the path including the detour path) in the configurations of FIGS. 11 and 12 is (1) The path from the gate pad GP to the gate wiring GW via the first contact member CM1, the eighth extending portion P8, the tenth contact member CM10, the second conductive member CE2, the ninth contact member CM9, the first extending portion P1, the fifth contact member CM5, the first conductive member CE1, the sixth contact member CM6, the third extending portion P3, and the third contact member CM3, and (2) The path from the gate pad GP to the gate wiring GW via the second contact member CM2, the ninth extending portion P9, the eleventh contact member CM11, the second conductive member CE2, the twelfth contact member CM12, the second extending portion P2, the eighth contact member CM8, the first conductive member CE1, the seventh contact member CM7, the fourth extending portion P4, and the fourth contact member CM4 were two parallel paths.

[0051] The path of the current flowing from the gate pad GP to the gate wiring GW (including the detour path) in the configuration of FIG. 13 is (1) The path from the gate pad GP to the gate wiring GW via the first contact member CM1, the first extending portion P1, the fifth contact member CM5, the first conductive member CE1, the sixth contact member CM6, the third extending portion P3, and the third contact member CM3, and (2) The path from the gate pad GP to the gate wiring GW via the second contact member CM2, the second extending portion P2, the eighth contact member CM8, the first conductive member CE1, the seventh contact member CM7, the fourth extending portion P4, and the fourth contact member CM4 are two parallel paths.

[0052] Compared with the configurations of FIGS. 11 and 12, the current path is shorter in the configuration of FIG. 13. In other words, by changing the positions of the first and second contact members CM1 and CM2 from the configurations of FIGS. 11 and 12, the electrical resistance value of the current path from the gate pad GP to the gate wiring GW can be reduced.

[0053] <Modification Example 2 of Embodiment 2> FIG. 14 is a principal part plan view showing a modification 2 of the semiconductor device in Embodiment 2. Compared with the configurations of FIGS. 11 and 12, the positions of the third and fourth contact members CM3 and CM4 are different, and the third and fourth contact members CM3 and CM4 electrically connect the gate wiring GW to the first and second extending portions P1 and P2, respectively.

[0054] The path of the current flowing from the gate pad GP to the gate wiring GW (the path including the detour path) in the configuration of FIG. 14 is (1) a path reaching the gate wiring GW via the first contact member CM1, the eighth extending portion P8, the tenth contact member CM10, the second conductive member CE2, the ninth contact member CM9, the first extending portion P1, and the third contact member CM3; and (2) a path reaching the gate wiring GW via the second contact member CM2, the ninth extending portion P9, the eleventh contact member CM11, the second conductive member CE2, the twelfth contact member CM12, the second extending portion P2, and the fourth contact member CM4 which are two parallel paths.

[0055] Compared with the configurations of FIGS. 11 and 12, the current path is shorter in the configuration of FIG. 14. Also, when the distance (distance in the Y direction) between the first conductive member CE1 and the gate wiring GW is larger than the distance (distance in the Y direction) between the second conductive member CE2 and the gate pad GP, the current path is shorter in the configuration of FIG. 14 compared with the configuration of FIG. 13. In other words, by changing the positions of the third and fourth contact members CM3 and CM4 from the configurations of FIGS. 11 and 12, the electrical resistance value of the current path from the gate pad GP to the gate wiring GW can be lowered.

[0056] <Modification 3 of Embodiment 2> FIG. 15 is a principal part plan view showing a modification 3 of the semiconductor device in Embodiment 2. Compared with the configurations of FIGS. 11 and 12, the positions of the first to fourth contact members CM1 to CM4 are different. The first and second contact members CM1 and CM2 electrically connect the gate pad GP to the first and second extending portions P1 and P2, respectively. The third and fourth contact members CM3 and CM4 electrically connect the gate wiring GW to the first and second extending portions P1 and P2, respectively.

[0057] The path of the current flowing from the gate pad GP to the gate wiring GW (the path including the detour path) in the configuration of FIG. 15 is (1) the path reaching the gate wiring GW via the first contact member CM1, the first extending portion P1, and the third contact member CM3, and (2) the path reaching the gate wiring GW via the second contact member CM2, the second extending portion P2, and the fourth contact member CM4 are two parallel paths.

[0058] Compared with the configurations of FIGS. 11 and 12, the configuration of FIG. 13, and the configuration of FIG. 14, the current path is shorter in the configuration of FIG. 15. In other words, by changing the positions of the first to fourth contact members CM1 to CM4 from the configurations of FIGS. 11 and 12, the electrical resistance value of the current path from the gate pad GP to the gate wiring GW can be reduced.

[0059] (Embodiment 3) Figs. 16 and 17 are principal part plan views showing the semiconductor device 100 in Embodiment 3. In Embodiment 3, the shape of the resistance element Rg is similar to that in Embodiment 2 (Figs. 11 and 12), and the extending portions and contact members through which the current path from the gate pad GP to the gate wiring GW passes are the same. However, the widths of the gate pad GP and the gate wiring GW in the Y direction are larger than their respective widths in Embodiment 2. By adopting the configurations shown in Figs. 16 and 17, there is a greater margin for changing the positions of the first and second contact members CM1 and CM2 in the Y direction while maintaining electrical connection with the gate pad GP, and there is also a greater margin for changing the positions of the third and fourth contact members CM3 and CM4 in the Y direction while maintaining electrical connection with the gate wiring GW. Such a change in position makes it possible to change the electrical resistance value of the current path from the gate pad GP to the gate wiring GW.

[0060] <Modification Example of Embodiment 3> Fig. 18 is a principal part plan view showing a modification example of the semiconductor device in Embodiment 3. Compared with the configurations of Figs. 16 and 17, the positions of the first and second contact members CM1 and CM2 have moved in the positive Y direction, and the positions of the third and fourth contact members CM3 and CM4 have moved in the negative Y direction. Such movement shortens the current path from the gate pad GP to the gate wiring GW, and the electrical resistance value of the current path in the configuration of Fig. 18 is lower than that of the current path in the configurations of Figs. 16 and 17.

[0061] (Embodiment 4) Fig. 19 is a principal part plan view showing the semiconductor device 100 in Embodiment 4. In Embodiment 4, the shape of the resistance element Rg is similar to that in Embodiment 2 (Figs. 11 and 12), and the extending portions and contact members through which the current path from the gate pad GP to the gate wiring GW passes are the same. However, a well contact member (contact member (plug) PG) formed in the well contact hole CH4 for electrically connecting the emitter electrode EE and the well region PW is formed.

[0062] FIG. 20 is a cross-sectional view taken along line E-E in the plan view of FIG. 19. Five well contact members (contact members (plugs) PG) electrically connect the emitter electrode EE and the well region PW. With such a configuration, the potential difference of the well region PW between the regions on the positive X-direction side and the negative X-direction side of the trench TR can be reduced. Further, dielectric breakdown of the gate insulating film GI in the trench TR in which the resistance element Rg is embedded can be prevented.

[0063] <Method of manufacturing a semiconductor device> Hereinafter, each manufacturing step included in the method of manufacturing the semiconductor device 100 in Embodiment 1 will be described with reference to FIGS. 21 to 35.

[0064] First, a semiconductor substrate SUB having an n-type drift region NV is prepared. The semiconductor substrate SUB is made of n-type silicon. Note that the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate while introducing phosphorus (P) by an epitaxial growth method. Next, as shown in FIG. 21, an n-type hole barrier region NHB is formed in the semiconductor substrate SUB in region 1A on the upper surface side of the semiconductor substrate SUB by photolithography technology and ion implantation. Next, a p-type floating region PF is formed in the semiconductor substrate SUB in region 1A on the upper surface side of the semiconductor substrate SUB by photolithography technology and ion implantation (FIG. 21), and at the same time and in parallel, as shown in FIG. 22, a p-type well region PW is formed in the semiconductor substrate SUB in region 2A. The floating region PF is physically separated from the well region PW.

[0065] Subsequently, as shown in FIG. 23, on the upper surface side of the semiconductor substrate SUB, a pair of trenches TR are formed in the semiconductor substrate SUB of the active cell AC and the inactive cell IAC in the region 1A, respectively. First, a resist pattern RP1 is formed on the upper surface of the semiconductor substrate SUB in the region 1A so as to cover a part of the region 1A and the region 2A. Next, using the resist pattern RP1 as a mask, an anisotropic etching process is performed on the semiconductor substrate SUB in the region 1A. As a result, a plurality of trenches TR are formed in the semiconductor substrate SUB in the region 1A. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0066] In parallel with the process shown in FIG. 23, as shown in FIG. 24, on the upper surface side of the semiconductor substrate SUB, a trench TR (see FIG. 3) that forms a closed path in plan view for forming the resistance element Rg is formed in the semiconductor substrate SUB in the region 1B, particularly in the well region PW. The method of forming the trench TR is the same as the method of forming the trench TR in the region 1A.

[0067] As shown in FIGS. 25 and 26, a sacrificial oxide film SOF is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB. Thereby, the damaged layer formed in the semiconductor substrate SUB is removed. Thereafter, the sacrificial oxide film SOF is removed by an isotropic etching process using, for example, a solution containing hydrofluoric acid.

[0068] Note that the sacrificial oxide film SOF is formed by performing a heat treatment on the semiconductor substrate SUB. This heat treatment is performed, for example, in an atmosphere filled with oxygen gas, at 1100 ° C., and under the condition of 30 minutes or more and 60 minutes or less. By this heat treatment, the impurities contained in the hole barrier region NHB, the floating region PF, and the well region PW are diffused.

[0069] Next, as shown in FIGS. 27 and 28, a gate insulating film GI and a conductive film CF1 are formed. First, the gate insulating film GI is formed by a thermal oxidation method inside the trench TR and on the upper surface of the semiconductor substrate SUB.

[0070] Next, a conductive film CF1 is formed, for example, by CVD method, on the inside of the trench TR and on the upper surface of the semiconductor substrate SUB so as to fill the inside of the trench TR through the gate insulating film GI. The conductive film CF1 is, for example, a polycrystalline silicon film into which n-type impurities are introduced.

[0071] As shown in FIG. 29, a gate insulating film GI and gate electrodes GE1, GE2 are formed inside the trench TR. First, the conductive film CF1 formed outside the trench TR is removed by anisotropic etching. The conductive film CF1 formed inside the trench TR remains as the gate electrodes GE1, GE2. Next, the gate insulating film GI formed outside the trench TR is removed by isotropic etching, anisotropic etching, or an etching process combining these.

[0072] In parallel with the process shown in FIG. 29, as shown in FIG. 30, a resistance element Rg is formed inside the trench TR. First, the conductive film CF1 formed outside the trench TR is removed by anisotropic etching. The conductive film CF1 formed inside the trench TR remains as the resistance element Rg. Next, the gate insulating film GI formed outside the trench TR is removed by isotropic etching, anisotropic etching, or an etching process combining these.

[0073] Next, as shown in FIG. 31, on the upper surface side of the semiconductor substrate SUB, a p-type base region PB is formed in the semiconductor substrate SUB (floating region PF and hole barrier region NHB) of region 1A by photolithography technology and ion implantation method. Next, an n-type emitter region NE is formed in the base region PB by photolithography technology and ion implantation method. Thereafter, the semiconductor substrate SUB is heat-treated to activate the impurities contained in each impurity region.

[0074] Next, as shown in FIGS. 32 and 33, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB in regions 1A and 2A so as to cover the trench TR in region 1A and cover the resistance element Rg in region 2A, for example, by a CVD method. Subsequently, in order to planarize the upper surface of the interlayer insulating film IL, a polishing process is performed on the interlayer insulating film IL in regions 1A and 2A by a CMP method. Further, contact holes CH1 to CH3 are formed in the interlayer insulating film IL in regions 1A and 2A by photolithography technology and anisotropic etching processing. Next, as shown in FIG. 32, a p-type high-concentration diffusion region PR is formed at the bottoms of the contact holes CH1 and CH2 by an ion implantation method.

[0075] The contact hole CH1 penetrates through the interlayer insulating film IL and the emitter region NE and reaches the inside of the base region PB. The contact hole CH2 penetrates through the interlayer insulating film IL and reaches the inside of the base region PB. Also, the contact hole CH2 is formed so as to overlap the gate electrode GE2 in plan view. Contact holes CH3 (eight contact holes CH3 are formed corresponding to the first to eighth contact members CM1 to CM8 shown in FIG. 5) penetrate through the interlayer insulating film IL and reach the inside of the resistance element Rg.

[0076] As shown in FIGS. 34 and 35, a contact member PG is formed inside each of the contact holes CH1 to CH3. First, a barrier metal film is formed inside each of the contact holes CH1 to CH3 and on the interlayer insulating film IL. For example, a titanium film can be formed inside each of the contact holes CH1 to CH3 and on the interlayer insulating film IL by a sputtering method, and the barrier metal film can be formed by forming a titanium nitride film on the titanium film by a sputtering method, for example.

[0077] Next, a conductive film made of, for example, a tungsten film is formed on the barrier metal film by, for example, CVD method so as to embed each of the inside of the contact holes CH1 to CH3. Next, the conductive film and the barrier metal film formed outside each of the contact holes CH1 to CH3 are removed by anisotropic etching treatment. Thereby, the contact member PG is formed so as to embed each of the inside of the contact holes CH1 to CH3.

[0078] Next, a gate pad GP (including a gate pad wiring GPW), a gate wiring GW, a first conductive member CE1, and an emitter electrode EE are formed on the interlayer insulating film IL. First, a TiW film is formed on the interlayer insulating film IL by, for example, sputtering method, and an aluminum alloy film is formed on the TiW film by, for example, sputtering method. Next, the TiW film and the aluminum alloy film are patterned by photolithography technology and dry etching treatment to form the gate pad GP, the gate wiring GW, the first conductive member CE1, and the emitter electrode EE.

[0079] Thereafter, through the following manufacturing processes, the structures shown in FIGS. 3 to 9 are obtained. First, an n-type field stop region NS and a p-type collector region PC are formed by performing ion implantation from the lower surface side of the semiconductor substrate SUB. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film such as, for example, an Au film, a Ni film, a Ti film, or an AlSi film is formed under the lower surface of the semiconductor substrate SUB by, for example, sputtering method. This metal film becomes the collector electrode CE. The collector electrode CE may be a laminated film in which the above-described metal films are appropriately laminated.

[0080] The manufacturing method of the semiconductor device 100 in Embodiments 2 to 4 is also substantially the same as the method described with reference to FIGS. 21 to 35. When forming the second conductive member CE2, the second conductive member CE2 may be formed on the interlayer insulating film IL in the same manner as the first conductive member CE1. When forming a well contact member (contact member PG) in the well contact hole CH4, the well contact holes CH1 to CH3 are formed as shown in FIGS. 33 to 35, and the well contact hole CH4 may be formed simultaneously with the process of forming the contact member PG in the contact holes CH1 to CH3, and the contact member PG may be formed in the well contact hole CH4.

[0081] As described above, the present invention has been described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.

[0082] For example, in the above embodiment, an IGBT is exemplified as the device formed in the cell region 1A. However, the technology disclosed in the above embodiment is not limited to the IGBT, and can also be applied to a power MOSFET having a vertical trench gate structure.

[0083] Also, the material used for the semiconductor substrate SUB is not limited to silicon (Si), and may be silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or the like. The n-type impurity may be, for example, phosphorus (P), arsenic (As), or the like, and the p-type impurity may be, for example, boron (B), indium (In), or the like.

[0084] Also, the various configurations described in each of the embodiments and their modifications can be implemented in combination with each other. This specification describes, for example, the following configurations.

[0085] (Supplementary Note) (Supplementary Note 1) A semiconductor substrate having a first main surface and a well region formed on the first main surface, and having, The interlayer insulating film formed on the first main surface, The gate pad, gate wiring, and first conductive member formed on the interlayer insulating film, A resistor element formed inside a trench that forms a closed path in plan view and formed via an insulating film in the well region, First to eighth contact members that penetrate the interlayer insulating film and reach the resistor element And having, The resistor element is A first extending portion and a second extending portion that extend in a first direction in plan view and are spaced apart from each other in a second direction intersecting the first direction in plan view, A first connecting portion that electrically connects one end of the first extending portion and one end of the second extending portion, A second connecting portion that electrically connects the other end of the first extending portion and the other end of the second extending portion And having, The first and second contact members each electrically connect the gate pad and the resistor element, The third and fourth contact members each electrically connect the gate wiring and the resistor element, The fifth to eighth contact members each electrically connect the first conductive member and the resistor element Semiconductor device.

[0086] (Appendix 2) The second connecting portion is Third and fourth extending portions that extend in the first direction, are spaced apart from each other in the second direction, and are disposed between the first extending portion and the second extending portion in plan view, A fifth extending portion that extends in the second direction and electrically connects one end of the third extending portion and one end of the fourth extending portion, A sixth extending portion that extends in the second direction and electrically connects the other end of the first extending portion and the other end of the third extending portion, A seventh extending portion that extends in the second direction and electrically connects the other end of the second extending portion and the other end of the fourth extending portion And having, The fifth contact member electrically connects the first conductive member and the first extending portion, the sixth contact member electrically connects the first conductive member and the third extending portion, the seventh contact member electrically connects the first conductive member and the fourth extending portion, and the eighth contact member electrically connects the first conductive member and the second extending portion. The semiconductor device according to Supplementary Note 1.

[0087] (Supplementary Note 3) The third contact member electrically connects the gate wiring and the third extending portion, and the fourth contact member electrically connects the gate wiring and the fourth extending portion. The semiconductor device according to Supplementary Note 1 or 2.

[0088] (Supplementary Note 4) The width in the second direction in the plan view of the first to fourth extending portions is larger than the width in the first direction in the plan view of the fifth to seventh extending portions. The semiconductor device according to any one of Supplementary Notes 1 to 3.

[0089] (Supplementary Note 5) The fifth to eighth contact members are arranged at least a predetermined distance apart from the sixth and seventh extending portions in the first direction. The semiconductor device according to any one of Supplementary Notes 1 to 4.

[0090] (Supplementary Note 6) The first to eighth contact members have lengths within a predetermined range in the first direction. The semiconductor device according to any one of Supplementary Notes 1 to 5.

[0091] (Supplementary Note 7) There are a plurality of sets of the insulating film, the resistive element, and the first to eighth contact members, Each of the sets is arranged apart from each other in the second direction in the plan view, The gate pad has a gate pad wiring, and the gate pad wiring overlaps the first and second contact members in each of the plurality of sets in the plan view. The gate wiring overlaps the third and fourth contact members in each of the plurality of sets in a plan view. The first conductive member overlaps the fifth to eighth contact members in each of the plurality of sets in a plan view. The semiconductor device according to any one of Appendices 1 to 6.

[0092] (Appendix 8) A second conductive member formed on the interlayer insulating film, Ninth to twelfth contact members that penetrate the interlayer insulating film and reach the resistance element and further has The first connection portion extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in a plan view. Eighth and ninth extending portions, A tenth extending portion that extends in the second direction and electrically connects one end of the first extending portion and one end of the eighth extending portion, An eleventh extending portion that extends in the second direction and electrically connects one end of the second extending portion and one end of the ninth extending portion A twelfth extending portion that extends in the second direction and electrically connects the other end of the eighth extending portion and the other end of the ninth extending portion, and has The ninth contact member electrically connects the second conductive member and the first extending portion. The tenth contact member electrically connects the second conductive member and the eighth extending portion. The eleventh contact member electrically connects the second conductive member and the ninth extending portion. The twelfth contact member electrically connects the second conductive member and the second extending portion. The semiconductor device according to any one of Appendices 1 to 7.

[0093] (Appendix 9) The gate pad has gate pad wiring. The gate pad wiring has a width of at least a first predetermined length in the first direction in a plan view. The gate wiring has a width of at least a second predetermined length in the first direction in a plan view. The semiconductor device according to any one of Appendices 1 to 8.

[0094] (Appendix 10) An emitter electrode formed on the interlayer insulating film, A well contact member that penetrates the interlayer insulating film and reaches the well region, and further having, wherein the well contact member electrically connects the emitter electrode and the well region, the semiconductor device according to any one of Appendices 1 to 9.

[0095] (Appendix 11) (a) A step of preparing a semiconductor substrate having a first main surface, (b) A step of forming a well region on the first main surface of the semiconductor substrate, (c) A step of forming a trench that forms a closed path in plan view in the well region, (d) A step of forming an insulating film inside the trench, (e) A step of forming a resistance element inside the trench via the insulating film, (f) A step of forming an interlayer insulating film on the first main surface, (g) A step of forming first to eighth contact members that penetrate the interlayer insulating film and reach the resistance element, (h) A step of forming a gate pad, a gate wiring, and a first conductive member on the interlayer insulating film having, In the step (e), the resistance element is, In plan view, a first extending portion and a second extending portion that extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction in plan view, A first connection portion that electrically connects one end of the first extending portion and one end of the second extending portion, A second connection portion that electrically connects the other end of the first extending portion and the other end of the second extending portion having, In the steps (g) and (h), the first and second contact members each electrically connect the gate pad and the resistance element, The third and fourth contact members electrically connect the gate wiring and the resistance element, respectively. The fifth to eighth contact members are formed such that the first to eighth contact members, the gate pad, the gate wiring, and the first conductive member electrically connect the first conductive member and the resistance element, respectively. A method of manufacturing a semiconductor device.

[0096] (Appendix 12) In the step (e), the second connection portion extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in a plan view, and third and fourth extending portions; extends in the second direction, and a fifth extending portion that electrically connects one end of the third extending portion and one end of the fourth extending portion; extends in the second direction, and a sixth extending portion that electrically connects the other end of the first extending portion and the other end of the third extending portion; extends in the second direction, and a seventh extending portion that electrically connects the other end of the second extending portion and the other end of the fourth extending portion The resistance element is formed to have In the step (g) and the step (h), The fifth contact member electrically connects the first conductive member and the first extending portion, the sixth contact member electrically connects the first conductive member and the third extending portion, the seventh contact member electrically connects the first conductive member and the fourth extending portion, and the eighth contact member electrically connects the first conductive member and the second extending portion. The method of manufacturing a semiconductor device according to Appendix 11, wherein the fifth to eighth contact members and the first conductive member are formed.

[0097] (Appendix 13) In the step (g) and the step (h), The method of manufacturing a semiconductor device according to appended claim 11 or 12, wherein the third contact member electrically connects the gate wiring and the third extending portion, and the fourth contact member electrically connects the gate wiring and the fourth extending portion, and the third and fourth contact members and the gate wiring are formed.

[0098] (Appended claim 14) In the step (e), the resistance element is formed such that the width in the second direction in a plan view of the first to fourth extending portions is larger than the width in the first direction in a plan view of the fifth to seventh extending portions, according to the method of manufacturing a semiconductor device according to any one of appended claims 11 to 13.

[0099] (Appended claim 15) In the step (g), the fifth to eighth contact members are arranged at least a predetermined distance apart from the sixth and seventh extending portions in the first direction, according to the method of manufacturing a semiconductor device according to any one of appended claims 11 to 14.

[0100] (Appended claim 16) In the step (g), the first to eighth contact members are formed to have a length within a predetermined range in the first direction, according to the method of manufacturing a semiconductor device according to any one of appended claims 11 to 15.

[0101] (Appended claim 17) In the steps (c) to (e), a plurality of the trenches, the insulating films, and the resistance elements are respectively formed. In the step (g), by forming a plurality of the first to eighth contact members respectively, the semiconductor device has a plurality of sets of the insulating film, the resistance element, and the first to eighth contact members. Each of the sets is arranged to be separated from each other in the second direction in a plan view. In the step (h), the gate pad has gate pad wirings, and the gate pad is formed such that the gate pad wirings overlap the first and second contact members in each of the plurality of sets in a plan view. In the step (h), the gate wiring is formed so as to overlap the third and fourth contact members in each of the plurality of sets in a plan view. In the step (h), the first conductive member is formed so as to overlap the fifth to eighth contact members in each of the plurality of sets in a plan view. A method of manufacturing a semiconductor device according to any one of Appendices 11 to 16.

[0102] (Appendix 18) In the step (g), ninth to twelfth contact members that penetrate the interlayer insulating film and reach the resistance element are further formed respectively. In the step (h), a second conductive member is further formed on the interlayer insulating film. In the step (e), The first connection portion extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in a plan view, eighth and ninth extending portions, extends in the second direction, and a tenth extending portion that electrically connects one end of the first extending portion and one end of the eighth extending portion, extends in the second direction, and an eleventh extending portion that electrically connects one end of the second extending portion and one end of the ninth extending portion extends in the second direction, and a twelfth extending portion that electrically connects the other end of the eighth extending portion and the other end of the ninth extending portion, The resistance element is formed so as to have In the steps (g) and (h), The ninth contact member electrically connects the second conductive member and the first extending portion, the tenth contact member electrically connects the second conductive member and the eighth extending portion, the eleventh contact member electrically connects the second conductive member and the ninth extending portion, and the twelfth contact member electrically connects the second conductive member and the second extending portion. A method of manufacturing a semiconductor device according to any one of Appendices 11 to 17, wherein the ninth to twelfth contact members and the second conductive member are formed.

[0103] (Appendix 19) In the step (h), the gate pad is formed such that the gate pad has a gate pad wiring, and the gate pad wiring has a width of at least a first predetermined length in the first direction in a plan view, and the gate wiring is formed such that the gate wiring has a width of at least a second predetermined length in the first direction in a plan view. A method of manufacturing a semiconductor device according to any one of Appendices 11 to 18.

[0104] (Appendix 20) In the step (g), a well contact member that penetrates the interlayer insulating film and reaches the well region is further formed. In the step (h), an emitter electrode is further formed on the interlayer insulating film. The well contact member electrically connects the emitter electrode and the well region. A method of manufacturing a semiconductor device according to any one of Appendices 11 to 19.

Explanation of Signs

[0105] 100 Semiconductor device 1A Cell region 1B Peripheral region AC Active cell CE Collector electrode CE1 First conductive member CE2 Second conductive member CH1 to CH3 Contact hole CH4 Well contact hole CM1 to CM12, the 1st to 12th contact members EE, emitter electrode GE1, GE2, gate electrodes GI, gate insulating film GP, gate pad GPW, gate pad wiring GW, gate wiring IAC, inactive cell IL, interlayer insulating film NE, emitter region NHB, hole barrier region NS, field stop region NV, drift region OPE, OPG, openings PB, base region PC, collector region PG, contact member (plug) PR, high-concentration diffusion region PV, protective film PW, well region P1 to P12, the 1st to 12th extending parts RGA, resistor element region Rg, resistor element SUB, semiconductor substrate SUBa, the 1st main surface SUBb, the 2nd main surface TR, trench

Claims

1. A semiconductor substrate having a first main surface, and a well region formed on the first main surface and having, An interlayer insulating film formed on the first main surface, A gate pad, a gate wiring, and a first conductive member formed on the interlayer insulating film, A resistor element formed in the well region and formed via an insulating film inside a trench that forms a closed path in plan view, First to eighth contact members that penetrate the interlayer insulating film and reach the resistor element and having, The resistor element In plan view, a first and a second extending portion extending in a first direction and spaced apart from each other in a second direction intersecting the first direction in plan view, A first connection portion that electrically connects one end of the first extending portion and one end of the second extending portion, A second connection portion that electrically connects the other end of the first extending portion and the other end of the second extending portion and having, The first and the second contact members each electrically connect the gate pad and the resistor element, The third and the fourth contact members each electrically connect the gate wiring and the resistor element, The fifth to eighth contact members each electrically connect the first conductive member and the resistor element, a semiconductor device.

2. The second connection portion Extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in plan view, third and fourth extending portions, A fifth extending portion extending in the second direction and electrically connecting one end of the third extending portion and one end of the fourth extending portion, A sixth extending portion extending in the second direction and electrically connecting the other end of the first extending portion and the other end of the third extending portion, A seventh extending portion that extends in the second direction and electrically connects the other end of the second extending portion and the other end of the fourth extending portion. and has The fifth contact member electrically connects the first conductive member and the first extending portion, the sixth contact member electrically connects the first conductive member and the third extending portion, the seventh contact member electrically connects the first conductive member and the fourth extending portion, and the eighth contact member electrically connects the first conductive member and the second extending portion. The semiconductor device according to claim 1. **Claim 3** The third contact member electrically connects the gate wiring and the third extending portion, and the fourth contact member electrically connects the gate wiring and the fourth extending portion. The semiconductor device according to claim 2. **Claim 4** The width in the second direction in a plan view of the first to fourth extending portions is larger than the width in the first direction in a plan view of the fifth to seventh extending portions. The semiconductor device according to claim 2. **Claim 5** The fifth to eighth contact members are arranged at least a predetermined distance apart from the sixth and seventh extending portions in the first direction. The semiconductor device according to claim 2. **Claim 6** The first to eighth contact members have lengths within a predetermined range in the first direction. The semiconductor device according to claim 1. **Claim 7** There are a plurality of sets of the insulating film, the resistance element, and the first to eighth contact members. Each of the sets is arranged apart from each other in the second direction in a plan view. The gate pad has a gate pad wiring, and the gate pad wiring overlaps the first and second contact members in each of the plurality of sets in a plan view. The gate wiring overlaps the third and fourth contact members in each of the plurality of sets in a plan view. The semiconductor device according to claim 1, wherein the first conductive member overlaps the fifth to eighth contact members in each of the plurality of sets in a plan view.

8. a second conductive member formed on the interlayer insulating film; ninth to twelfth contact members that penetrate the interlayer insulating film and reach the resistance element; and further has The first connection portion extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in a plan view, the eighth and ninth extending portions; a tenth extending portion that extends in the second direction and electrically connects one end of the first extending portion and one end of the eighth extending portion; an eleventh extending portion that extends in the second direction and electrically connects one end of the second extending portion and one end of the ninth extending portion; a twelfth extending portion that extends in the second direction and electrically connects the other end of the eighth extending portion and the other end of the ninth extending portion; and has The ninth contact member electrically connects the second conductive member and the first extending portion, the tenth contact member electrically connects the second conductive member and the eighth extending portion, the eleventh contact member electrically connects the second conductive member and the ninth extending portion, and the twelfth contact member electrically connects the second conductive member and the second extending portion. The semiconductor device according to claim 1.

9. The gate pad has a gate pad wiring, and the gate pad wiring has a width of at least a first predetermined length in the first direction in a plan view, and the gate wiring has a width of at least a second predetermined length in the first direction in a plan view. The semiconductor device according to claim 1.

10. an emitter electrode formed on the interlayer insulating film; a well contact member that penetrates the interlayer insulating film and reaches the well region; further includes, and the well contact member electrically connects the emitter electrode and the well region, the semiconductor device according to claim 1.

11. (a) A step of preparing a semiconductor substrate having a first main surface, (b) A step of forming a well region on the first main surface of the semiconductor substrate, (c) A step of forming a trench that forms a closed path in a plan view in the well region, (d) A step of forming an insulating film inside the trench, (e) A step of forming a resistor element inside the trench via the insulating film, (f) A step of forming an interlayer insulating film on the first main surface, (g) A step of forming first to eighth contact members that penetrate the interlayer insulating film and reach the resistor element, (h) A step of forming a gate pad, a gate wiring, and a first conductive member on the interlayer insulating film having, In the step (e), the resistor element has, a first and a second extending portion that extend in a first direction in a plan view and are spaced apart from each other in a second direction intersecting the first direction in a plan view, a first connecting portion that electrically connects one end of the first extending portion and one end of the second extending portion, a second connecting portion that electrically connects the other end of the first extending portion and the other end of the second extending portion, having, In the steps (g) and (h), the first and the second contact members each electrically connect the gate pad and the resistor element, the third and the fourth contact members each electrically connect the gate wiring and the resistor element, A method of manufacturing a semiconductor device, wherein the fifth to eighth contact members each electrically connect the first conductive member and the resistance element, and the first to eighth contact members, the gate pad, the gate wiring, and the first conductive member are formed.

12. In the step (e), the second connection portion extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending portion and the second extending portion in a plan view, and third and fourth extending portions; extends in the second direction and electrically connects one end of the third extending portion and one end of the fourth extending portion; a fifth extending portion; extends in the second direction and electrically connects the other end of the first extending portion and the other end of the third extending portion; a sixth extending portion; extends in the second direction and electrically connects the other end of the second extending portion and the other end of the fourth extending portion; a seventh extending portion is formed such that the resistance element has, In the step (g) and the step (h), the fifth contact member electrically connects the first conductive member and the first extending portion, the sixth contact member electrically connects the first conductive member and the third extending portion, the seventh contact member electrically connects the first conductive member and the fourth extending portion, and the eighth contact member electrically connects the first conductive member and the second extending portion, and the fifth to eighth contact members and the first conductive member are formed. The method of manufacturing a semiconductor device according to claim 11.

13. In the step (g) and the step (h), the third contact member electrically connects the gate wiring and the third extending portion, and the fourth contact member electrically connects the gate wiring and the fourth extending portion, and the third and fourth contact members and the gate wiring are formed. The method of manufacturing a semiconductor device according to claim 12.

14. In the step (e), the resistance element is formed such that the width in the second direction in the plan view of the first to fourth extending portions is larger than the width in the first direction in the plan view of the fifth to seventh extending portions. The method of manufacturing a semiconductor device according to claim 12.

15. In the step (g), the fifth to eighth contact members are arranged at least a predetermined distance apart from the sixth and seventh extending portions in the first direction. The method of manufacturing a semiconductor device according to claim 12.

16. In the step (g), the first to eighth contact members are formed to have lengths within a predetermined range in the first direction. The method of manufacturing a semiconductor device according to claim 11.

17. In the steps (c) to (e), a plurality of the trenches, the insulating films, and the resistance elements are respectively formed. In the step (g), a plurality of the first to eighth contact members are respectively formed, so that the semiconductor device has a plurality of sets of the insulating film, the resistance element, and the first to eighth contact members. Each of the sets is arranged at a distance from each other in the second direction in the plan view. In the step (h), the gate pad has a gate pad wiring, and the gate pad is formed such that the gate pad wiring overlaps the first and second contact members in each of the plurality of sets in the plan view. In the step (h), the gate wiring is formed to overlap the third and fourth contact members in each of the plurality of sets in the plan view. In the step (h), the first conductive member is formed to overlap the fifth to eighth contact members in each of the plurality of sets in the plan view. The method of manufacturing a semiconductor device according to claim 11.

18. In the step (g), ninth to twelfth contact members that penetrate the interlayer insulating film and reach the resistance element are further formed respectively. In the step (h), a second conductive member is further formed on the interlayer insulating film. In the step (e), The first connection part extends in the first direction, is spaced apart from each other in the second direction, and is disposed between the first extending part and the second extending part in a plan view, and eighth and ninth extending parts; extends in the second direction and electrically connects one end of the first extending part and one end of the eighth extending part; a tenth extending part; extends in the second direction and electrically connects one end of the second extending part and one end of the ninth extending part; an eleventh extending part; extends in the second direction and electrically connects the other end of the eighth extending part and the other end of the ninth extending part; a twelfth extending part; The resistance element is formed so as to have the above. In the step (g) and the step (h), The ninth contact member electrically connects the second conductive member and the first extending part, the tenth contact member electrically connects the second conductive member and the eighth extending part, the eleventh contact member electrically connects the second conductive member and the ninth extending part, and the twelfth contact member electrically connects the second conductive member and the second extending part. The ninth to twelfth contact members and the second conductive member are formed. The method for manufacturing a semiconductor device according to claim 11.

19. In the step (h), the gate pad has a gate pad wiring, and the gate pad is formed such that the gate pad wiring has a width of at least a first predetermined length in the first direction in a plan view, and the gate wiring is formed such that the gate wiring has a width of at least a second predetermined length in the first direction in a plan view. The method for manufacturing a semiconductor device according to claim 11.

20. In the step (g), a well contact member that penetrates the interlayer insulating film and reaches the well region is further formed. In the step (h), an emitter electrode is further formed on the interlayer insulating film. The well contact member electrically connects the emitter electrode and the well region. The manufacturing method of the semiconductor device according to claim 11.

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