Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device 100 comprising a body diode of low resistance and a manufacturing method thereof.SOLUTION: The semiconductor device 100 comprises: a drift region 2 of a first conductivity type; a well region 3 of a second conductivity type which is formed in contact with the drift region 2; a drain region 5 of the first conductivity type which is formed within the drift region 2; a source region 4 of the first conductivity type which is formed within the well region 3; a back gate region 9 of the second conductivity type disposed on a bottom part of a groove 8 which is formed in contact with the source region 4, the well region 3, and the drift region 2 and in contact with the well region 3; a gate electrode 7 which is a part of the groove 8 on the back gate region 9 and disposed via an inter-layer insulation film 6a in a part of the groove 8 including a side face of the groove 8 opposed with the drain region 5; a back gate electrode 15 which is disposed in the remaining part of the groove 8 on the back gate region 9 and ohmic-connected to the back gate electrode 9; and a second electrode 11 which is electrically connected to the source region 4 and the back gate electrode 15.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 describes a transistor in which a groove is provided in a semiconductor substrate, and a gate electrode and a gate insulating film are disposed in the groove.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A built-in PN diode (body diode) formed between a well region and a drift region may be used as a reflux diode in an inverter circuit or the like. However, since the resistance component of the well region between the PN junction site and the source electrode is large, the reflux loss is increased.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device having a low-resistance body diode and a method for manufacturing the same.

Means for Solving the Problems

[0006] A semiconductor device according to one aspect of the present invention includes a drift region of a first conductivity type formed in contact with one main surface of a semiconductor substrate, a well region of a second conductivity type formed in contact with the drift region, a drain region of the first conductivity type formed in the drift region separated from the well region, a first electrode electrically connected to the drain region, a source region of the first conductivity type formed in the well region, a back gate region of the second conductivity type disposed at the bottom of a groove formed in contact with the source region, the well region, and the drift region and in contact with the well region, and a gate electrode disposed via an interlayer insulating film in a part of the groove on the back gate region, the part including a side surface of the groove facing the drain region, a back gate electrode disposed in the remaining part of the groove on the back gate region and ohmically connected to the back gate region, and a second electrode electrically connected to the source region and the back gate electrode.

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a semiconductor device having a low-resistance body diode and a method for manufacturing the same.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Hereinafter, the semiconductor device and the manufacturing method of the semiconductor device according to the embodiment will be described in detail with reference to the drawings. Note that the embodiments described below show comprehensive or specific examples. The numerical values, shapes, materials, installation positions, and connection forms of the components shown in the following embodiments are examples and are not intended to limit the present disclosure. Also, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may be different from the actual ratios. In addition, the following embodiments and their modifications may include the same components, and the same components are given common reference numerals and duplicate explanations are omitted.

[0010] (First Embodiment) [Structure of Semiconductor Device] The semiconductor device 100 according to the first embodiment is a MOS (Metal-Oxide-Semiconductor) field-effect transistor (MOSFET) having a trench gate structure and a lateral structure. FIG. 1 is a cross-sectional perspective view showing the structure of the semiconductor device 100 according to the first embodiment.

[0011] The semiconductor device 100 includes a semiconductor substrate 1, a drift region 2 of a first conductivity type, a well region 3 of a second conductivity type, a drain region 5 of the first conductivity type, a first electrode 12, a source region 4 of the first conductivity type, a back gate region 9 of the second conductivity type, an interlayer insulating film 6, a gate electrode 7, a back gate electrode 15, and a second electrode 11.

[0012] The direction from the first electrode 12 to the second electrode 11 is defined as the X-axis direction. One direction perpendicular to the X-axis direction is defined as the Y-axis direction. The direction perpendicular to the X-axis direction and the Y-axis direction is defined as the Z-axis direction. The X-axis, Y-axis, and Z-axis are common to all the figures illustrated in the following description.

[0013] FIG. 2 is a cross-sectional view of the semiconductor device 100 in the XZ plane including the II-II cutting line of FIG. 1. FIG. 3 is a cross-sectional view of the semiconductor device 100 in the YZ plane including the III-III cutting line of FIG. 1.

[0014] FIG. 1 shows the unit cell structure of the MOSFET. In an actual device, the unit cell structure is repeated in the Y direction, and in the X direction, a structure planar with respect to the side surface parallel to the YZ plane of the unit cell structure is repeated.

[0015] The first conductivity type and the second conductivity type are different from each other. That is, if the first conductivity type is P-type, the second conductivity type is N-type, and if the first conductivity type is N-type, the second conductivity type is P-type. In the present embodiment, the case where the first conductivity type is N-type and the second conductivity type is P-type will be described.

[0016] The semiconductor substrate 1 can use, for example, a semi-insulating silicon carbide substrate (SiC substrate). Since SiC is a wide-bandgap semiconductor and has a small number of intrinsic carriers, high insulation can be obtained, and a semiconductor device 100 with a high breakdown voltage can be realized. There are several polytypes (crystal polymorphs) in SiC, and a typical 4H SiC substrate in the hexagonal system can be used as the semiconductor substrate 1. By using an SiC substrate for the semiconductor substrate 1, the breakdown voltage of the semiconductor substrate 1 can be increased. Also, the thermal conductivity of silicon carbide is large, and heat generated by the on-current of the semiconductor device 100 can be efficiently dissipated. A semiconductor device 100 with high cooling performance can be provided.

[0017] Also, the semiconductor substrate 1 is not limited to an SiC substrate, and other semiconductor materials with a wide bandgap may be used. Examples of semiconductor materials with a wide bandgap include III-V compound semiconductors using nitrogen as a group V element such as GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), InN (indium nitride), diamond, ZnO (zinc oxide), and the like.

[0018] The N-type drift region 2 is formed in contact with one main surface 1a of the semiconductor substrate 1. One main surface 1a is the surface facing the positive direction of the Z-axis of the semiconductor substrate 1, that is, the top surface. In the Z-axis direction, the direction in which the drift region 2 is located as viewed from the semiconductor substrate 1 is also referred to as the upward direction, and the direction in which the semiconductor substrate 1 is located as viewed from the drift region 2 is also referred to as the downward direction. The surface facing upward of each member is called the top surface, the surface facing downward is called the bottom surface, and the surface connecting the top surface and the side surface is called the side surface. For example, the N-type drift region 2 is a region formed in the upper part of the semiconductor substrate 1 including the top surface (one main surface 1a) of the semiconductor substrate 1.

[0019] The N-type drift region 2 is the region where current flows through the semiconductor device 100 when the transistor (semiconductor device 100) is in the on state. The current flows from the drain region 5 to the source region 4 (in the positive X-axis direction) in the drift region 2. The drift region 2 is in contact with the P-type well region 3 in the positive X-axis direction (arrow direction) and is in contact with the N-type drain region 5 in the negative X-axis direction (opposite to the arrow direction). The well region 3 and the drain region 5 are not in direct contact but are electrically connected via the drift region 2.

[0020] The drift region 2 may be formed of a wide bandgap semiconductor. Thereby, it is possible to achieve both low on-resistance and high breakdown voltage. The semiconductor substrate 1, the well region 3, and the drift region 2 may be formed of the same material. Thereby, it is possible to prevent performance degradation such as lattice mismatch that occurs when different materials are used.

[0021] The P-type well region 3 is formed in contact with the N-type drift region 2. The interface between the well region 3 and the drift region 2 forms a PN junction. The PN junction forms the body diode of the semiconductor device 100 and functions as a freewheeling diode in an inverter circuit or the like. The P-type impurity concentration of the well region 3 is, for example, 1E15 cm -3 or more and 1E19 cm -3 or less. Similar to the drift region 2, the well region 3 is preferably formed of a wide bandgap semiconductor. It is possible to achieve both low on-resistance and high breakdown electric field.

[0022] The N-type source region 4 is formed within the well region 3. The interface between the source region 4 and the well region 3 forms a PN junction. The N-type impurity concentration of the source region 4 is higher than that of the drift region 2, for example, 1E18 cm -3 or more and 1E21 cm -3 or less. The source region 4 is joined to the second electrode 11 on its upper surface. The source region 4 and the second electrode 11 form an ohmic contact.

[0023] In the manufacturing process of the semiconductor device 100, a groove 8 is formed in the semiconductor substrate 1. The groove 8 is in contact with the source region 4, the well region 3, and the drift region 2. The groove 8 is defined by a bottom 8a and a side surface 8b that connects the bottom 8a and the main surface 1a of the semiconductor substrate 1. The groove 8 is in contact with the source region 4, the well region 3, and the drift region 2 on the side surface 8b that is parallel to the positive direction of the X-axis, that is, at least in the direction of the current flowing from the drain region 5 to the source region 4. The groove 8 penetrates the source region 4 and the drift region 2 when viewed in the negative direction of the Z-axis. The bottom 8a of the groove 8 reaches the well region 3.

[0024] The P-type back gate region 9 is disposed at the bottom 8a of the groove 8. The back gate region 9 is in contact with the well region 3 exposed at the bottom 8a of the groove. Similar to the well region 3, the back gate region 9 is preferably formed of a wide bandgap semiconductor. The back gate region 9 can be electrically connected to the well region 3 with low resistance.

[0025] The gate electrode 7 is a part of the groove 8 on the back gate region 9 and includes a part of the side surface 8b of the groove 8 facing the drain region 5, and is disposed via the interlayer insulating film 6. On the side surface of the part of the groove 8 where the gate electrode 7 and the interlayer insulating film 6 are disposed, the drift region 2, the well region 3, and the source region 4 are exposed. The gate electrode 7 faces the drift region 2, the well region 3, and the source region 4 via the interlayer insulating film 6.

[0026] As the material of the gate electrode 7, for example, polysilicon doped with a high concentration of N-type or P-type impurities can be used. Instead of polysilicon, other semiconductor materials such as silicon carbide (SiC) and silicon germanium (SiGe), or metal materials such as aluminum (Al) may be used. As the material of the interlayer insulating film 6, silicon oxide (SiO2) can be used.

[0027] The back gate electrode 15 is disposed in the remaining portion of the groove 8 on the back gate region 9. The back gate electrode 15 makes an ohmic connection to the back gate region 9 at the bottom 8a of the groove 8. The back gate electrode 15 makes an ohmic connection to the second electrode 11 on the main surface 1a of the semiconductor substrate 1. The back gate electrode 15 is electrically insulated from the gate electrode 7 by the interlayer insulating film 6. The back gate electrode 15 makes an ohmic connection to the source region 4 at the side surface 8b of the groove 8.

[0028] The first electrode 12 makes an ohmic connection to the drain region 5 on the main surface 1a of the semiconductor substrate 1. The second electrode 11 makes an ohmic connection to the source region 4 and the back gate electrode 15.

[0029] The interlayer insulating film 6 includes a first interlayer insulating film 6a and a second interlayer insulating film 6b. The first interlayer insulating film 6a is formed on the bottom 8a of the groove 8, the side surface 8b of the groove 8 parallel to the X-axis direction, which is the direction of the current flowing from the drain region 5 to the source region 4, and the side surface 8b of the groove 8 perpendicular to the X-axis direction facing the drain region 5. On the other hand, the second interlayer insulating film 6b is formed on the side surface 8b of the groove 8 perpendicular to the X-axis direction facing the back gate electrode 15. The thickness of the second interlayer insulating film 6b in contact with the back gate electrode 15 is thicker than the thickness of the first interlayer insulating film 6a in contact with the well region 3. By forming the second interlayer insulating film 6b thick, the capacitance between the back gate electrode 15 and the gate electrode 7 is reduced. For example, the film thickness of the first interlayer insulating film 6a is several tens of nm, and the film thickness of the second interlayer insulating film 6b is several hundreds of nm.

[0030] The impurity concentration of the semiconductor substrate 1 may be lower than the impurity concentration of the drift region 2. Alternatively, the semiconductor substrate 1 may be a semi-insulating semiconductor substrate. Thereby, when cooling the semiconductor device 100, an insulating material between the semiconductor device 100 and the cooler becomes unnecessary. The cooling performance is improved, and the attachment to the cooler can be facilitated. Also, when the semiconductor device 100 is off, the semiconductor substrate 1 and the first electrode 12 are not at the same potential. Therefore, a high electric field is not applied to the well region 3 or the back gate region 9 in contact with the semiconductor substrate 1 as compared with a conductive substrate. Thus, the breakdown voltage of the semiconductor device 100 is improved.

[0031] Next, the basic operation of the semiconductor device 100 shown in FIGS. 1 to 3 will be described.

[0032] The semiconductor device 100 operates as a transistor by controlling the potential of the gate electrode 7 with a positive potential applied to the first electrode 12 with reference to the potential of the second electrode 11. At this time, the potential of the P-type back gate region 9 is fixed by the back gate electrode 15, and the potential of the back gate electrode 15 is fixed by the second electrode 11. The potential of the well region 3 is fixed by the back gate region 9. When the potential difference between the gate electrode 7 and the second electrode 11 becomes equal to or higher than a predetermined threshold voltage, an inversion layer is formed at the interface between the P-type well region 3 in contact with the side surface 8b of the groove 8 and the first interlayer insulating film 6a (gate insulating film), the transistor becomes on state, and current flows from the first electrode 12 to the second electrode 11. Specifically, electrons supplied from the second electrode 11 flow into the drift region 2 through the inversion layer from the source region 4, and flow from the drift region 2 to the first electrode 12 through the drain region 5.

[0033] On the one hand, when the potential difference between the gate electrode 7 and the second electrode 11 becomes less than a predetermined threshold voltage, the inversion layer disappears, the transistor turns off, and the current is cut off. In the off state, a high voltage is applied between the first electrode 12 and the second electrode 11. As a result, a depletion layer spreads from the surface where the well region 3 and the drift region 2 are in contact into the drift region 2. The higher the voltage between the first electrode 12 and the second electrode 11, the wider the width of the depletion layer. When the voltage between the first electrode 12 and the second electrode 11 reaches a predetermined maximum voltage, the spread of the depletion layer stops. At this time, the distance between the drain region 5 and the well region 3 is designed so that the electric field applied inside the semiconductor device 100 is below the breakdown electric field of each material.

[0034] Next, the turn-on operation of the transistor will be described. Generally, when the transistor switches from the off state to the on state, it is preferable that the potential of the gate electrode 7 changes immediately to a predetermined potential. However, since there is a capacitance Cgs between the gate electrode 7 and the second electrode 11, the rise of the gate potential starts after the capacitance Cgs is charged. The power generated during this period becomes switching loss. To increase the potential of the gate electrode 7 quickly, it is preferable that the capacitance Cgs is small. Therefore, the thickness of the second interlayer insulating film 6b in contact with the back gate electrode 15 is made thicker than the thickness of the first interlayer insulating film 6a in contact with the well region 3. Thereby, the capacitance formed between the gate electrode 7 and the back gate electrode 15 can be reduced. Therefore, since the capacitance Cgs can be lowered, the gate potential is applied earlier, and the turn-on loss can be reduced.

[0035] When the semiconductor device 100 (transistor) is used in an inverter circuit for motor drive, even when the transistor is in the off state, the motor rotates due to inertia, and a reverse current may flow through the body diode built in the transistor. In the present embodiment, the body diode between the P-type well region 3 and the N-type drift region 2 functions as a freewheeling diode. The well region 3 is electrically connected to the second electrode 11 via the back gate region 9 and the back gate electrode 15. By forming the back gate electrode 15 of a material having a lower resistance than P-type silicon carbide, such as a metal material or the like, a semiconductor device 100 having a PN diode (body diode) with a built-in low resistance element can be provided. Therefore, the reverse current loss of the PN diode with a built-in element can be reduced.

[0036] In addition, according to the semiconductor device 100, the following operational effects can be obtained.

[0037] The back gate region 9 is disposed over the entire bottom 8a of the groove 8. For this reason, ion implantation can be performed on the bottom surface of the groove 8 using the mask used for forming the groove 8. Therefore, a dedicated mask for forming the back gate region 9 becomes unnecessary, and the influence on the semiconductor size due to the mask design rules is eliminated, so that the semiconductor device 100 can be miniaturized.

[0038] Furthermore, since the back gate electrode 15 has the same potential as the second electrode 11, the electrical resistance from the second electrode 11 to the well region 3 is also kept low, and the potential of the well region 3 is easily fixed.

[0039] The back gate electrode 15 can have the same potential as the second electrode 11 by making an ohmic contact with the source region 4 on the side surface 8b of the groove 8. Therefore, a semiconductor device 100 with a large contact area between the source region 4 and the second electrode 11 and low contact resistance can be provided.

[0040] The impurity concentration of the semiconductor substrate 1 may be lower than the impurity concentration of the drift region 2. Alternatively, the semiconductor substrate 1 may be a semi-insulating semiconductor substrate. As a result, when cooling the semiconductor device 100, it is not necessary to provide an insulating material for insulation between the semiconductor substrate 1 and the cooler, so the cooling performance is improved and the attachment to the cooler becomes easier. Further, when the semiconductor substrate 1 is a semi-insulating substrate, the semiconductor substrate 1 and the first electrode 12 are not at the same potential when the transistor is off. Therefore, compared with a conductive substrate, a high electric field is not applied to the well region 3 or the back gate region 9 in contact with the semiconductor substrate 1, so the breakdown voltage of the semiconductor device 100 is improved.

[0041] The back gate electrode 15 is formed of a metal material, and the semiconductor substrate 1 is made of silicon carbide. Since the electrical resistance of the metal material is lower than that of the well region 3 made of P-type silicon carbide, a low-resistance body diode can be formed.

[0042] [Method for manufacturing a semiconductor device] Next, with reference to FIGS. 4A to 11, an example of a method for manufacturing the semiconductor device 100 according to the present embodiment will be described.

[0043] First, a semiconductor substrate 1 without added impurities is prepared. As shown in FIGS. 4A and 4B, a drift region 2 is formed in the semiconductor substrate 1 by an ion implantation method. Specifically, N-type impurities are ion-implanted into the semiconductor substrate 1 to form a drift region 2 made of N-type silicon carbide. The implantation concentration is 1E14 cm -3 ~1E18 cm -3 and the thickness of the drift region 2 may be adjusted by the acceleration energy during ion implantation. The thickness of the drift region 2 is desirably several μm or less.

[0044] Note that the region to be ion-implanted may be patterned. In this case, ion implantation is performed using a mask material made of a silicon oxide film as a mask. Specifically, as the method for depositing the silicon oxide film, a thermal CVD method or a plasma CVD method can be used. A resist is patterned on the silicon oxide film (not shown). As the patterning method, a general photolithography method can be used. Using the patterned resist as a mask, the mask material is etched. As the etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. After etching the mask material, the resist is removed with oxygen plasma or sulfuric acid, etc. Using the mask material as a mask, N-type impurities such as nitrogen (N) are ion-implanted. By performing ion implantation while heating the semiconductor substrate 1 to about 600 °C, it is possible to suppress the occurrence of crystal defects in the implanted region. After ion implantation, the mask material is removed by etching using, for example, hydrofluoric acid. The cross-section after forming the drift region 2 is shown in FIGS. 4A and 4B.

[0045] Next, a P-type well region 3, an N-type source region 4, and an N-type drain region 5 are formed using an ion implantation method. As the formation order, it is preferable to first form the well region 3. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The method for patterning the region to be ion-implanted can be the same method as that for the drift region 2 described above. As the P-type impurity, aluminum (Al) or boron (B) can be used. As the N-type impurity, nitrogen (N) can be used. The impurity concentration of the source region 4 and the drain region 5 is preferably 1E18 cm -3 ~1E21 cm -3 is suitable. Also, the concentration of the well region 3 is preferably 1E15 cm -3 ~1E19 cm -3 is suitable.

[0046] Thereafter, the heat treatment process is used to activate the ion-implanted impurities. A heat treatment temperature of about 1700°C may be used. As the atmosphere during the heat treatment, argon (Ar) or nitrogen (N) can be preferably used. As a result, as shown in FIGS. 5A and 5B, a drift region 2, a well region 3, a source region 4, and a drain region 5 are formed above one main surface 1a of the semiconductor substrate 1.

[0047] Next, as shown in FIGS. 6A and 6B, a part of the semiconductor substrate 1 is etched to form a groove 8. Specifically, a mask material made of a silicon oxide film is formed and patterned. Using the patterned mask material as a mask, a part of the drift region 2, the well region 3, the source region 4, and the drain region 5 is etched by dry etching to form the groove 8. The groove 8 is formed deeper than the drift region 2 and shallower than the well region 3.

[0048] Next, using the mask used for forming the groove 8 as it is, a back gate region 9 is formed at the bottom of the groove 8. Specifically, P-type impurities are ion-implanted into the bottom of the groove 8 through the mask. As the P-type impurities, aluminum (Al) or boron (B) can be used. When implanting, by ion-implanting in a state where the temperature of the semiconductor substrate 1 is heated to about 600°C, it is possible to suppress the occurrence of crystal defects in the implanted region. After the ion implantation, the mask material is removed by hydrofluoric acid cleaning.

[0049] Next, the ion-implanted impurities are activated by heat treatment. A heat treatment temperature of about 1700°C can be used. As the atmosphere, argon or nitrogen can be preferably used. The cross-sectional structure after the heat treatment is shown in FIGS. 6A and 6B. A back gate region 9 made of P-type silicon carbide is formed over the entire bottom 8a of the groove 8.

[0050] Next, a first interlayer insulating film 6a is formed on the inner surface of the groove 8, that is, on the bottom 8a and the side surface 8b of the groove 8. The first interlayer insulating film 6a may be formed using a thermal oxidation method. The semiconductor substrate 1 is heated to about 1160°C in an oxygen atmosphere. A silicon oxide film is formed on all surfaces exposed to oxygen. The processing time is set so that a silicon oxide film with a thickness of several tens of nm is formed on the silicon carbide (2, 3, 4, 9) exposed on the bottom 8a and the side surface 8b of the groove 8. The first interlayer insulating film 6a on the main surface 1a of the semiconductor substrate 1 is selectively etched while leaving the first interlayer insulating film 6a on the inner surface of the groove 8. The cross-sectional structure after the first interlayer insulating film 6a is formed on the inner surface of the groove 8 is shown in FIGS. 7A and 7B.

[0051] After forming the first interlayer insulating film 6a, in order to reduce the interface states at the interface between the well region 3 and the first interlayer insulating film 6a, annealing may be performed at about 1000°C in an atmosphere such as nitrogen, argon, or N2O (nitrous oxide). Also, direct thermal oxidation in a NO (nitric oxide) or N2O atmosphere is possible. In that case, a temperature of 1100°C to 1400°C is suitable.

[0052] A gate electrode 7 is deposited inside the groove 8 surrounded by the first interlayer insulating film 6a. Poly-silicon is generally used as the material for the gate electrode 7. Here, an explanation will be given using poly-silicon. As a method for depositing poly-silicon, a low-pressure CVD method can be used. The deposition thickness of the poly-silicon is not limited, but it may be about 1μm. After depositing the poly-silicon, annealing in phosphoryl chloride (POCl3) forms a conductive N-type poly-silicon film. The annealing temperature is preferably 950°C. By leaving the poly-silicon film inside the groove 8 and etching the other poly-silicon films, as shown in FIGS. 8A and 8B, a gate electrode 7 is formed inside the groove 8 via the first interlayer insulating film 6a.

[0053] Next, as shown in FIG. 9, the gate electrode 7 of the remaining portion 8d of the groove 8 where the back gate electrode 15 is disposed is selectively etched. An anisotropic etching method can be used as the etching method. A resist may be used as the mask for etching. The gate electrode 7 remains in a part 8c of the groove 8, and the gate electrode 7 of the remaining portion 8d of the groove 8 is removed.

[0054] Next, a second interlayer insulating film 6b is formed inside the groove 8. As the forming method, a thermal oxidation method can be used. The semiconductor substrate 1 is heated in an oxygen atmosphere to a temperature of 1160° C. or lower, for example, about 1100° C. A silicon oxide film is formed at all portions exposed to oxygen. As shown in FIGS. 10A and 10B, a part of the polysilicon serving as the gate electrode 7 is thermally oxidized to form a part of the interlayer insulating film (second interlayer insulating film 6b). Specifically, a part of the side surface of the gate electrode 7 exposed by the etching of the gate electrode 7 is thermally oxidized to form the second interlayer insulating film 6b. A first interlayer insulating film 6a made of a silicon oxide film has already been formed on the side surface 8b of the groove 8 in the steps shown in FIGS. 7A and 7B. Therefore, oxidation does not proceed so much in the steps shown in FIGS. 10A and 10B. On the other hand, since the material of the gate electrode 7 is silicon and it is exposed to an oxygen atmosphere, the oxidation rate of the gate electrode 7 (polysilicon) is much faster than that of the side surface 8b of the groove 8. Thus, the second interlayer insulating film 6b having a thickness thicker than that of the first interlayer insulating film 6a can be formed.

[0055] As shown in FIG. 11, after the thermal oxidation process of the gate electrode 7 is performed, an etching process using diluted hydrofluoric acid is carried out. Thereby, while leaving the second interlayer insulating film 6b, the oxide film in contact with the inner surface of the remaining portion 8d of the groove 8 is removed, the back gate region 9 can be exposed on the bottom surface of the remaining portion 8d of the groove 8, and the source region 4 can be exposed on the side surface of the remaining portion 8d of the groove 8. At the same time, the second interlayer insulating film 6b on the gate electrode 7 is also removed.

[0056] Finally, the second electrode 11, the first electrode 12, and the back gate electrode 15 are formed simultaneously. As the electrode material, titanium (Ti), nickel (Ni), molybdenum (Mo), or a laminated film such as Ni / Ti / Al can be used. The deposition method of the electrode film can use the sputtering method. After depositing the electrode film, the electrode film is patterned using a mask material. Through the above manufacturing process, the semiconductor device 100 shown in FIGS. 1 to 3 is completed.

[0057] According to the manufacturing method of the semiconductor device 100, the following operational effects can be obtained.

[0058] In the manufacturing process shown in FIGS. 10A and 10B, polysilicon can be selectively oxidized by heat oxidation treatment at 1160°C or lower. The second interlayer insulating film 6b having a thickness thicker than that of the first interlayer insulating film 6a can be easily formed.

[0059] Since the back gate electrode 15 and the second electrode 11 can be manufactured in the same metal film forming process, the number of manufacturing processes is reduced and the manufacturing cost is reduced.

[0060] (Second Embodiment) [Structure of Semiconductor Device] FIG. 12 is a cross-sectional perspective view showing the structure of the semiconductor device 101 according to the second embodiment. FIG. 13 is a cross-sectional view of the semiconductor device 101 in the XZ plane including the XIII-XIII cut line of FIG. 12. The cross-sectional view of the semiconductor device 101 in the YZ plane including the III-III cut line of FIG. 12 is the same as FIG. 3. The semiconductor device 101 according to the second embodiment is different in that it further has a P-type electric field protection region 13A compared to the semiconductor device 100. The other configurations of the semiconductor device 101 are the same as those of the semiconductor device 100, and the same reference numerals are given in FIGS. 12 and 13, and the repeated description is omitted.

[0061] The electric field protection region 13A is formed in contact with the first interlayer insulating film 6a on the side surface 8b of the groove 8 facing the drain region 5. The length of the electric field protection region 13A in the Y-axis direction is approximately the same as that of the groove 8, and the side surface of the electric field protection region 13A parallel to the XZ plane and the side surface of the groove 8 may be flush. The length of the electric field protection region 13A in the Z-axis direction reaches the semiconductor substrate 1 deeper than the drift region 2 from the main surface 1a of the semiconductor substrate 1. The electric field protection region 13A is made of a wide-gap semiconductor such as silicon carbide, the same as the drift region 2, and a PN junction is formed between the electric field protection region 13A and the drift region 2. The electric field protection region 13A is a region where P-type impurities are added at a high concentration of 5E18 cm -3 or more.

[0062] When the voltage between the gate electrode 7 and the second electrode 11 is made below a predetermined threshold voltage, the transistor becomes an off state. At this time, a high voltage is applied between the first electrode 12 and the second electrode 11. At this time, an electric field concentrates in the drift region 2 in contact with the side surface 8b of the groove 8 facing the drain region 5, and the first interlayer insulating film 6a in contact with the side surface 8b of the groove 8 may be damaged. Therefore, a P-type electric field protection region 13A in contact with the first interlayer insulating film 6a is provided on the side surface 8b of the groove 8 facing the drain region 5. Since the P-type electric field protection region 13A alleviates the electric field concentration on the side surface 8b of the groove 8 facing the drain region 5, a semiconductor device 101 with high breakdown voltage can be provided.

[0063] The basic operation of the semiconductor device 101 and the turn-on operation of the transistor are the same as those of the first embodiment, and the description thereof is omitted.

[0064] According to the semiconductor device 101, the same operational effects as those of the semiconductor device 100 can be obtained.

[0065] [Method for manufacturing a semiconductor device] Next, an example of a method for manufacturing the semiconductor device 101 according to the present embodiment will be described.

[0066] As shown in FIGS. 4A and 4B, the process of forming the N-type drift region 2 in the semiconductor substrate 1 is the same as that in the first embodiment. Next, in the process of forming the P-type well region 3, the N-type source region 4, and the N-type drain region 5 shown in FIGS. 5A and 5B, a P-type electric field protection region 13A is formed. Specifically, as shown in FIG. 14, the P-type well region 3 can be formed first, and then the P-type electric field protection region 13A can be formed. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The impurity concentration of the electric field protection region 13A is different from that of the well region 3 and may be 1E18 cm -3 or more and 1E21 cm -3 or less. The implantation depth is deeper than the drift region 2 and reaches the semiconductor substrate 1. The activation process of the impurities after ion implantation is the same as that in the first embodiment.

[0067] As shown in FIG. 15, the groove 8 is formed such that the electric field protection region 13A appears on the side surface on the drift region 2 side. Next, using the mask used for forming the groove 8 as it is, a back gate region 9 is formed at the bottom of the groove 8. The cross-sectional structure in the YZ cross-section including the III-III cut line in FIG. 12 is the same as that in FIG. 6B, and the illustration is omitted.

[0068] Thereafter, the manufacturing process of the semiconductor device 101 is the same as the manufacturing process of the semiconductor device 100 described with reference to FIGS. 7A to 11, and the illustration and the description are omitted again.

[0069] According to the manufacturing method of the semiconductor device 101 described above, the same operational effects as those of the manufacturing method of the semiconductor device 100 can be obtained.

[0070] (Third Embodiment) [Structure of Semiconductor Device] FIG. 16 is a cross-sectional perspective view showing the structure of the semiconductor device 102 according to the third embodiment. FIG. 17 is a cross-sectional view of the semiconductor device 102 in the XZ plane including the cut line XVII-XVII of FIG. 16. The cross-sectional view of the semiconductor device 102 in the YZ plane including the cut line III-III of FIG. 16 is the same as FIG. 3. The semiconductor device 102 according to the third embodiment is different from the semiconductor device 100 in that it further has a P-type electric field protection region 13B. The electric field protection region 13B is formed in contact with the first interlayer insulating film 6a on the side surface 8b of the groove 8 facing the drain region 5. The length of the electric field protection region 13B in the X direction is longer than that of the electric field protection region 13A in FIGS. 12 and 13. The end portion of the electric field protection region 13B on the side of the first electrode 12 is located near the drain region 5. The lengths of the electric field protection region 13B in the Y-axis direction and the Z-axis direction are the same as those of the electric field protection region 13A. Different from the electric field protection region 13A, the electric field protection region 13B is a region doped with P-type impurities at the following concentration. -3 The region doped with the following concentration.

[0071] When the voltage between the gate electrode 7 and the second electrode 11 is made equal to or lower than a predetermined threshold voltage, the transistor is turned off. At this time, a high voltage is applied between the first electrode 12 and the second electrode 11. At this time, a depletion layer spreads from the interface where the well region 3 and the drift region 2 are in contact into the drift region 2. Further, depletion layers spread from the interface where the electric field protection region 13B and the drift region 2 are in contact into the drift region 2 and the electric field protection region 13B, respectively. The higher the voltage between the first electrode 12 and the second electrode 11, the wider the width of the depletion layer, and the drift region 2 and the electric field protection region 13B are in a completely depleted state (pinch-off state). By entering the pinch-off state, a superjunction structure is formed between the electric field protection region 13B and the drift region 2. Thereby, while increasing the impurity concentration of the drift region 2 and reducing the resistivity, the breakdown voltage of the transistor can be maintained high. That is, a semiconductor device 102 with high breakdown voltage and low resistance can be provided.

[0072] Other configurations, operations, and technical effects are the same as those of the semiconductor device 101, and the same reference numerals are given in FIGS. 16 and 17, and the repeated description is omitted. [Method for manufacturing a semiconductor device] Next, an example of a method for manufacturing the semiconductor device 102 according to the present embodiment will be described.

[0073] As shown in FIGS. 4A and 4B, the process of forming the N-type drift region 2 in the semiconductor substrate 1 is the same as that in the first embodiment. Next, in the process of forming the P-type well region 3, the N-type source region 4, and the N-type drain region 5 shown in FIGS. 5A and 5B, a P-type field protection region 13B is formed. Specifically, as shown in FIG. 18, the P-type well region 3 may be formed first, and then the P-type field protection region 13B may be formed. Thereafter, the source region 4 and the drain region 5 may be formed simultaneously. The impurity concentration of the field protection region 13B is different from that of the well region 3 and is 1E17 cm -3 above 1E18 cm -3 below. The implantation depth may be deeper than the drift region 2 and reach the semiconductor substrate 1. The activation process of the impurities after ion implantation is the same as that in the first embodiment.

[0074] As shown in FIG. 19, the groove 8 is formed such that the field protection region 13B appears on the side surface on the drift region 2 side. The cross-sectional structure in the YZ cross-section including the III-III cutting line in FIG. 16 is the same as that in FIG. 6B, and the illustration is omitted.

[0075] The subsequent manufacturing process of the semiconductor device 102 is the same as the manufacturing process of the semiconductor device 100 described with reference to FIGS. 7A to 11, and the illustration and description are omitted.

[0076] According to the method for manufacturing the semiconductor device 102 described above, the same operational effects as those of the method for manufacturing the semiconductor device 100 can be obtained.

[0077] As described above, the embodiments of the present invention have been described, but it should not be understood that the discussions and drawings forming a part of this disclosure limit this invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0078] As a method for forming the drift region 2, a method of ion implantation into the semiconductor substrate 1 has been described. However, the drift region 2 made of single-crystalline SiC may be grown on the main surface of the semiconductor substrate 1 by using an epitaxial growth method.

Explanation of Reference Numerals

[0079] 1 Semiconductor substrate 1a Main surface 2 Drift region 3 Well region 4 Source region 5 Drain region 6 Interlayer insulating film 6a First interlayer insulating film 6b Second interlayer insulating film 7 Gate electrode 8 Groove 8a Bottom 8b Side surface 8c Part 8d Remaining part 9 Back gate region 11 Second electrode 12 First electrode 13A, 13B Electric field protection region 15 Back gate electrode 100 - 102 Semiconductor device

Claims

1. A semiconductor substrate, A drift region of a first conductivity type formed in contact with one main surface of the semiconductor substrate, A well region of a second conductivity type formed in contact with the drift region, A drain region of a first conductivity type formed in the drift region separated from the well region, A first electrode electrically connected to the drain region, A source region of a first conductivity type formed in the well region, A back gate region of a second conductivity type disposed at the bottom of a groove formed in contact with the source region, the well region, and the drift region and in contact with the well region, A gate electrode disposed via an interlayer insulating film in a part of the groove on the back gate region, the part including a side surface of the groove facing the drain region, A back gate electrode disposed in a remaining part of the groove on the back gate region and ohmically connected to the back gate region, A second electrode electrically connected to the source region and the back gate electrode, A semiconductor device having the above.

2. The semiconductor device according to claim 1, wherein a thickness of the interlayer insulating film in contact with the back gate electrode is thicker than a thickness of the interlayer insulating film in contact with the well region.

3. The semiconductor device according to claim 1, further comprising a protection region of a second conductivity type in contact with the interlayer insulating film on a side surface of the groove facing the drain region.

4. The semiconductor device according to claim 1, wherein the back gate electrode is ohmically connected to the source region on a side surface of the groove.

5. The semiconductor device according to claim 1, wherein an impurity concentration of the semiconductor substrate is lower than an impurity concentration of the drift region, or the semiconductor substrate is a semi-insulating semiconductor substrate.

6. The semiconductor substrate is made of silicon carbide, The back gate electrode is made of a metal material. The semiconductor device according to claim 1.

7. The semiconductor substrate is made of silicon carbide, It has a thermal oxidation process of forming a part of the interlayer insulating film by thermally oxidizing a part of the polysilicon serving as the gate electrode, The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the thermal oxidation process is performed at a temperature of the semiconductor substrate of 1160 ° C or lower.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the second electrode and the back gate electrode are formed in the same manufacturing process.

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