Semiconductor device

Abstract

To provide a semiconductor device with a reduced occupied area that is capable of operating at low power and can retain data even when power supply is interrupted.SOLUTION: A semiconductor device includes a first transistor 101, a second transistor 102, and a first capacitor 103. The semiconductor device writes data by storage of charge in the capacitor via the second transistor, and retains data by making the second transistor an off state. The transistor having a gate connected to a holding node between the second transistor and the capacitor reads the data without damaging the data. The semiconductor device has the configuration where the second transistor and the capacitor are provided overlapping with the first transistor, and the gate of the first transistor is electrically connected to one electrode of the second transistor and one electrode of the capacitor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including memory devices, electro-optical devices, semiconductor circuits, electronic components, and electronic equipment. This is one aspect of a semiconductor device. [Background technology]

[0003] One of the semiconductor devices that uses semiconductor elements is a memory device. Volatile memory devices lose their contents when the power supply is cut off, while non-volatile memory devices retain their contents even when the power supply is cut off. They can be broadly classified into non-volatile memory devices that store information and non-volatile memory devices that store information.

[0004] A typical example of a volatile memory device is a dynamic random access memory (DRAM). Access Memory) and SRAM (Static Random Access These volatile storage devices are Although the contents of the memory are lost, the power consumption is low because it does not require a large voltage like non-volatile memory. is relatively small.

[0005] DRAM can apply one transistor and one capacitance to one memory element, so it can occupy The area can be reduced, but the data retention period is extremely short and refresh operations must be performed frequently. This means that power consumption cannot be reduced sufficiently.

[0006] SRAM is capable of high speed operation, but each memory element requires at least six transistors. In addition, as transistors become smaller, Since the off-current of the transistor increases, the power consumption during the data retention period cannot be sufficiently reduced, which is a problem.

[0007] A typical example of a non-volatile memory device is a flash memory. A flash memory is a memory device that has a semi-permanent data retention period by holding charges in a floating gate (see, for example, Patent Document 1). However, since a high voltage is required for writing and erasing, the flash memory has high power consumption and also has a problem that it is not easy to speed up these operations. Furthermore, since a high electric field is applied to an insulating film to generate a tunneling current for injecting charges into the floating gate for writing and erasing, there is also a problem that the insulating film deteriorates as the number of rewrites increases.

[0008] In recent years, transistors fabricated using oxide semiconductors with a large bandgap have been found to have extremely high off-resistance, and it has been proposed to fabricate memory elements and signal processing circuits that constitute a memory device using this (see Patent Documents 2 to 4).

[0009] Since these memory elements have a high off-resistance of the transistor, it takes a long time for the charges stored in the capacitive element connected in series with the transistor to disappear, and the consumption of the current for memory retention required in a flip-flop circuit included in a normal SRAM or the like can be reduced, and thus the power consumption can be further reduced. Alternatively, since an extremely large capacitive element as required in a DRAM is not necessary, the circuit can be miniaturized, and the manufacturing process can be simplified and the yield can be improved. .

Prior Art Documents

Patent Documents

[0010] Patent Document 1 Japanese Patent Application Laid-Open No. 57-105889 Patent Document 2 U.S. Patent Application Publication No. 2011 / 0121878 Patent Document 3 U.S. Patent Application Publication No. 2011 / 0134683 Patent Document 4 U.S. Patent Application Publication No. 2011 / 0175646 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] In recent years, with the high integration of elements constituting semiconductor devices, reduction in the occupied area of such elements has been demanded. By reducing the occupied area of semiconductor devices, the number of devices per substrate can be increased, and the cost per semiconductor device can be reduced. In a memory device, the smaller the occupied area of the memory elements, the higher the density at which the memory elements can be arranged, and the larger the data amount per unit area can be increased. In addition, in order to reduce the power consumption of devices to which semiconductor devices are applied, semiconductor devices capable of operating at low power are demanded. From such a viewpoint, in a memory device, it is required to be able to hold data even when the power supply is stopped. The present invention has been made under such a technical background. Therefore, one aspect of the present invention is to provide a semiconductor device with a reduced occupied area. Or, one aspect of the present invention is to provide a semiconductor device capable of operating at low power. Or, one aspect of the present invention is to provide a semiconductor device in which the supply of power is stopped. and data can still be retained.

[0012] Also, in order to achieve low power consumption of the equipment to which the semiconductor device is applied, a semiconductor device capable of operating at low power is required. From this perspective, in a memory device, it is required to be able to retain data even when the power supply is stopped. The present invention has been made under such a technical background. Therefore, one aspect of the present invention is to provide a semiconductor device with a reduced occupied area as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device capable of operating at low power as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device in which the supply of power is stopped.

[0013] The present invention has been made under such a technical background. Therefore, one aspect of the present invention is to provide a semiconductor device with a reduced occupied area as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device capable of operating at low power as one of the problems. Or, one aspect of the present invention is to provide a semiconductor device in which the supply of power is stopped. Another aspect of the present invention is to provide a semiconductor device with a reduced occupied area. Or, another aspect of the present invention is to provide a semiconductor device capable of operating at low power. Or, another aspect of the present invention is to provide a semiconductor device in which the supply of power is stopped. ​​​One of the problems is to provide a semiconductor device capable of retaining data even when stopped.

[0014] One aspect of the present invention solves at least one of the above problems.

Means for Solving the Problem

[0015] The semiconductor device according to one aspect of the present invention includes a first transistor, a second transistor, and a configuration having a single capacitance. It has a configuration with a single capacitance.

[0016] Also, the semiconductor device writes data by accumulating charge in the capacitance via the second transistor, and retains the data by turning off the second transistor. Further, the potential of the node (also referred to as the holding node) between the second transistor and the capacitance is applied to the gate electrode of the first transistor. By detecting the conduction state of the first transistor, reading can be performed without destroying the data. It writes data by accumulating charge in the capacitance via the second transistor, and retains the data by turning off the second transistor. Also, the potential of the node (also referred to as the holding node) between the second transistor and the capacitance is applied to the gate electrode of the first transistor. By detecting the conduction state of the first transistor, reading can be performed without destroying the data. Also, the potential of the node (also referred to as the holding node) between the second transistor and the capacitance is applied to the gate electrode of the first transistor. By detecting the conduction state of the first transistor, reading can be performed without destroying the data. Also, the potential of the node (also referred to as the holding node) between the second transistor and the capacitance is applied to the gate electrode of the first transistor. By detecting the conduction state of the first transistor, reading can be performed without destroying the data. By detecting the conduction state of the first transistor, reading can be performed without destroying the data.

[0017] Furthermore, the second transistor and the capacitance are provided so as to overlap on the first transistor. More preferably, they are provided so as to overlap with the gate electrode constituting the first transistor. Also, one electrode (either the source electrode or the drain electrode) of the second transistor and one electrode of the capacitance are configured to be electrically connected to the gate electrode of the first transistor. Furthermore, the second transistor and the capacitance are provided so as to overlap on the first transistor. More preferably, they are provided so as to overlap with the gate electrode constituting the first transistor. Also, one electrode (either the source electrode or the drain electrode) of the second transistor and one electrode of the capacitance are configured to be electrically connected to the gate electrode of the first transistor. Furthermore, the second transistor and the capacitance are provided so as to overlap on the first transistor. More preferably, they are provided so as to overlap with the gate electrode constituting the first transistor. Also, one electrode (either the source electrode or the drain electrode) of the second transistor and one electrode of the capacitance are configured to be electrically connected to the gate electrode of the first transistor. Furthermore, the second transistor and the capacitance are provided so as to overlap on the first transistor. More preferably, they are provided so as to overlap with the gate electrode constituting the first transistor. Also, one electrode (either the source electrode or the drain electrode) of the second transistor and one electrode of the capacitance are configured to be electrically connected to the gate electrode of the first transistor.

[0018] That is, the semiconductor device according to one aspect of the present invention includes a first transistor, a second transistor, and a capacitance. The first transistor includes a first semiconductor layer, a first insulating layer in contact with the first semiconductor layer, and a first electrode layer in contact with the first insulating layer and overlapping the first semiconductor layer. Also, the second transistor is provided so as to overlap on the first electrode layer, and the first... The first transistor includes a first semiconductor layer, a first insulating layer in contact with the first semiconductor layer, and a first electrode layer in contact with the first insulating layer and overlapping the first semiconductor layer. Also, the second transistor is provided so as to overlap on the first electrode layer, and the first... The first transistor includes a first semiconductor layer, a first insulating layer in contact with the first semiconductor layer, and a first electrode layer in contact with the first insulating layer and overlapping the first semiconductor layer. Also, the second transistor is provided so as to overlap on the first electrode layer, and the first... The first transistor includes a first semiconductor layer, a first insulating layer in contact with the first semiconductor layer, and a first electrode layer in contact with the first insulating layer and overlapping the first semiconductor layer. Also, the second transistor is provided so as to overlap on the first electrode layer, and the first... A second semiconductor layer electrically connected to the electrode layer, a second insulating layer in contact with a side surface of the second semiconductor layer, a second electrode layer in contact with the second insulating layer and covering at least a part of the side surface of the second semiconductor layer, and a third electrode layer provided on the second semiconductor layer and electrically connected to the second semiconductor layer. Further, the capacitor has a fourth electrode layer overlapping the first electrode layer and a dielectric layer between the first electrode layer and the fourth electrode layer.

[0019] By adopting such a configuration, a semiconductor device with a reduced occupied area can be realized.

[0020] Furthermore, when writing or erasing data to the semiconductor device, only a voltage sufficient to turn on the second transistor is required, eliminating the need for the high voltage required in flash memories. Therefore, a semiconductor device capable of operating at extremely low power can be achieved.

[0021] Also, the first semiconductor layer in the semiconductor device is preferably composed of single crystal silicon.

[0022] By adopting such a configuration, the read operation of data held in the semiconductor device can be performed extremely fast.

[0023] Also, a semiconductor device according to another aspect of the present invention includes a first transistor, a second transistor, and a capacitor. The first transistor includes a fifth electrode layer, a first semiconductor layer provided to overlap the fifth electrode layer and electrically connected to the fifth electrode layer, a first insulating layer in contact with a side surface of the first semiconductor layer, and a second electrode layer in contact with the first insulating layer and covering at least a part of the side surface of the first semiconductor layer. a first electrode layer that partially covers; and a sixth electrode layer provided on the first semiconductor layer and electrically connected to the first semiconductor layer. Further, the second transistor is provided on the first electrode layer in a stacked manner, and includes a second semiconductor layer that is electrically connected to the first electrode layer, a second insulating layer that contacts a side surface of the second semiconductor layer, a second electrode layer that contacts the second insulating layer and covers at least a part of the side surface of the second semiconductor layer, and a third electrode layer that is provided on the second semiconductor layer and electrically connected to the second semiconductor layer. Furthermore, the capacitor includes a fourth electrode layer that overlaps the first electrode layer, and a dielectric layer between the first electrode layer and the fourth electrode layer. By adopting such a configuration, the occupied area of the first transistor itself can be reduced, so that the occupied area of the semiconductor device itself can be further reduced. In any of the above semiconductor devices, the second semiconductor layer preferably includes a semiconductor having a wider bandgap than silicon. In this way, a transistor with a reduced off-current can be used as the second transistor. Therefore, even when the power supply is stopped, the potential held in the holding node can be maintained for a long period of time. Thus, a semiconductor device capable of retaining data even when the power supply is stopped can be achieved. Also, the semiconductor of the second semiconductor layer is preferably an oxide semiconductor. Further, the oxide semiconductor preferably contains In, Ga, and Zn.

[0024]

[0025]

[0026]

[0027]

[0028]

[0029] ​​​​​​​​​​​Thus, in particular, it is preferable to use an oxide semiconductor as the semiconductor forming the channel of the second transistor. An oxide semiconductor having a wider band gap than silicon can achieve a low off-current. In particular, when an oxide semiconductor containing In, Ga, and Zn is used for the transistor, even an amorphous oxide semiconductor formed at a relatively low temperature has good electrical characteristics (such as high field-effect mobility and small S value) and high reliability compared to other oxide semiconductors, which is preferable. Here, for example, zinc oxide, which is one of the oxide semiconductors, tends to be in a polycrystalline state at a low temperature, and it is difficult to obtain electrical characteristics such as desired field-effect mobility and S value due to its grain boundaries.

[0030]

[0031] In the semiconductor device to which a semiconductor having a wider band gap than the above silicon is applied, the dielectric layer is preferably formed of the same film as the second semiconductor layer.

[0032] Since the semiconductor used for the second semiconductor layer has an extremely high resistance value, it can also be used as the dielectric layer constituting the capacitor. Therefore, by adopting the above-described configuration, a second transistor and a capacitor can be formed on the gate electrode of the first transistor by a common process. Therefore, the manufacturing process of the semiconductor device can be simplified, and a semiconductor device with low cost and high yield can be realized.

[0033] In any of the above semiconductor devices, it is preferable to provide a driving circuit below the first transistor.

[0034] ​​​​​​​​​​​​​In this way, by forming a semiconductor device having a driver circuit in the lower part, In comparison with the case where the configuration of the second transistor or the capacitor and the drive circuit are arranged without overlapping each other, As a result, the area occupied by the semiconductor device can be reduced.

[0035] In any one of the above semiconductor devices, the first transistor and the second transistor It is preferable that a plurality of layers of the semiconductor device including the capacitor and the capacitor are stacked.

[0036] In this manner, a plurality of semiconductor devices according to one embodiment of the present invention can be stacked. By using such a stacked semiconductor device, it is possible to achieve extremely high integration of the semiconductor device. This makes it possible to significantly increase the amount of data that can be stored per occupied area of ​​a semiconductor device. Cut.

[0037] Note that in this specification, a memory device is one embodiment of a semiconductor device. It also refers to a device that at least retains the stored state of data. A device including a plurality of storage devices is also an aspect of the storage device. The driving circuit and the module on which the IC (integrated circuit) is mounted are also included in the memory device. do. Effect of the Invention

[0038] According to the present invention, it is possible to provide a semiconductor device that occupies a reduced area. In addition, a semiconductor device capable of retaining data even when the power supply is stopped can be provided. A body device can be provided. [Brief description of the drawings]

[0039]

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Embodiments for Carrying Out the Invention

[0040] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. However, the present invention should not be construed as being limited to the above description. In the drawings, the same reference numerals are used to denote the same parts or parts having similar functions. , and a repeated explanation will be omitted.

[0041] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0042] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0043] In addition, the functions of "source" and "drain" may differ when using transistors with different polarities. In some cases, such as when the direction of the current changes during circuit operation, the two may be interchanged. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably. It is possible.

[0044] In this specification, either the source or the drain of a transistor The first electrode is called the source or drain, and the other is called the second electrode. It may also be referred to as the "pole" or the "second electrode". Also, for the gate, it is also called "gate" or "gate electrode".

[0045] Also, in this specification and the like, "electrically connected" includes the case where it is connected through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, coils, capacitance elements, and other elements having various functions. For example, "something having some electrical action" includes electrodes, wiring, switching elements such as transistors, resistance elements, coils, capacitance elements, and other elements having various functions. is included.

[0046] Note that in this specification and the like, a node refers to an element (such as wiring) that enables the electrical connection of elements constituting a circuit. Therefore, "the node to which A is connected" refers to the wiring that is electrically connected to A and can be regarded as having the same potential as A. Note that even if one or more elements (such as switches, transistors, capacitance elements, inductors, resistance elements, diodes, etc.) that enable electrical connection are arranged in the middle of the wiring, as long as it has the same potential as A, that wiring can be regarded as the node to which A is connected. resistance elements, diodes, etc.) that enable electrical connection are arranged in the middle of the wiring, as long as it has the same potential as A, that wiring can be regarded as the node to which A is connected.

[0047] Note that in this specification and the like, when two or more components are formed simultaneously of the same material, these components are defined to exist as the same layer. For example, when one layer is formed and then processed into components A and B by etching or the like, these are components that exist as the same layer. layer is formed and then processed into components A and B by etching or the like, these are components that exist as the same layer.

[0048] (Embodiment 1) In the present embodiment, as an example of a semiconductor device according to an aspect of the present invention, a configuration example of a memory device will be described with reference to the drawings. Hereinafter, it will be described with reference to the drawings.

[0049] FIG. 1(A) is a circuit diagram of a main part of a memory device according to an aspect of the present invention. The memory device includes a transistor 101, a transistor 102, and a capacitor 103.

[0050] The memory device includes a node (holding node R) to which the gate electrode of the transistor 101, the first electrode of the transistor 102, and one electrode of the capacitor 103 are electrically connected. Hereinafter, it will be described with reference to the drawings. is provided.

[0051] Also, a wiring electrically connected to the first electrode of the transistor 101 is defined as wiring S2, and a wiring electrically connected to the second electrode is defined as wiring D. Further, a wiring electrically connected to the gate electrode of the transistor 102 is defined as wiring W1, and a wiring electrically connected to the second electrode is defined as wiring S1. Also, a wiring electrically connected to the second electrode of the transistor 102 is defined as wiring S1. Also, a wiring electrically connected to the gate electrode of the transistor 102 is defined as wiring W1, and a wiring electrically connected to the second electrode is defined as wiring S1. Also, a wiring electrically connected to the other electrode of the capacitor 103 is defined as wiring W2.

[0052] When writing data to the memory device, a potential for turning on the transistor 102 is input to the wiring W1, and a predetermined potential is input from the wiring S1 to the second electrode of the transistor 102. Thereby, a predetermined potential can be written to the holding node R via the transistor 102. Thereafter, when a potential for turning off the transistor 102 is input to the wiring W1, the potential written to the holding node R is held. is held. Thereafter, when a potential for turning off the transistor 102 is input to the wiring W1, the potential written to the holding node R is held.

[0053] Also, depending on the potential held in the holding node R, the transistor 101 having its gate electrode connected to the holding node R takes either an on state or an off state. Therefore, the transistor 101 having its gate electrode connected to the holding node R takes either an on state or an off state. Therefore, A potential for reading is input to one of the wirings S2 and D, and the potential of the other is detected. In this way, reading can be performed.

[0054] In this way, when writing or erasing data to or from a storage device according to one embodiment of the present invention, A voltage sufficient to turn on the transistor 102 is used. In other words, the hold node The voltage required to write to R controls the on or off state of transistor 101. Therefore, in driving the memory device of one embodiment of the present invention, Unlike flash memory, it does not require high voltage, so it is a memory with extremely low power consumption. A memory device can be realized.

[0055] Here, the transistor 102 is a transistor using silicon as a semiconductor in which a channel is formed. A transistor that has a reduced leakage current (off current) in the off state compared to a transistor. Specifically, a silicon semiconductor is used as the semiconductor in which the channel is formed. The transistor uses a semiconductor with a wider band gap than silicon. Compound semiconductors are semiconductors that have a band gap. For example, oxide semiconductors and nitride semiconductors semiconductors, etc.

[0056] Specifically, to obtain a very high off-resistance, silicon (band gap 1.1 A band gap of 2.5 to 4 electron volts is preferred. It is preferable to use a wide band gap semiconductor having a voltage of 3 electron volts or more and 3.8 electron volts or less. For example, oxide semiconductors such as indium oxide and zinc oxide, gallium nitride, etc. or a sulfide semiconductor such as zinc sulfide.

[0057] In particular, it is preferable to use an oxide semiconductor as the semiconductor constituting the channel of the transistor 102. The oxide semiconductor has a large energy gap of 3.0 eV or more. In a transistor obtained by processing the oxide semiconductor under appropriate conditions, the leakage current (off-current) per channel width of 1 μm between the source and the drain in the off state is 100 zA (1 × 10 A) or less, or 10 zA (1 × 10 A) or less, and further 1 zA (1 × 10 -19 A) or less, at a voltage of 3.5 V between the source and the drain under the temperature conditions during use (for example, 25°C). -20 Therefore, a semiconductor device with low power consumption can be realized. (1 × 10 -21 A) or less.

[0058] In particular, when an oxide semiconductor containing In, Ga, and Zn is used for the transistor, even an amorphous oxide semiconductor formed at a relatively low temperature has good electrical characteristics (such as high field-effect mobility and small S value) and high reliability compared to other oxide semiconductors. Therefore, it is preferable. Here, for example, zinc oxide, which is one of the oxide semiconductors, tends to be in a polycrystalline state at low temperatures, and it is difficult to obtain electrical characteristics such as desired field-effect mobility and S value due to its grain boundaries.

[0059] Thus, by applying a transistor with a reduced off-current to the transistor 102, the potential held at the holding node R can be held for a long period. Furthermore, data can be held even when the power supplied to the memory device is stopped.

[0060] FIG. 1(B) is a schematic diagram of a memory device according to an aspect of the present invention.

[0061] The memory device is provided with the transistor 102 and the capacitor 103 stacked on the transistor 101. They are stacked.

[0062] The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115. The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115. The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115. The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115. The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115. The transistor 101 is a transistor in which a single-crystal semiconductor is applied to a semiconductor in which a channel is formed. The transistor 101 includes a semiconductor layer 115, a first electrode layer 112 and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111 that contacts the gate insulating layer 114 and overlaps the channel formation region of the semiconductor layer 115. The channel direction of the transistor 101 is parallel to the upper surface of the semiconductor layer 115.

[0063] The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115. The transistor 102 is provided on the gate electrode layer 111 and includes a semiconductor layer 125 that is electrically connected to the gate electrode layer 111, an electrode layer 122 that is provided on the semiconductor layer 125 and is electrically connected to the semiconductor layer 125, a gate insulating layer 124 that contacts the side surface of the semiconductor layer 125, and a gate electrode layer 121 that contacts the gate insulating layer 124 and is provided opposite to the side surface of the semiconductor layer 125. The transistor 102 is a so-called vertical transistor. Therefore, the channel direction of the transistor 102 is perpendicular to the channel direction of the transistor 101 and the upper surface of the semiconductor layer 115.

[0064] The capacitor 103 includes an electrode layer 132 provided on the gate electrode layer 111 and a dielectric layer 134 sandwiched between the gate electrode layer 111 and the electrode layer 132. Therefore, the channel of the transistor 101 is the semiconductor layer 125 of the transistor 102 and the dielectric of the capacitor 103. The capacitor 103 includes an electrode layer 132 provided on the gate electrode layer 111 and a dielectric layer 134 sandwiched between the gate electrode layer 111 and the electrode layer 132. Therefore, the channel of the transistor 101 is the semiconductor layer 125 of the transistor 102 and the dielectric of the capacitor 103. The capacitor 103 includes an electrode layer 132 provided on the gate electrode layer 111 and a dielectric layer 134 sandwiched between the gate electrode layer 111 and the electrode layer 132. Therefore, the channel of the transistor 101 is the semiconductor layer 125 of the transistor 102 and the dielectric of the capacitor 103. It overlaps with the electric layer 134.

[0065] Here, the electrode layer 122 is electrically connected to the wiring S1 in FIG. 1(A). Similarly, the gate electrode layer 121 is connected to the wiring W1, the electrode layer 132 is connected to the wiring W2, and the first electrode layer 112 is connected to the wiring S2, and the second electrode layer 113 is electrically connected to the wiring D, respectively. Also, the gate elec trode layer 111 corresponds to the holding node R.

[0066] As shown in FIG. 1(B), by laminating the transistor 102, which is a vertical transistor, and the capacitor 103 on the gate electrode layer 111 of the transistor 101, a memory device with a reduced occupied area can be realized. Also, by configuring the gate electrode layer 111 to also serve as one electrode of the transistor 10 2 and one electrode of the capacitor 103, the configuration of the memory device is simplified, and fabrication at a lower cost becomes possible. In particular, by applying a single-crystal semiconductor to the transistor 101 that performs the read operation,

[0067] the read operation can be accelerated.

[0068] Also, when a material with a wider bandgap than silicon is used as the semiconductor for the semiconductor layer 125, since the resistance value of the material is extremely high, it can also be used as the dielectric layer that constitutes the capacitor. At this time, as shown in FIG. 1(B), it is preferable to apply the dielectric layer 134 made of the same material as the semiconductor layer 1 25 of the transistor 102 to the capacitor 103. That is, it is preferable that the semiconductor layer 125 and the dielectric layer 134 exist as the same layer. By adopting such a configuration, the transistor 102 and the capacitor 103 can be fabricated by a common fabrication process. This makes it possible to simplify the manufacturing process of the memory device, achieving a low-cost and high-yield memory device.

[0069] Also, as shown in Fig. 2(A), a thin film of an insulating material may be used as the dielectric layer 134 with a capacitance of 103. By using a thin film of an insulating material for the dielectric layer 134, the thickness of the dielectric layer 134 can be made thin, so that the capacitance value of the capacitance 103 can be increased.

[0070] Here, the channel length of the transistor 102 can be controlled by changing the thickness of the semiconductor layer 125. Therefore, even when the line widths of the gate electrode layer 111, the electrode layer 122, etc. become extremely small with miniaturization, an arbitrary channel length can be set according to the thickness of the semiconductor layer 125.

[0071] Also, in Fig. 1(B) and Fig. 2(A), the semiconductor layer 125 is shown as a prismatic shape, but it can also have a different shape. Fig. 2(B) shows a schematic diagram when the shape of the semiconductor layer 125 is a cylindrical shape. Fig. 2(C) is a diagram in which the gate electrode layer 121 and the gate insulating layer 124 in Fig. 2(B) are shown by broken lines.

[0072] If the shape of the semiconductor layer 125 is, for example, a prismatic shape, the effective width of the channel formed near its side surface can be increased, so that the on-current of the transistor 102 can be increased. Also, as shown in Fig. 2(B) and Fig. 2(C), when the semiconductor layer 125 is cylindrical, there is no protruding portion on its side surface, so that the gate electric field is uniformly applied to the entire side surface, resulting in a highly reliable transistor 102. Also, for example, further When it is desired to increase the current, the shape of the bottom surface of the semiconductor layer 125 is, for example, a star-shaped polygon , and at least one interior angle is a polygon exceeding 180° (concave polygon), and the effective channel width may be increased.

[0073] Also, in FIG. 1(B), the gate electrode layer 121 is provided to face a part of the side surface of the semiconductor layer 125 via the gate insulating layer 124. However, it is sufficient that at least a part of the side surface of the semiconductor layer 125 is covered. For example, the gate electrode layer 121 may be configured to surround the outside of the semiconductor layer 125, or the gate electrode layer 121 may be provided only on one side surface of the semiconductor layer 125, and the integration degree can be increased. As shown in FIGS. 2(B) and 2(C), if the side surface of the semiconductor layer 125 is surrounded, the effective channel width of the transistor 102 can be increased, so that the on-current can be increased.

[0074] In the memory device exemplified in this embodiment, the transistor 102 and the capacitor 103 are stacked on the transistor 101, and a vertical transistor is applied as the transistor 102. Therefore, it is a memory device with an extremely reduced occupied area. Furthermore, since a high voltage is not required as the voltage used for writing and erasing, it is a memory device that can operate with extremely low power consumption.

[0075] Also, by applying a transistor with a reduced off-current as the transistor 102, data can be retained even when the power supply is stopped, and a memory device that can retain data for an extremely long period can be realized.

[0076] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. ​

[0077] (Embodiment 2) In this embodiment, as an example of a semiconductor device according to one aspect of the present invention, another configuration example of a memory device will be described with reference to the drawings. Note that descriptions of parts overlapping with the above embodiment will be omitted or simplified.

[0078] <Configuration Example> FIG. 3(A) is a circuit diagram of a main part of a memory device exemplified in this embodiment.

[0079] Here, a configuration including two transistors and one capacitor is collectively referred to as one memory element.

[0080] The memory device shown in FIG. 3(A) includes a memory element 110a including a transistor 101a, a transistor 102a, and a capacitor 103a, and a memory element 110b including a transistor 101b, a transistor 102b, and a capacitor 103b. The configurations of the memory element 110a and the memory element 110b can be the same as those of the memory device exemplified in Embodiment 1.

[0081] Wiring W1 that is electrically connected to each gate of the transistor 102a and the transistor 102b, and wiring W2 that is electrically connected to one electrode of each of the capacitors 103a and 103b, wiring S11 that is electrically connected to the first electrode of the transistor 102a and the first electrode of the transistor 101a, wiring S12 that is electrically connected to the first electrode of the transistor 102b and the first electrode of the transistor 101b, and wiring S2 that is electrically connected to the second electrode of each of the transistors 101a and 101b are connected to the memory device.

[0082] ​​​ In this way, by sharing the wiring S1 and the wiring D exemplified in the first embodiment as the wiring S11 (or wiring S12), and sharing the wiring S2 between adjacent memory elements, the number of wirings can be reduced.

[0083] Here, for simplicity, the configuration including two memory elements is described with reference to FIG. 3(A). Actually, it is preferable that pairs of these two memory elements are periodically arranged along the wiring W1, the wiring S2, etc.

[0084] Next, the operation of the memory device shown in FIG. 3(A) will be described.

[0085] When writing, a potential that turns on the transistors 102a and 102b is applied to the wiring W1. Subsequently, by applying a desired potential to each of the wirings S11 and S12, data can be written to the holding nodes of the respective memory elements via the transistor 102a or the transistor 102b.

[0086] When reading, a common potential is applied to the wiring S2. Here, when a potential that turns on the transistor 101a or the transistor 101b is maintained at the holding node of each memory element, the potential of the wiring S11 or the wiring S12 changes. On the other hand, when the potential of the holding node is a potential that turns off the transistor, the potential of the wiring S11 or the wiring S12 does not change. Therefore, by detecting the change in the potential of the wiring S11 or the wiring S12 with a sense amplifier or the like, the data written in each memory element can be read. 2

[0087] Here, when reading other memory elements arranged along the wiring S2, it is necessary to surely turn off the transistors 101a and 101b. At that time a desired potential is applied to the wiring W2, and the potential of each holding node is changed to a potential that turns off the transistor 101a or the transistor 101b through the capacitor 103a or the capacitor 103b. In this way, reading of other memory elements arranged along the wiring S2 can be surely performed.

[0088] The above is the explanation of the operation of the memory device.

[0089] FIG. 3(B) is a schematic top view of the memory device illustrated in the present embodiment.

[0090] In FIG. 3(B), a wiring layer 201 that functions as the wiring W1, a wiring layer 202 that functions as the wiring W2, a wiring layer 203a that functions as the wiring S11, a wiring layer 203b that functions as the wiring S12, and a wiring layer 204 that functions as the wiring S2 are illustrated.

[0091] Further, a transistor 102a is provided in a region where the wiring layer 201 and the wiring layer 203a overlap. Similarly, a transistor 102b is provided in a region where the wiring layer 201 and the wiring layer 203b overlap, a capacitor 103a is provided in a region where the wiring layer 202 and the wiring layer 203a overlap, and a capacitor 103b is provided in a region where the wiring layer 202 and the wiring layer 203b overlap.

[0092] FIGS. 4(A) to 4(C) respectively show schematic cross-sectional views taken along the cutting lines A-A', B-B', and C-C' in FIG. 3(B). FIG. 4(A) is a schematic cross-sectional view taken along the wiring layer 203a. FIG. 4 is a schematic cross-sectional view of a region including the transistor 102a and the capacitor 103a cut therealong. FIG. 4(B) is a schematic cross-sectional view of a region including the transistor 102a and the transistor 102b cut along the wiring layer 201. FIG. 4(C) is a schematic cross-sectional view of a region including the wiring layer 202, the connection electrode layer 213b connected to the capacitor 103a, and the connection electrode layer 213c cut therealong. In the memory element 110a, the transistor 102a and the capacitor 103a are stacked on the gate electrode layer 111a of the transistor 101a. In the memory element 110b, the transistor 102b and the capacitor 103b are stacked on the gate electrode layer 111b of the transistor 101b.

[0093] Here, the transistors 101a and 101b are transistors using a single crystal semiconductor as a semiconductor in which a channel is formed. The transistor 101a includes a semiconductor layer 115, a first electrode layer 112a and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111a that contacts the gate insulating layer 114 and overlaps the semiconductor layer 115. Similarly, the transistor 101b includes a semiconductor layer 115, a first electrode layer 112b and a second electrode layer 113, a gate insulating layer 114, and a gate electrode layer 111b. The first electrode layer 112b of the transistor 101b is electrically connected to the wiring layer 203b via the connection electrode layer 213c. The first electrode layer 112a of the transistor 101a...

[0094] Here, the transistors 101a and 101b are transistors using a single crystal semiconductor as a semiconductor in which a channel is formed. The transistor 101a is a transistor using a single crystal semiconductor as a semiconductor in which a channel is formed.

[0095] The transistor 101a includes a semiconductor layer 115, a first electrode layer 112a electrically connected to the semiconductor layer 115, a second electrode layer 113, a gate insulating layer 114 in contact with the semiconductor layer 115, and a gate electrode layer 111a in contact with the gate insulating layer 114 and overlapping the semiconductor layer 115. The first electrode layer 112a and the second electrode layer 113 are electrically connected to the semiconductor layer 115. The gate insulating layer 114 is in contact with the semiconductor layer 115, and the gate electrode layer 111a is in contact with the gate insulating layer 114 and overlaps the semiconductor layer 115. The transistor 101a has a semiconductor layer 115, a first electrode layer 112a and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111a that contacts the gate insulating layer 114 and overlaps the semiconductor layer 115. The transistor 101a includes a semiconductor layer 115, a first electrode layer 112a and a second electrode layer 113 that are electrically connected to the semiconductor layer 115, a gate insulating layer 114 that contacts the semiconductor layer 115, and a gate electrode layer 111a that contacts the gate insulating layer 114 and overlaps the semiconductor layer 115.

[0096] Similarly, the transistor 101b also includes a semiconductor layer 115, a first electrode layer 112b, a second electrode layer 113, a gate insulating layer 114, and a gate electrode layer 111b. The transistor 101b has a semiconductor layer 115, a first electrode layer 112b, a second electrode layer 113, a gate insulating layer 114, and a gate electrode layer 111b.

[0097] The first electrode layer 112b of the transistor 101b is electrically connected to the wiring layer 203b via the connection electrode layer 213c. The first electrode layer 112a of the transistor 101a... Similarly, the wiring layer 203a is electrically connected to the connecting electrode layer 213c (not shown). In addition, the second electrode layer 11 is common to the transistor 101a and the transistor 101b. 3 is electrically connected to the wiring layer 204 via the connection electrode layer 213b.

[0098] As shown in FIGS. 4A to 4C, the gate electrode layer 111a and the gate electrode layer 11 A sidewall insulating layer may be provided on the side surface of 1b.

[0099] The transistor 102a includes a semiconductor layer 125 in contact with the upper surface of the gate electrode layer 111a and a semiconductor The electrode layer 122 is in contact with the top surface of the semiconductor layer 125, and the gate insulating layer 123 is in contact with the side surface of the semiconductor layer 125. Further, the semiconductor layer 125 is in contact with the gate insulating layer 124 and has a side surface surrounded by the semiconductor layer 125. A wiring layer 201 is provided. A part of the wiring layer 201 is connected to the gate of the transistor 102a. Therefore, the gate electrode of the transistor 102a functions as a gate electrode of the transistor 101. a and the electrode layer 122 of the transistor 102a.

[0100] Similarly, the transistor 102b has a semiconductor layer 125 in contact with the gate electrode layer 111b and an The electrode layer 122 and the gate insulating layer 124 are included, and the side surface of the semiconductor layer 125 is surrounded by the wiring layer 201. The gate electrode of the transistor 102b is also formed on the gate electrode layer 1 of the transistor 101b. 11b and the electrode layer 122 of transistor 102b.

[0101] The electrode layer 122 of the transistor 102a is connected to the wiring layer 203a via the connection electrode layer 213a. The electrode layer 122 of the transistor 102b is also electrically connected to the It is electrically connected to the wiring layer 203b via the pole layer 213a.

[0102] The capacitance 103a has a dielectric layer 134 that contacts the gate electrode layer 111a of the transistor 101a. 4. A wiring layer 202 is provided in contact with the upper surface of the dielectric layer 134. Part of the wiring layer 2 02 functions as one electrode of the capacitance 103a. Here, the dielectric layer 134 is composed of the same layer as the semiconductor layer 125. That is, the dielectric layer 134 exists as the same layer as the semiconductor layer 125.

[0103] Similarly, the capacitance 103b has a dielectric layer 134 that contacts the gate electrode layer 111b, and a wiring layer 202 is provided in contact with the upper surface of the dielectric layer 134.

[0104] Also, as shown in FIGS. 4(A) to (C), in order to electrically isolate the electrode layers and wiring layers constituting the memory device, an insulating layer is provided between each electrode layer, between wiring layers, or between an electrode layer and a wiring layer. 212a to 212h is provided.

[0105] Also, on the substrate constituting the semiconductor layer 115, an element isolation layer 211 is provided for electrically isolating between transistors including the semiconductor layer 115.

[0106] Here, in the memory device exemplified in this embodiment, the widths of the electrode layers and wiring layers constituting the memory device, and the intervals between electrode layers, between wiring layers, or between an electrode layer and a wiring layer can be formed by the minimum processing dimension in the manufacturing method used. Here, if the minimum processing dimension is F, the value of F is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 30 nm or less.

[0107] ​​​​​​​Here, in this configuration example, the occupation areas of the transistor 102a and the capacitor 103a, which are vertical transistors, can be reduced to F 2 .

[0108] In this way, by sharing one of the electrode layers of the transistor 101a and the transistor 101b, the two memory elements can be arranged as close to each other as possible. Furthermore, by laminating and providing the transistor 102a and the capacitor 103 a on the gate electrode layer 111a of the transistor 101a, the occupation area of one memory element can be reduced.

[0109] The above is the description of the configuration example of the memory device illustrated in this embodiment.

[0110] <Modification example> In the above configuration example, as the dielectric layer constituting the capacitor, the same layer as the semiconductor layer of the vertical transistor is used (that is, the dielectric layer and the semiconductor layer exist as the same layer). Hereinafter, the case where a thin film of an insulating material is used as the dielectric layer will be described.

[0111] FIG. 5 is a diagram showing a different configuration of the capacitor 103a among the cross-sectional schematic diagrams shown in FIG. 4(A). Note that the configuration is the same as that of the above configuration example except for the configuration of the capacitor 103a.

[0112] The capacitor 103a has a dielectric layer 13 4 that contacts the gate electrode layer 111a of the transistor 101a, and an electrode layer 132 that contacts the upper surface of the dielectric layer 134. Also, a wiring layer 202 is provided that contacts the upper surface of the electrode layer 132.

[0113] The dielectric layer 134 is composed of a thin film made of an insulating material. With such a configuration, ​​Therefore, the dielectric layer 134 can be formed thinner, increasing the capacitance value per unit area. It is possible to

[0114] Here, as shown in FIG. 5, the dielectric layer 134 preferably exists as the same layer as the gate insulating layer 124 of the transistor 102a. Further, the electrode layer 132 preferably exists as the same layer as the wiring layer 201. By configuring the dielectric layer 134 and the electrode layer 132 as the same layers as the layers constituting the transistor 102a, the capacitor 103a and the transistor 102a can be formed in the same process, thus simplifying the manufacturing process. It is possible to Here, as shown in FIG. 5, the dielectric layer 134 preferably exists as the same layer as the gate insulating layer 124 of the transistor 102a. Further, the electrode layer 132 preferably exists as the same layer as the wiring layer 201. By configuring the dielectric layer 134 and the electrode layer 132 as the same layers as the layers constituting the transistor 102a, the capacitor 103a and the transistor 102a can be formed in the same process, thus simplifying the manufacturing process. Here, as shown in FIG. 5, the dielectric layer 134 preferably exists as the same layer as the gate insulating layer 124 of the transistor 102a. Further, the electrode layer 132 preferably exists as the same layer as the wiring layer 201. By configuring the dielectric layer 134 and the electrode layer 132 as the same layers as the layers constituting the transistor 102a, the capacitor 103a and the transistor 102a can be formed in the same process, thus simplifying the manufacturing process. Here, as shown in FIG. 5, the dielectric layer 134 preferably exists as the same layer as the gate insulating layer 124 of the transistor 102a. Further, the electrode layer 132 preferably exists as the same layer as the wiring layer 201. By configuring the dielectric layer 134 and the electrode layer 132 as the same layers as the layers constituting the transistor 102a, the capacitor 103a and the transistor 102a can be formed in the same process, thus simplifying the manufacturing process. It is possible to

[0115] The above is the description of this modified example.

[0116] <Manufacturing Process Example> Hereinafter, an example of a method for manufacturing the memory device illustrated in the above configuration example will be described with reference to the drawings. Note that in this manufacturing process example, only a schematic overview is shown, excluding some parts. For details, known semiconductor integrated circuit manufacturing techniques may be referred to. Hereinafter, an example of a method for manufacturing the memory device illustrated in the above configuration example will be described with reference to the drawings. Note that in this manufacturing process example, only a schematic overview is shown, excluding some parts. For details, known semiconductor integrated circuit manufacturing techniques may be referred to. Hereinafter, an example of a method for manufacturing the memory device illustrated in the above configuration example will be described with reference to the drawings. Note that in this manufacturing process example, only a schematic overview is shown, excluding some parts. For details, known semiconductor integrated circuit manufacturing techniques may be referred to.

[0117] FIGS. 6 to 9 show schematic top views and cross-sectional views at each stage in this manufacturing process example. For example, FIG. 6(A) shows a schematic top view at that stage, and FIG. 6(B) shows a schematic cross-sectional view taken along the cutting lines A-A' and B-B' in FIG. 6(A). FIGS. 6 to 9 show schematic top views and cross-sectional views at each stage in this manufacturing process example. For example, FIG. 6(A) shows a schematic top view at that stage, and FIG. 6(B) shows a schematic cross-sectional view taken along the cutting lines A-A' and B-B' in FIG. 6(A). FIGS. 6 to 9 show schematic top views and cross-sectional views at each stage in this manufacturing process example. For example, FIG. 6(A) shows a schematic top view at that stage, and FIG. 6(B) shows a schematic cross-sectional view taken along the cutting lines A-A' and B-B' in FIG. 6(A).

[0118] First, a substrate containing a semiconductor material is prepared. As the substrate containing a semiconductor material, a single-crystalline semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, a substrate containing a semiconductor material is used. First, a substrate containing a semiconductor material is prepared. As the substrate containing a semiconductor material, a single-crystalline semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, a substrate containing a semiconductor material is used. First, a substrate containing a semiconductor material is prepared. As the substrate containing a semiconductor material, a single-crystalline semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, a substrate containing a semiconductor material is used. An example of using a single-crystalline silicon substrate as the substrate is shown. In general, the term "S OI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is assumed to include a substrate having a configuration in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the SOI substrate includes a configuration in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. Subsequently, an element isolation layer 211 is formed on the substrate. The element isolation layer 211 may be formed using a known LOCO S (Local Oxidation of Silicon) process or the like. Further, before and after this step, in order to control the threshold voltages of the transistors 101a and

[0119] 101b to be formed later, impurity elements imparting n-type conductivity or impurity elements imparting p-type conductivity may be added to the substrate. When the semiconductor material contained in the substrate is silicon, for example, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. On the other hand, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium, or the like can be used. After forming the element isolation layer 211, it is preferable to planarize the substrate surface. For example, polishing treatment such as CMP (Chemical Mechanical Polishing) or etching treatment may be used. Next, an insulating film is formed on the substrate surface, and a conductive film is formed on the insulating film. The insulating film is the gate of the transistors 101a and 101b to be formed later. The insulating film is the gate of the transistors 101a and 101b to be formed later. The insulating film is the gate of the transistors 101a and 101b to be formed later.

[0120] Also, after forming the element isolation layer 211, it is preferable to planarize the substrate surface. For example, polishing treatment such as CMP (Chemical Mechanical Polishing) or etching treatment may be used. Next, an insulating film is formed on the substrate surface, and a conductive film is formed on the insulating film.

[0121] Next, an insulating film is formed on the substrate surface, and a conductive film is formed on the insulating film.

[0122] The above insulating film is the gate of the transistors 101a and 101b to be formed later. It becomes the gate insulating layer 114 and can be obtained by using a CVD method, a sputtering method, or the like, such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), hafnium silicate with nitrogen added, hafnium aluminate (HfAl x O y (x>0, y>0)), etc., and a single-layer structure or a stacked structure of a film containing the like is preferable. Alternatively, the insulating film may be formed by oxidizing or nitriding the surface of the substrate by high-density plasma treatment or heat treatment (such as thermal oxidation treatment or thermal nitridation treatment). The high-density plasma treatment can be performed using, for example, a mixed gas of a noble gas such as He, Ar, Kr, Xe, and oxygen, nitrogen oxide, ammonia, nitrogen, etc. Also, the thickness of the insulating film is not particularly limited, but can be, for example, 1 nm or more and 100 nm or less. The conductive film becomes the gate electrode layers 111a and 111b of the transistors 101a and 101b formed later, and can be formed using a metal material such as aluminum, copper, titanium, tantalum,

[0123] tungsten, chromium, nickel, molybdenum, etc. Alternatively, a conductive film may be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The forming method is not particularly limited, and various film-forming methods such as an evaporation method, a CVD method, a sputtering method, and a spin coating method can be used. In this embodiment, an example in the case of using a metal material as the conductive film is shown.

[0124] ​​In addition, since the conductive film also functions as one of the electrodes of the transistors 102a and 102b to be formed later, it is preferable to select a material considering the electron affinity of the semiconductor material used for the semiconductor layer 125. Further, the conductive film may be a laminated film in which two or more films are laminated, and a conductive film made of a material suitable for the electrodes of the transistors 102a and 102b may be used for the uppermost layer (the layer in contact with the semiconductor layer 125) of the laminated film. Subsequently, unnecessary portions of the conductive film are etched to form the gate electrode layers 111a and 111b. Subsequently, a sidewall insulating layer is formed on the side surfaces of the gate electrode layers 111a and 111b. The sidewall insulating layer can be formed self-aligned by applying an anisotropic etching process to the insulating film after forming an insulating film covering the gate electrode layers 111a and 111b. Also, by the etching process when forming the sidewall insulating layer, the portion of the insulating film that becomes the gate insulating layer 114 and does not overlap with the gate electrode layers 111a and 111b and the sidewall insulating layer is etched simultaneously, thereby forming the gate insulating layer 114. By providing the sidewall insulating layer, in the step of adding impurities described later, impurity regions in which impurity elements are added at different concentrations can be formed. By doing so, the influence of the short-channel effect and the like can be suppressed, which is preferable. Note that high integration is required.

[0125] In addition, since the conductive film also functions as one of the electrodes of the transistors 102a and 102b to be formed later, it is preferable to select a material considering the electron affinity of the semiconductor material used for the semiconductor layer 125. Further, the conductive film may be a laminated film in which two or more films are laminated, and a conductive film made of a material suitable for the electrodes of the transistors 102a and 102b may be used for the uppermost layer (the layer in contact with the semiconductor layer 125) of the laminated film. Subsequently, unnecessary portions of the conductive film are etched to form the gate electrode layers 111a and 111b.

[0126] Subsequently, a sidewall insulating layer is formed on the side surfaces of the gate electrode layers 111a and 111b. The sidewall insulating layer can be formed self-aligned by applying an anisotropic etching process to the insulating film after forming an insulating film covering the gate electrode layers 111a and 111b. Also, by the etching process when forming the sidewall insulating layer, the portion of the insulating film that becomes the gate insulating layer 114 and does not overlap with the gate electrode layers 111a and 111b and the sidewall insulating layer is etched simultaneously, thereby forming the gate insulating layer 114. By providing the sidewall insulating layer, in the step of adding impurities described later, impurity regions in which impurity elements are added at different concentrations can be formed. By doing so, the influence of the short-channel effect and the like can be suppressed, which is preferable. Note that high integration is required. In addition, since the conductive film also functions as one of the electrodes of the transistors 102a and 102b to be formed later, it is preferable to select a material considering the electron affinity of the semiconductor material used for the semiconductor layer 125. Further, the conductive film may be a laminated film in which two or more films are laminated, and a conductive film made of a material suitable for the electrodes of the transistors 102a and 102b may be used for the uppermost layer (the layer in contact with the semiconductor layer 125) of the laminated film.

[0127] Subsequently, unnecessary portions of the conductive film are etched to form the gate electrode layers 111a and 111b. Subsequently, a sidewall insulating layer is formed on the side surfaces of the gate electrode layers 111a and 111b. The sidewall insulating layer can be formed self-aligned by applying an anisotropic etching process to the insulating film after forming an insulating film covering the gate electrode layers 111a and 111b. Also, by the etching process when forming the sidewall insulating layer, the portion of the insulating film that becomes the gate insulating layer 114 and does not overlap with the gate electrode layers 111a and 111b and the sidewall insulating layer is etched simultaneously, thereby forming the gate insulating layer 114. By providing the sidewall insulating layer, in the step of adding impurities described later, impurity regions in which impurity elements are added at different concentrations can be formed. By doing so, the influence of the short-channel effect and the like can be suppressed, which is preferable. Note that high integration is required.

[0128] By providing the sidewall insulating layer, in the step of adding impurities described later, impurity regions in which impurity elements are added at different concentrations can be formed. By doing so, the influence of the short-channel effect and the like can be suppressed, which is preferable. Note that high integration is required. In addition, since the conductive film also functions as one of the electrodes of the transistors 102a and 102b to be formed later, it is preferable to select a material considering the electron affinity of the semiconductor material used for the semiconductor layer 125. Further, the conductive film may be a laminated film in which two or more films are laminated, and a conductive film made of a material suitable for the electrodes of the transistors 102a and 102b may be used for the uppermost layer (the layer in contact with the semiconductor layer 125) of the laminated film. Subsequently, unnecessary portions of the conductive film are etched to form the gate electrode layers 111a and 111b. In the case where there is no sidewall, the transistor size can be reduced by adopting such a configuration. It can be reduced.

[0129] Next, the gate electrode layer 111a, the gate electrode layer 111b, and the sidewall insulating layer are used as masks, and impurities such as phosphorus and arsenic are added to form the first electrode layer 112a, the first electrode layer 112b, and the second electrode layer 113. When forming a p-channel type transistor, impurity elements such as boron and aluminum may be added, and when forming an n-channel type transistor, impurity elements such as phosphorus and arsenic may be added. The concentration of the added impurities can be set as appropriate, but when the semiconductor element is highly miniaturized, it is desirable to increase the concentration. Note that after adding the impurity elements, heat treatment is preferably performed to activate the impurity elements and improve defects generated during the addition of the impurity elements. Next, the gate electrode layer 111a, the gate electrode layer 111b, and the sidewall insulating layer are used as masks, and impurities such as phosphorus and arsenic are added to form the first electrode layer 112a, the first electrode layer 112b, and the second electrode layer 113. When forming a p-channel type transistor, impurity elements such as boron and aluminum may be added, and when forming an n-channel type transistor, impurity elements such as phosphorus and arsenic may be added. The concentration of the added impurities can be set as appropriate, but when the semiconductor element is highly miniaturized, it is desirable to increase the concentration. Note that after adding the impurity elements, heat treatment is preferably performed to activate the impurity elements and improve defects generated during the addition of the impurity elements. In the case of forming a p-channel type transistor, impurity elements such as boron and aluminum may be added, and in the case of forming an n-channel type transistor, impurity elements such as phosphorus and arsenic may be added. In the case of forming a p-channel type transistor, impurity elements such as boron and aluminum may be added, and in the case of forming an n-channel type transistor, impurity elements such as phosphorus and arsenic may be added. In the case of forming an n-channel type transistor, impurity elements such as phosphorus and arsenic may be added. The concentration of the added impurities can be set as appropriate, but when the semiconductor element is highly miniaturized, it is desirable to increase the concentration. Note that after adding the impurity elements, heat treatment is preferably performed to activate the impurity elements and improve defects generated during the addition of the impurity elements. The concentration of the added impurities can be set as appropriate, but when the semiconductor element is highly miniaturized, it is desirable to increase the concentration. Note that after adding the impurity elements, heat treatment is preferably performed to activate the impurity elements and improve defects generated during the addition of the impurity elements. After adding the impurity elements, heat treatment is preferably performed to activate the impurity elements and improve defects generated during the addition of the impurity elements. It is desirable.

[0130] Through the above steps, the transistor 101a and the transistor 101b can be formed.

[0131] After that, after forming an insulating film that will become the subsequent insulating layer 212a, a planarization process is performed so that the gate electrode layer 111a and the gate electrode layer 111b are exposed, and the insulating layer 212a is formed. After that, after forming an insulating film that will become the subsequent insulating layer 212a, a planarization process is performed so that the gate electrode layer 111a and the gate electrode layer 111b are exposed, and the insulating layer 212a is formed.

[0132] As the insulating film that will become the insulating layer 212a, a single film or a laminated film of a film containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide can be used. Also, if it can withstand the heat involved in subsequent processes, it can also be formed using an organic insulating material such as polyimide or an acrylic resin. As the insulating film that will become the insulating layer 212a, a single film or a laminated film of a film containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide can be used. Also, if it can withstand the heat involved in subsequent processes, it can also be formed using an organic insulating material such as polyimide or an acrylic resin. As the insulating film that will become the insulating layer 212a, a single film or a laminated film of a film containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, or tantalum oxide can be used. Also, if it can withstand the heat involved in subsequent processes, it can also be formed using an organic insulating material such as polyimide or an acrylic resin. Also, if it can withstand the heat involved in subsequent processes, it can also be formed using an organic insulating material such as polyimide or an acrylic resin. It can also be formed.

[0133] Note that the top surface schematic diagram and the cross-sectional schematic diagram at this stage correspond to FIGS. 6(A) and (B), respectively. Corresponding.

[0134] Subsequently, a semiconductor film that will become the later semiconductor layer 125 is formed on the gate electrode layer 111a, the gate electrode layer 111b, and the insulating layer 212a. Here, considering that the film thickness will decrease in the later planarization process, it is preferably formed to be thicker than the desired channel length in advance. As the material of the semiconductor film, semiconductor materials such as silicon can be used, but it is preferable to use a semiconductor material with a wider bandgap than silicon. There are compound semiconductors as semiconductors having a wider bandgap than silicon. For example, there are oxide semiconductors, nitride semiconductors, etc. Considering that the film thickness will decrease in the later planarization process, it is preferably formed to be thicker than the desired channel length in advance. It is preferable to form it.

[0135] As the material of the semiconductor film, semiconductor materials such as silicon can be used, but it is preferable to use a semiconductor material with a wider bandgap than silicon. There are compound semiconductors as semiconductors having a wider bandgap than silicon. For example, there are oxide semiconductors, nitride semiconductors, etc. There are compound semiconductors as semiconductors having a wider bandgap than silicon. For example, there are oxide semiconductors, nitride semiconductors, etc. Semiconductors such as oxide semiconductors and nitride semiconductors.

[0136] The off-resistance of the transistor is inversely proportional to the concentration of thermally excited carriers in the semiconductor layer where the channel is formed. Even in a state where there are no carriers due to donors or acceptors (intrinsic semiconductor), in the case of silicon, since the bandgap is 1.1 electron volts, the concentration of thermally excited carriers at room temperature (300K) is about 1×10 On the other hand, in the case of a semiconductor with a bandgap of 3.2 electron volts, for example, the concentration of thermally excited carriers is about 1×10 cm 11 cm -3 The degree is about.

[0137] On the other hand, in the case of a semiconductor with a bandgap of 3.2 electron volts, for example, the concentration of thermally excited carriers is about 1×10 cm -7 cm -3 The degree is about. Since the resistivity is inversely proportional to the carrier concentration when the electron mobility is the same, the resistivity of a semiconductor with a bandgap of 3.2 electron volts is 18 orders of magnitude larger than that of silicon. Since the resistivity is inversely proportional to the carrier concentration when the electron mobility is the same, the resistivity of a semiconductor with a bandgap of 3.2 electron volts is 18 orders of magnitude larger than that of silicon. Larger.

[0138] A transistor to which such a semiconductor with a wide bandgap is applied can achieve an extremely low off current. By applying such transistors to transistor 102a and transistor 1 02b, the potential held at the holding node of each memory element can be held for an extremely long period.

[0139] In this embodiment, an oxide semiconductor film is formed as the semiconductor film by sputtering. Specifically, it is formed by sputtering using an In-Ga-Zn-based oxide semiconductor target.

[0140] Note that the material that can be used as the oxide semiconductor film is not limited to the above. As the oxide semiconductor, it is preferably to contain at least indium (In) or zinc (Zn). In particular, it is preferably to contain In and Zn.

[0141] In addition, as a stabilizer for reducing the variation in the electrical characteristics of transistors using an oxide semiconductor, it preferably has one or more selected from gallium (Ga), tin (Sn), hafnium (Hf) , aluminum (Al), or lanthanoids.

[0142] Examples of lanthanoids include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd) , terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (E r), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0143] ​​​​For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, etc. can be used. This is possible.

[0144] Also, as the oxide semiconductor, In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, etc. can be used.

[0145] Also, as the oxide semiconductor, In-Ga-Zn-based oxide (also denoted as IGZO), I n-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, In-Al-Zn-based oxide, In -Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In- Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-E u-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy -Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm- Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, Al-Ga-Z n-based oxide, Sn-Al-Zn-based oxide, etc. can be used.

[0146] Also, as the oxide semiconductor, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Z n-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In -Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide, etc. can be used .

[0147] Here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn is not limited. Also, In and Ga and Zn, and the ratio of In, Ga, and Zn is not limited. Also, In and Metal elements other than Ga and Zn may be contained.

[0148] In addition, an oxide semiconductor film can be formed with an oxide semiconductor containing SiO2 in the above metal oxide. This can also be done.

[0149] In addition, the oxide semiconductor film can be formed of an oxide semiconductor represented by InMO3(ZnO) m (m > 0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. One or more metal elements selected from Ga, Al, Mn, and Co. For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1 or In:Ga:Zn = 2:2:1, or oxides in the vicinity of their compositions can be used.

[0150] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1 or In:Ga:Zn = 2:2:1, or oxides in the vicinity of their compositions can be used. Or, In-Sn-Zn-based oxides with an atomic ratio of In:Sn:Zn = 1:1:1, In:Sn:Zn = 2:1:3, or In:Sn:Zn = 2:1:5, or oxides in the vicinity of their compositions may be used.

[0151] Or, In-Sn-Zn-based oxides with an atomic ratio of In:Sn:Zn = 1:1:1, In:Sn:Zn = 2:1:3, or In:Sn:Zn = 2:1:5, or oxides in the vicinity of their compositions may be used. However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, It is preferable to make the carrier concentration, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. appropriate.

[0152] For example, in In-Sn-Zn-based oxides, relatively high mobility can be obtained easily. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk. For example, in In-Sn-Zn-based oxides, relatively high mobility can be obtained easily. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk.

[0153] For example, in In-Sn-Zn-based oxides, relatively high mobility can be obtained easily. However, even in In-Ga-Zn-based oxides, the mobility can be increased by reducing the defect density in the bulk. This can be done.

[0154] Note that, for example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn = a:b:c (a + b + c = 1), the composition of the oxide is in the vicinity of the composition of the oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 +(b - B) 2 +(c - C) 2 ≦ r 2 where r may be, for example, 0.05. The same applies to other oxides.

[0155] The oxide semiconductor may be single crystal or polycrystal. In the case of polycrystal, it may be amorphous or polycrystalline and may also have a structure including a crystalline part in the amorphous. Note that since amorphous has many defects, non - amorphous is preferred.

[0156] An oxide semiconductor in an amorphous state can relatively easily obtain a flat surface. Therefore, when a transistor is fabricated using this, interface scattering can be reduced, and relatively easily, relatively high mobility can be obtained.

[0157] Also, in an oxide semiconductor having crystallinity, more bulk defects can be reduced, and if the flatness of the surface is increased, mobility higher than that of an amorphous oxide semiconductor can be obtained .

[0158] Here, it is preferable to form the oxide semiconductor film so that impurities such as alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, or hydrogen compounds are not incorporated as much as possible. For example, ensure that the above impurities are not incorporated into the sputtering target or the gas used for film formation. Also during film formation, evacuate the inside of the film formation apparatus sufficiently, and perform film formation while heating the substrate temperature during film formation. ​​Thus, the impurity concentration contained in the formed oxide semiconductor film can be reduced.

[0159] In addition, after the formation of the oxide semiconductor film, a dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film, and the film is purified to contain as few impurities as possible. To compensate for the oxygen vacancies increased by the dehydration treatment (dehydrogenation treatment), it is preferable to perform a treatment of adding oxygen to the oxide semiconductor film. The supply of oxygen can be carried out by a method of performing a heat treatment in an oxygen atmosphere, or by arranging the oxide semiconductor film near a film that releases oxygen by heating and performing a heat treatment. In this specification, etc., when oxygen is supplied to the oxide semiconductor film, it may be referred to as an oxygen addition treatment, or when the oxygen contained in the oxide semiconductor film is made more than the stoichiometric composition, it may be referred to as a peroxygenation treatment. Thus, the oxide semiconductor film can be made into an i-type (intrinsic) or an oxide semiconductor film extremely close to the i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and compensating for oxygen vacancies by oxygen addition treatment. In such an oxide semiconductor film, the carriers derived from donors are extremely few (close to zero), and the carrier concentration is less than 1×10¹⁰ / cm³, preferably less than 1×10⁹ / cm³, more preferably less than 1×10⁸ / cm³, and even more preferably less than 1.45×10⁷ / cm³. Also, in this way, the hydrogen concentration is sufficiently reduced and purified, and with sufficient supply of oxygen

[0160]

[0161] 14 3 12 3 0 14 / cm 3 12 3 / cm 11 3 11 / cm 3 10 3 / cm 3 10

[0161] A transistor including an oxide semiconductor film in which defect levels in an energy gap due to oxygen deficiency are reduced can achieve extremely excellent off-current characteristics. For example, at room temperature (25°C) the off-current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (zeptoampere) is 1×10 -21 A) or less, desirably 10 zA or less. Also , at 85°C, it is 100 zA (1×10 -19 A) or less, desirably 10 zA (1×10 - 20 A) or less. Thus, by using an i-type (intrinsic) or substantially i-type oxide semiconductor film, a transistor with extremely excellent off-current characteristics can be obtained.

[0162] Subsequently, unnecessary portions of the semiconductor film are etched to form the semiconductor layer 125 and the dielectric layer 134.

[0163] Etching of the semiconductor film is preferably performed using a hard mask. First, an inorganic film that will serve as a hard mask later is formed on the semiconductor film, and a resist is formed so as to overlap the regions where the semiconductor layer 125 and the dielectric layer 134 are to be formed on the inorganic film. Here, it is preferable to perform so-called slimming processing, which involves ashing the formed resist to reduce the width of the resist. By performing the slimming processing, the width of the semiconductor layer 125 or the dielectric layer 134 can be made smaller than the minimum processing dimension F. Therefore, the semiconductor layer 125 and the dielectric layer 134 can be provided in the inner region even when the width of the gate electrode layer 111a or the gate electrode layer 111b is formed with the minimum processing dimension F.

[0164] The hard mask is obtained by etching the inorganic film in the region not covered by the resist. The resist may be removed after the formation of the hard mask.

[0165] The etching of the semiconductor film is performed using an anisotropic etching method on the portion not covered by the hard mask. Here, conditions are used such that the layer provided below the semiconductor film during etching is not etched. In this way, a columnar (including cylindrical and polygonal columnar) semiconductor layer 125 can be formed. Subsequently, the hard mask is removed. Also, in the case where the resist on the hard mask has not been removed, the hard mask is removed after removing the resist.

[0166]

[0167] Subsequently, an insulating film is formed to cover the side surface and the upper surface of the semiconductor layer 125. A part of the insulating film functions as the gate insulating layer 124. Therefore, it is preferable to form the insulating film so that the portion in contact with the side surface of the semiconductor layer 125 has a uniform thickness. The insulating film can be formed by a film formation method such as CVD method or sputtering method. Also, it is preferable that impurities containing hydrogen atoms such as water, hydrogen, and hydrogen compounds are sufficiently reduced in the insulating film and at the interface with the semiconductor layer 125.

[0168]

[0169] Here, for the formation of the insulating film, it is preferable to use high-density plasma CVD using microwaves (for example, frequency 2.45 GHz) because a high-quality insulating film that is dense and has a high breakdown voltage can be formed. By bringing the highly purified oxide semiconductor into contact with the high-quality gate insulating layer, interface levels can be reduced and interface characteristics can be improved.

[0169]

[0169] Examples of the insulating film include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate ( HfSi x O y (x>0, y>0)), hafnium silicate with nitrogen added (HfS i x O y N z (x>0, y>0, z>0)), hafnium aluminate with nitrogen added (HfAl x O y N z (x>0, y>0, z>0)), etc. A film containing such materials can be formed as a single layer or by laminating them.

[0170] The top view and cross-sectional view at this stage correspond to FIGS. 7(A) and (B), respectively. respectively.

[0171] Subsequently, a conductive film that will become the wiring layer 201 is formed on the insulating film that constitutes the gate insulating layer 124, and unnecessary portions of the conductive film are etched. Then, an insulating film that will become the subsequent insulating layer 212b is formed on the insulating film and the conductive film. Next, a planarization process is performed so that the upper surfaces of the semiconductor layer 125 and the dielectric layer 134 are exposed, thereby forming the wiring layer 201 and the insulating layer 212b. The conductive film that will become the wiring layer 201 can be formed by the same materials and methods as the conductive film used for the gate electrode layer 111a and the gate electrode layer 111b. Hereinafter, the conductive films used for the wiring layer 202, the wiring layer 203a, the wiring layer 203b, and the wiring layer 204 are the same. formed.

[0172] The conductive film that will become the wiring layer 201 can be formed by the same materials and methods as the conductive film used for the gate electrode layer 111a and the gate electrode layer 111b. In addition, the insulating film that constitutes the insulating layer 212b is the same material as the insulating film used for the insulating layer 212a. Note that hereinafter, the same applies to the conductive films used for the wiring layer 202, the wiring layer 203a, the wiring layer 203b, and the wiring layer 204.

[0173] The insulating film that constitutes the insulating layer 212b is the same material as the insulating film used for the insulating layer 212a. , it can be formed by a method. Hereinafter, the same applies to the insulating films used for the insulating layer 212c, the insulating layer 212d, the insulating layer 212 e, the insulating layer 212f, the insulating layer 212g, and the insulating layer 212h.

[0174] Subsequently, an insulating film that becomes the insulating layer 212c is formed in contact with the semiconductor layer 125, the dielectric layer 134, the gate insulating layer 124, the wiring layer 201, and the insulating layer 212b. Thereafter, an opening reaching the semiconductor layer 125 or the dielectric layer 134 is formed in the insulating film that becomes the insulating layer 212 c, whereby the insulating layer 212c is formed.

[0175] Subsequently, a conductive film that will become the later wiring layer 202 or the electrode layer 122 is formed on the semiconductor layer 125, the dielectric layer 134, and the insulating layer 212c. Thereafter, unnecessary portions of the conductive film are etched to form the wiring layer 202 and the electrode layer 122.

[0176] Through the above steps, the transistor 102a and the capacitor 103a can be formed on the gate electrode layer 111a of the transistor 101a. At the same time, the transistor 102b and the capacitor 103b are formed on the gate electrode layer 111b of the transistor 101b.

[0177] The top view and the cross-sectional view at this stage correspond to FIGS. 8(A) and (B), respectively.

[0178] Subsequently, an insulating film that becomes the insulating layer 212d is formed on the wiring layer 202, the electrode layer 122, and the insulating layer 212c. Thereafter, a planarization process is performed so that the upper surfaces of the wiring layer 202 and the electrode layer 122 are exposed, thereby forming the insulating layer 212d.

[0179] Subsequently, an insulating film that becomes the insulating layer 212e is formed to form the insulating layer 212e.

[0180] Subsequently, an opening reaching the electrode layer 122 is formed in the insulating layer 212e. Thereafter, a conductive film that will become the connection electrode layer 213a is formed on the insulating layer 212e and the electrode layer 122, and a planarization process is performed so that the upper surface of the insulating layer 212 e is exposed, thereby forming a connection electrode layer 213a that is electrically connected to the electrode layer 122.

[0181] At the same time, openings reaching the first electrode layer 11 2a or the first electrode layer 112b are formed in the insulating layer 212e, the insulating layer 212d, the insulating layer 212c, the insulating layer 21 2b, the insulating film constituting the gate insulating layer 124, and the insulating layer 212a, thereby forming a connection electrode layer 213c (see FIG. 4 ) that is electrically connected to the first electrode layer 112a or the first electrode layer 112b.

[0182] Subsequently, a conductive film that will become the wiring layer 203a and the wiring layer 203b is formed on the insulating layer 212e, the connection electrode layer 213a, and the connection electrode layer 213c, and then unnecessary portions of the conductive film are etched to form the wiring layer 203a and the wiring layer 203b.

[0183] Thereafter, an insulating film that will become the insulating layer 212f is formed on the insulating layer 212e, the wiring layer 203a, and the wiring layer 203b, and then a planarization process is performed so that the upper surfaces of the wiring layer 203a and the wiring layer 203b are exposed to form the insulating layer 212f.

[0184] Subsequently, an insulating film that will become the insulating layer 212g is formed on the insulating layer 212f, the wiring layer 203a, and the wiring layer 203b, and the insulating layer 212g is formed.

[0185] Subsequently, on the insulating layer 212g, the insulating layer 212f, the insulating layer 212e, the insulating layer 212d, the insulating layer​​​​​ 212c, the insulating layer 212b, the insulating film forming the gate insulating layer 124, and the insulating layer 212a An opening (not shown) reaching the second electrode layer 113 is formed therein. Thereafter, the insulating layer 2 On 12g and the second electrode layer 113, a conductive film serving as the connection electrode layer 213b is formed, and the insulating layer 2 A planarization process is performed so that the upper surface of 12g is exposed, thereby forming a connection electrode layer 213b (not shown) that is electrically Connected to the second electrode layer 113 (see Fig. 4(C)).

[0186] Subsequently, on the insulating layer 212g and the connection electrode layer 213b (not shown), a conductive film that becomes the wiring layer 204 is formed, and then unnecessary portions of the conductive film are etched to form the wiring layer 204 (see Fig. 4(C)). 204 is formed (see Fig. 4(C)).

[0187] Thereafter, an insulating layer 212h covering the insulating layer 212g and the wiring layer 204 may be formed. Also After forming an insulating film that becomes the insulating layer 212h, the upper surface of the insulating film may be planarized by a planarization process to form the insulating layer 212h. Flattened to form the insulating layer 212h.

[0188] The top view and the cross-sectional view at this stage correspond to Figs. 9(A) and (B), respectively. To.

[0189] Through the above steps, a memory device including the memory elements 110a and 110b exemplified in the configuration example of the present embodiment can be manufactured. 110b can be manufactured.

[0190] Here, in the above, a method of forming the semiconductor layer 125 and the dielectric layer 134 using a hard mask has been described. However, the semiconductor layer 125 and the dielectric layer 134 can also be formed by a method different from this. Here, a method of forming the semiconductor layer 125 and the dielectric layer 134 has been described, but the semiconductor layer 125 and the dielectric layer 134 can also be formed by a method different from this. In the following, a manufacturing method different from the above will be described with reference to Fig. 10. Hereinafter, a manufacturing method different from the above will be described with reference to Fig. 10.

[0191] First, form the transistor 101a and the insulating layer 212a in the same manner as described above.

[0192] Subsequently, an insulating layer 212i and a conductive film serving as the wiring layer 201 are laminated and formed on the insulating layer 212a and the gate electrode layer 111a. Here, the insulating layer 212i is provided to insulate the gate electrode layer 111a from the wiring layer 201. 1. from the wiring layer 201.

[0193] Subsequently, an opening reaching the gate electrode layer 111a is formed in the conductive film and the insulating layer 212i. A schematic cross-sectional view at this stage corresponds to FIG. 10(A). 10(A).

[0194] Subsequently, an insulating film that will later become the gate insulating layer 124 is formed so as to contact the side surface and the bottom surface of the opening. Alternatively, the upper surface and the side surface of the conductive film may be oxidized to form an insulating film. 124 is formed so as to contact the side surface and the bottom surface of the opening. Alternatively, the upper surface and the side surface of the conductive film may be oxidized to form an insulating film. 23.

[0195] Thereafter, by subjecting the insulating film to an anisotropic etching treatment, the upper surfaces of the conductive film and the gate electrode layer 111a are exposed, and the insulating film can be left only on the side walls of the opening. In this way, the gate insulating layer 124 that contacts the side walls of the opening can be formed. 111a are exposed, and the insulating film can be left only on the side walls of the opening. In this way, the gate insulating layer 124 that contacts the side walls of the opening can be formed. 124 that contacts the side walls of the opening can be formed. 33.

[0196] Subsequently, a semiconductor film that will become the semiconductor layer 125 and the dielectric layer 134 is formed on the conductive film and the gate electrode layer 111a so as to contact the gate insulating layer 124. Thereafter, by performing a planarization treatment so that the upper surface of the conductive film is exposed, the semiconductor layer 125 and the dielectric layer 134 can be formed in the opening. A schematic cross-sectional view at this stage corresponds to FIG. 10(B). 124. Thereafter, by performing a planarization treatment so that the upper surface of the conductive film is exposed, the semiconductor layer 125 and the dielectric layer 134 can be formed in the opening. A schematic cross-sectional view at this stage corresponds to FIG. 10(B). 125 and the dielectric layer 134 can be formed in the opening. A schematic cross-sectional view at this stage corresponds to FIG. 10(B). 10(B). 45.

[0197] Subsequently, a resist is formed on the upper surfaces of the conductive film, the gate insulating layer 124, the semiconductor layer 125, and the dielectric layer 134 and the wiring layer 201 is formed by etching away the unnecessary portions of the conductive film. is formed.

[0198] Thereafter, an insulating film that becomes the insulating layer 212b is formed, and planarization processing is performed so that the upper surfaces of the wiring layer 201, the semiconductor layer 125, the dielectric layer 134, and the gate insulating layer 124 are exposed, thereby forming the insulating layer 212b. The schematic cross-sectional view at this stage corresponds to FIG. 10(C).

[0199] Thereafter, the insulating layer 212c, the electrode layer 122, and the wiring layer 202 are formed according to the above-described method. The schematic cross-sectional view at this stage corresponds to FIG. 10(D).

[0200] Through the above steps, the transistor 102a and the capacitor 103a can be formed on the transistor 101a.

[0201] By using such a method, the semiconductor layer 125 and the dielectric layer 134 can be surely formed in the region inside the gate electrode layer 111a without using a slimming process. .

[0202] The above is the description of this manufacturing process example.

[0203] <Modification Example> Hereinafter, an example of a method for manufacturing a memory device using a thin film of an insulating material as the dielectric layer of the capacitor shown in FIG. 5 will be described with reference to the drawings. Note that hereinafter, the description of the portions overlapping with the above manufacturing process example will be omitted. is omitted.

[0204] FIG. 11 is a schematic cross-sectional view at each stage of this modification example.

[0205] First, a transistor 101a is formed by the method described in the above manufacturing process example.

[0206] Subsequently, a semiconductor layer 125 is formed on the gate electrode layer 111a. Here, in the above configuration example, a dielectric layer 134 made of the same material was formed simultaneously with the semiconductor layer 125, but it should be noted that in this modified example, it is not formed.

[0207] Subsequently, an insulating film constituting the gate insulating layer 124 is formed. At this time, a part of the insulating film can be used as the dielectric layer 134. A schematic cross-sectional view at this stage corresponds to FIG. 11(A). )

[0208] Subsequently, in the process of forming the wiring layer 201, an island-shaped pattern made of the same conductive film as the wiring layer 201 is formed in the region where the capacitor 103a is formed, thereby forming the electrode layer 132. In this way, a capacitor 103a can be formed in which the dielectric layer 134 made of an insulating film is sandwiched between the gate electrode layer 111a and the electrode layer 132. A schematic cross-sectional view at this stage corresponds to FIG. 11(B). )

[0209] Subsequently, the insulating layer 212b and the insulating layer 212c are formed. Then, when forming an opening in the insulating layer 212c that reaches the semiconductor layer 125, an opening that reaches the electrode layer 132 is also formed simultaneously.

[0210] Subsequently, the electrode layer 122 and the wiring layer 202 are formed. The wiring layer 202 is electrically connected to the electrode layer 132 through an opening provided in the insulating layer 212c. A schematic cross-sectional view at this stage corresponds to FIG. 11(C). )

[0211] Thereafter, by proceeding with the steps based on the above-described manufacturing process example, a memory device including a capacitor 103 to which an insulating film is applied as the dielectric layer 134 can be manufactured.

[0212] According to such a method, a vertical transistor and a capacitor can be manufactured simultaneously without increasing the number of photomasks or the manufacturing steps, so that a memory device can be manufactured at low cost and with high yield.

[0213] The above is the description of this modification.

[0214] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0215] (Embodiment 3) In this embodiment, as an example of a semiconductor device according to an aspect of the present invention, a configuration example of a memory device different from the above-described embodiment will be described with reference to the drawings. In the following, descriptions of portions overlapping with the above-described embodiment will be omitted or simplified.

[0216] FIG. 12(A) is a circuit diagram of a main part of the memory device illustrated in this embodiment.

[0217] The memory device includes a transistor 101, a transistor 102, and a capacitor 103.

[0218] In addition, a wiring S1 electrically connected to the first electrodes of the transistor 101 and the transistor 102, a wiring S2 electrically connected to the second electrode of the transistor 101, a wiring W1 connected to the gate of the transistor 102, and a wiring W2 electrically connected to one electrode of the capacitor 103 are provided.

[0219] Figure 12(B) is a schematic top view of the memory device illustrated in this embodiment. Also, Figure 12( C) is a schematic cross-sectional view taken along the cutting line D-D’ in Figure 12(B).

[0220] The memory device shown in Figures 12(B) and 12(C) has a configuration in which the transistor 101 in the memory device illustrated in Embodiment 2 is replaced with a vertical transistor. The memory device includes a wiring layer 204 provided on an insulating surface, a transistor 101 which is a vertical transistor provided on the wiring layer 204, a transistor 102 and a capacitor 103 provided on the gate electrode layer 11

[0221] 1, a wiring layer 201 that functions as a gate electrode of the transistor 102, a wiring layer 202 that functions as one electrode of the capacitor 103, and a wiring layer 203 provided on the transistor 101 and the capacitor 103 and electrically connected to the transistor 101 and the transistor 102. The wiring layer 201 functions as the wiring W1 shown in Figure 12(A). Similarly, the wiring layer 202 functions as the wiring W2, the wiring layer 203 functions as the wiring S1, and the wiring layer 204 functions as the wiring S 2. Also, the gate electrode layer 111 corresponds to the holding node. As shown in Figures 12(B) and 12(C), since the wiring layer 204 can be provided in a lower layer than the transistor 101, the wiring layer 204 and the wiring layer 203 can be provided overlapping each other.

[0222] At this time, the wiring layer 204 and the wiring layer 203 are formed via the layer in which the transistor 101 is provided and the layer in which the transistor 102 and the capacitor 103 are provided. Therefore, the wiring layer 204 and the wiring layer 203 can be provided overlapping each other.

[0223] As shown in Figures 12(B) and 12(C), since the wiring layer 204 can be provided in a lower layer than the transistor 101, the wiring layer 204 and the wiring layer 203 can be provided overlapping each other. Since the wiring layer 204 can be provided in a lower layer than the transistor 101 as shown in Figures 12(B) and 12(C), the wiring layer 204 and the wiring layer 203 can be provided overlapping each other. At this time, the wiring layer 204 and the wiring layer 203 are formed via the layer in which the transistor 101 is provided and the layer in which the transistor 102 and the capacitor 103 are provided. Therefore, the wiring layer 204 and the wiring layer 203 can be provided overlapping each other. ​Means that these distances can be formed with sufficient separation. Therefore, the capacitance between the wiring layers can be ignored It can be reduced to such an extent. In this way, by forming two wiring layers on top of each other The occupied area of the memory device can be made extremely small.

[0224] Also, in FIG. 12(C), the gate electrode layer 111 and the wiring layer 204 are shown to be electrically insulated by the insulating film constituting the gate insulating layer 114 However, an insulating layer may be separately formed between the gate electrode layer 111 and the wiring layer 204 to reduce the capacitance therebetween. In that case The wiring layer 204 and the second electrode layer 113 may be connected by a connection electrode layer penetrating the insulating layer That is, a configuration may be adopted.

[0225] The transistor 101 is provided on the wiring layer 204 and is electrically connected to the second electrode layer 113 which is in electrical connection with the wiring layer 204 A semiconductor layer 115 provided on the second electrode layer 113 and electrically connected to the second electrode layer 113 A first electrode layer 112 provided on the semiconductor layer 115 and electrically connected to the semiconductor layer 11 5, a gate insulating layer 114 provided in contact with the side surfaces of the semiconductor layer 115, the first electrode layer 112, and the second electrode layer 113, and at least a semiconductor A gate electrode layer 111 provided facing the side surface of the body layer 115. The channel The direction is perpendicular to the insulating surface.

[0226] For the semiconductor layer 115, an amorphous semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, etc. can be used

[0227] Typical examples of amorphous semiconductors include hydrogenated amorphous silicon. Also, typical examples of polycrystalline semiconductors include polysilicon (polycrystalline silicon)​​​ Polysilicon includes so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800°C or higher as the main material, so-called low-temperature polysilicon using polysilicon formed at a process temperature of 600°C or lower as the main material, and polysilicon obtained by crystallizing amorphous silicon using elements that promote crystallization, etc. Of course, a microcrystalline semiconductor or a semiconductor including a crystalline phase in a part of the semiconductor layer can also be used.

[0228] Also, as the semiconductor used for the semiconductor layer 115, the above-described oxide semiconductor may be used. In that case, the first electrode layer 112 and the second electrode layer 113 may not be provided.

[0229] When forming the transistor 101, the manufacturing method of the above-described transistor 102 can be adopted. At this time, instead of the single-layer film of the semiconductor constituting the semiconductor layer 125, a laminated film of a semiconductor film doped with impurities constituting the second electrode layer 113, a semiconductor film constituting the semiconductor layer 115, and a semiconductor film doped with impurities constituting the first electrode layer 112 is used, whereby the transistor 101 can be formed.

[0230] The transistor 102 and the capacitor 103 can adopt the configurations exemplified in the above embodiment.

[0231] Thus, by making the transistor 101 a vertical transistor, the transistor 101 can be accommodated within the area range of F. Similarly, the transistor 102 and the capacitor 103 can also be accommodated within the area range of F respectively. Therefore, highly integrated 2 2 ​​​​​​​​​​​​​​Even in this case, it is possible to realize a storage device with an extremely reduced occupied area.

[0232] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0233] (Embodiment 4) In this embodiment, as an example of a semiconductor device according to one embodiment of the present invention, a semiconductor device different from that in the above embodiment will be described. An example of the configuration of the storage device will be described with reference to the drawings. For the parts that overlap with the above description, the explanation will be omitted or will be simplified.

[0234] A memory device according to one embodiment of the present invention includes a first transistor 101 and a second transistor 102. A layer of a memory device (or a layer of a semiconductor device) having a capacitance 103. Hereinafter, the memory layer By stacking multiple layers of semiconductor devices, it is possible to achieve a high degree of integration. A driving circuit may be provided below the memory layer. An example of a structure in which a memory layer is layered and a structure in which a driver circuit is provided below a memory layer will be described.

[0235] <Configuration example 1> The top view of the storage device exemplified in this configuration example is shown in FIG. 3B. -A' and a schematic cross-sectional view taken along line B-B' correspond to FIG.

[0236] The memory device is formed on an insulating surface, and the transistor 101a and the transistor The difference is the configuration of the filter 101b in the second embodiment (for example, FIGS. 4A and 4B). It is different from a storage device.

[0237] The transistor 101a includes a semiconductor layer 115 formed on an insulating surface and a semiconductor layer 115 is provided in contact with the side surface thereof, and includes a first electrode layer 112a and a second electrode layer 113 that are each electrically connected to the semiconductor layer 115, a gate insulating layer 114 provided in contact with the upper surface of the semiconductor layer 115, and a gate electrode layer 111a provided in contact with the upper surface of the gate insulating layer 114. Also, similarly, the transistor 101b includes the semiconductor layer 115, the first electrode layer 112b, the second electrode layer 113, the gate insulating layer 114, and the gate electrode layer 111b. Further, an element isolation layer 211 is provided in contact with the side surfaces of the semiconductor layer 115, the first electrode layer 112a, the first electrode layer 112b, and the second electrode layer 113.

[0238] As the semiconductor used for the semiconductor layer 115, the semiconductors exemplified in Embodiment 3 can be used. Preferably, a manufacturing method of an SOI substrate is applied as the semiconductor used for the semiconductor layer 115, and a single crystal semiconductor is used.

[0239] As the manufacturing method of the SOI substrate, after implanting oxygen ions into a mirror-polished wafer and then performing high-temperature heating, an oxide layer is formed to a certain depth from the surface, and defects generated in the surface layer are eliminated. A method of splitting a semiconductor substrate by utilizing the growth by heat treatment of microvoids formed by hydrogen ion irradiation, a method of forming a single crystal semiconductor layer by crystal growth on an insulating surface, or the like can be used. On the gate electrode layer 111a, a transistor 102a and a capacitor 103a are provided.

[0240]

[0241]

[0242]

[0243] ​​​​​​​​​​Further, a transistor 102b and a capacitor 103b (not shown) are provided on the gate electrode layer 111b. are provided.

[0244] Here, at least the transistor 101a, the transistor 102a, and the capacitor 103a are collectively referred to as a memory layer 250. Preferably, the memory layer 250 has a plurality of storage devices provided in parallel in a direction parallel to the formation surface. Further, the memory layer 250 includes a wiring layer for electrically connecting transistors and capacitors.

[0245] In this way, by configuring the transistors 101a and 101b to be formed on an insulating surface, it becomes possible to stack a plurality of memory layers 250 or to provide a drive circuit in a layer below the memory layer 250.

[0246] FIG. 14 shows a configuration of a storage device in which a memory layer 250a and a memory layer 250b are stacked on a drive circuit portion 260 formed using a conventional CMOS process. The memory layer 250a is provided on the drive circuit portion 260 via an interlayer insulating layer 251a. Further, the memory layer 250b is provided on the memory layer 250a via an interlayer insulating layer 251b.

[0247] The surface of the interlayer insulating layer 251a and the interlayer insulating layer 251b is preferably planarized. Further, in order to reduce the parasitic capacitance between the drive circuit portion 260 and the memory layer 250a, or between the memory layer 250a and the memory layer 250b, it is preferable to use an insulating material with a low dielectric constant for the interlayer insulating layer 251a and the interlayer insulating layer 251b, or to form them thick enough.

[0248] The surface of the interlayer insulating layer 251a and the interlayer insulating layer 251b is preferably planarized. Further, in order to reduce the parasitic capacitance between the drive circuit portion 260 and the memory layer 250a, or between the memory layer 250a and the memory layer 250b, it is preferable to use an insulating material with a low dielectric constant for the interlayer insulating layer 251a and the interlayer insulating layer 251b, or to form them thick enough. Also, in order to reduce the parasitic capacitance between the drive circuit portion 260 and the memory layer 250a, or between the memory layer 250a and the memory layer 250b, it is preferable to use an insulating material with a low dielectric constant for the interlayer insulating layer 251a and the interlayer insulating layer 251b, or to form them thick enough. 51b, or to form them thick enough. is preferred. ​​​​​

[0249] Each wiring layer included in the memory layer 250a and the memory layer 250b is The driving circuit section 260 is electrically connected via a connection electrode layer, and the driving circuit section 260 This controls operations such as writing, erasing, and reading data.

[0250] In this way, by using a configuration in which multiple memory layers are stacked, the occupied area of ​​the memory device can be reduced. The amount of data per pixel can be increased. In addition, the driving circuit is placed below the memory layer. This makes it possible to suppress an increase in the occupied area.

[0251] This concludes the description of this configuration example.

[0252] <Modification> In addition, a vertical transistor is used as the transistor 101 in the example of Embodiment 3. In this case, multiple memory layers can be stacked as in the above configuration example, and a driving circuit can be placed on the lower layer. It is possible to provide.

[0253] FIG. 15 shows a memory device in which a vertical transistor is used as the transistor 101. An example of the configuration is shown below.

[0254] As in the above configuration example, the memory layer 250a is connected to the drive circuit section 2 via the interlayer insulating layer 251a. The memory layer 250b is provided on the memory cell 60 via an interlayer insulating layer 251b. The insulating layer 250a is provided on the insulating layer 250b.

[0255] Here, the memory layer 250a and the memory layer 250b are A storage device with a significantly reduced area is applied. By stacking multiple layers, the amount of data per unit area can be made extremely large. can be achieved.

[0256] The above is the description of this modified example.

[0257] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. and can be achieved.

[0258] (Embodiment 5) As an oxide semiconductor applicable to the semiconductor layer 125 exemplified in the above embodiment, when a semiconductor film having crystallinity is used, the electrical characteristics of the transistor can be improved. Preferably, it is preferable to use a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film as the semiconductor film. Hereinafter, a semiconductor device to which a CAAC-OS film is applied will be described. has, the electrical characteristics of the transistor can be improved. Preferably, as the semiconductor film, it is preferable to use a CAAC-OS (C Axis Aligned Crystalline O xide Semiconductor) film. Hereinafter, a semiconductor device to which a CAAC C-OS film is applied will be described.

[0259] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous material. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed-phase structure having a crystal part and an amorphous part in an amorphous phase. Note that the crystal part is often sized to fit within a cube with a side length of less than 100 nm. In addition, in an observation image by a transmission electron microscope (TEM: Transmission Electro n Microscope), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Also, no grain boundaries (also referred to as grain boundaries) can be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is suppressed. is suppressed. resulting from grain boundaries is suppressed.

[0260] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the formation surface of the CAAC-OS film. They are aligned in a direction parallel to the normal vector of the torus or the surface, and viewed from a direction perpendicular to the ab plane, they have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included. They have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included. They have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included. They have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included. They have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included. They have a triangular or hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a axis and the b axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, the range of -5° or more and 5° or less is also included.

[0261] Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may be amorphous in the impurity addition region. Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may be amorphous in the impurity addition region. Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may be amorphous in the impurity addition region. Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may be amorphous in the impurity addition region. Note that in the CAAC-OS film, the distribution of crystal parts may not be uniform. For example, in the process of forming the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of crystal parts may be higher near the surface than near the formation surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may be amorphous in the impurity addition region.

[0262] The c axes of the crystal parts included in the CAAC-OS film are aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the surface, so depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions from each other. The c axes of the crystal parts included in the CAAC-OS film are aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the surface, so depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions from each other. The c axes of the crystal parts included in the CAAC-OS film are aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the surface, so depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface), they may face different directions from each other. Note that the direction of the c axis of the crystal part is parallel to the normal vector of the formation surface of the CAAC-OS film or the surface when the CAAC-OS film is formed. The crystal part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Note that the direction of the c axis of the crystal part is parallel to the normal vector of the formation surface of the CAAC-OS film or the surface when the CAAC-OS film is formed. The crystal part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation. Note that the direction of the c axis of the crystal part is parallel to the normal vector of the formation surface of the CAAC-OS film or the surface when the CAAC-OS film is formed. The crystal part is formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0263] A transistor using the CAAC-OS film has little change in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability. A transistor using the CAAC-OS film has little change in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0264] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0265] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk are reduced. By improving the flatness of the surface, the transfer rate can be reduced to a level equal to or greater than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, an oxide semiconductor is formed on the flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, and preferably It is advisable to form it on the surface with a thickness of 0.3 nm or less, more preferably 0.1 nm or less.

[0266] In addition, Ra is defined in JIS B 0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness defined above so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from the reference surface to the specified surface" and is given by the following formula (1): is defined.

[0267]

number

[0268] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),( The specified surface is the xy plane, and the rectangular area is represented by four points, x2, y2, f(x2, y2), The area of ​​the rectangle projected onto the surface is S0, and the height of the reference surface (the average height of the specified surface) is Z0. a is taken with an atomic force microscope (AFM). It is measurable.

[0269] As a method for obtaining the above-mentioned CAAC-OS film, for example, a method for forming the CAAC-OS film by heating a substrate (e.g. The oxide semiconductor film was formed with the substrate temperature at 170° C., and the c-axis orientation was approximately perpendicular to the surface. There is a way to make it happen.

[0270] Note that the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. Either the oxide semiconductor film or the second oxide semiconductor film has a crystal structure different from that of the CAAC-OS. That is, a CAAC-OS and a single-crystal oxide semiconductor may be used. , a polycrystalline oxide semiconductor, or an amorphous oxide semiconductor may be appropriately combined. In addition, at least one of the first oxide semiconductor film and the second oxide semiconductor film is amorphous. By applying a high-temperature oxide semiconductor, the internal stress and external stress of the stacked oxide semiconductor film can be reduced. This reduces the variation in transistor characteristics and further improves the reliability of the transistor. On the other hand, amorphous oxide semiconductors have impurities that act as donors, such as hydrogen. It is easy to absorb oxygen and oxygen vacancies occur easily, so it is easy to become n-type. The oxide semiconductor film on the insulating layer side is made of a crystalline oxide semiconductor such as CAAC-OS. It is preferred.

[0271] In addition, the oxide semiconductor film has a stacked structure of three or more layers, and the oxide semiconductor film has crystallinity. The amorphous oxide semiconductor film may be sandwiched between two insulating films. Alternatively, the oxide semiconductor film may be formed by stacking an amorphous oxide semiconductor film and an amorphous oxide semiconductor film alternately. When the above-mentioned structure is a laminated structure of a plurality of films, each of them can be used in appropriate combination. can be done.

[0272] As described above, by using a CAAC-OS film as the oxide semiconductor film, in the heat treatment ( dehydrogenation treatment), hydrogen can be easily removed from the upper surface of the CAAC-OS film. In addition, in this heat treatment, the release of oxygen can be reduced and a large amount of hydrogen can be selectively released.

[0273] This embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0274] (Embodiment 6) In this embodiment, as an example of a semiconductor device, a CPU (Central Processing Unit) that uses at least a part of the memory device disclosed in the above embodiment will be described.

[0275] FIG. 16(A) is a block diagram showing a specific configuration of the CPU. The CPU shown in FIG. 16(A) has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 ( ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 16(A) is only an example showing a simplified configuration thereof, and an actual CPU has various configurations depending on its application. ​​​​​​

[0276] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, and after being decoded, are input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0277] Based on the decoded instructions, the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194 determines and processes interrupt requests from external input / output devices and peripheral circuits during the execution of the CPU's program, based on their priorities and mask states. The register controller 1197 generates addresses for the registers 1196 and performs read and write operations on the registers 1196 according to the state of

[0278] the CPU. Also, the timing controller 1195 generates signals for controlling the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies

[0279] the internal clock signal CLK2 to the various circuits described above. In the CPU shown in FIG. 16(A), memory cells are provided in the registers 1196 As the memory cell, the storage device shown in the first to fourth embodiments can be applied. The memory cell of register 1196 includes a logic element that inverts a logical value and the storage device disclosed in the above embodiments. Both are provided.

[0280] In the CPU shown in FIG. 16(A), register controller 1197 selects the holding operation in register 1196 according to an instruction from ALU119 1. That is, in the memory cell included in register 1196, it is selected whether to hold data by a logic element that inverts a logical value or to hold data by a storage device. When holding of data by a logic element that inverts a logical value is selected, power supply voltage is supplied to the memory cell in register 1196. When holding of data in the storage device is selected, data is rewritten to the storage device, and supply of power supply voltage to the memory cell in register 1196 can be stopped.

[0281] Regarding power supply stop, as shown in FIG. 16(B) or FIG. 16(C), a switching element is provided between the memory cell group and the node to which power supply potential VDD or power supply potential VSS is applied. The circuit of FIG. 16(B) and FIG. 16(C) will be described below.

[0282] In FIG. 16(B) and FIG. 16(C), register 1196 includes a switching element that controls supply of power supply potential to the memory cell.

[0283] Register 1196 shown in FIG. 16(B) includes switching element 1141 and memory cell 1 It has a memory cell group 1143 having a plurality of 142. Specifically, each memory cell 11 42 is provided with both a logic element for inverting a logical value and the above storage device. Each memory cell 1142 included in the memory cell group 1143 is supplied with a high-level power supply potential VDD via a switching element 1141. Furthermore, each memory cell 1142 included in the memory cell group 1143 is given the potential of the signal IN and the potential of the low-level power supply potential VSS.

[0284] In FIG. 16(B), a transistor is used as the switching element 1141, and the switching of the transistor is controlled by a signal SigA applied to its gate electrode.

[0285] Note that in FIG. 16(B), the switching element 1141 is shown having only one transistor, but it is not particularly limited and may have a plurality of transistors. When the switching element 1141 has a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, in series, or in a combination of series and parallel.

[0286] Also, FIG. 16(C) shows an example of a register 1196 in which a low-level power supply potential VSS is supplied to each memory cell 1142 included in the memory cell group 1143 via a switching element 1141. The supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143 can be controlled by the switching element 1141.

[0287] ​​​​​​​​​​​​Between a memory cell group and a node supplied with a power supply potential VDD or a power supply potential VSS, a switching element is provided, and it is possible to temporarily stop the operation of the CPU and stop the supply of the power supply voltage, and it is possible to hold data even in such a case, and power consumption can be reduced. Specifically, for example, even while a user of a personal computer has stopped inputting information to an input device such as a keyboard, it is possible to stop the operation of the CPU without losing the data in the memory cell group, and thereby reduce the power consumption. That is, it is possible to reduce the power consumption.

[0288] In addition, since the power consumption of an electronic device to which such a CPU is applied is reduced, for example, it can be sufficiently operated even with relatively small power obtained by a solar cell or non-contact power supply (also referred to as wireless power supply). For example, the electronic device is configured to include a solar cell module or a non-contact power supply module and a secondary battery ( such as a lithium ion battery) that stores the power obtained by such a module. Here, although the CPU has been described as an example, it can also be applied to LSIs such as DSP (Digital Signal Processor), custom LSI, and FPGA (Field Programmab

[0289] le Gate Array). Processor), custom LSI, FPGA (Field Programmable Gate Array), etc.

[0290] (Embodiment 7) The storage device and semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of the electronic device include display devices such as televisions and monitors, lighting devices, desk top or notebook personal computers, word processors, and still images or recorded on a recording medium such as a DVD (Digital Versatile Disc). Image playback devices for playing videos, portable CD players, radios, tape recorders, head phone stereos, stereos, cordless phone handsets, transceivers, portable radios, mobile phones , car phones, portable game machines, calculators, portable information terminals, electronic organizers, e-books, electronic translators , voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens , rice cookers, washing machines, vacuum cleaners, air conditioning equipment such as air conditioners , dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, freezers , refrigerator-freezers, freezers for DNA storage, medical devices such as smoke detectors, radiation measuring devices, dialysis devices , etc. Furthermore, industrial equipment such as induction lamps, traffic lights, belt conveyors, elevators, escalators , industrial robots, power storage systems, etc. can also be mentioned. Also, engines using oil , and moving bodies propelled by electric motors using power from non-aqueous secondary batteries, etc. are to be included in the category of electronic devices. As the above-mentioned moving bodies, for example, electric vehicles (EVs) , hybrid vehicles (HEVs) having both an internal combustion engine and an electric motor, plug-in hybrid vehicles (PHEVs), tracked vehicles obtained by changing the tires of these vehicles to endless tracks, motorized bicycles including electric assist bicycles , motorcycles, electric wheelchairs, golf carts, small or large ships, submarines , helicopters, aircraft, rockets, artificial satellites, space exploration vehicles, planetary exploration vehicles, spaceships can be mentioned. Specific examples of these electronic devices are shown in FIGS. 17 and 18.

[0291] FIG. 17(A) is a portable music player. The main body 3021 is provided with a display unit 3023, a fixing unit 3022 for wearing on the ear , operation buttons 3024, an external connection port 3025, etc. It may also have a speaker. By applying the memory device or the semiconductor device exemplified in the above embodiment to the memory, CPU, etc. built in the main body 3021, a more power-saving portable music player (PDA) can be obtained.

[0292] Furthermore, if the portable music player shown in Fig. 17(A) is provided with an antenna, a microphone function, and a wireless function and is linked with a mobile phone, it is possible to have a hands-free wireless conversation while driving a vehicle such as a car.

[0293] Fig. 17(B) shows a computer, which includes a main body 9201 including a CPU, a housing 9202, a display unit 9203, a keyboard 9204, an external connection port 9205, a pointing device 9 206, etc. By using the semiconductor devices such as the memory device and the CPU shown in the above embodiment, it is possible to obtain a power-saving computer.

[0294] In Fig. 18(A), a television device 8000 has a display unit 8002 incorporated in a housing 8001. The display unit 8002 can display an image and output sound from a speaker unit 8003. The memory device or semiconductor device exemplified in the above embodiment can be used for a drive circuit for operating the display unit 8002 incorporated in the housing 8001.

[0295] The display unit 8002 can use a light-emitting device having a light-emitting element such as a liquid crystal display device or an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Devi ce), a PDP (Plasma Display Panel), etc., a semiconductor display device.

[0296] The television apparatus 8000 may be provided with a receiver, a modem, etc. The television apparatus 8000 can receive general television broadcasts by a receiver, and further by connecting to a wired or wireless communication network via a modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between the receivers, etc.) information communication can also be performed.

[0297] Also, the television apparatus 8000 may be provided with a CPU and a memory for performing information communication. The television apparatus 8000 can use the storage device and semiconductor devices such as a CPU exemplified in the above embodiment.

[0298] In FIG. 18(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a semiconductor device such as a CPU exemplified in the above embodiment. Specifically, the indoor unit 8200 has a housing 8201, an air outlet 8202, a CPU 8203, etc. In FIG. 18(A), the case where the CPU 8203 is provided in the indoor unit 8200 is exemplified, but the CPU 8203 may be provided in the outdoor unit 8204. Or the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the CPU exemplified in the above embodiment, an air conditioner excellent in power saving can be realized.

[0299] In FIG. 18(A), an electric refrigerator-freezer 8300 is an example of an electronic device provided with a semiconductor device such as a CPU exemplified in the above embodiment. Specifically, the electric refrigerator-freezer 8300 , having a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, etc. . In FIG. 18(A), the CPU 8304 is provided inside the housing 8301. The above-mentioned semiconductor devices such as the CPU exemplified in the above embodiment are used for the CPU 8304 of the electric refrigerating refrigerator 8300, thereby achieving power saving.

[0300] In FIGS. 18(B) and 18(C), an example of an electric vehicle, which is an example of an electronic device, is shown. An electric vehicle 9700 is equipped with a secondary battery 9701. The power of the secondary battery 9701 is adjusted by a control circuit 9702 and supplied to a drive device 9703. The control circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using the semiconductor devices such as the storage device and the CPU exemplified in the above embodiment for the processing device 9704 of the electric vehicle 9700, power saving can be achieved.

[0301] The drive device 9703 is composed of a DC motor or an AC motor alone, or a combination of a motor and an internal combustion engine. The processing device 9704 outputs a control signal to the control circuit 9702 based on the input information such as the operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and the information during running (information such as uphill and downhill, load information applied to the drive wheels, etc.). The control circuit 9702 adjusts the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704 to control the output of the drive device 9703. In the case of mounting an AC motor, although not shown, an inverter for converting DC to AC is also built in.

[0302] This embodiment can be implemented in appropriate combination with other embodiments described in this specification. It is possible.

Description of Signs

[0303] 101 Transistor 101a Transistor 101b Transistor 102 Transistor 102a Transistor 102b Transistor 103 Capacitance 103a Capacitance 103b Capacitance 110a Memory Element 110b Memory Element 111 Gate Electrode Layer 111a Gate Electrode Layer 111b Gate Electrode Layer 112 First Electrode Layer 112a First Electrode Layer 112b First Electrode Layer 113 Second Electrode Layer 114 Gate Insulating Layer 115 Semiconductor Layer 121 Gate Electrode Layer 122 Electrode Layer 124 Gate Insulating Layer 125 Semiconductor Layer 132 Electrode Layer 134 Dielectric Layer 201 Wiring Layer 202 Wiring Layer 203 Wiring Layer 203a Wiring Layer 203b Wiring Layer 204 Wiring Layer 211 Element Isolation Layer 212a Insulating Layer 212b Insulating Layer 212c Insulating Layer 212d Insulating Layer 212e Insulating Layer 212f Insulating Layer 212g Insulating Layer 212h Insulating Layer 212i Insulating Layer 213a Connection electrode layer 213b Connection electrode layer 213c Connection electrode layer 250 Memory layer 250a Memory layer 250b Memory layer 251a Interlayer insulation layer 251b Interlayer insulation layer 260 Drive circuit section 1141 Switching element 1142 Memory cell 1143 Memory cell group 1189 ROM interface 1190 Substrate 1191 ALU 1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM 3021 Main body 3022 Fixing part 3023 Display part 3024 Operation button 3025 External connection port 8000 Television device 8001 Housing 8002 Display part 8003 Speaker part 8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Door for refrigerator compartment 8303 Door for freezer compartment 8304 CPU 9201 Main body 9202 Housing 9203 Display Unit 9204 Keyboard 9205 External Connection Port 9206 Pointing Device 9700 Electric Vehicle 9701 Secondary Battery 9702 Control Circuit 9703 Driving Device 9704 Processing Device

Claims

[Claim 1] A first transistor; a second transistor overlapping the first transistor; a capacitance provided to overlap the first transistor; A first semiconductor layer; a first insulating layer having a region on the first semiconductor layer; a first conductive layer having a region provided on the first insulating layer and having a region overlapping with the first semiconductor layer; a second semiconductor layer having a region provided on the first conductive layer and electrically connected to the first conductive layer; a second insulating layer having a region in contact with a side surface of the second semiconductor layer; a second conductive layer having a region facing the side surface of the second semiconductor layer via the second insulating layer; a third conductive layer having a region provided on the second semiconductor layer and electrically connected to the second semiconductor layer; a fourth conductive layer having an area overlapping the first conductive layer; a dielectric layer having an area between the first conductive layer and the fourth conductive layer; the first semiconductor layer has a channel formation region of the first transistor; the second semiconductor layer has a channel formation region of the second transistor; the first conductive layer functions as one electrode of the capacitance; The fourth conductive layer functions as the other electrode of the capacitor.

Images