Thin film transistor and display apparatus comprising the same

Abstract

To provide a thin film transistor in which the conduction penetration depth can be controlled.SOLUTION: A thin film transistor (100) comprises an active layer (130) and a gate electrode (150) spaced apart from the active layer to at least partially overlap the active layer. The active layer includes a channel area (130a) that is overlapped by the gate electrode in the plan view, a source area (130b) connected to one side of the channel area without being overlapped by the gate electrode in the plan view and a drain area (130c) connected to the other side of the channel area without being overlapped by the gate electrode in the plan view. The source area and the drain area are spaced apart from each other with the channel area interposed therebetween. The active layer includes a first source conductive control area (135a) and a first drain conductive control area (136a), which are spaced apart from each other. At least a portion of the first source conductive control area overlaps at least a portion of the gate electrode, and at least a portion of the first drain conductive control area overlaps at least a portion of the gate electrode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a display device including transistors and transistors.

Background Art

[0002] Transistors are widely used as switching devices and driving devices in the field of electronic devices. In particular, thin film transistors can be manufactured on a glass substrate or a plastic substrate, and thus are widely used as switching elements of display devices such as liquid crystal display devices and organic light emitting devices.

[0003] Thin film transistors can be classified into amorphous silicon thin film transistors in which amorphous silicon is used as an active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as an active layer, and oxide semiconductor thin film transistors in which an oxide semiconductor is used as an active layer.

[0004] Amorphous silicon thin film transistors (a-Si TFTs) have the advantage that an active layer can be formed by depositing amorphous silicon in a short time, so that the manufacturing process time is short and the production cost is low. On the other hand, they have the disadvantage that they have low mobility, poor current driving ability, and a change in threshold voltage, so their use is restricted in active matrix organic light emitting elements (AMOLEDs) and the like.

[0005] A polycrystalline silicon thin film transistor (poly-Si TFT) is formed by depositing amorphous silicon and then crystallizing the amorphous silicon. Since a process of crystallizing amorphous silicon is required in the manufacturing process of the polycrystalline silicon thin film transistor, the number of processes increases and the manufacturing cost rises. Also, because the crystallization process is performed at a high process temperature, it is difficult to apply the polycrystalline silicon thin film transistor to large-area devices. Further, due to the polycrystalline characteristics, it is difficult to ensure the uniformity of the polycrystalline silicon thin film transistor.

[0006] An oxide semiconductor thin film transistor (Oxide semiconductor TFT) can form an oxide constituting the active layer at a relatively low temperature, has a high mobility, and has a large resistance change according to the oxygen content, so that desired physical properties can be easily obtained. Also, due to the characteristics of the oxide, the oxide semiconductor is transparent, which is also advantageous for realizing a transparent display.

[0007] In the case of an oxide semiconductor thin film transistor, selective conductivity may be required for the oxide semiconductor layer. In this case, control of the conductivity region and the conductivity penetration depth formed in the oxide semiconductor layer is very important. Therefore, techniques for controlling the conductivity region and the conductivity penetration depth are being studied.

Summary of the Invention

Problems to be Solved by the Invention

[0008] One embodiment of the present invention provides a thin film transistor capable of controlling the conductivity penetration depth even when the active layer includes a pattern and the channel region has a large width.

[0009] One embodiment of the present invention provides a thin film transistor that prevents or suppresses the threshold voltage (Vth) from shifting in the negative (-) direction even when the active layer includes a pattern and the channel region has a large width.

[0010] One embodiment of the present invention provides a thin film transistor in which the active layer includes a pattern and the reliability is improved.

[0011] Another embodiment of the present invention provides a display device including the above-described transistor.

Means for Solving the Problems

[0012] One embodiment of the present invention for achieving the above-described technical problems includes an active layer and a gate electrode spaced apart from the active layer and at least partially overlapping the active layer. In plan view, the active layer includes a channel region overlapping the gate electrode, a source region not overlapping the gate electrode in plan view and connected to one side of the channel region, and a drain region not overlapping the gate electrode in plan view and connected to the other side of the channel region. The source region and the drain region are spaced apart from each other with the channel region therebetween. The active layer includes a first source conductivity adjustment region and a first drain conductivity adjustment region spaced apart from each other. At least a part of the first source conductivity adjustment region overlaps at least a part of the gate electrode, and at least a part of the first drain conductivity adjustment region overlaps at least a part of the gate electrode, and provides a thin film transistor.

Effects of the Invention

[0013] The thin film transistor according to one embodiment of the present invention can control the conductivity penetration depth even when the active layer includes a pattern and the channel region has a large width.

[0014] The thin film transistor according to one embodiment of the present invention can control the shift of the threshold voltage (Vth) in the negative (-) direction even when the active layer includes a pattern and the channel region has a large width.

[0015] According to one embodiment of the present invention, since the active layer of the thin film transistor includes a pattern, it can have stability and excellent reliability.

[0016] In addition to the above-described effects, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the technical field to which the present invention pertains from such technology and description.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0018] The advantages and features of the present invention, and the method for achieving them, will become apparent by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but is configured in various different forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention.

[0019] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals can refer to the same components. In the description of the present invention, when it is determined that a specific description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof is omitted.

[0020] When terms such as "including", "having", "consisting of", etc. referred to in the present invention are used, other parts can be added unless "only" is used. When a component is expressed in the singular, it includes a plurality unless otherwise explicitly stated.

[0021] In interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0022] For example, when the positional relationship between two parts is described by "on ~", "above ~", "below ~", "beside ~", etc., one or more other parts can be located between the two parts unless the expressions "immediately" or "directly" are used.

[0023] Spatially relative terms such as "below", "beneath", "above", "upper", etc. can be used to easily describe the correlation between one element or component and another element or component, as shown in the figures. Spatially relative terms should be understood as terms that include different directions of elements relative to each other during use or operation, in addition to the directions shown in the figures. For example, when the elements shown in the figure are inverted, an element described as "below" or "lower" than another element can be placed "above" the other element. Therefore, the exemplary term "below" can include both the downward and upward directions. Similarly, the exemplary terms "above" or "upper" can include both the upward and downward directions.

[0024] In the case of an explanation regarding a time relationship, for example, when a time sequence relationship is explained using terms such as "after", "subsequent to", "next", "before", etc., it can include cases that are not continuous unless the expressions "immediately" or "directly" are used.

[0025] Terms such as "first", "second", etc. are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component mentioned below can also be the second component within the technical idea of the present invention.

[0026] The term "at least one" should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of "at least one of the first item, the second item, and the third item" can mean not only each of the first item, the second item, or the third item alone, but also all combinations of two or more of the first item, the second item, and the third item that can be presented.

[0027] The features of each of several embodiments of the present invention can be partially or wholly combined or combined with each other, enabling various linkages and drives technically. Each embodiment can be implemented independently of each other or can be implemented together in an associated relationship.

[0028] When adding reference numerals to the components of each figure illustrating an embodiment of the present invention, for the same component, even if it is shown in different figures, it can have the same numeral as much as possible.

[0029] In an embodiment of the present invention, the source electrode and the drain electrode are only distinguished for the convenience of explanation, and the source electrode and the drain electrode can be interchanged with each other. The source electrode can become the drain electrode, and the drain electrode can become the source electrode. Also, the source electrode of any one embodiment can be the drain electrode in other embodiments, and the drain electrode of any one embodiment can be the source electrode in other embodiments.

[0030] In some embodiments of the present invention, for the convenience of explanation, the source region and the source electrode can be distinguished, and the drain region and the drain electrode can be distinguished, but the embodiments of the present invention are not limited thereto. The source region can be used as the source electrode, and the drain region can be used as the drain electrode. Also, the source region can become the drain electrode, and the drain region can become the source electrode.

[0031] FIG. 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. FIG. 2A is a cross-sectional view taken along line I-I' of FIG. 1. FIG. 2B is a cross-sectional view taken along line II-II' of FIG. 1.

[0032] Referring to FIGS. 1, 2A and 2B, a transistor 100 according to an embodiment of the present invention can include an active layer 130 and a gate electrode 150.

[0033] Specifically, referring to FIGS. 1, 2A, and 2B, it can include an active layer 130 and a gate electrode 150 that is separated from the active layer 130 and at least partially overlaps the active layer 130.

[0034] According to an embodiment of the present invention, the thin film transistor 100 can further include a base substrate 110. Referring to FIGS. 2A and 2B, the active layer 130 is disposed on the base substrate 110.

[0035] According to an embodiment of the present invention, the thin film transistor 100 can further include a buffer layer 120. Referring to FIGS. 2A and 2B, the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0036] According to an embodiment of the present invention, the thin film transistor 100 can further include a gate insulating film 140. Referring to FIGS. 2A and 2B, the gate insulating film 140 is disposed on the active layer 130. Specifically, the gate insulating film 140 is disposed between the active layer 130 and the gate electrode 150.

[0037] According to an embodiment of the present invention, the thin film transistor 100 can further include an interlayer insulating film 160. Referring to FIG. 2A, the interlayer insulating film 160 is disposed on the gate electrode 150. Specifically, the gate electrode 150 is disposed between the gate insulating film 140 and the interlayer insulating film 160.

[0038] According to an embodiment of the present invention, the thin film transistor 100 can further include a source electrode 171 and a drain electrode 172. Referring to FIG. 2A, the source electrode 171 and the drain electrode 172 are disposed on the interlayer insulating film 160. Specifically, the interlayer insulating film 160 is disposed between the gate electrode 150 and the source electrode 171 and the drain electrode 172.

[0039] Hereinafter, the components of the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0040] The base substrate 110 can be made of glass or plastic. As the plastic, a transparent plastic having flexible properties, such as polyimide, can be used.

[0041] When using polyimide as the base substrate 110, considering that a high-temperature evaporation process is performed on the base substrate 110, heat-resistant polyimide that can withstand high temperatures can be used. In this case, for the formation of the thin film transistor, processes such as evaporation and etching can be carried out while the polyimide substrate is placed on a carrier substrate made of a highly durable material such as glass.

[0042] Referring to FIGS. 2A and 2B, a buffer layer 120 can be disposed on the base substrate 110.

[0043] The buffer layer 120 is formed on the base substrate 110 and can be formed of an inorganic material or an organic material. For example, it can contain insulating oxides such as silicon oxide (SiOx) and aluminum oxide (Al2O3).

[0044] The buffer layer 120 blocks impurities such as moisture and oxygen flowing in from the base substrate 110 to protect the active layer 130, plays a role in planarizing the upper part of the base substrate 110, and can be formed as a single layer or a plurality of layers.

[0045] Referring to FIGS. 2A and 2B, an active layer 130 can be disposed on the buffer layer 120.

[0046] The active layer 130 can include a channel region 130a, a source region 130b, and a drain region 130c.

[0047] Specifically, the active layer 130 can include a channel region 130a that overlaps with the gate electrode 150 in plan view, a source region 130b that does not overlap with the gate electrode 150 in plan view and is connected to one side of the channel region 130a, and a drain region 130c that does not overlap with the gate electrode 150 in plan view and is connected to the other side of the channel region 130a.

[0048] According to an embodiment of the present invention, the source region 130b and the drain region 130c are separated from each other with the channel region 130a interposed therebetween.

[0049] According to an embodiment of the present invention, the active layer 130 can be formed of a semiconductor material. The active layer 130 can include an oxide semiconductor material.

[0050] The oxide semiconductor material can include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and an FIZO (FeInZnO)-based oxide semiconductor material. However, an embodiment of the present invention is not limited thereto, and the active layer 130 can also be made of other oxide semiconductor materials known in the art.

[0051] The source region 130b and the drain region 130c can be formed by selective conductivity conversion with respect to the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, selective conductivity conversion refers to imparting conductivity to a specific site of the active layer 130 so that it can play a role like a conductor.

[0052] For example, the active layer 130 can be selectively made conductive by ion doping. As a result, the source region 130b and the drain region 130c can be formed. However, an embodiment of the present invention is not limited to this, and the active layer 130 can also be selectively made conductive by other methods known in the art.

[0053] The source region 130b and the drain region 130c do not overlap with the gate electrode 150. The source region 130b and the drain region 130c have excellent conductivity and high mobility compared to the channel region 130a. Therefore, the source region 130b and the drain region 130c can each serve as wiring.

[0054] Referring to FIG. 1, the channel region 130a has a channel length (L) and a channel width (W). Here, the channel length (L) of the channel region 130a means the length in the directions of the source region 130b and the drain region 130c. Also, the channel width (W) of the channel region 130a means the length in the direction perpendicular to the length of the channel region 130a.

[0055] According to an embodiment of the present invention, the active layer 130 can include a first source conductivity adjustment region 135a and a first drain conductivity adjustment region 136a. Also, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a are spaced apart from each other. Specifically, they are spaced apart from each other with at least a part of the channel region 130a interposed therebetween.

[0056] Referring to FIGS. 1 and 2B, the first source-conductivization adjustment region 135a can overlap at least a part of the channel region 130a. FIG. 1 shows a configuration in which the first source-conductivization adjustment region 135a overlaps at least a part of the channel region 130a. Specifically, at least a part of the first source-conductivization adjustment region 135a can overlap at least a part of the gate electrode 150. FIG. 1 shows a configuration in which at least a part of the first source-conductivization adjustment region 135a overlaps at least a part of the gate electrode 150. However, an embodiment of the present invention is not limited to this, and the first source-conductivization adjustment region 135a can overlap the channel region 130a and at the same time overlap the source region 130b. Specifically, it is possible that at least a part of the first source-conductivization adjustment region 135a overlaps the gate electrode 150 and at the same time another part of the first source-conductivization adjustment region 135a does not overlap the gate electrode 150. Here, the fact that the first source-conductivization adjustment region 135a overlaps at least a part of the channel region 130a can be regarded as the same structural expression as the fact that the first source-conductivization adjustment region 135a overlaps at least a part of the gate electrode 150. The same applies to the first source-conductivization adjustment region 136a below.

[0057] Further, the first drain conductivity adjustment region 136a can overlap at least a part of the channel region 130a. FIG. 1 shows a configuration in which the first drain conductivity adjustment region 136a overlaps at least a part of the channel region 130a. More specifically, at least a part of the first drain conductivity adjustment region 136a can overlap at least a part of the gate electrode 150. FIG. 1 shows a configuration in which at least a part of the first drain conductivity adjustment region 136a overlaps at least a part of the gate electrode 150. However, an embodiment of the present invention is not limited to this. Referring to FIG. 1, the first drain conductivity adjustment region 136a can overlap the channel region 130a and at the same time overlap the drain region 130c. More specifically, it is possible that at least a part of the first drain conductivity adjustment region 136a overlaps the gate electrode 150 while another part of the first drain conductivity adjustment region 136a does not overlap the gate electrode 150.

[0058] According to an embodiment of the present invention, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a can be formed by patterning the active layer 130. Specifically, the first source conductivity adjustment region 135a overlaps at least a part of the channel region 130a and can be said to be a region surrounded by the active layer 130 on the periphery. Specifically, the first source conductivity adjustment region 135a overlaps at least a part of the gate electrode 150 and can be said to be a region surrounded by the active layer 130 on the periphery. For example, the first source conductivity adjustment region 135a can be said to be a part where the active layer 130 is partially patterned and removed.

[0059] Further, the first drain conductivity adjustment region 136a overlaps at least a part of the channel region 130a and can be said to be a region surrounded by the active layer 130 on the periphery. Specifically, the first drain conductivity adjustment region 136a overlaps at least a part of the gate electrode 150 and can be said to be a region surrounded by the active layer 130 on the periphery. For example, the first drain conductivity adjustment region 136a can be said to be a part where the active layer 130 is partially patterned and removed.

[0060] Referring to FIG. 1, according to an embodiment of the present invention, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a have a width (D) and a length (S), where the width (D) can be in the range of 0.5 to 5 μm.

[0061] Referring to FIG. 1, according to an embodiment of the present invention, if the length of the region where the first source conductivity adjustment region 135a overlaps with the gate electrode 150 is S1, then S1 can be in the range of 0.5 to 1.5 μm. The same applies to the case of the first drain conductivity adjustment region 136a. If the length of the region where the first drain conductivity adjustment region 136a overlaps with the gate electrode 150 is S2, then S2 can be in the range of 0.5 to 1.5 μm.

[0062] According to an embodiment of the present invention, the first source conductivity adjustment region 135a can overlap with the source region 130b. Specifically, the first source conductivity adjustment region 135a can protrude from the gate electrode 150 toward the source region 130b in a plan view. If the length of the region where the first source conductivity adjustment region 135a overlaps with the source region 130b is S3, then S3 can be in the range of 0.5 to 5 μm. Specifically, if the length of the region where the first source conductivity adjustment region 135a protrudes from the gate electrode 150 in a plan view is S3, then S3 can be in the range of 0.5 to 5 μm. The same applies to the case of the first drain conductivity adjustment region 136a. If the length of the region where the first drain conductivity adjustment region 136a overlaps with the drain region 130c is S4, then S4 can be in the range of 0.5 to 5 μm. Specifically, if the length of the region where the first drain conductivity adjustment region 136a protrudes from the gate electrode 150 in a plan view is S4, then S4 can be in the range of 0.5 to 5 μm.

[0063] Referring to FIG. 13, according to an embodiment of the present invention, the first source conductivity adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. Specifically, the first source conductivity adjustment region 135a can be disposed at a distance from the boundary between the gate electrode 150 and the source region 130b. More specifically, the first source conductivity adjustment region 135a can be disposed within the gate electrode 150 at a distance from the boundary between the gate electrode 150 and the source region 130b. If the shortest distance between the first source conductivity adjustment region 135a and the boundary between the channel region 130a and the source region 130b is S5, S5 can be in the range of 0.5 to 1.5 μm. This is the same for the first drain conductivity adjustment region 136a. If the shortest distance between the first drain conductivity adjustment region 136a and the boundary between the channel region 130a and the drain region 130c is S6, S6 can be in the range of 0.5 to 1.5 μm.

[0064] According to an embodiment of the present invention, the channel region 130a can be partially conductive. Specifically, since the channel region 130a overlaps with the gate electrode 150, it is not a direct object of conductivity in the conductivity process. However, the boundaries between the channel region 130a and the source region 130b and between the channel region 130a and the drain region 130c can be partially conductive due to the diffusion of dopants such as metal ions, the diffusion of hydrogen, and the indirect influence of plasma during the conductivity process. As a result, the boundaries between the channel region 130a and the source region 130b and between the channel region 130a and the drain region 130c can each have a carrier concentration gradient. The carrier concentration gradient will be described in detail with reference to FIGS. 17 and 18.

[0065] Generally, when the channel region 130a of the active layer 130 has a large channel width (W), the conductivity diffusion can progress significantly at the boundary regions between the channel region 130a and the source region and the drain regions 130b and 130c. When the conductivity diffusion progresses, the threshold voltage (Vth) of the thin film transistor 100 may shift in the negative (-) direction, and the driving stability of the thin film transistor 100 may decrease.

[0066] When the channel region 130a of the active layer 130 has a small channel width (W), the conductive diffusion can be reduced at the boundary regions between the channel region 130a and the source region and the drain regions 130b, 130c. On the other hand, when the channel region 130a of the active layer 130 has a small channel width (W), the total amount of carriers passing through the channel region 130a of the thin film transistor 100 decreases, and the on-current characteristics may deteriorate. As a result, if a large amount of current flows through the thin film transistor 100 having a small channel width (W) in the channel region 130a, the thin film transistor 100 may be damaged and the driving stability may deteriorate. Therefore, it is necessary to control the conductive diffusion while the active layer 130 has a large channel width (W).

[0067] Referring to FIGS. 3, 4A, and 4B, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a according to an embodiment of the present invention are formed by patterning the first active layer 131. In the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, the first active layer 131 may not be laminated or the thickness of the first active layer 130 may become thin. As a result, the concentration of the dopant may be low or almost non-existent in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, and the diffusion of the dopant can be prevented or suppressed around the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. Therefore, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a can play the same role as when a plurality of channel regions 130a having a small channel width (W) are formed in the active layer 130, and the conductive penetration can be controlled even if the channel region 130a has a large width.

[0068] Referring to FIG. 1, when the active layer 130 includes the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, conductivity can be suppressed on the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. Therefore, among the channel regions 130a of the active layer 130, conductivity proceeds in the regions excluding the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. As a result, even when the channel region 130a of the active layer 130 has a large channel width (W), the width of the region where conductivity proceeds becomes narrow, and conductivity penetration into the channel region 130a can be prevented or controlled.

[0069] According to an embodiment of the present invention, the first drain conductivity adjustment region 136a can be disposed on a first line (LN) that is the shortest line connecting the source region 130b and the drain region 130c across the first source conductivity adjustment region 135a. Specifically, referring to FIG. 1, the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a can be disposed on the first line (LN). However, an embodiment of the present invention is not limited to this, and the first drain conductivity adjustment region 136a and the first source conductivity adjustment region 135a can also be disposed on the first line (LN) that is the shortest line connecting the source region 130b and the drain region 130c across them.

[0070] According to an embodiment of the present invention, the active layer 130 can include a first active layer 131. Specifically, the first active layer 131 can be disposed in at least a part of the channel region 130a, at least a part of the source region 130b, and at least a part of the drain region 130c. Also, the first active layer 131 may not be disposed in at least a part of the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a.

[0071] When the first active layer 131 is disposed in the first source-conductivization adjustment region 135a, the thickness of the first active layer 131 disposed in the first source-conductivization adjustment region 135a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first source-conductivization adjustment region 135a (see FIG. 4B).

[0072] Further, when the first active layer 131 is disposed in the first drain-conductivization adjustment region 136a, the thickness of the first active layer 131 disposed in the first drain-conductivization adjustment region 136a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first drain-conductivization adjustment region 136a (see FIG. 4B).

[0073] According to an embodiment of the present invention, the first source conductivity adjustment region 135a may overlap with the boundary between the channel region 130a and the source region 130b and may overlap with at least a part of the source region 130b. Specifically, the first source conductivity adjustment region 135a may protrude from the gate electrode 150 toward the source region 130b in a plan view. FIG. 1 shows a configuration in which the first source conductivity adjustment region 135a overlaps with the boundary between the channel region 130a and the source region 130b and overlaps with the source region 130b. Also, FIG. 1 shows a configuration in which the first source conductivity adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, an embodiment of the present invention is not limited to this, and the first source conductivity adjustment region 135a may overlap with the boundary between the channel region 130a and the source region 130b and may not overlap with the source region 130b. Specifically, at least a part of the ends of the first source conductivity adjustment region 135a may be disposed at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductivity adjustment region 135a may not protrude from the gate electrode 150 toward the source region 130b in a plan view (see FIG. 9). Also, the first source conductivity adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. Specifically, the first source conductivity adjustment region 135a may be disposed at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view (see FIG. 13).

[0074] Also, according to an embodiment of the present invention, the first drain conductivity adjustment region 136a may overlap with the boundary between the channel region 130a and the drain region 130c and may overlap with at least a part of the drain region 130c. Specifically, the first drain conductivity adjustment region 136a may protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 1 shows a configuration in which the first drain conductivity adjustment region 136a overlaps with the boundary between the channel region 130a and the drain region 130c and overlaps with the drain region 130c. Also, FIG. 1 shows a configuration in which the first drain conductivity adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, an embodiment of the present invention is not limited thereto, and the first drain conductivity adjustment region 136a may overlap with the boundary between the channel region 130a and the drain region 130c and may not overlap with the drain region 130c. Specifically, at least a part of the ends of the first drain conductivity adjustment region 136a may be disposed at the boundary between the gate electrode 150 and the drain region 130c in a plan view, and the first drain conductivity adjustment region 136a may not protrude from the gate electrode 150 toward the drain region 130c in a plan view (see FIG. 9). Also, the first drain conductivity adjustment region 136a may not overlap with the boundary between the channel region 130a and the drain region 130c. Specifically, the first drain conductivity adjustment region 136a may be disposed at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view (see FIG. 13).

[0075] Referring to FIG. 1 or FIG. 9, the channel region 130a may have a first diffusion region (A1) and a second diffusion region (A2). Specifically, according to an embodiment of the present invention, the first diffusion region (A1) and the second diffusion region (A2) are disposed apart from each other.

[0076] According to an embodiment of the present invention, the first diffusion region (A1) is disposed on the channel region 130a and may contact the source region 130b. The second diffusion region (A2) is disposed on the channel region 130a and may contact the drain region 130c.

[0077] More specifically, the first diffusion region (A1) and the second diffusion region (A2) do not overlap with the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a.

[0078] The first diffusion region (A1) and the second diffusion region (A2) are partially conductive regions, and the first diffusion region (A1) and the second diffusion region (A2) mean regions that are partially conductive in the channel region 130a. Specifically, since the first diffusion region (A1) and the second diffusion region (A2) overlap with the gate electrode 150, they are not direct targets for conductivity in the conductivity process. However, the first diffusion region (A1) and the second diffusion region (A2) can be partially conductive due to the diffusion of dopants, the diffusion of hydrogen, and the indirect influence of plasma during the conductivity process. Therefore, the first diffusion region (A1) and the second diffusion region (A2) each have a carrier concentration gradient. The carrier concentration gradient will be described in detail with reference to FIGS. 17 and 18.

[0079] Referring also to FIG. 1, the first diffusion region (A1) and the second diffusion region (A2) are regions where the channel region 130a is partially conductive, and the length or the conductive distance of the region where the channel region 130a is conductive is called the conductivity penetration depth (ΔL).

[0080] According to an embodiment of the present invention, when the lengths of the first diffusion region (A1) and the second diffusion region (A2) are the conductivity penetration depth (ΔL), the conductivity penetration depth (ΔL) can be in the range of 0 to 1 μm.

[0081] Specifically, in the process of selective conductivity of the active layer 130, a part of the channel region 130a is made conductive, and the conductive region cannot serve as a channel. In FIG. 1, the conductive penetration depth, which is the length of the first diffusion region (A1) and the second diffusion region (A2) in the channel region 130a, is denoted as "ΔL". Also, in the channel region 130a, the region that can effectively serve as a channel without being made conductive is called an effective channel. As the conductive penetration depth (ΔL) increases, the length of the effective channel decreases.

[0082] In order for the thin film transistor to serve as a switch, it is preferable to maintain the length of the effective channel at a predetermined value or more, and it is preferable to adjust the conductive penetration depth (ΔL) to ensure a predetermined effective channel length. Therefore, the conductive penetration depth (ΔL) is preferably in the range of 0 to 1 μm.

[0083] The gate insulating film 140 can be disposed on the active layer 130. Specifically, referring to FIG. 2A, the gate insulating film 140 is disposed between the active layer 130 and the gate electrode 150.

[0084] The gate insulating film 140 can contain at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 can have a single film structure or a multilayer film structure.

[0085] The gate electrode 150 can be disposed on the gate insulating film 140. The gate electrode 150 can contain at least one of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Although not shown in the figure, the gate electrode 150 can also have a multilayer film structure including two conductive films with different physical properties.

[0086] The gate electrode 150 serves as a hydrogen barrier film that prevents hydrogen from flowing in from above the gate electrode 150.

[0087] The thin film transistor 100 according to an embodiment of the present invention may further include an interlayer insulating film 160. The interlayer insulating film 160 is disposed on the gate electrode 150. The interlayer insulating film 160 is an insulating layer made of an insulating material. The interlayer insulating film 160 may be made of an organic material, may be made of an inorganic material, or may be made of a laminate of an organic material layer and an inorganic material layer.

[0088] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 171 and a drain electrode 172. The source electrode 171 and the drain electrode 172 may be disposed on the interlayer insulating film 160, for example, as shown in FIG. 2A.

[0089] The source electrode 171 and the drain electrode 172 may be spaced apart from each other and connected to the active layer 130. Referring to FIG. 2A, the source electrode 171 and the drain electrode 172 may be connected to the active layer 130 through contact holes, respectively. More specifically, the source electrode 171 and the drain electrode 172 may be connected to the source region 130b and the drain region 130c of the active layer 130 through contact holes, respectively.

[0090] The source electrode 171 and the drain electrode 172 may each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0091] In one embodiment of the present invention and in the figures, the source electrode 171 and the drain electrode 172 are only distinguished for convenience of explanation, and the source electrode 171 and the drain electrode 172 are not limited by the figures and the above description. The source electrode 171 and the drain electrode 172 can be interchanged with each other. The source region 130b and the drain region 130c are also only distinguished for convenience of explanation, and the source region 130b and the drain region 130c can be interchanged with each other.

[0092] FIG. 3 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention.

[0093] According to one embodiment of the present invention, the first active layer 131 may further include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to FIG. 3, the second oxide semiconductor layer 131b can be disposed on the first oxide semiconductor layer 131a.

[0094] FIG. 4A is a plan view of a thin film transistor 300 according to still another embodiment of the present invention and a cross-sectional view taken along line III-III' of the plan view, and FIG. 4B is a plan view of a thin film transistor according to still another embodiment of the present invention and a cross-sectional view taken along line III-III' of the plan view.

[0095] According to FIG. 4A, compared with FIG. 1, according to one embodiment of the present invention, the active layer 130 may further include a first active layer 131 and a second active layer 132 on the first active layer 131.

[0096] According to one embodiment of the present invention, the second active layer 132 can be formed of a semiconductor material. The second active layer 132 can include an oxide semiconductor material.

[0097] The second active layer 132 can also be made of the same oxide semiconductor material as the first active layer 131, or can be made of an oxide semiconductor material different from the first active layer 131.

[0098] According to an embodiment of the present invention, the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. Specifically, the second active layer 132 can be disposed in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. FIG. 4 shows a configuration in which the second active layer 132 is disposed in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. More specifically, at least a part of the second active layer 132 can contact the side surface of the first active layer 131 within the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a.

[0099] More specifically, FIG. 4A shows a configuration in which the first active layer 131 is not disposed in at least a part of the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, and the second active layer 132 is disposed in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. Referring to FIG. 4A, the second active layer 132 can also contact the buffer layer 120 within the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a.

[0100] On the other hand, FIG. 4B shows a configuration in which the first active layer 131 is disposed in the first source conductivity adjustment region 135a as compared with FIG. 4A. Specifically, when the first active layer 131 is disposed in the first source conductivity adjustment region 135a, the thickness of the first active layer 131 disposed in the first source conductivity adjustment region 135a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first source conductivity adjustment region 135a. Here, the second active layer 132 does not contact the buffer layer 120 within the first source conductivity adjustment region 135a.

[0101] In addition, the first active layer 131 can also be disposed in the first drain-conductivization adjustment region 136a. Specifically, when the first active layer 131 is disposed in the first drain-conductivization adjustment region 136a, the thickness of the first active layer 131 disposed in the first drain-conductivization adjustment region 136a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first drain-conductivization adjustment region 136a. Here, the second active layer 132 does not contact the buffer layer 120 within the first drain-conductivization adjustment region 136a.

[0102] According to an embodiment of the present invention, even when the active layer 130 has a multilayer structure, the first source-conductivization adjustment region 135a and the first drain-conductivization adjustment region 136a are thinner than the region of the active layer 130 excluding the first source-conductivization adjustment region 135a and the first drain-conductivization adjustment region 136a, and the depth of conductor penetration (ΔL) into the channel region 130a can be controlled.

[0103] FIG. 5 is a plan view of a thin film transistor 400 according to another embodiment of the present invention and a cross-sectional view taken along the line IV-IV' of the plan view.

[0104] According to FIG. 5, compared with FIG. 4, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to FIG. 5, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b on the first oxide semiconductor layer 131a. Specifically, the first active layer 131 is patterned to form a first source conductivization adjustment region 135a and a first drain conductivization adjustment region 136a, and the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, the second active layer 132 can be disposed in the first source conductivization adjustment region 135a and the first drain conductivization adjustment region 136a. At least a part of the second active layer 132 can be in contact with any one of the first oxide semiconductor layer 131a and the second oxide semiconductor layer 131b in the first source conductivization adjustment region 135a and the first drain conductivization adjustment region 136a.

[0105] FIG. 6 is a plan view of a thin film transistor 500 according to another embodiment of the present invention and a cross-sectional view taken along V-V' of the plan view.

[0106] According to FIG. 6, compared with FIG. 4, the second active layer 132 can include a third oxide semiconductor layer 132a and a fourth oxide semiconductor layer 132b. Referring to FIG. 6, the second active layer 132 can include a third oxide semiconductor layer 132a and a fourth oxide semiconductor layer 132b on the third oxide semiconductor layer 132a. Specifically, the first active layer 131 is patterned to form a first source conductivization adjustment region 135a and a first drain conductivization adjustment region 136a, and the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, at least a part of the second active layer 132 can be in contact with at least a part of the third oxide semiconductor layer 132a in the first source conductivization adjustment region 135a and the first drain conductivization adjustment region 136a.

[0107] FIG. 7 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present invention.

[0108] Referring to FIG. 7, according to one embodiment of the present invention, the gate insulating film 140 can be patterned in various forms that cover the upper surface of the channel region 130a of the active layer 130 and expose the upper surfaces of the source region 130b and the drain region 130b.

[0109] FIG. 7 shows a configuration in which the gate insulating film 140 covers the entire upper surface of the active layer 130. However, one embodiment of the present invention is not limited thereto, and the gate insulating film 140 can also expose the upper surfaces of the source region 130b and the drain region 130b (see FIG. 2A).

[0110] FIG. 8 is a plan view of a thin film transistor 700 according to another embodiment of the present invention.

[0111] According to FIG. 8, compared with FIG. 1, it can further include a second source conductivity adjustment region 135b and a second drain conductivity adjustment region 136b.

[0112] According to one embodiment of the present invention, the active layer 130 includes a second source conductivity adjustment region 135b and a second drain conductivity adjustment region 136b that are separated from each other, and the second source conductivity adjustment region 135b can overlap at least a part of the channel region 130a. Specifically, at least a part of the second source conductivity adjustment region 135b can overlap at least a part of the gate electrode 150.

[0113] The second drain conductivity adjustment region 136b can overlap at least a part of the channel region 130a. Specifically, at least a part of the second drain conductivity adjustment region 136b can overlap at least a part of the gate electrode 150.

[0114] As shown in FIG. 8, the first source conductor formation adjustment region 135a, the second source conductor formation adjustment region 135b, the first drain conductor formation adjustment region 136a, and the second drain conductor formation adjustment region 136b are shown in the figure as being of the same size. However, an embodiment of the present invention is not limited to this, and the first source conductor formation adjustment region 135a, the second source conductor formation adjustment region 135b, the first drain conductor formation adjustment region 136a, and the second drain conductor formation adjustment region 136b may not each be of the same size.

[0115] In FIG. 8, the first source conductor formation adjustment region 135a is shown disposed above the second source conductor formation adjustment region 135b in a plan view. However, an embodiment of the present invention is not limited to this, and the positions of the first source conductor formation adjustment region 135a and the second source conductor formation adjustment region 135b can be interchanged. This also applies similarly to the case of the first drain conductor formation adjustment region 136a and the second drain conductor formation adjustment region 136b.

[0116] The second source conductivity adjustment region 135b overlaps with the boundary between the channel region 130a and the source region 130b and can overlap with at least a part of the source region 130b. Specifically, the second source conductivity adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in a plan view. FIG. 8 shows a configuration in which the second source conductivity adjustment region 135b overlaps with the boundary between the channel region 130a and the source region 130b and overlaps with at least a part of the source region 130b. Further, FIG. 8 shows a configuration in which the second source conductivity adjustment region 135b protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, an embodiment of the present invention is not limited to this, and the second source conductivity adjustment region 135b may not overlap with the source region 130b and may not overlap with the boundary between the channel region 130a and the source region 130b. Specifically, at least a part of the ends of the second source conductivity adjustment region 135b is arranged at the boundary between the gate electrode 150 and the source region 130b in a plan view, the second source conductivity adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a plan view, and the second source conductivity adjustment region 135b can be arranged at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view.

[0117] The second drain conductivity adjustment region 136b overlaps with the boundary between the channel region 130a and the drain region 130c and can overlap with at least a part of the drain region 130c. Specifically, the second drain conductivity adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 8 shows a configuration in which the second drain conductivity adjustment region 136b overlaps with the boundary between the channel region 130a and the drain region 130c and overlaps with at least a part of the drain region 130c. Further, FIG. 8 shows a configuration in which the second drain conductivity adjustment region 136b protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, an embodiment of the present invention is not limited to this, and the second drain conductivity adjustment region 136b may not overlap with the drain region 130b and may not overlap with the boundary between the channel region 130a and the drain region 130c. Specifically, at least a part of the ends of the second drain conductivity adjustment region 136b is disposed at the boundary between the gate electrode 150 and the drain region 130c in a plan view, the second drain conductivity adjustment region 136b may not protrude from the gate electrode 150 toward the drain region 130c in a plan view, and the second drain conductivity adjustment region 136b can be disposed at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view.

[0118] Referring to FIG. 8, the first diffusion region (A1) can also be disposed between the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b. Here, the first diffusion region (A1) does not overlap with the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b.

[0119] Referring to FIG. 8, the second diffusion region (A2) can also be disposed between the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b. Here, the second diffusion region (A2) does not overlap with the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b.

[0120] According to an embodiment of the present invention, when the active layer 130 includes the second source conductivity adjustment region 135b, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b are separated from each other. When the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b are separated, the first diffusion region (A1) can be disposed between the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b.

[0121] When the active layer 130 includes the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b, the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b are separated from each other. When the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b are separated, the second diffusion region (A2) can be disposed between the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b.

[0122] According to an embodiment of the present invention, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b can be arranged at an interval of 0.5 to 20 μm.

[0123] Also, the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b can be arranged at an interval of 0.5 to 20 μm. Here, the interval between the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b and the interval between the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b may be the same or different.

[0124] When the distance between the first source metallization adjustment region 135a and the second source metallization adjustment region 135b exceeds 20 μm, the width of the region where metallization progresses in the channel region 130a becomes wider, and the metallization of the channel region 130a may become uncontrollable or impossible to prevent. As a result, the metallization penetration depth (ΔL) of the diffusion regions (A1, A2) becomes longer, and it has a relatively short effective channel length. Also, the threshold voltage (Vth) of the thin-film transistor may shift in the negative (-) direction, reducing the driving stability of the thin-film transistor. This is the same when the distance between the first drain metallization adjustment region 136a and the second drain metallization adjustment region 136b exceeds 20 μm.

[0125] When the distance between the first source metallization adjustment region 135a and the second source metallization adjustment region 135b is in the range of 0.5 to 20 μm, the width of the region where metallization progresses in the channel region 130a becomes narrower, and the metallization of the channel region 130a can be prevented or controlled. On the other hand, when the distance between the first source metallization adjustment region 135a and the second source metallization adjustment region 135b is less than 0.5 μm, the width of the region where metallization progresses is too narrow, reducing the total carrier amount passing through the channel region 130a of the thin-film transistor 100, and the on (ON) current can be suppressed. As a result, if a large current flows through the thin-film transistor 100 with a narrow width of the region where metallization progresses, the thin-film transistor 100 may be damaged and the driving stability may decrease. This is the same when the distance between the first drain metallization adjustment region 136a and the second drain metallization adjustment region 136b is less than 0.5 μm.

[0126] According to an embodiment of the present invention, the active layer 130 may further include a third source conductivity adjustment region and a third drain conductivity adjustment region. FIG. 8 shows only the first source conductivity adjustment region 135a, the second source conductivity adjustment region 135b, the first drain conductivity adjustment region 136a, and the second drain conductivity adjustment region 136b, but the implementation of the present invention is not limited thereto. Although not shown in the figure, the source home and the drain home may each have three or more.

[0127] FIG. 9 is a plan view of a thin film transistor 800 according to another embodiment of the present invention.

[0128] According to FIG. 9, compared with FIG. 8, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b may overlap with the boundary between the channel region 130a and the source region 130b and may not overlap with the source region 130b. Also, the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b may overlap with the boundary between the channel region 130a and the drain region 130c and may not overlap with the drain region 130c. Specifically, at least a part of the ends of the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b are arranged at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a plan view. The same applies to the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b.

[0129] According to an embodiment of the present invention, even when the first source metallization adjustment region 135a, the second source metallization adjustment region 135b, the first drain metallization adjustment region 136a, and the second drain metallization adjustment region 136b do not overlap with the source region 130b and the drain region 130c, respectively, the metallization diffusion into the channel region 130a can be prevented or controlled. Specifically, even when the first source metallization adjustment region 135a and the second source metallization adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in plan view, and the first drain metallization adjustment region 136a and the second drain metallization adjustment region 136b do not protrude from the gate electrode 150 toward the drain region 130c in plan view, the metallization diffusion into the channel region 130a can be prevented or controlled.

[0130] FIG. 10 is a plan view of a thin film transistor 900 according to another embodiment of the present invention.

[0131] According to FIG. 10, compared with FIG. 9, at least one of the first source metallization adjustment region 135a and the second source metallization adjustment region 135b can overlap with the source region 130b. Specifically, at least one of the first source metallization adjustment region 135a and the second source metallization adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in plan view.

[0132] FIG. 10 shows a configuration in which the first source metallization adjustment region 135a overlaps with the source region 130b and the second source metallization adjustment region 135b does not overlap with the source region 130b. Specifically, FIG. 10 shows a configuration in which the first source metallization adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in plan view and the second source metallization adjustment region 135b does not protrude toward the source region 130b. However, an embodiment of the present invention is not limited to this, and the first source metallization adjustment region 135a may not overlap with the source region 130b, and the second source metallization adjustment region 135b may also overlap with the source region 130b.

[0133] According to an embodiment of the present invention, at least one of the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b can overlap with the drain region 130c. Specifically, at least one of the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 10 shows a configuration in which the first drain conductivity adjustment region 136a overlaps with the drain region 130c and the second drain conductivity adjustment region 136b does not overlap with the drain region 130c. Specifically, FIG. 10 shows a configuration in which the first drain conductivity adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view and the second drain conductivity adjustment region 136b does not protrude toward the drain region 130c. However, an embodiment of the present invention is not limited to this, and the first drain conductivity adjustment region 136a may not overlap with the drain region 130c, and the second drain conductivity adjustment region 136b may overlap with the drain region 130c.

[0134] FIG. 11A is a plan view of a thin film transistor according to another embodiment of the present invention.

[0135] FIG. 11B is a cross-sectional view taken along line VI-VI' of FIG. 11A.

[0136] FIG. 11C is a cross-sectional view taken along line VII-VII' of FIG. 11A.

[0137] According to an embodiment of the present invention, the first source conductivity adjustment region 135a overlaps with the longitudinal edge (R) of the channel region 130a, and specifically, the first source conductivity adjustment region 135a can be arranged at the longitudinal edge (R) of the channel region 130a in a plan view. Here, the longitudinal direction of the channel region 130a is the direction connecting the source region 130b and the drain region 130c.

[0138] Referring to FIGS. 11A, 11B, and 11C, the active layer 130 of the thin film transistor 1000 according to an embodiment of the present invention includes a first active layer 131 and a second active layer 132.

[0139] Specifically, the active layer 130 includes a first source conductivity adjustment region 135a and a second source conductivity adjustment region 135b, and the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b overlap with the longitudinal edge (R) of the channel region 130a. More specifically, referring to FIG. 8, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b are shown in a configuration that does not overlap with the longitudinal edge (R) of the channel region 130a. For example, in FIG. 8, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b are arranged at a distance from the longitudinal edge (R) of the channel region 130a.

[0140] According to an embodiment of the present invention, the first drain conductivity adjustment region 136a can overlap with the longitudinal edge (R) of the channel region 130a. Specifically, the first drain conductivity adjustment region 136a can be arranged at the longitudinal edge (R) of the channel region 130a in a plan view.

[0141] Referring to FIGS. 11A, 11B, and 11C, the active layer 130 includes a first drain conductivity adjustment region 136a and a second drain conductivity adjustment region 136b, and the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b overlap with the longitudinal edge (R) of the channel region 130a. The content overlapping with the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b is omitted.

[0142] FIGS. 11B and 11C show a configuration including the first active layer 131 and the second active layer 132. However, an embodiment of the present invention is not limited thereto, and the second active layer 132 may not be included.

[0143] FIG. 12A is a cross-sectional view taken along VI-VI' of the thin film transistor according to another embodiment of FIG. 11A.

[0144] FIG. 12B is a cross-sectional view taken along VII-VII' of the thin film transistor according to another embodiment of FIG. 11A.

[0145] FIGS. 12A and 12B show a configuration that does not include the second active layer 132 as compared with FIGS. 11B and 11C.

[0146] FIG. 13 is a plan view of a thin film transistor 1100 according to still another embodiment of the present invention.

[0147] According to an embodiment of the present invention, the first source conductivity adjustment region 135a may not overlap with the boundary between the channel region 130a and the source region 130b. Also, the first drain conductivity adjustment region 136a may not overlap with the boundary between the channel region 130a and the drain region 130c. Specifically, the first source conductivity adjustment region 135a can be arranged at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first drain conductivity adjustment region 136a can be arranged at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view.

[0148] According to FIG. 13, compared with FIG. 8, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b may not overlap with the source region 130b and may not overlap with the boundary between the source region 130b and the channel region 130a.

[0149] According to an embodiment of the present invention, even when the first source metallization adjustment region 135a and the second source metallization adjustment region 135b do not overlap with the boundary between the source region 130b and the channel region 130a, the metallization diffusion into the channel region 130a can be prevented or controlled. Specifically, even when the first source metallization adjustment region 135a and the second source metallization adjustment region 135b are arranged at a distance from the boundary between the gate electrode 150 and the source region 130b in a plan view, the metallization diffusion into the channel region 130a can be prevented or controlled. Also in the case of the first drain metallization adjustment region 136a and the second drain metallization adjustment region 136b, even when they do not overlap with the boundary between the drain region 130c and the channel region 130a, the metallization diffusion into the channel region 130a can be prevented or controlled. Specifically, even when the first drain metallization adjustment region 136a and the second drain metallization adjustment region 136b are arranged at a distance from the boundary between the gate electrode 150 and the drain region 130c in a plan view, the metallization diffusion into the channel region 130a can be prevented or controlled.

[0150] FIG. 14 is a plan view of a thin film transistor 1200 according to another embodiment of the present invention.

[0151] FIG. 14 shows a configuration in which, as compared with FIG. 13, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b overlap with the boundary between the source region 130b and the channel region 130a and do not overlap with the source region 130b. Specifically, in FIG. 14, at least a part of the ends of the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b is disposed at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in a plan view. On the other hand, an embodiment of the present invention is not limited to this, and only the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b may overlap with the boundary between the drain region 130c and the channel region 130a and may not overlap with the drain region 130c. Also in this case, the conductivity diffusion into the channel region 130a can be controlled or prevented.

[0152] FIG. 15 is a plan view of a thin film transistor 1300 according to another embodiment of the present invention.

[0153] FIG. 15 shows a configuration in which, as compared with FIG. 13, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b overlap with the source region 130b. Specifically, in FIG. 15, the first source conductivity adjustment region 135a and the second source conductivity adjustment region 135b protrude from the gate electrode 150 toward the source region 130b in a plan view. On the other hand, an embodiment of the present invention is not limited to this, and only the first drain conductivity adjustment region 136a and the second drain conductivity adjustment region 136b may overlap with the drain region 130c. In any case, the conductivity diffusion into the channel region 130a can be controlled or prevented.

[0154] FIG. 16A is a graph showing the measurement of the threshold voltage (Vth) of thin film transistors according to an example and a comparative example.

[0155] FIG. 16B is a plan view of the thin film transistor according to the comparative example of FIG. 16A.

[0156] Referring to FIG. 16A, the a graph is the measurement result of the threshold voltage (Vth) of the thin film transistor according to the example, and the b graph is the measurement result of the threshold voltage (Vth) of the thin film transistor according to the comparative example.

[0157] In the graph of FIG. 16A, the horizontal axis represents the gate voltage (V G ), and the vertical axis represents the logarithmic (log) value of the drain-source current (I DS ).

[0158] The thin film transistor according to one example includes a first source conductivity adjustment region 135a and a first drain conductivity adjustment region 136a. On the other hand, the thin film transistor according to the comparative example does not include the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a (see FIG. 16B). The thin film transistor according to the example may further include a second source conductivity adjustment region 135b and a second drain conductivity adjustment region 136b.

[0159] In the case of the example including the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, the conductivity penetration can be prevented or controlled at the boundary between the channel region 130a and the source region 130b and at the boundary between the channel region 130a and the drain region 130c. As a result, even when the channel region 130a of the active layer 130 has a large channel width (W), the channel width (W) of the region where the conductivity progresses becomes narrow, and the conductivity to the channel region 130a can be suppressed or controlled.

[0160] Therefore, when the conversion into a conductor in the channel region 130a is suppressed or controlled, the length of the conversion penetration depth (ΔL) becomes shorter, and it has a relatively large effective channel length. Also, when the conversion into a conductor in the channel region 130a is suppressed or controlled, it is possible to control the threshold voltage (threshold voltage: Vth) of the thin film transistor from moving in the negative (-) direction, thereby improving the driving stability of the thin film transistor.

[0161] Referring to FIG. 16B, in the case of a comparative example that does not include the first source conversion adjustment region 135a and the first drain conversion adjustment region 136a, the progress of conversion can occur at the boundary between the channel region 130a and the source region 130b and at the boundary between the channel region 130a and the drain region 130c.

[0162] Therefore, when the conversion into a conductor in the channel region 130a progresses, the length of the conversion penetration depth (ΔL) becomes longer, and it has a relatively short effective channel length. Also, when the conversion into a conductor in the channel region 130a progresses, the threshold voltage (threshold voltage: Vth) of the thin film transistor moves in the negative (-) direction, and the driving stability of the thin film transistor may decrease.

[0163] Comparing the thin film transistor according to an embodiment of the present invention having the active layer 130 including the first source conversion adjustment region 135a and the first drain conversion adjustment region 136a with the thin film transistor according to a comparative example of the present invention having the active layer 130 not including the first source conversion adjustment region 135a and the first drain conversion adjustment region 136a, it can be confirmed that the threshold voltage (threshold voltage: Vth) of the thin film transistor according to the comparative example of the present invention has moved in the negative (-) direction when the same on (ON) current is applied.

[0164] FIG. 17 is a graph of the carrier concentration for each region of the active layer 130. Specifically, FIG. 17 is a graph of the carrier concentration by VII-VII' of the active layer 130. Here, the active layer 130 can be made of an oxide semiconductor material.

[0165] The horizontal axis of the graph in FIG. 17 represents the source region 130b, the channel region 130a, and the drain region 130c in order. The first source conductivity adjustment region 135a overlaps with the source region 130b and the channel region 130a, and the first drain conductivity adjustment region 136a overlaps with the channel region 130a and the drain region 130c. The horizontal axis of FIG. 17 can correspond to the distance measured from the left end of the active layer 130 shown in FIG. 17.

[0166] The vertical axis of the graph in FIG. 17 indicates the carrier concentration (a.u.).

[0167] Referring to FIG. 17, the first active layer 131 may not be laminated on the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, or the thickness of the first active layer 130 may be thin. As a result, the concentration of dopants in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a may be low or almost non-existent. Therefore, the carrier concentration in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a may be non-existent or very low. On the other hand, the thickness of the first active layer 131 disposed in the channel region 130a excluding the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a is thicker than the thickness of the first active layer 131 disposed in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a, and the carrier concentration in the channel region 130a excluding the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a is greater than the carrier concentration in the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a. The source region 130b and the drain region 130c are regions formed by conductivity and have a high carrier concentration.

[0168] FIG. 18 is a graph of the carrier concentration for each region of the active layer 130. Specifically, FIG. 18 is a graph of the carrier concentration by IX-IX' of the active layer 130. Here, the active layer 130 can be made of an oxide semiconductor material.

[0169] The vertical axis of the graph in FIG. 18 is the same as the vertical axis in FIG. 17 and is omitted.

[0170] The horizontal axis of the graph in FIG. 18 represents the source region 130b, the channel region 130a, and the drain region 130c in order. The channel region 130a includes a first diffusion region (A1) and a second diffusion region (A2). The horizontal axis of FIG. 18 can correspond to the distance measured from the left end of the active layer 130 shown in FIG. 18.

[0171] Referring to FIG. 18, the channel region 130a excluding the first source conductivity adjustment region 135a and the first drain conductivity adjustment region 136a has a high carrier concentration. The source region 130b and the drain region 130c are regions formed by conductivity and have a high carrier concentration. Also, a carrier concentration gradient is formed in the first diffusion region (A1) and the second diffusion region (A2).

[0172] According to an embodiment of the present invention, the first diffusion region (A1) has a carrier concentration gradient that decreases along the direction away from the source region 130b. Specifically, referring to the graph in FIG. 18, the carrier concentration is the highest in the source region 130b. The carrier concentration gradually decreases in the first diffusion region (A1) as it moves away from the source region 130b, and the carrier concentration is the lowest in the region of the channel region 130a that is not the first diffusion region (A1) or the second diffusion region (A2).

[0173] According to an embodiment of the present invention, the second diffusion region (A2) has a carrier concentration gradient that decreases along the direction away from the drain region 130c. Specifically, referring to the graph in FIG. 18, the carrier concentration is the highest in the drain region 130c. The carrier concentration gradually decreases in the second diffusion region (A2) as it moves away from the drain region 130c, and the carrier concentration is the lowest in the region of the channel region 130a that is not the first diffusion region (A1) or the second diffusion region (A2).

[0174] FIG. 19 is a schematic diagram of a display device 1500 according to another embodiment of the present invention.

[0175] As shown in FIG. 19, a display device 1500 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a control unit 340.

[0176] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged in the intersection regions of the gate lines (GL) and the data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), the data lines (DL), and the pixels (P) can be arranged on a base substrate 110.

[0177] The control unit 340 controls the gate driver 320 and the data driver 330.

[0178] The control unit 340 outputs a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330 by using signals supplied from an external system (not shown). Further, after sampling the input video data input from the external system, the control unit 340 re-arranges it and supplies the re-arranged digital video data (RGB) to the data driver 330.

[0179] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), a gate clock (GCLK), and the like. Also, the gate control signal (GCS) can include a control signal for controlling a shift register.

[0180] The data control signal (DCS) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like.

[0181] The data driver 330 supplies data voltages to the data lines (DL) of the display panel 310. Specifically, the data driver 330 converts the input video data (RGB) from the control unit 340 into analog data voltages and supplies the data voltages to the data lines (DL).

[0182] According to an embodiment of the present invention, the gate driver 320 can be implemented on the display panel 310. In this way, the structure in which the gate driver 320 is directly implemented on the display panel 310 is called a gate in panel (GIP) structure. Specifically, in the gate in panel (GIP) structure, the gate driver 320 can be arranged on the base substrate 110.

[0183] The display device 1500 according to an embodiment of the present invention can include the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 described above. According to an embodiment of the present invention, the gate driver 320 can include the above-described thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0184] The gate driver 320 can include a shift register 350.

[0185] The shift register 350 sequentially supplies gate pulses to the gate lines (GL) during one frame using a start signal and a gate clock transmitted from the control unit 340. Here, one frame refers to the period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on the switching element (thin film transistor) arranged in the pixel (P).

[0186] Further, during the remaining period in one frame when the gate pulse is not supplied, the shift register 350 supplies a gate-off signal that can turn off the switching element to the gate line (GL). Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal (SS or Scan).

[0187] The shift register 350 can include the above-described thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0188] FIG. 20 is a schematic diagram of the shift register 350.

[0189] Referring to FIG. 20, the shift register 350 can include g stages 351 (ST1 to STg).

[0190] The shift register 350 transmits one scan signal (SS) to a pixel (P) connected to one gate line (GL) via one gate line (GL). Each of the stages 351 can be connected to one gate line (GL). When g gate lines (GL) are formed on the display panel 110, the shift register 350 can include g stages 351 (ST1 to STg) and can generate g scan signals (SS1 to SSg).

[0191] Generally, each stage 351 outputs a gate pulse (GP) once in one frame, and the gate pulse (GP) is sequentially output at each stage 351.

[0192] FIG. 21 is a circuit diagram of any one pixel (P) in FIG. 19.

[0193] The circuit diagram in FIG. 21 is an equivalent circuit diagram for the pixel (P) of the display device 1500 including an organic light emitting diode (OLED) as the display element 710.

[0194] Referring to FIG. 21, the pixel (P) includes a display element 710 and a pixel driving circuit (PDC) that drives the display element 710. Specifically, the display device 1500 according to an embodiment of the present invention can include a pixel driving circuit (PDC) on the base substrate 110.

[0195] The pixel driving circuit (PDC) in FIG. 21 includes a first thin film transistor (TR1) which is a switching transistor and a second thin film transistor (TR2) which is a driving transistor. The display device 1500 according to another embodiment of the present invention can include at least one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0196] The first thin film transistor (TR1) is connected to the gate line (GL) and the data line (DL), and is turned on or off by a scan signal (SS) supplied through the gate line (GL).

[0197] The data line (DL) provides a data voltage (Vdata) to the pixel driving circuit (PDC), and the first thin film transistor (TR1) controls the application of the data voltage (Vdata).

[0198] The driving power line (PL) provides a driving voltage (Vdd) to the display element 710, and the first thin film transistor (TR1) controls the driving voltage (Vdd). The driving voltage (Vdd) is a pixel driving voltage for driving the organic light emitting diode (OLED) which is the display element 710.

[0199] When the first thin film transistor (TR1) is turned on by a scan signal (SS) applied from the gate driver 320 via the gate line (GL), the data voltage (Vdata) supplied via the data line (DL) is supplied to the gate electrode of the second thin film transistor (TR2) connected to the display element 710. The data voltage (Vdata) is charged in a storage capacitor (Cst) formed between the gate electrode and the source electrode of the second thin film transistor (TR2).

[0200] The amount of current supplied to the organic light emitting diode (OLED) which is the display element 710 through the second thin film transistor (TR2) is controlled by the data voltage (Vdata), whereby the gradation of light output from the display element 710 can be controlled.

[0201] FIG. 22 is a circuit diagram of any one pixel (P) of the display device 1600 according to another embodiment of the present invention.

[0202] FIG. 22 is an equivalent circuit diagram for the pixel (P) of the organic light emitting display device.

[0203] The pixel (P) of the display device 1600 shown in FIG. 22 includes an organic light emitting diode (OLED) which is the display element 710, and a pixel driving circuit (PDC) for driving the display element 710. The display element 710 is connected to the pixel driving circuit (PDC).

[0204] Signal lines (DL, GL, PL, RL, SCL) for supplying signals to the pixel driving circuit (PDC) are arranged in the pixel (P).

[0205] A data voltage (Vdata) is supplied to the data line (DL), a scan signal (SS) is supplied to the gate line (GL), a driving voltage (Vdd) for driving the pixel is supplied to the driving power line (PL), a reference voltage (Vref) is supplied to the reference line (RL), and a sensing control signal (SCS) is supplied to the sensing control line (SCL).

[0206] The pixel driving circuit (PDC) includes, for example, a first thin film transistor (TR1) (switching transistor) connected to a gate line (GL) and a data line (DL), a second thin film transistor (TR2) (driving transistor) that controls the magnitude of the current output to the display element 710 by a data voltage (Vdata) transmitted through the first thin film transistor (TR1), and a third thin film transistor (TR3) (sensing transistor) for sensing the characteristics of the second thin film transistor (TR2).

[0207] The first thin film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL), and transmits the data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin film transistor (TR2).

[0208] The third thin film transistor (TR3) is connected to a first node (n1) between the second thin film transistor (TR2) and the display element 710 and a reference line (RL), is turned on or off by a sensing control signal (SCS), and senses the characteristics of the second thin film transistor (TR2) which is a driving transistor during a sensing period.

[0209] A second node (n2) connected to the gate electrode of the second thin film transistor (TR2) can be connected to the first thin film transistor (TR1). A storage capacitor (Cst) is formed between the second node (n2) and the first node (n1).

[0210] When the first thin film transistor (TR1) is turned on, the data voltage (Vdata) supplied through the data line (DL) is supplied to the gate electrode of the second thin film transistor (TR2). The data voltage (Vdata) is charged in a storage capacitor (Cst) formed between the gate electrode and the source electrode of the second thin film transistor (TR2).

[0211] When the second thin film transistor (TR2) is turned on, a driving voltage (Vdd) that drives the pixel supplies a current to the display element 710 through the second thin film transistor (TR2), and light is output from the display element 710.

[0212] The display device 1600 according to still another embodiment of the present invention can include at least one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0213] FIG. 23 is a circuit diagram of any one pixel (P) of the display device 1700 according to still another embodiment of the present invention.

[0214] The pixel (P) of the display device 1700 shown in FIG. 23 includes an organic light emitting diode (OLED) which is the display element 710, and a pixel driving circuit (PDC) that drives the display element 710. The display element 710 is connected to the pixel driving circuit (PDC).

[0215] The pixel driving circuit (PDC) includes thin film transistors (TR1, TR2, TR3, TR4).

[0216] Signal lines (DL, EL, GL, PL, SCL, RL) for supplying a driving signal to the pixel driving circuit (PDC) are arranged in the pixel (P).

[0217] The pixel (P) in FIG. 23 further includes an emission control line (EL) as compared with the pixel (P) in FIG. 22. An emission control signal (EM) is supplied to the emission control line (EL). Also, the pixel driving circuit (PDC) in FIG. 23 further includes a fourth thin film transistor (TR4) which is an emission control transistor for controlling the emission timing of the second thin film transistor (TR2) as compared with the pixel driving circuit (PDC) in FIG. 22.

[0218] The first thin film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL), and transmits a data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin film transistor (TR2).

[0219] A storage capacitor (Cst) is located between the gate electrode of the second thin film transistor (TR2) and the display element 710.

[0220] The third thin film transistor (TR3) is connected to the reference line (RL), is turned on or off by a sensing control signal (SCS), and senses the characteristics of the second thin film transistor (TR2) which is the driving transistor during the sensing period.

[0221] The fourth thin film transistor (TR4) transmits a driving voltage (Vdd) to the second thin film transistor (TR2) or cuts off the driving voltage (Vdd) by an emission control signal (EM). When the fourth thin film transistor (TR4) is turned on, current is supplied to the second thin film transistor (TR2), and light is output from the display element 710.

[0222] A pixel driving circuit (PDC) according to another embodiment of the present invention can be formed in various structures other than the structure described above. The pixel driving circuit (PDC) can also include, for example, five or more thin film transistors.

[0223] The present invention described above is not limited by the above-described embodiments and the accompanying drawings, and it will be apparent to those having ordinary knowledge in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within the scope not departing from the technical matters of the present invention. Therefore, the scope of the present invention is indicated by the claims described below, and all changes or modified forms derived from the meaning, scope, and equivalent concepts of the claims must be construed as being included in the scope of the present invention.

Explanation of Reference Numerals

[0224] 110: Base substrate 120: Buffer layer 130: Active layer 130a: Channel region 130b: Source region 130c: Drain region 131: First active layer 132: Second active layer 131a: First oxide semiconductor layer 131b: Second oxide semiconductor layer 132a: Third oxide semiconductor layer 132b: Fourth oxide semiconductor layer 135a: First source conductivity adjustment region 135b: Second source conductivity adjustment region 136a: First drain conductivity adjustment region 136b: Second drain conductivity adjustment region 140: Gate insulating film 150: Gate electrode 160: Interlayer insulating film 171: Source electrode 172: Drain electrode

Claims

1. The active layer, a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; The active layer is a channel region overlapping the gate electrode in a plan view; a source region that does not overlap the gate electrode in a plan view and is connected to one side of the channel region; a drain region that does not overlap the gate electrode in a plan view and is connected to the other side of the channel region, the source region and the drain region are spaced apart from each other with the channel region therebetween; the active layer includes a first source conductive adjustment region and a first drain conductive adjustment region spaced apart from each other; At least a portion of the first source conductor adjustment region overlaps with at least a portion of the gate electrode; At least a portion of the first drain conductor adjustment region overlaps with at least a portion of the gate electrode, the channel region includes an area extending from the first source conductor adjustment region to the first drain conductor adjustment region based on a longitudinal direction of the channel region; A thin film transistor, wherein the thickness of the region is the same as the thickness of the source region and the drain region.

2. 2. The thin film transistor according to claim 1, wherein the first drain conductor adjustment region is disposed on a first line that is the shortest line that crosses the first source conductor adjustment region and connects the source region and the drain region.

3. The thin film transistor of claim 1 , wherein the active layer is absent from at least a portion of the first source conductive adjustment region and the first drain conductive adjustment region.

4. the active layer includes a first active layer and a second active layer on the first active layer; The thin film transistor of claim 1 , wherein the first active layer is disposed over at least a portion of the channel region, at least a portion of the source region, and at least a portion of the drain region.

5. a thickness of the first active layer disposed in the first source conductor adjustment region is smaller than a thickness of the first active layer disposed in the channel region excluding the first source conductor adjustment region; The thin film transistor according to claim 4 , wherein the thickness of the first active layer disposed in the first drain conductor adjustment region is thinner than the thickness of the first active layer disposed in the channel region excluding the first drain conductor adjustment region.

6. the first active layer is not disposed in at least a part of the first source conductive adjustment region and the first drain conductive adjustment region; The thin film transistor of claim 4 , wherein the second active layer is disposed over the channel region, the source region, and the drain region.

7. the second active layer is disposed in the first source conductive adjustment region and the first drain conductive adjustment region; 5. The thin film transistor of claim 4, wherein at least a portion of the second active layer contacts sides of the first active layer in the first source conductive adjustment region and the first drain conductive adjustment region.

8. The thin film transistor of claim 4 , wherein the first active layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

9. The thin film transistor of claim 4 , wherein the second active layer comprises a third oxide semiconductor layer and a fourth oxide semiconductor layer on the third oxide semiconductor layer.

10. the active layer further comprising a second active layer on the first active layer; 9. The thin film transistor of claim 8, wherein at least a portion of the second active layer contacts one of the first oxide semiconductor layer and the second oxide semiconductor layer in the first source conductor adjustment region and the first drain conductor adjustment region.

11. 10. The thin film transistor of claim 9, wherein at least a portion of the first active layer contacts at least a portion of the third oxide semiconductor layer in the first source conductive adjustment region and the first drain conductive adjustment region.

12. at least a part of an end of the first source conductor adjustment region is disposed at a boundary between the gate electrode and the source region in a plan view; The thin film transistor according to claim 1 , wherein the first source conductor adjustment region does not protrude from the gate electrode toward the source region in a plan view.

13. At least a part of an end of the first drain conductor adjustment region is disposed at a boundary between the gate electrode and the drain region in a plan view, The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region does not protrude from the gate electrode toward the drain region in a plan view.

14. The thin film transistor according to claim 1 , wherein the first source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

15. The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

16. The thin film transistor according to claim 1 , wherein the first source conductor adjustment region is disposed apart from a boundary between the gate electrode and the source region in a plan view.

17. The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region is disposed apart from a boundary between the gate electrode and the drain region in a plan view.

18. the active layer includes a second source conductive adjustment region and a second drain conductive adjustment region spaced apart from each other; At least a portion of the second source conductor adjustment region overlaps with at least a portion of the gate electrode; At least a portion of the second drain conductor adjustment region overlaps with at least a portion of the gate electrode, the first source conductor adjustment region and the second source conductor adjustment region are spaced apart from each other; The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region and the second drain conductor adjustment region are spaced apart from each other.

19. the first source conductor adjustment region and the second source conductor adjustment region are arranged at intervals of 0.5 to 20 μm; 20. The thin film transistor according to claim 18, wherein the first drain conductor adjustment region and the second drain conductor adjustment region are arranged at an interval in the range of 0.5 to 20 μm.

20. 20. The thin film transistor according to claim 18, wherein at least one of the first source conductor adjustment region and the second source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

21. The thin film transistor according to claim 18 , wherein at least one of the first drain conductor adjustment region and the second drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

22. The first source conductor adjustment region is disposed on an edge (R) of the channel region in a longitudinal direction in a plan view, The thin film transistor according to claim 1 , wherein the longitudinal direction of the channel region is a direction connecting the source region and the drain region.

23. The first drain conductor adjustment region is disposed at an edge (R) in a longitudinal direction of the channel region in a plan view, The thin film transistor according to claim 1 , wherein the longitudinal direction of the channel region is a direction connecting the source region and the drain region.

24. the channel region having a first diffusion region and a second diffusion region spaced apart from each other; the first diffusion region is disposed on the channel region and in contact with the source region; the second diffusion region is disposed on the channel region and in contact with the drain region; the first diffusion region and the second diffusion region do not overlap the first source conductor adjustment region and the first drain conductor adjustment region; the first diffusion region has a carrier concentration gradient that decreases along a direction away from the source region; The thin film transistor of claim 1 , wherein the second diffusion region has a decreasing carrier concentration gradient along a direction away from the drain region.

Images