Electro-optic device and electronic apparatus

Abstract

To provide an electro-optic device including a capacitive element capable of coping with a narrower pixel pitch, and an electronic apparatus.SOLUTION: An electro-optic device comprises: an opening area on which a pixel electrode is provided; and a light-blocking area on which a transistor including a semiconductor layer electrically connected to the pixel electrode and extending in a first direction is provided. The electro-optic device further comprises: a first insulation layer with an insulation property provided on the opening area and the light-blocking area; an insulative projection provided on the light-blocking area and projecting toward a layer provided with the pixel electrode from the first insulation layer; and a capacitive element provided on the light-blocking area. The capacitive element includes: a first capacitance electrode covering the projection and functioning as wiring; a second capacitance electrode separated from the first capacitance electrode; and a dielectric film provided between the first capacitance electrode and the second capacitance electrode.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In electronic devices such as projectors, electro-optical devices such as liquid crystal display devices whose optical characteristics can be changed for each pixel are used. As an example of the electro-optical device, a liquid crystal device described in Patent Document 1 is known.

[0003] The liquid crystal device described in Patent Document 1 includes a pixel electrode provided on a substrate, a first insulating film and a second insulating film provided between the substrate and the pixel electrode, and a storage capacitor having a groove portion provided in a groove penetrating the first insulating film and the second insulating film. In the liquid crystal device described in the document, a storage capacitor having the above-described groove portion is provided so as to improve the capacitance value of the storage capacitor within a limited area on the substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, with the reduction of the pixel pitch due to high resolution, the area where the storage capacitor is provided has a tendency to shrink. When the area constituting the storage capacitor shrinks, the planar area of the grooves provided in the first insulating film and the second insulating film described above shrinks. As a result, it becomes difficult to provide a storage capacitor having a groove portion.

Means for Solving the Problems

[0006] One aspect of the electro-optical device of the present invention is an electro-optical device including an opening region where a pixel electrode is provided, and a light-shielding region where a transistor having a semiconductor layer electrically connected to the pixel electrode and extending in a first direction is provided, the electro-optical device including a first insulating layer having insulating properties provided in the opening region and the light-shielding region, an insulating protrusion provided in the light-shielding region and protruding from the first insulating layer toward the layer where the pixel electrode is provided, and a capacitor element provided in the light-shielding region, the capacitor element including a first capacitor electrode that covers the protrusion and functions as a wiring, a second capacitor electrode spaced apart from the first capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the dimensions or scales of each part in the drawings are appropriately different from the actual ones, and there are also parts schematically shown for easy understanding. Further, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description.

[0009] 1. Electro-optical device 1A. Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A of the electro-optical device 100 shown in FIG. 1. In FIG. 1, the illustration of the counter substrate 3 is omitted. Further, hereinafter, for convenience of explanation, the X-axis, Y-axis, and Z-axis orthogonal to each other will be appropriately used for explanation. Also, one direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction.

[0010] Also, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α but also the case where element α and element β are separated. Further, the "electrical connection" between element α and element β includes not only a configuration in which element α and element β are directly joined to conduct electricity but also a configuration in which element α and element β are indirectly conducted through another conductor.

[0011] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device of the active matrix driving type. The electro-optical device 100 includes a device substrate 2, a counter substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in FIG. 2, the device substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in the Z1 direction in this order. Note that viewing from the Z1 direction or the Z2 direction, which is the direction in which these overlap, is referred to as "plan view". Also, although the shape of the electro-optical device 100 in plan view shown in FIG. 1 is a quadrangle, it may be a polygon other than a quadrangle or a circle.

[0012] The device substrate 2 shown in FIG. 2 includes a first substrate 21, a laminate 20, a plurality of pixel electrodes 25, and a first alignment film 29 having translucency. The first substrate 21, the laminate 20, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in the Z1 direction in this order. Each of the first substrate 21, the laminate 20, the plurality of pixel electrodes 25, and the first alignment film 29 has translucency. Note that "translucency" means permeability to visible light, and preferably means that the transmittance of visible light is 50% or more.

[0013] The first substrate 21 corresponds to the "substrate". The first substrate 21 is a flat plate having translucency and insulating properties, and is formed of, for example, a glass substrate or a quartz substrate. The laminate 20 includes a plurality of insulating films having translucency. In addition, various wirings and the like are provided in the laminate 20. The pixel electrode 25 is used to apply an electric field to the liquid crystal layer 5. The pixel electrode 25 includes, for example, a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown, the device substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in plan view. Also, the first alignment film 29 has translucency and insulating properties. The first alignment film 29 aligns the liquid crystal molecules included in the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0014] The counter substrate 3 is disposed opposite to the element substrate 2. The counter substrate 3 includes a second substrate 31, an inorganic insulating layer 32, a common electrode 33, and a second alignment film 34. The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are laminated in this order in the Z2 direction.

[0015] The second substrate 31 is a flat plate having translucency and insulating properties, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 has translucency and insulating properties, and is formed of an inorganic material containing silicon such as silicon oxide. The common electrode 33 is a counter electrode disposed with respect to the plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 has translucency and conductivity. The common electrode 33 contains a transparent conductive material such as ITO, IZO, and FTO, for example. The second alignment film 34 has translucency and insulating properties. The second alignment film 34 aligns the liquid crystal molecules included in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide. Although not shown, the counter substrate 3 has a light-shielding cut-off that surrounds the plurality of pixel electrodes 25 in plan view.

[0016] The seal member 4 is disposed between the element substrate 2 and the counter substrate 3. The seal member 4 is formed using an adhesive or the like containing various curable resins such as epoxy resin. The seal member 4 may include a gap material composed of an inorganic material such as glass.

[0017] The liquid crystal layer 5 is disposed in a region surrounded by the element substrate 2, the counter substrate 3, and the seal member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The alignment of the liquid crystal molecules changes according to the voltage applied to the liquid crystal layer 5.

[0018] As shown in FIG. 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. A part of the plurality of external terminals 13 is connected to a wiring (not shown) routed from the scanning line driving circuit 11 or the signal line driving circuit 12. Further, the plurality of external terminals 13 include a terminal to which a fixed potential is applied. The terminal is electrically connected to the common electrode 33 of the counter substrate 3 via a wiring and a conductive material (not shown). Therefore, a fixed potential is supplied to the common electrode 33.

[0019] Such an electro-optical device 100 has a display area A10 and a peripheral area A20. The display area A10 is an area for displaying an image. The peripheral area A20 is an area located outside the display area A10 in a plan view and surrounds the display area A10 in a plan view. Further, a plurality of pixels P arranged in a matrix are provided in the display area A10. A plurality of pixel electrodes 25 are arranged one-to-one for the plurality of pixels P. On the other hand, the aforementioned common electrode 33 is provided in common for the plurality of pixels P. Further, the scanning line driving circuit 11 and the signal line driving circuit 12 are arranged in the peripheral area A20.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in FIG. 2, after the light LL is incident on the counter substrate 3 and modulated while exiting from the element substrate 2, an image is displayed. Note that an image may be displayed by modulating the light incident on the element substrate 2 while exiting from the counter substrate 3.

[0021] Further, the electro-optical device 100 is applied to a display device that performs color display, such as a personal computer and a smartphone, which will be described later. When applied to the display device, a color filter is appropriately used for the electro-optical device 100. Further, the electro-optical device 100 is applied to a projection type projector, which will be described later, for example. In this case, the electro-optical device 100 functions as a light valve. Note that in this case, the color filter is omitted for the electro-optical device 100.

[0022] 1B. Electrical Configuration of Element Substrate 2 FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n constant potential lines 243. n and m are each integers of 2 or more. Transistors 23 are arranged corresponding to each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0023] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2,..., and Gn are sequentially supplied to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.

[0024] Each of the m signal lines 242 shown in FIG. 3 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding plurality of transistors 23. The m signal lines 242 are electrically connected to the signal line driving circuit 12 shown in FIG. 1. Image signals S1, S2,..., and Sm are supplied in parallel to the 1st to mth signal lines 242 from the signal line driving circuit 12.

[0025] The n scanning lines 241 and the m signal lines 242 shown in FIG. 3 are electrically insulated from each other and are arranged in a grid pattern in plan view. The region surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to the pixel P. A transistor 23, a pixel electrode 25, and a capacitor element 22 are provided for each pixel P. The pixel electrodes 25 are provided one-to-one with respect to the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0026] Each of the n constant potential lines 243 extends in the X1 direction, and the n constant potential lines 243 are arranged at equal intervals in the Y2 direction. Also, the n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m signal lines 242 and are arranged at intervals with respect to these. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitance element 22. Each capacitance element 22 is a capacitance element for holding the potential of the pixel electrode 25. The capacitance elements 22 are provided one-to-one with respect to the transistors 23. Also, the other of the two electrodes of each capacitance element 22 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 22, and the other electrode is electrically connected to the drain of the transistor 23.

[0027] When the scanning signals G1, G2, …, and Gn are sequentially activated and the n scanning lines 241 are sequentially selected, the transistors 23 connected to the selected scanning lines 241 are turned on. Then, image signals S1, S2, …, and Sm having magnitudes corresponding to the gradations to be displayed are taken into the pixel P corresponding to the selected scanning line 241 via the m signal lines 242 and are applied to the pixel electrode 25. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the alignment of the liquid crystal molecules changes according to the applied voltage. Also, the applied voltage is held by the capacitance element 22. Such a change in the alignment of the liquid crystal molecules modulates light and enables gradation display.

[0028] 1C. Opening Region and Light-Shielding Region FIG. 4 is a diagram for explaining the opening region A11 and the light-shielding region A12 in the display region A10 of FIG. 2. As shown in FIG. 4, the display region A10 has a plurality of opening regions A11 and a light-shielding region A12. The plurality of opening regions A11 are spaced apart from each other and are arranged in a matrix in plan view. The shape of the light-shielding region A12 in plan view is a frame shape located between the plurality of opening regions A11.

[0029] Each opening region A11 is an area where the pixel electrode 25 is disposed and is an area where light is transmitted. On the other hand, the light-shielding region A12 is an area where the transistor 23 is disposed and is an area having light-shielding properties. Note that the "light-shielding property" means light-shielding property against visible light, preferably the transmittance of visible light is less than 50%, and more preferably 10% or less. Although not shown in FIG. 4, various wirings such as the scanning line 241, the signal line 242, and the constant potential line 243 shown in FIG. 3 and the capacitive element 22 are disposed in the light-shielding region A12.

[0030] Further, the light-shielding region A12 includes a plurality of first extending portions A121, a plurality of wide portions A122, and a plurality of second extending portions A123. Each first extending portion A121 corresponds to an "extending portion" and is a portion extending in the direction along the Y-axis. Each second extending portion A123 is a portion extending in the direction along the X-axis. Each wide portion A122 is a portion wider in plan view than the width of the first extending portion A121 and the width of the second extending portion A123. Each wide portion A122 is located between two first extending portions A121 and between two second extending portions A123 in plan view. Each wide portion A122 is connected to each of the two first extending portions A121 and the two second extending portions A123.

[0031] 1D. Element Substrate FIG. 5 is a cross-sectional view taken along line A1-A1 in FIG. 4. FIG. 6 is a cross-sectional view taken along line A2-A2 in FIG. 4. The Y1 direction or the Y2 direction, which is the direction along the Y-axis, corresponds to the "first direction". Also, viewing from the Z1 direction or the Z2 direction is defined as a plan view.

[0032] As shown in FIGS. 5 and 6, the element substrate 2 includes a first substrate 21 which is a "substrate" and a laminate 20. The laminate 20 includes a plurality of insulating layers 201, 202, 203, 204, 205, 206, a first insulating layer 207, and a second insulating layer 208. The insulating layers 201, 202, 203, 204, 205, 206, the first insulating layer 207, and the second insulating layer 208 are laminated in this order from the first substrate 21. The insulating layers 201 to 206, the first insulating layer 207, and the second insulating layer 208 have translucency and insulation properties. Each material of the insulating layers 201 to 206, the first insulating layer 207, and the second insulating layer 208 is, for example, an inorganic material containing silicon such as silicon oxide and silicon oxynitride. Each of the insulating layers 201 to 206, the first insulating layer 207, and the second insulating layer 208 may be formed of one layer or may be formed of a plurality of layers. Further, each of the insulating layers 201 to 206, the first insulating layer 207, and the second insulating layer 208 is provided across the aforementioned plurality of opening regions A11 and light-shielding regions A12.

[0033] A transistor 23, a scanning line 241, a signal line 242, and a capacitive element 22 are arranged in the laminate 20. Further, relay electrodes 244, 245, 246, 247, 248, and 249 are arranged in the laminate 20. Also, a light-shielding portion 210 is arranged on the first substrate 21.

[0034] As described above, the first substrate 21 is composed of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess H1. The recess H1 is a depression formed in the first substrate 21 and is formed for each transistor 23. The recess H1 is formed along the Y1 direction which is the extending direction of a semiconductor layer 231 described later.

[0035] The light-shielding portion 210 is arranged in the recess H1. The light-shielding portion 210 is formed, for example, using a damascene process. The light-shielding portion 210 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. Note that the first substrate 21 may not have the recess H1. In this case, the light-shielding portion 210 is arranged on a flat surface facing the Z1 direction of the first substrate 21.

[0036] On the insulating layer 201, a transistor 23 is disposed. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is disposed on the insulating layer 201. The gate electrode 232 is disposed on the insulating layer 202. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. The region of the insulating layer 202 corresponding to the gate electrode 232 in plan view corresponds to the gate insulating film 233.

[0037] The transistor 23 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the Y1 direction as the "first direction" in plan view. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a lightly doped drain region 231d, and a lightly doped source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The lightly doped drain region 231d is located between the channel region 231c and the drain region 231a. The lightly doped source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. Regions excluding the channel region 231c are doped with impurities to increase conductivity. The impurity concentration in the lightly doped drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the lightly doped source region 231e is lower than the impurity concentration in the source region 231b. Note that, for example, the transistor 23 may not have an LDD structure, and the lightly doped source region 231e and the lightly doped drain region 231d may be omitted.

[0038] The gate electrode 232 is formed, for example, by doping polysilicon with impurities that enhance conductivity. Note that the gate electrode 232 may be formed using a material having conductivity such as a metal, a metal oxide, and a metal compound. The gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231 in a plan view. Further, the gate insulating film 233 is composed of, for example, a silicon oxide film formed by thermal oxidation or a CVD (chemical vapor deposition) method or the like. Such a transistor 23 overlaps the aforementioned light-shielding portion 210 in a plan view.

[0039] As shown in FIG. 5, relay electrodes 244 and 245 are disposed in the insulating layer 203. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. The relay electrode 244 and the contact 271 are integrally formed, for example, and are formed so as to fill a hole penetrating the insulating layers 202 and 203. Further, the relay electrode 245 is electrically connected to the drain region 231a of the semiconductor layer 231 via a contact 272. The relay electrode 245 and the contact 272 are integrally formed, for example, and are formed so as to fill a hole penetrating the insulating layers 202 and 203. Further, the relay electrode 245 and the contact 272 function as a light-shielding layer that blocks the intrusion of light into the low-concentration drain region 231d of the semiconductor layer 231.

[0040] As shown in FIG. 5, a scanning line 241, relay electrodes 246 and 247 are disposed on the insulating layer 204. The scanning line 241 is electrically connected to the gate electrode 232 via a contact 2410. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 penetrating the insulating layer 204. The relay electrode 247 is electrically connected to the relay electrode 245 via a contact 274 penetrating the insulating layer 204. Further, the contact 2410 is a contact plug that fills a hole penetrating the insulating layers 203 and 204, for example. Each of the contacts 273 and 274 is a contact plug that fills a hole penetrating the insulating layer 204, for example.

[0041] As shown in FIG. 6, the contact 2410 has a first connection portion 2411, a second connection portion 2412, and a third connection portion 2413. The first connection portion 2411 is a portion provided in the Z2 direction from the gate electrode 232. Each of the second connection portion 2412 and the third connection portion 2413 is a portion extending in the Z2 direction from the first connection portion 2411. When viewed in the direction along the Y axis, the gate electrode 232 is disposed between the second connection portion 2412 and the third connection portion 2413. Each of the second connection portion 2412 and the third connection portion 2413 is connected to the light shielding portion 210. Therefore, the light shielding portion 210 has the same potential as the gate electrode 232, and the light shielding portion 210 functions as a back gate. Further, the contact 2410 functions as a light shielding layer that blocks the intrusion of light into the low-concentration drain region 231d of the semiconductor layer 231.

[0042] As shown in FIG. 5, a relay electrode 248 and a relay electrode 249 are disposed on the insulating layer 205. The relay electrode 248 is electrically connected to the relay electrode 247 via a contact 276 provided in the insulating layer 205. The contact 276 is formed integrally with the relay electrode 248, for example. The contact 276 is a trench electrode formed along the wall surface of a groove formed in the insulating layer 205. Further, the relay electrode 249 is electrically connected to the relay electrode 246 via a contact 275 provided in the insulating layer 205. The contact 275 is formed integrally with the relay electrode 249, for example. The contact 275 is a trench electrode formed along the wall surface of a groove formed in the insulating layer 205.

[0043] A signal line 242 is disposed on the insulating layer 206. The signal line 242 is electrically connected to the relay electrode 249 via a contact 277 provided in the insulating layer 206. Therefore, the signal line 242 is electrically connected to the source region 231b via the contact 275, the relay electrode 246, the contact 273, the relay electrode 244, and the contact 271.

[0044] As shown in FIG. 6, a relay electrode 249 is disposed on the insulating layer 206. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 278 provided in the insulating layer.

[0045] As shown in FIG. 5, an insulating layer and a protruding portion 220 having translucency are disposed on the first insulating layer 207. For example, the protruding portion 220 is formed integrally with the first insulating layer 207. The protruding portion 220 is provided in the aforementioned light-shielding region A12. Further, the protruding portion 220 protrudes from the first insulating layer 207 toward the second insulating layer 208 which is the layer where the pixel electrode 25 is provided, from the first insulating layer 207. The protruding portion 220 has a convex shape protruding from the first insulating layer 207 along the Z1 direction which is the thickness direction of the first insulating layer 207. Note that the layer where the pixel electrode 25 is provided may be regarded as the first alignment film 29.

[0046] In addition, a capacitor element 22 is disposed on the first insulating layer 207 and the protruding portion 220. The protruding portion 220 has a convex shape serving as the base of the capacitor element 22. The capacitor element 22 is provided in the aforementioned light-shielding region A12. The capacitor element 22 is provided corresponding to each pixel electrode 25. The capacitor element 22 includes a first capacitor electrode 221, a second capacitor electrode 222, and a dielectric film 223.

[0047] The first capacitor electrode 221 of the capacitor element 22 is provided on the first insulating layer 207 so as to cover the protruding portion 220. Further, some of the plurality of first capacitor electrodes 221 arranged along the same line of the Y axis are connected to each other to form a constant potential line 243. Therefore, the first capacitor electrode 221 functions as the constant potential line 243 as a “wiring”. Further, the second capacitor electrode 222 is spaced apart from and faces the first capacitor electrode 221. A dielectric film 223 is provided between the second capacitor electrode 222 and the first capacitor electrode 221.

[0048] As described above, the capacitive element 22 is provided so as to cover the protruding portion 220. Specifically, the capacitive element 22 covers the side surface and the upper surface of the protruding portion 220 and has a three-dimensional structure. In this way, by providing the capacitive element 22 so as to cover the protruding portion 220 protruding from the first insulating layer 207, it is possible to increase the capacitive area as compared with the case where the capacitive element is provided on a flat surface. Furthermore, by providing the capacitive element 22 so as to cover the protruding portion 220, it is not necessary to form the capacitive element in the groove formed in the first insulating layer 207 as in the prior art. Therefore, even if the light-shielding region A12 is reduced with the narrowing of the pixel pitch, the capacitive element 22 can be surely formed.

[0049] In addition, since the first capacitive electrode 221 is provided so as to cover the protruding portion 220, it is easier to form the first capacitive electrode 221 thicker than in the case where the first capacitive electrode 221 is formed in the groove. Therefore, it is easy to make the first capacitive electrode 221 thick enough to be used as the constant potential line 243. Therefore, since the first capacitive electrode 221 is provided so as to cover the protruding portion 220, the first capacitive electrode 221 can be utilized as the constant potential line 243. Thus, it is not necessary to separately provide the constant potential line 243. For this reason, the number of stacked layers of the element substrate 2 can be reduced, which is suitable for miniaturization in addition to the narrowing of the pixel pitch.

[0050] Also, the first insulating layer 207 and the protruding portion 220 may be made of different materials and may be configured separately, but it is preferable that they are made of the same material. By being made of the same material, the protruding portion 220 can be easily formed by etching. Also, even if the light-shielding region A12 is reduced with the narrowing of the pixel pitch, it is easy to provide the protruding portion 220 in the light-shielding region A12. Therefore, even if the light-shielding region A12 is reduced with the narrowing of the pixel pitch, the capacitive element 22 with an increased capacitive area can be more surely formed.

[0051] Also, as shown in FIG. 5, a protective film 225 is disposed on the first capacitive electrode 221. The protective film 225 is a film that protects the first capacitive electrode 221 during the formation of the capacitive element 22. The surface of the protective film 225 opposite to the first capacitive electrode 221 is in contact with the second insulating layer 208. The protective film 225 includes, for example, an inorganic material containing silicon such as silicon oxide or silicon oxynitride. The protective film 225 may be the same material as the first insulating layer 207 or the second insulating layer 208, or may be a different material.

[0052] Also, as shown in FIG. 6, a second insulating layer 208 is provided on the second capacitive electrode 222. A pixel electrode 25 is disposed on the second insulating layer 208. Therefore, the second insulating layer 208 is a layer provided between the second capacitive electrode 222 and the pixel electrode 25.

[0053] The pixel electrode 25 is electrically connected to the second capacitive electrode 222 through a contact 270 provided in the second insulating layer 208. The contact 270 is provided in a portion of the second insulating layer 208 that does not overlap the protrusion 220 in plan view. The thickness of the portion of the second insulating layer 208 that does not overlap the protrusion 220 in plan view is thicker than the thickness of the overlapping portion.

[0054] Also, the contact 270 is a contact plug that fills a hole H0 penetrating along the Z axis formed in the second insulating layer 208. By the contact 270 being a contact plug, a contact 270 with a high aspect ratio can be realized. For this reason, the contact 270 can be provided in the thick portion of the second insulating layer 208. Furthermore, since it is possible to provide the contact 270 in the thick portion of the second insulating layer 208, even if the light-shielding region A12 shrinks with the narrowing of the pixel pitch, the electrical connection between the second capacitive electrode 222 and the pixel electrode 25 can be surely made.

[0055] Note that, as shown in FIG. 5 or FIG. 6, the pixel electrode 25 is electrically connected to the drain region 231a via the contact 270, the second capacitor electrode 222, the contact 279, the relay electrode 249, the contact 278, the relay electrode 248, the contact 276, the relay electrode 247, the contact 274, the relay electrode 245, and the contact 272.

[0056] Further, each of the aforementioned scanning line 241, signal line 242, relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be a single layer or a laminate. For example, these may be composed of a laminate of an aluminum film and a titanium nitride film. Each of the first capacitor electrode 221 and the second capacitor electrode 222 includes, for example, metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, and metal silicides. The dielectric film 223 includes, for example, silicon oxide formed by thermal oxidation or a CVD method or the like.

[0057] Further, the aforementioned contacts 271 to 279, 270, and 2410 include, for example, metals such as tungsten, titanium, chromium, iron, and aluminum, metal nitrides, and metal silicides. Each of the contacts 271 to 279, 270, and 2410 may be a single layer or a laminate. Also, each of the contacts 274 to 279 may be a contact plug instead of a trench electrode.

[0058] Note that the configuration of the element substrate 2 shown in FIGS. 5 and 6 is an example. For example, the scanning line 241, the signal line 242, and the capacitor element 22 are arranged in this order in the Z1 direction, but they do not have to be arranged in this order.

[0059] 1E. Protrusion and Capacitor Element FIG. 7 is a plan view showing the positional relationship between the transistor 23 and the protruding portion 220 in FIG. 5. As shown in FIG. 7, in the wide portion A122 of the light-shielding region A12, a channel region 231c of the semiconductor layer 231 is provided. Further, in the wide portion A122, the aforementioned protruding portion 220 is provided. The shape of the protruding portion 220 in plan view is, for example, a rectangular shape. The protruding portion 220 and the channel region 231c overlap in plan view.

[0060] The wide portion A122 is wider and has higher light-shielding properties than other portions of the light-shielding region A12. Therefore, by providing the channel region 231c of the semiconductor layer 231 in the wide portion A122, the incidence of light on the semiconductor layer 231 can be effectively suppressed. From this perspective, it is more preferable that the low-concentration drain region 231d of the semiconductor layer 231 is also provided in the wide portion A122.

[0061] Further, as described above, the wide portion A122 is wider than other portions of the light-shielding region A12. Therefore, by providing the protruding portion 220 in the wide portion A122, it is easier to increase the width of the protruding portion 220 compared to the case where it is provided in the first extending portion A121, for example. Therefore, the capacitance of the capacitive element 22 formed to cover the protruding portion 220 can be increased. For this reason, even when the light-shielding region A12 is reduced with the narrowing of the pixel pitch, the capacitive element 22 with an enlarged capacitance area can be more reliably formed.

[0062] Note that the planar shape of the protruding portion 220 is not limited to a quadrangle, and may be, for example, a polygon other than a quadrangle, a circle, or a cross shape. In the example of FIG. 7, the planar shape of the protruding portion 220 is a rectangular shape with the direction along the Y-axis as the longitudinal direction, and the protruding portion 220 overlaps the channel region 231c in plan view. Note that the planar shape of the protruding portion 220 may also be a rectangular shape with the X-axis as the longitudinal direction.

[0063] FIG. 8 is a plan view showing a part of the first capacitive electrode 221 in FIG. 5. As shown in FIG. 8, the first capacitive electrode 221 overlaps the protruding portion 220 in plan view and extends along the Y-axis. The extending direction of the first capacitive electrode 221 is the same as the extending direction of the semiconductor layer 231.

[0064] The first capacitance electrode 221 includes a first wide electrode portion 2211 including a first portion 2215, a second portion 2212, and a third portion 2213. The first wide electrode portion 2211 is a portion provided in the wide portion A122 of the light-shielding region A12. The first portion 2215 is a portion of the first wide electrode portion 2211 that overlaps the protruding portion 220 in plan view. The second portion 2212 is a portion extending along the Y axis from the first wide electrode portion 2211 and is provided in the first extending portion A121 of the light-shielding region A12. The third portion 2213 is a portion extending in the X2 direction from the first wide electrode portion 2211 and is provided in the second extending portion A123 of the light-shielding region A12.

[0065] FIG. 9 is a plan view showing the second capacitance electrode 222 and the protective film 225 in FIG. 5. As shown in FIG. 9, the second capacitance electrode 222 overlaps the first capacitance electrode 221 in plan view and also overlaps the protruding portion 220.

[0066] The second capacitance electrode 222 includes a second wide electrode portion 2221, a first extending electrode portion 2222, a second extending electrode portion 2223, and a third extending electrode portion 2224. The second wide electrode portion 2221 is a portion provided in the wide portion A122 of the light-shielding region A12. The second wide electrode portion 2221 overlaps the first wide electrode portion 2211 in plan view. In the illustrated example, the plan view shape of the second wide electrode portion 2221 and the plan view shape of the first wide electrode portion 2211 are the same as each other, but they may be different. However, from the viewpoint of expanding the capacitance area, it is preferable that they are the same as each other.

[0067] The first extending electrode portion 2222 and the second extending electrode portion 2223 are provided in the first extending portion A121 of the light-shielding region A12 and overlap the second portion 2212 in plan view. The first extending electrode portion 2222 is a portion extending in the Y2 direction from the second wide electrode portion 2221. The second extending electrode portion 2223 is a portion extending in the Y1 direction from the second wide electrode portion 2221. The third extending electrode portion 2224 is provided in the second extending portion A123 of the light-shielding region A12 and overlaps the third portion 2213 in plan view. The third extending electrode portion 2224 is a portion extending in the X2 direction from the second wide electrode portion 2221.

[0068] Also, the shape of the dielectric film 223 in plan view is substantially the same as the shape of the second capacitive electrode 222 in plan view. Therefore, the dielectric film 223 overlaps each of the second wide electrode portion 2221, the first extending electrode portion 2222, the second extending electrode portion 2223, and the third extending electrode portion 2224.

[0069] Also, two adjacent second capacitive electrodes 222 along the Y-axis are spaced apart from each other. Similarly, two adjacent dielectric films 223 along the Y-axis are spaced apart from each other. And, in plan view, a protective film 225 is disposed between the two second capacitive electrodes 222. Similarly, a protective film 225 is disposed between the two dielectric films 223. Viewed in another way, the protective film 225 has a portion that does not overlap the dielectric film 223 and the second capacitive electrode 222 in plan view. On the other hand, the protective film 225 overlaps the first capacitive electrode 221 in plan view. Specifically, as shown in FIG. 5, the protective film 225 is disposed on the surface s221 opposite to the first insulating layer 207 of the second portion 2212 of the first capacitive electrode 221. Also, the protective film 225 is provided at a position different from the protruding portion 220 in plan view.

[0070] Such a protective film 225 has a function of protecting a part of the second portion 2212 of the first capacitive electrode 221 during the formation of the capacitive element 22. Therefore, in the manufacture of the capacitive element 22 described later, a plurality of capacitive elements 22 can be formed collectively with high precision. Therefore, a capacitive element 22 suitable for a narrow pixel pitch can be provided.

[0071] Further, as shown in FIG. 9, the contact 270 overlaps with the pixel electrode 25 and the third extending electrode portion 2224 of the second capacitive electrode 222 in plan view. The contact 270 electrically connects the second capacitive electrode 222 and the pixel electrode 25 at a position different from the protruding portion 220 in plan view.

[0072] As described above, since the contact 270 is a contact plug, a contact 270 with a high aspect ratio can be realized. Therefore, as described above, since the protruding portion 220 is provided on the first insulating layer 207, even if the thickness of the second insulating layer 208 increases, the contact 270 can surely electrically connect the second capacitive electrode 222 and the pixel electrode 25.

[0073] According to the electro-optical device 100 described above, even if the light-shielding region A12 shrinks as the pixel pitch is narrowed, the capacitive element 22 with an enlarged capacitive area can be provided.

[0074] 1F. Manufacturing Method of Capacitive Element etc. FIG. 10 is a flowchart showing a manufacturing method of a part of the element substrate 2 shown in FIG. 5. As shown in FIG. 10, the manufacturing method of the element substrate 2 included in the electro-optical device 100 includes a protruding portion forming step S11, a capacitive element forming step S12, a contact forming step S13, and a pixel electrode forming step S14. The capacitive element forming step S12 includes a first electrode layer forming step S121, a protective film forming step S122, a dielectric layer forming step S123, a second electrode layer forming step S124, and a batch removal step S125.

[0075] Each of FIGS. 11 and 12 is a diagram for explaining the protruding portion forming step S11. As shown in FIG. 11, in the protruding portion forming step S11, first, an insulating base material layer 207a is formed on the insulating layer 206 so as to cover the signal line 242. Although not shown in FIG. 11, the insulating base material layer 207a is formed so as to cover the relay electrode 249 on the insulating layer 206 shown in FIG. 6.

[0076] For example, the insulating base material layer 207a is formed by depositing an inorganic material containing silicon using a deposition method such as CVD (chemical vapor deposition). Further, after film formation by the deposition method, planarization treatment is appropriately performed by polishing such as CMP (chemical mechanical polishing).

[0077] Next, etching is performed to remove a part of the insulating base material layer 227a using the resist mask R1. As a result, as shown in FIG. 12, the first insulating layer 207 and the protruding portion 220 are formed. Thereafter, the mask R1 is removed. Note that before forming the insulating base material layer 227a, a stopper film that functions as an etching stopper may be formed.

[0078] Each of FIGS. 13, 14, and 15 is a diagram for explaining the first electrode layer forming step S121 in FIG. 10. As shown in FIGS. 13 and 14, in the first electrode layer forming step S121, first, the first electrode layer 221a is formed on the first insulating layer 207 so as to cover the protruding portion 220. For example, the first electrode layer 221a is formed by depositing a metal material by a sputtering method or the like. Next, as shown in FIG. 15, etching is performed to remove a part of the first electrode layer 221a using the resist mask R2. Note that after that, the mask R2 is removed.

[0079] Each of FIGS. 16, 17, and 18 is a diagram for explaining the protective film forming step S122 in FIG. 10. As shown in FIGS. 16 and 17, in the protective film forming step S122, first, the protective base material layer 225a is formed on the first insulating layer 207 so as to cover the first electrode layer 221a. For example, the protective base material layer 225a is formed by depositing an inorganic material containing silicon using a deposition method such as CVD (chemical vapor deposition).

[0080] Next, as shown in FIG. 18, by performing etching to remove a part of the protective base material layer 225a using the resist mask R3, a protective film 225 is formed on the first electrode layer 221a. Thereafter, the mask R3 is removed.

[0081] Each of FIGS. 19 and 20 is a diagram for explaining the dielectric layer forming step S123 of FIG. 10. As shown in FIG. 19, in the dielectric layer forming step S123, first, a dielectric layer 223a is formed on the first insulating layer 207 so as to cover the protective film 225 and the first electrode layer 221a. For example, the dielectric layer 223a is formed by depositing silicon oxide using thermal oxidation or the CVD method or the like.

[0082] Next, as shown in FIG. 20, etching is performed to remove a part of the dielectric layer 223a using the resist mask R4. Thereafter, the mask R4 is removed.

[0083] Each of FIGS. 21 and 22 is a diagram for explaining the second electrode layer forming step S124 of FIG. 10. As shown in FIG. 21, in the second electrode layer forming step S124, first, a resist mask R5 is formed on the first insulating layer 207 so as to cover the dielectric layer 223a. Then, by removing a part of the dielectric layer 223a and a part of the first insulating layer 207 using the resist mask R5, a hole H2 is formed, and a part of the relay electrode 248 is exposed. Thereafter, the mask R5 is removed. Note that, for example, the mask R5 may be formed by adding a resist without removing the aforementioned mask R4.

[0084] Next, as shown in FIG. 22, a second electrode layer 222a is formed on the first insulating layer 207 so as to cover the dielectric layer 223a. At this time, a contact 279 along the inner wall surface forming the hole H2 is formed integrally with the second electrode layer 222a.

[0085] Each of FIGS. 23 and 24 is a diagram for explaining the batch removal step S125 of FIG. 10. As shown in FIGS. 23 and 24, in the batch removal step S125, by etching using a resist mask (not shown), a part of each of the first electrode layer 221a, the dielectric layer 223a, and the second electrode layer 222a is removed in a batch. As a result, as shown in FIG. 23, the first capacitive electrode 221 having an end face 2210, the dielectric film 223 having an end face 2230, and the second capacitive electrode 222 having an end face 2220 are formed.

[0086] Since the above batch removal is performed, the end faces 2210, 2230, and 2220 overlap each other in plan view. The end faces 2210, 2230, and 2220 constitute the side surfaces of the continuous surface of the capacitive element 22. By performing the batch removal, the end faces 2210, 2230, and 2220 can be aligned. Since the end faces 2210, 2230, and 2220 overlap each other in plan view, the capacitive area can be increased as compared with the case where they do not overlap. Therefore, the capacitance value can be increased.

[0087] Also, as shown in FIG. 24, since the protective film 225 is formed, in the batch removal, the portion corresponding to the second portion 2212 of the first capacitive electrode 221 in the first electrode layer 221a is not removed. Therefore, in this step, the capacitive element 22 can be formed, and the constant potential line 243 composed of a plurality of first capacitive electrodes 221 can be formed.

[0088] Each of FIGS. 25 and 26 is a diagram for explaining the contact formation step S13 of FIG. 10. As shown in FIG. 25, in the contact formation step S13, first, a second insulating layer 208 is formed on the first insulating layer 207 so as to cover the capacitive element 22. Then, a hole H0 is formed in the second insulating layer 208 by etching. The hole H0 is formed so as to overlap the second capacitive electrode 222 in plan view and expose a part of the second capacitive electrode 222. The hole H0 does not overlap the protrusion 220 in plan view and is formed at a position different from the protrusion 220. The hole H0 overlaps the third extending electrode portion 2224 of the second capacitive electrode 222 in plan view.

[0089] Next, as shown in FIG. 26, a contact 270 which is a contact plug for filling the hole H0 is formed. The contact 270 is deposited by flowing a metal material such as tungsten into the hole H0 by CVD method. Note that the contact 270 may have a laminated structure. Further, a planarization process is appropriately performed on the upper surface of the contact 270 by polishing such as CMP.

[0090] FIG. 27 is a diagram for explaining the pixel electrode forming step S14 in FIG. 10. As shown in FIG. 27, in the pixel electrode forming step S14, a pixel electrode 25 is formed on the second insulating layer 208. A part of the pixel electrode 25 is formed so as to overlap the contact 270 in plan view and is connected to the contact 270.

[0091] By the above method, the protruding portion 220, the capacitor element 22 covering the protruding portion 220, the contact 270 connected to the second capacitor electrode 222, and the pixel electrode 25 are formed. According to the above method, even if the light shielding region A12 is reduced with the narrowing of the pixel pitch, a capacitor element 22 having a large capacitance area can be easily and surely formed.

[0092] 2. Second Embodiment For elements whose functions are the same as those in the first embodiment in the following examples, the reference numerals used in the description of the first embodiment are reused and the detailed description of each is appropriately omitted.

[0093] FIG. 28 is a diagram for explaining a contact 270 that electrically connects the second capacitor electrode 222 and the pixel electrode 25 in the second embodiment. FIG. 29 is a diagram showing a planar arrangement of the contact 270 in FIG. 28. In this embodiment, the contact 270 is omitted, and instead, a contact 270 is provided.

[0094] As shown in FIGS. 28 and 29, the contact 251 electrically connects the second capacitive electrode 222 and the pixel electrode 25. The contact 251 is formed integrally with the pixel electrode 25. Therefore, the material of the contact 251 is the same as that of the pixel electrode 25. The contact 251 is a trench electrode formed along the inner wall surface of the hole H4 in the second insulating layer 208.

[0095] In plan view, the contact 251 overlaps with the second wide electrode portion 2221 of the second capacitive electrode 222. The contact 270 is connected to the second wide electrode portion 2221. Also, the contact 270 is provided at a position overlapping with the protruding portion 220 in plan view.

[0096] The thickness of the portion of the second insulating layer 208 that overlaps with the protruding portion 220 in plan view is thinner than the thickness of the non-overlapping portion. Therefore, by providing the contact 270 in the portion of the second insulating layer 208 that overlaps with the protruding portion 220 in plan view, even if it is a trench electrode instead of a tungsten plug, the electrical connection between the second capacitive electrode 222 and the pixel electrode 25 can be surely made.

[0097] 3. Modification The embodiments exemplified above can be variously modified. Specific modification modes applicable to the foregoing embodiments are exemplified below. Two or more modes arbitrarily selected from the following examples can be appropriately combined within a range not conflicting with each other.

[0098] FIG. 30 is a diagram showing the arrangement of the contact 270 in the modification. As shown in FIG. 30, the contact 270 may be provided, for example, so as to overlap with the second wide electrode portion 2221 of the second capacitive electrode 222 in plan view. Thus, the arrangement of the contact 270 is not limited to the example of the first embodiment described above. Also, the contact 270 may be a tungsten plug and may overlap with the protruding portion 220 in plan view.

[0099] In each of the foregoing embodiments, the active matrix type electro-optical device 100 is exemplified, but it is not limited thereto, and the driving method of the electro-optical device 100 may be, for example, a passive matrix type or the like.

[0100] The driving method of the "electro-optical device" is not limited to the vertical electric field method, and the horizontal electric field method may also be used. As the horizontal electric field method, for example, the IPS (In Plane Switching) mode can be mentioned. As the vertical electric field method, the TN (Twisted Nematic) mode, VA (Virtical Alignment), PVA mode, and OCB (Optically Compensated Bend) mode can be mentioned.

[0101] 4. Electronic device The electro-optical device 100 can be used in various electronic devices.

[0102] FIG. 31 is a perspective view showing a personal computer 2000 which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main body 2010 where a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0103] FIG. 32 is a plan view showing a smartphone 3000 which is an example of an electronic device. The smartphone 3000 includes an operation button 3001, an electro-optical device 100 for displaying various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 is changed according to the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0104] FIG. 33 is a schematic diagram showing a projector which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. The electro-optical device 1r is the electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is the electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is the electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0105] The illumination optical system 4001 supplies the red component r of the emitted light from the illumination device 4002 which is a light source to the electro-optical device 1r, supplies the green component g to the electro-optical device 1g, and supplies the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as a light modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to the display image. The projection optical system 4003 synthesizes the emitted light from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0106] The above-described electronic device includes the aforementioned electro-optical device 100 and the control unit 2003, 3002, or 4005. The aforementioned electro-optical device 100 includes the capacitive element 22 corresponding to the narrow pixel pitch. Therefore, the electro-optical device 100 can correspond to the narrow pixel pitch. Thus, by providing the electro-optical device 100, the miniaturization and display quality of the personal computer 2000, the smartphone 3000, or the projection display device 4000 can be improved.

[0107] Note that the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices. For example, they include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of sale) terminals, etc. Furthermore, the electronic devices to which the present invention is applied include printers, scanners, copiers, video players, or devices equipped with touch panels, etc.

[0108] Also, in the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited thereto. For example, the electro-optical device of the present invention can also be applied to image sensors, etc.

[0109] As described above, the present invention has been described based on preferred embodiments, but the present invention is not limited to the above-described embodiments. Also, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as that of the above-described embodiments, and any configuration can be added.

Explanation of Reference Numerals

[0110] 2... element substrate, 3... counter substrate, 4... sealing member, 5... liquid crystal layer, 20... laminate, 21... first substrate, 22... capacitive element, 23... transistor, 25... pixel electrode, 100... electro-optical device, 207... first insulating layer, 208... second insulating layer, 220... protrusion, 221... first capacitive electrode, 222... second capacitive electrode, 223... dielectric film, 225... protective film, 231... semiconductor layer, 231a... drain region, 231b... source region, 231c... channel region, 231d... low-concentration drain region, 231e... low-concentration source region, 232... gate electrode, 233... gate insulating film, 243... constant potential line, 270... contact, 2211... first wide electrode portion, 2212... second portion, 2213... third portion, 2215... first portion, 2221... second wide electrode portion, 2222... first extending electrode portion, 2223... second extending electrode portion, 2224... third extending electrode portion, 2210... end face, 2220... end face, 2230... end face, 2411... first connection portion, 2412... second connection portion, 2413... third connection portion, A10... display region, A11... opening region, A12... light-shielding region, A121... first extending portion, A122... wide portion, A123... second extending portion, A20... peripheral region, D1... distance, D2... distance, H0... hole, H4... hole, P... pixel, s221... surface.

Claims

1. An electro-optical device comprising an opening region where a pixel electrode is provided, and a light-shielding region where a transistor having a semiconductor layer electrically connected to the pixel electrode and extending in a first direction is provided, a first insulating layer having insulating properties provided in the opening region and the light-shielding region, an insulating protrusion provided in the light-shielding region and protruding from the first insulating layer toward the layer where the pixel electrode is provided, a capacitive element provided in the light-shielding region, wherein the capacitive element includes a first capacitive electrode that covers the protrusion and functions as a wiring, a second capacitive electrode spaced apart from the first capacitive electrode, and a dielectric film provided between the first capacitive electrode and the second capacitive electrode, characterized in that it is an electro-optical device.

2. The semiconductor layer has a channel region, the light-shielding region has an extending portion extending along the first direction and a widened portion wider than the extending portion, each of the channel region and the protrusion is provided in the widened portion, the channel region and the protrusion overlap in plan view, The electro-optical device according to claim 1.

3. The first capacitive electrode has a first portion overlapping the protrusion in plan view and a second portion provided at a position different from the protrusion in plan view and extending in the first direction, an insulating protective film for protecting a part of the second portion is provided on a surface of the second portion opposite to the first insulating layer, The electro-optical device according to claim 1.

4. The protective film has a portion that does not overlap the dielectric film and the second capacitive electrode in plan view, The electro-optical device according to claim 3.

5. The first insulating layer and the protrusion are made of the same material, The electro-optical device according to claim 1.

6. The first capacitive electrode, the dielectric film, and the second capacitive electrode have end faces overlapping each other in plan view, The electro-optical device according to claim 1.

7. further comprising a second insulating layer provided between the second capacitive electrode and the pixel electrode, the second capacitive electrode is electrically connected to the pixel electrode through a contact plug penetrating the second insulating layer at a position different from the protrusion in plan view, The electro-optical device according to claim 1.

8. further comprising a second insulating layer provided between the second capacitive electrode and the pixel electrode, The second capacitive electrode is electrically connected to the pixel electrode through a trench electrode along an inner wall surface of a hole provided in the second insulating layer at a position overlapping the protruding portion in a plan view. The electro-optical device according to claim 1. Claim 9 An electro-optical device according to any one of claims 1 to 8, and a control unit configured to control operation of the electro-optical device, wherein the electro-optical device is characterized by having the control unit.

Images