Reference voltage circuit

Abstract

To provide a reference voltage circuit capable of reducing variations in reference voltage due to process variation, temperature variation, and power supply voltage variation, and having enhanced radiation resistance.SOLUTION: A reference voltage generation unit 2 includes: a transistor M1 constituted by a depletion-type field-effect transistor in which a gate electrode containing an n-type impurity is formed;, and a transistor M2 constituted by an enhancement-type field-effect transistor in which a gate electrode containing a p-type impurity is formed. Aspect ratios of the transistors M1 and M2 are equal. A temperature characteristic correction unit 3 includes: transistors M11 and M12 having different aspect ratios; a resistance R1 to which differences between gate-source voltages of the transistors M11 and M12 are applied; and a resistance R2 which is connected between a gate and an output terminal of the transistor M2 and to which current flowing through the resistance R1 is turned back.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a reference voltage circuit.

Background Art

[0002] In electronic devices used in environments irradiated with radiation such as outer space and around nuclear reactors, and in electronic components such as those subjected to radiation transmission inspection in non-destructive inspection in the manufacturing process, where X-rays or γ-rays are irradiated, various radiation damages are caused by the irradiation of ionizing radiation such as X-rays and γ-rays, resulting in malfunction or characteristic variation of the circuit, and sometimes leading to a reduction in the function of the system. With the rapid progress of the communication and informatization society, the radiation resistance of electronic devices and electronic components has become a major issue. Many semiconductor integrated circuits are used in electronic devices, and the present invention aims to enhance the radiation resistance of a reference voltage circuit widely used as a constant voltage source of a semiconductor integrated circuit and contribute to the stable operation of electronic devices.

[0003] Conventionally, as a reference voltage circuit used in a semiconductor integrated circuit, a circuit using the principle of the work function difference of the gate electrode of a transistor as shown in FIG. 7 is known (see, for example, Patent Documents 1 and 2). The reference voltage circuit 100 shown in FIG. 7 mainly includes a depletion-type field-effect transistor M1 formed of polysilicon containing an n-type impurity in the gate electrode, an enhancement-type field-effect transistor M2 formed of polysilicon containing a p-type impurity in the gate electrode, a source follower circuit including a transistor M3 and a constant current source 11 (see, for example, Patent Document 3).

[0004] The impurity concentrations of the substrates and channel doping regions for forming transistors M1 and M2 are made the same, and the conductivity type of the polysilicon for forming the gate electrodes is such that the gate electrode of the depletion-type field-effect transistor M1 is n-type and the gate electrode of the enhancement-type field-effect transistor M2 is p-type. By using the difference in work function caused by the difference in the conductivity type of the gate electrodes, a difference is provided in the threshold voltages of transistors M1 and M2, generating a reference voltage of about 1V (see, for example, Patent Document 4). In this case, since the impurity concentrations of the substrates and channel doping regions of transistors M1 and M2 are equal, it is possible to reduce the variation in the reference voltage due to process variations, temperature variations, and power supply voltage variations.

[0005] The gate and source of transistor M1 are connected to the drain of transistor M2, the gate of transistor M3 is connected to the drain of transistor M2, and the gate of transistor M2 is connected to the source of transistor M3. The constant current source 11 is connected to the source of transistor M3. The constant current generated by transistor M1 is passed through transistor M2, and a voltage corresponding to the difference in the threshold voltages of transistors M1 and M2, that is, the difference in the work functions of the gate electrodes of transistors M1 and M2, is output as a reference voltage from the connection between the gate of transistor M2 and the source of transistor M3.

[0006] The temperature characteristic of the reference voltage is such that since the gate electrode of transistor M1 is formed of polysilicon containing n-type impurities and the gate electrode of transistor M2 is formed of polysilicon containing p-type impurities, the temperature characteristics of the work functions of the gate electrodes of transistors M1 and M2 have opposite polarities, resulting in a difference in the temperature coefficients of the threshold voltages. When the aspect ratios S (W / L) of the channel widths W and channel lengths L of transistors M1 and M2 are equal (S M1 = S M2 ), the temperature coefficient does not become zero and has a negative temperature characteristic of about -0.5 mV / °C (see, for example, Patent Document 4).

[0007] Since the reference voltage VREF is the voltage difference between the threshold voltages of the transistors M1 and M2 as expressed by Equation 1, it is possible to generate a stable reference voltage that is less affected by process variations and power supply voltage fluctuations. Also, good temperature characteristics can be obtained by adjusting the aspect ratio S (W / L) of the channel widths W and channel lengths L of the transistors M1 and M2.

[0008]

Equation

[0009] Here, V TH_M1 is the threshold voltage of transistor M1, V TH_M2 is the threshold voltage of transistor M2, S M1 is the aspect ratio (W M1 / L M1 ) of transistor M1, S M2 is the aspect ratio (W M2 / L M2 ) of transistor M2.

[0010] The characteristic degradation due to radiation irradiation is mainly caused by the generation of positive charges in the silicon oxide film and the increase in the interface trap density at the interface between the silicon oxide film and the silicon substrate, which reduces the threshold voltages of the transistors M1 and M2 constituting the reference voltage circuit 100 (see, for example, Non-Patent Document 1).

[0011] In the conventional reference voltage circuit 100 described above, since the amount of change in the threshold voltages of the transistors M1 and M2 due to radiation irradiation is equal, when the ratio of the aspect ratio (W M1 / L M1 ) of transistor M1 and the aspect ratio (W M2 / L M2 ) of transistor M2 is equal (S M1 = S M2 ), the reference voltage does not change due to radiation irradiation. However, in order to correct the temperature characteristics, the aspect ratio (W M1 / L M1 ) of transistor M1 and the aspect ratio (W M2 / L M2) at different ratios (S M1 ≠S M2 ) When this is the case, when irradiated with radiation, since the amount of variation of each of the first term and the second term in Equation 1 is different, there is a problem that the reference voltage fluctuates.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Non-Patent Documents

[0013]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0014] The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a reference voltage circuit capable of reducing variations in the reference voltage due to process variations, temperature variations, and power supply voltage variations and enhancing radiation resistance.

Means for Solving the Problems

[0015] In order to achieve the above-described object, the reference voltage circuit according to the present invention is characterized by the following [1] to [6]. [1] A depletion-type first field-effect transistor having a gate electrode containing n-type impurities, and A gate electrode containing p-type impurities is formed, and it has an enhancement-type second field-effect transistor having the same aspect ratio as the first field-effect transistor. A reference voltage generation unit that causes a constant current generated by the first field-effect transistor to flow through the second field-effect transistor, and generates a voltage corresponding to the difference between the threshold voltage of the first field-effect transistor and the threshold voltage of the second field-effect transistor between the gate and source of the second field-effect transistor. A first transistor and a second transistor having different aspect ratios. A first resistor having a difference in voltage between the gate-source voltage or the base-emitter voltage of the first transistor and the second transistor applied across both ends. A temperature characteristic correction unit having a second resistor connected between the gate of the second field-effect transistor and the output terminal, and the current flowing through the first resistor is folded back and supplied. It is a reference voltage circuit. [2] In the reference voltage circuit according to [1], The temperature characteristic correction unit A third transistor serially connected to the second transistor. A fourth transistor serially connected to the first transistor. Further has a fifth transistor serially connected to the second resistor. The first transistor and the second transistor are connected in a current mirror configuration. The third transistor and the fourth transistor are connected in a current mirror configuration. The first transistor or the third transistor and the fifth transistor are connected in a current mirror configuration. The sources or emitters of the first transistor and the second transistor are respectively connected to both ends of the first resistor. It is a reference voltage circuit. [3] In the reference voltage circuit according to [1], The temperature characteristic correction unit includes a third transistor connected in series to the first transistor, a fourth transistor connected in series to the second transistor, a current source commonly connected to the sources or emitters of the first transistor and the second transistor, a fifth transistor connected in series to the second resistor, and a sixth transistor connected in series to the first resistor, and the third transistor and the fourth transistor are connected in a current mirror configuration, the fifth transistor and the sixth transistor are connected in a current mirror configuration, the gates or bases of the first transistor and the second transistor are respectively connected to both ends of the first resistor, which is a reference voltage circuit. [4] In the reference voltage circuit according to [3], the current source is composed of the first field effect transistor with its gate-source connected, includes an eighth transistor connected in a current mirror configuration to the third transistor and folding back the current flowing through the third transistor, and the current folded back by the eighth transistor is supplied to the second field effect transistor, which is a reference voltage circuit. [5] In the reference voltage circuit according to any one of [1] to [4], at least one of the transistors is composed of a field effect transistor, which is a reference voltage circuit. [6] In the reference voltage circuit according to any one of [1] to [4], at least one of the transistors is composed of a bipolar transistor, which is a reference voltage circuit.

Advantages of the Invention

[0016] According to the present invention, it is possible to reduce variations in the reference voltage due to process variations, temperature variations, and power supply voltage variations, and to provide a reference voltage circuit with enhanced radiation resistance.

[0017] As described above, the present invention has been briefly explained. Furthermore, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0019] Specific embodiments of the present invention will be described below with reference to the respective drawings.

[0020] (First Embodiment) First, the reference voltage circuit 1 of the first embodiment will be described with reference to FIG. 1. As shown in the figure, the reference voltage circuit 1 includes a reference voltage generation unit 2 that generates a reference voltage, and a temperature characteristic correction unit 3 that generates a PTAT (Proportional To Absolute Temperature) voltage for correcting the temperature characteristic of the reference voltage.

[0021] The reference voltage generation unit 2 includes a transistor M1 (= first field effect transistor) and a transistor M2 (= second field effect transistor). The transistor M1 is composed of an N-channel depletion type field effect transistor in which polysilicon containing n-type impurities is formed as a gate electrode. The transistor M2 is composed of an N-channel enhancement type field effect transistor in which polysilicon containing p-type impurities is formed as a gate electrode.

[0022] The drain of the transistor M1 is connected to the positive power supply terminal T21. A positive power supply voltage VDD is supplied to the positive power supply terminal T21. The drain of the transistor M2 is connected to the gate and source of the transistor M1, and the source is connected to the negative power supply terminal T22. A negative power supply voltage VSS is supplied to the negative power supply terminal T22.

[0023] The constant current I1 generated by the transistor M1 is passed through the transistor M2, and a voltage corresponding to the difference between the threshold voltage of the transistor M2 and the threshold voltage of the transistor M1 is output as the gate-source voltage of the transistor M2. The transistors M1 and M2 are provided with equal aspect ratios. For this reason, the gate-source voltage of the transistor M2 has a negative temperature characteristic.

[0024] The temperature characteristic correction unit 3 has a PTAT voltage V with a positive temperature characteristic PTATIt is supplied to the gate of transistor M2 to reduce the temperature variation of the reference voltage VREF1. The temperature characteristic correction unit 3 includes a transistor M11 (= first transistor), a transistor M12 (= second transistor), a transistor M13 (= third transistor), a transistor M14 (= fourth transistor), a transistor M15 (= fifth transistor), a transistor M19, a resistor R1 (= first resistor), and a resistor R2 (= second resistor). Transistors M11, M12, M15, and M19 are composed of N-channel field-effect transistors. Transistors M13 and M14 are composed of P-channel field-effect transistors.

[0025] The source of transistor M11 is connected to the negative power supply terminal T22. The source of transistor M12 is connected to the negative power supply terminal T22 via resistor R1, and the gate is connected to the gate and drain of transistor M11. That is, transistors M11 and M12 are connected in a current mirror configuration, and the drain current I2 flowing through transistor M11 is copied and folded back to the drain current I2 of transistor M12.

[0026] The aspect ratio S of transistor M12 M12 is set to be N times (N > 1) the aspect ratio S of transistor M11 M11

[0027] The source of transistor M13 is connected to the positive power supply terminal T21, and the gate and drain are connected to the drain of transistor M12. That is, transistors M12 and M13 are connected in series.

[0028] ​The source of transistor M14 is connected to the positive power supply terminal T21, the gate is connected to the gate and drain of transistor M13, and the drain is connected to the gate and drain of transistor M11. That is, transistors M13 and M14 are connected in a current mirror configuration, and the drain current I2 flowing through transistor M13 is copied and folded back to the drain current I2 of transistor M14. Also, transistors M11 and M14 are connected in series.

[0029] The drain of transistor M19 is connected to the positive power supply terminal T21, and the gate is connected to the gate and source of transistor M1. The gate of transistor M15 is connected to the gate and drain of transistor M11. That is, transistors M11 and M15 are connected in a current mirror configuration, and the drain current I2 flowing through transistor M11 is copied and folded back to the drain current I2 of transistor M15. In this embodiment, transistors M11 and M15 are provided with the same aspect ratio.

[0030] Resistor R2 is connected between the drain of transistor M15 and the source of transistor M19. That is, transistor M15 and resistor R2 are connected in series, and the drain current I2 folded back by transistor M15 flows through resistor R2. Output terminal T3 is connected to the connection point between the source of transistor M19 and resistor R2. Also, the source of transistor M15 is connected to the negative power supply terminal T22, and the drain is connected to the connection point between the gate of transistor M2 and resistor R2.

[0031] Next, the operation of the reference voltage circuit 1 having the above-described configuration will be described. First, the operation of the reference voltage generation unit 2 will be described with reference to FIG. 2. FIG. 2 is a graph showing the relationship between the gate-source voltage Vgs and the drain current Ids of the transistors M1 and M2. As shown in the figure, the depletion-type transistor M1 connected to function as a current source supplies a constant current I1 to the drain of the enhancement-type transistor M2. Due to this constant current, a voltage corresponding to the difference between the threshold voltage of the transistor M2 and the threshold voltage of the transistor M1 is output as the gate-source voltage V GS_M2 of the transistor M2. This gate-source voltage V GS_M2 becomes the output voltage generated by the reference voltage generation unit 2. Considering the ratio of the aspect ratios of the transistors M1 and M2, the output voltage V GS_M2 generated by the reference voltage generation unit 2 is represented by Equation 2.

[0032]

Equation

[0033] Here, V TH_M1 is the threshold voltage of the transistor M1, V TH_M2 is the threshold voltage of the transistor M2, S M1 is the aspect ratio (W M1 / L M1 ) of the transistor M1, S M2 is the aspect ratio (W M2 / L M2 ) of the transistor M2.

[0034] The output voltage V GS_M2 generated by the reference voltage generation unit 2 represented by Equation 2 is less affected by process variations and power supply voltage fluctuations and can generate a stable voltage.

[0035] As described above, the gate electrode of transistor M1 is formed of polysilicon containing n-type impurities, and the gate electrode of transistor M2 is formed of polysilicon containing p-type impurities. Therefore, the temperature characteristics of the work functions of the gate electrodes of transistors M1 and M2 have opposite polarities, resulting in a difference in the temperature coefficient of the threshold voltage. When the aspect ratios S (W / L) of the channel widths W and channel lengths L of transistors M1 and M2 are equal (S M1 =S M2 ), if there is a difference in the temperature coefficient of the threshold voltage, the temperature coefficient of the output voltage V GS_M2 will not be zero. The output voltage V GS_M2 has a negative temperature characteristic of about -0.5 mV / °C.

[0036] To improve the temperature characteristics, the ratio S M1 of the channel width W M1 and channel length L M1 of transistor M1 (W M1 / L M1 ) and the ratio S M2 of the channel width W M2 and channel length L M2 of transistor M2 (W M2 / L M2 ) are adjusted respectively, and the ratio of the aspect ratios S (W / L) of transistors M1 and M2 (S M1 / S M2 ) is set in the range of about 1.5 to 2, so that the output voltage V GS_M2 can be stabilized against temperature changes.

[0037] However, due to radiation irradiation, positive charges are generated in the oxide film and the interface trap density at the interface between the silicon oxide film and the silicon substrate increases, so the threshold voltages of transistors M1 and M2 decrease. Since the amount of change in the threshold voltages of transistors M1 and M2 due to radiation irradiation is equal, the ratio of the aspect ratio (W M1 / L M1 ) of transistor M1 and the aspect ratio (W M2 / L M2 ) of transistor M2 is equal (S M1 =S M2) In this case, the reference voltage does not vary due to radiation irradiation, but in order to correct the temperature characteristics, the aspect ratios (W M1 / L M1 ) of transistor M1 and the aspect ratios (W M2 / L M2 ) of transistor M2 are made different ratios (S M1 ≠S M2 ). When irradiated with radiation, since the amounts of variation of the first term and the second term in Equation 2 are different, the output voltage V GS_M2 varies.

[0038] The reference voltage circuit 1 of the present invention equalizes the aspect ratios of transistors M1 and M2 in order to reduce the variation of the reference voltage VREF1 due to radiation irradiation. Also, in order to reduce the variation of the reference voltage VREF1 due to temperature, a PTAT voltage V PTAT having a positive temperature characteristic is generated by the temperature characteristic correction unit 3 and added to the output voltage V GS_M2 of the reference voltage generation unit 2.

[0039] Next, the operation of the temperature characteristic correction unit 3 will be described. As an initial state, it is assumed that currents of different densities flow through the current paths of transistors M11 and M12. Since transistors M13 and M14 and transistors M11 and M12 are respectively connected in a current mirror configuration, they are subject to the self-feedback bias action generated by each current control operation, and the ratio of the currents flowing through transistors M11 and M12 is always kept constant, and the currents flowing through each transistor maintain stable values.

[0040] For simplicity of explanation, it is assumed that the aspect ratios of transistors M13 and M14 are equal. Also, the aspect ratio S M12 of transistor M12 is set to N times (N>1) the aspect ratio S M11 of transistor M11.

[0041] Since the aspect ratios of transistors M13 and M14 are equal, equal currents I2 flow through transistors M13 and M14. Therefore, equal currents I2 also flow through transistors M11 and M12. The voltage drop V R1=R1·I2 is equal to the difference between the gate-source voltage V GS_M11 of transistor M11 and the gate-source voltage V GS_M12 of transistor M12, as expressed by Equation 3 below.

[0042]

Number

[0043] When transistors M11 and M12 operate in the subthreshold region, the drain current changes exponentially with respect to the change in the gate-source potential difference. Therefore, the gate-source voltages V GS_M11 , V GS_M12 of transistors M11 and M12 are expressed by Equations 4 and 5 below, respectively.

[0044]

Number

[0045]

Number

[0046] Here, V T is the thermal voltage (kT / q), k is the Boltzmann constant, T is the absolute temperature, q is the unit charge of an electron, η is the subthreshold swing coefficient, I S is the reverse saturation current of transistor M11, and I S ·S M12 / S M11 is the reverse saturation current of transistor M12.

[0047] From Equations 3 to 5, Equation 6 below is obtained.

[0048]

Number

[0049] When the ratio of the aspect ratios S(W / L) of the transistors M11 and M15 to which the current mirror is connected is equal (S M11 = S M15 ), a current I2 equal to the drain current of the transistor M11 flows through the resistor R2.

[0050] Therefore, the PTAT voltage V PTAT which is the voltage drop across the resistor R2, is represented by the following equations 7 and 8.

[0051] [Number]

[0052] [Number]

[0053] According to equations 7 and 8, the PTAT voltage V PTAT is a value obtained by multiplying the thermal voltage V T (kT / q) of the semiconductor material by a constant K G1 . The thermal voltage V T has a positive temperature characteristic of about +0.086 mV / °C.

[0054] The reference voltage VREF1 is represented by equation 9.

[0055] [Number]

[0056] That is, by adjusting the ratio of the aspect ratios S(W / L) of the transistors M11 and M12 (S M12 / S M11 ) and the ratio of the resistance values of the resistors R1 and R2, as shown in equation 10, the absolute value of the temperature characteristic of the output voltage V GS_M2 generated by the reference voltage generation unit 2 and the temperature characteristic of the thermal voltage V T generated by the temperature characteristic correction unit 3, the ratio of the temperature characteristics of the thermal voltage V T is represented by a constant K G1to be equal to. Under this condition, the output voltage V having a negative temperature coefficient generated by the reference voltage generation unit 2 GS_M2 and the PTAT voltage V having a positive temperature coefficient generated by the temperature characteristic correction unit 3 PTAT are added together, so that the temperature characteristic of the reference voltage circuit 1 can be canceled out.

[0057] [Number]

[0058] That is, the reference voltage circuit 1 in this first embodiment sets the ratio (S M1 / S M2 ) of the aspect ratios S(W / L) of the transistors M1 and M2 to an equal condition (about 1) so that the reference voltage VREF1 does not fluctuate even when irradiated with radiation, and has a circuit configuration in which the negative temperature characteristic generated by the reference voltage generation unit 2 is canceled out by the positive temperature characteristic generated by the temperature characteristic correction unit 3, thereby suppressing characteristic fluctuations due to radiation irradiation.

[0059] Therefore, it is possible to reduce the variation in the reference voltage due to process variation, temperature variation, and power supply voltage variation, and an effect of enhancing radiation resistance is obtained.

[0060] (Second Embodiment) Next, the reference voltage circuit 1B of the second embodiment will be described with reference to FIG. 3. In FIG. 3, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0061] As shown in the figure, the reference voltage circuit 1B includes, similarly to the first embodiment, a reference voltage generation unit 2 that generates a reference voltage, and a temperature characteristic correction unit 3B that generates a PTAT voltage for correcting the temperature characteristic of the reference voltage.

[0062] The differences between the temperature characteristic correction unit 3 of the first embodiment and the temperature characteristic correction unit 3B of the second embodiment are that the conductivity types of the transistors M11B to M14B corresponding to the transistors M11 to M14 are reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 connected to the transistors M11B to M14B is reversed. Also, the gate of the transistor M15B corresponding to the transistor M15 is connected to the gate-drain of the transistor M13B. That is, the transistors M15B and M13B are connected in a current mirror configuration, and the drain current I2 flowing through the transistor M13B is copied and folded back to the drain current I2 of the transistor M15B.

[0063] Therefore, similar to the first embodiment, the second embodiment can also reduce the variation in the reference voltage due to process variations, temperature variations, and power supply voltage variations, and can obtain the effect of enhancing radiation resistance.

[0064] (Third Embodiment) Next, the reference voltage circuit 1C of the third embodiment will be described with reference to FIG. 4. In FIG. 4, the same components as those in the circuit shown in FIG. 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0065] As shown in the figure, the reference voltage circuit 1C includes, similar to the first embodiment, a reference voltage generation unit 2 that generates a reference voltage, and a temperature characteristic correction unit 3C that generates a PTAT voltage for correcting the temperature characteristic of the reference voltage. Since the reference voltage generation unit 2 is the same as that in the first embodiment described above, detailed description thereof is omitted here.

[0066] The difference between the first embodiment and the third embodiment lies in the configuration of the temperature characteristic correction unit 3C. The temperature characteristic correction unit 3C includes a transistor M11C (= the first transistor), a transistor 12C (= the second transistor), a transistor M13C (= the third transistor), a transistor M14C (= the fourth transistor), a transistor M15C (= the fifth transistor), a transistor M16 (= the sixth transistor), a transistor M17 (= the seventh transistor), a resistor R1C (= the first resistor), a resistor R2 (= the second resistor), a resistor R3, and a constant current source 31 (= a current source). The transistors M11C, M12C, M15C, and M16 are composed of N-channel field effect transistors. The transistors M13C, M14C, and M17 are composed of P-channel field effect transistors.

[0067] The transistors M11C and M12C form a differential input section in which each source is commonly connected and currents having a current ratio corresponding to the input potential difference flow therethrough. The constant current source 31 is connected between each source of the transistors M11C and M12C and the negative power supply terminal T22.

[0068] The source of the transistor M13C is connected to the positive power supply terminal T21, and the gate and drain are connected to the drain of the transistor M11C. That is, the transistors M11C and M13C are connected in series.

[0069] The source of the transistor M14C is connected to the positive power supply terminal T21, the gate is connected to the gate and drain of the transistor M13C, and the drain is connected to the drain of the transistor M12C. That is, the transistors M13C and M14C are connected in a current mirror configuration, and the drain current flowing through the transistor M13C is copied and folded back to the drain current of the transistor M14C. Also, the transistors M12C and M14C are connected in series.

[0070] Transistor M17 has its gate connected to the connection point between transistor M12C and transistor 14C, its source connected to the positive power supply terminal T21, and its drain connected to the gate of transistor M11C.

[0071] For transistor M16, its source is connected to the negative power supply terminal T22, and its gate and drain are connected to the gate of transistor M15C. That is, transistors M16 and M15C are connected in a current mirror configuration, and the drain current flowing through transistor M16 is copied and folded back to the drain current of transistor M15C.

[0072] Resistor R1C is connected between the gate of transistor M11C and the gate of transistor M12C. Resistor R3 is connected between the gate of transistor M12C and the gate and drain of transistor M16. That is, transistor M16 is connected in series with resistors R1C and R3.

[0073] Next, the operation of the temperature characteristic correction unit 3C with the above-described configuration will be described. The reference voltage circuit 1C in such a configuration is basically the same as that in the first embodiment, except for the points described later.

[0074] Since transistors M13C and M14C are connected in a current mirror configuration, the ratio (shunt ratio) of the currents flowing from the constant current source 31 to transistors M11C and M12C is always kept constant. Transistor M17 controls the current I3 flowing through resistors R1C and R3, that is, the gate potential of transistors M11C and M12C, so that the current from the constant current source 31 always flows through transistors M11C and M12C at a constant ratio.

[0075] To simplify the explanation, assume that the aspect ratios of transistors M13C and M14C are equal. Also, the aspect ratio S M12C of transistor M12C is set to be N times (N>1) the aspect ratio S M11C of transistor M11C.

[0076] Assuming that the current flowing through transistor M17 is I3, the voltage drop V across resistor R1C R1C = R1C·I3 is equal to the difference between the gate-source voltage V of transistor M11C GS_M11C and the gate-source voltage V of transistor M12C GS_M12C as expressed by the following Equation 11.

[0077]

Equation

[0078] When transistors M11C and M12C operate in the subthreshold region, since the drain current changes exponentially with respect to the change in the gate-source potential difference, the gate-source voltages V of transistors M11C and M12C GS_M11C , V GS_M12C are expressed by the following Equations 12 and 13, respectively.

[0079]

Equation

[0080]

Equation

[0081] Here, V T is the thermal voltage (kT / q), k is the Boltzmann constant, T is the absolute temperature, q is the unit charge of an electron, η is the subthreshold swing coefficient, I S is the reverse saturation current of transistor M11C, and I S ·S M12C / S M11C is the reverse saturation current of transistor M12C.

[0082] From Equations 11 to 13, the following Equation 14 is obtained.

[0083]

Equation

[0084] When the ratio of the aspect ratios S (W / L) of the transistors M16 and M15C connected in the current mirror is equal (S M16 = S M15C ), a current I3 equal to the drain current of the transistor M16 flows through the resistor R2.

[0085] Therefore, the PTAT voltage V, which is the voltage drop across the resistor R2, PTAT is represented by the following equations 15 and 16.

[0086] [Number]

[0087] [Number]

[0088] According to equations 15 and 16, the PTAT voltage V PTAT is a value obtained by multiplying the thermal voltage V T (kT / q) of the semiconductor material by a constant K G2 . The thermal voltage V T has a positive temperature characteristic of about +0.086 mV / °C.

[0089] The reference voltage VREF2 is represented by equation 17.

[0090] [Number]

[0091] That is, by adjusting the ratio of the aspect ratios S (W / L) of the transistors M11C and M12C (S M12C / S M11C ) and the ratio of the resistance values of the resistors R1C and R2, as shown in equation 18, the absolute value of the temperature characteristic of the output voltage V GS_M2 generated by the reference voltage generation unit 2 and the temperature characteristic of the thermal voltage V T generated by the temperature characteristic correction unit 3C are compared, and the ratio with the temperature characteristic of the thermal voltage V T is the constant K representing the amplification factor of the thermal voltage VG2 to be equal. Under this condition, the output voltage V with a negative temperature coefficient generated by the reference voltage generation unit 2 GS_M2 and the PTAT voltage V with a positive temperature coefficient generated by the temperature characteristic correction unit 3C PTAT are added together, so that the temperature characteristic of the reference voltage circuit 1 can be offset.

[0092]

Number

[0093] That is, the reference voltage circuit 1C in this third embodiment sets the ratio (S M1 / S M2 ) of the aspect ratios S(W / L) of the transistors M1 and M2 to an equal condition (about 1) so that the reference voltage VREF2 does not fluctuate even when irradiated with radiation, and has a circuit configuration in which the negative temperature characteristic generated by the reference voltage generation unit 2 is offset by the positive temperature characteristic generated by the temperature characteristic correction unit 3C, thereby suppressing characteristic fluctuations due to radiation irradiation.

[0094] Therefore, it is possible to reduce the variation in the reference voltage due to process variation, temperature variation, and power supply voltage variation, and an effect of enhancing radiation resistance is obtained.

[0095] (Fourth Embodiment) Next, the reference voltage circuit 1D of the fourth embodiment will be described with reference to FIG. 5. In FIG. 5, the same components as those in the circuit shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0096] As shown in the figure, the reference voltage circuit 1D includes, similarly to the third embodiment, a reference voltage generation unit 2 that generates a reference voltage, and a temperature characteristic correction unit 3D that generates a PTAT voltage for correcting the temperature characteristic of the reference voltage.

[0097] The differences between the temperature characteristic correction section 3C of the third embodiment and the temperature characteristic correction section 3D of the fourth embodiment are that the conductivity types of the transistors M11D to M14D corresponding to the transistors M11C to M14C are reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed. The resistor R1D is connected between the gates of the transistors M11D and M12D.

[0098] Moreover, the difference between the third embodiment and the fourth embodiment lies in the connection destination of the gate of the transistor M16D. In the third embodiment, the gate of the transistor M16C was directly connected to its own drain, but in the fourth embodiment, the gate of the transistor M16D is connected to the connection point of the transistors M11D and M13D. That is, the gate of the transistor M16D is connected to the drain through the drain-gate of the transistor M11D and the resistor R1D. The transistors M15D and M16D are connected in a current mirror configuration, and the drain current flowing through the transistor M16D is copied and folded back to the drain current of the transistor M15D.

[0099] Also, in the fourth embodiment, the transistor M16D functions as the transistor M17 of the third embodiment, and the current I3 flowing through the resistor R1D, that is, the gate potential of the transistors M11D and M12D, is controlled so that the current from the constant current source 31D always flows through the transistors M11D and M12D at a constant ratio.

[0100] Furthermore, in the fourth embodiment, it includes a resistor R3D and a transistor M20. The resistor R3D is connected to the gate of the transistor M11D and the gate-drain of the transistor M20. The transistor M20 is composed of a P-channel transistor, and its source is connected to the positive power supply terminal T21.

[0101] Therefore, similar to the third embodiment, the fourth embodiment can also reduce the variation in the reference voltage due to process variations, temperature variations, and power supply voltage variations, and can obtain the effect of enhancing radiation resistance.

[0102] (Embodiment 5) Next, the reference voltage circuit 1E of the fifth embodiment will be described with reference to FIG. 6. In FIG. 6, the same components as those in the circuit shown in FIG. 4 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0103] As shown in the figure, the reference voltage circuit 1E includes, similarly to the third embodiment, a reference voltage generation unit 2E that generates a reference voltage, and a temperature characteristic correction unit 3E that generates a PTAT voltage for correcting the temperature characteristic of the reference voltage.

[0104] The temperature characteristic correction unit 3E of the fifth embodiment replaces the constant current source 31 of the third embodiment with a transistor M1E (= first field effect transistor). The transistor M1E is composed of an N-channel depletion type field effect transistor in which polysilicon containing n-type impurities is formed as a gate electrode.

[0105] The drain of the transistor M1E is connected to the common source of the transistors M11C and M12C, and the gate and source are connected to the negative power supply terminal T22.

[0106] The reference voltage generation unit 2E of the fifth embodiment replaces the transistor M1 of the third embodiment with a transistor M18 (= eighth transistor). The transistor M18 is composed of a P-channel field effect transistor.

[0107] The source of the transistor M18 is connected to the positive power supply terminal T21, the gate is connected to the gate and drain of the transistor M13C, and the drain is connected to the drain of the transistor M2. That is, the transistors M13C and M18 are connected in a current mirror configuration, and the drain current flowing through the transistor M13C is copied and folded back to the drain current of the transistor M18.

[0108] The ratio of the aspect ratio S (W / L) of each of the transistors M13C and M14C connected in a current mirror is equal (SM13C =S M14C ) When the ratio of the aspect ratios S (W / L) of the current mirror-connected transistors M3C and M18 is 2:1 (S M18 / S M13C =2), the drain current of transistor M18 is equal to the constant current I1 generated by transistor M1E. That is, the constant current I1 generated by transistor M1E is passed through transistor M2, and a voltage corresponding to the difference between the threshold voltage of transistor M2 and the threshold voltage of transistor M1C is output as the gate-source voltage of transistor M2.

[0109] Next, the operation of the reference voltage circuit 1E having the above-described configuration will be described. The reference voltage circuit 1E in such a configuration is basically the same as that of the third embodiment, except for the points described later.

[0110] Similar to the third embodiment, the PTAT voltage V PTAT is represented by the above equations 15 and 16.

[0111] According to equations 15 and 16, the PTAT voltage V PTAT is a value obtained by multiplying the thermal voltage V T of the semiconductor material by a constant K G2 . The thermal voltage V T has a positive temperature characteristic of about +0.086 mV / °C.

[0112] The reference voltage VREF3 generated by the reference voltage circuit 1E is represented by equation 19.

[0113]

Equation

[0114] That is, by adjusting the ratio of the aspect ratios S (W / L) of the transistors M11C and M12C (S M12C / S M11C ) and the ratio of the resistance values of the resistors R1C and R2, as shown in equation 20, the output voltage V GS_M2The absolute value of the temperature characteristic and the thermoelectric voltage V generated by the temperature characteristic correction unit 3E T The ratio of the temperature characteristic of T is made equal to the constant K representing the amplification factor of the thermoelectric voltage V G2 . Under this condition, the output voltage V having a negative temperature coefficient generated by the reference voltage generation unit 2E GS_M2 and the PTAT voltage V having a positive temperature coefficient generated by the temperature characteristic correction unit 3E PATA are added together, so that the temperature characteristic of the reference voltage VREF3 can be canceled out.

[0115]

Equation

[0116] That is, in the reference voltage circuit 1E in this fifth embodiment, in order to prevent the reference voltage VREF3 from fluctuating even when irradiated with radiation, the ratio (S M1E / S M2 ) of the aspect ratios S(W / L) of the transistors M1E and M2 is set to an equal condition (about 1), and the negative temperature characteristic generated by the reference voltage generation unit 2E is canceled out by the positive temperature characteristic generated by the temperature characteristic correction unit 3E, thereby suppressing characteristic fluctuations due to radiation irradiation.

[0117] Therefore, it is possible to reduce the variation in the reference voltage due to process variation, temperature variation, and power supply voltage variation, and an effect of enhancing radiation resistance is obtained.

[0118] Also, according to the fifth embodiment described above, it is not necessary to prepare a constant current source 31 separately from the transistor M1E.

[0119] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the material, shape, dimensions, number, arrangement location, etc. of each component in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

[0120] In the above-described embodiments, the transistors M11 to M20, M11B to M15B, M11C to M15C, M11D to M16D, and M18 were composed of field-effect transistors, but this is not restrictive. A bipolar transistor may be used instead of the field-effect transistor. In this case, "P-channel" can be read as "PNP type", "N-channel" as "NPN type", "gate" as "base", "source" as "emitter", and "drain" as "collector" for explanation.

Explanation of Reference Numerals

[0121] 1, 1B to 1E Reference voltage circuit 2, 2E Reference voltage generation section 3, 3B to 3E Temperature characteristic correction section M1 Transistor (first field-effect transistor) M1E Transistor (first field-effect transistor) M2 Transistor (second field-effect transistor) M11, M11B to M11D Transistors (first transistor) M12, M12B to M12D Transistors (second transistor) M13, M13B to M13D Transistors (third transistor) M14, M14B to M14D Transistors (fourth transistor) M15, M15B to M15D Transistors (fifth transistor) M16, M16D Transistors (sixth transistor) M17, 17D Transistors (seventh transistor) M18 Transistor (eighth transistor) R1, R1B, R1C Resistors (first resistor) R2 Resistor (second resistor)

Claims

1. A depletion-type first field-effect transistor having a gate electrode containing an n-type impurity, and an enhancement-type second field-effect transistor having a gate electrode containing a p-type impurity and having the same aspect ratio as the first field-effect transistor, a reference voltage generation unit that causes a constant current generated by the first field-effect transistor to flow through the second field-effect transistor to generate a voltage corresponding to the difference between the threshold voltage of the first field-effect transistor and the threshold voltage of the second field-effect transistor between the gate and source of the second field-effect transistor, a first transistor and a second transistor having different aspect ratios, a first resistor having a voltage difference between the gate-source voltage or base-emitter voltage of the first transistor and the second transistor applied across both ends thereof, and a temperature characteristic correction unit having a second resistor connected between the gate of the second field-effect transistor and an output terminal, and through which the current flowing through the first resistor is folded back and supplied. A reference voltage circuit.

2. In the reference voltage circuit according to Claim 1, the temperature characteristic correction unit further includes a third transistor connected in series to the second transistor, a fourth transistor connected in series to the first transistor, and a fifth transistor connected in series to the second resistor, wherein the first transistor and the second transistor are connected in a current mirror configuration, the third transistor and the fourth transistor are connected in a current mirror configuration, the first transistor or the third transistor and the fifth transistor are connected in a current mirror configuration, and the sources or emitters of the first transistor and the second transistor are respectively connected to both ends of the first resistor. A reference voltage circuit.

3. In the reference voltage circuit according to Claim 1, the temperature characteristic correction unit includes a third transistor connected in series to the first transistor, a fourth transistor connected in series to the second transistor, a current source commonly connected to the sources or emitters of the first transistor and the second transistor, a fifth transistor connected in series to the second resistor, and a sixth transistor connected in series to the first resistor. The third transistor and the fourth transistor are connected in a current mirror configuration, The fifth transistor and the sixth transistor are connected in a current mirror configuration, The gates or bases of the first transistor and the second transistor are respectively connected to both ends of the first resistor, A reference voltage circuit.

4. In the reference voltage circuit according to claim 3, The current source is composed of the first field effect transistor with its gate-source connected, It has an eighth transistor that is connected in a current mirror configuration to the third transistor and folds back the current flowing through the third transistor, The current folded back by the eighth transistor is supplied to the second field effect transistor, A reference voltage circuit.

5. In the reference voltage circuit according to any one of claims 1 to 4, At least one of the transistors is composed of a field effect transistor, A reference voltage circuit.

6. In the reference voltage circuit according to any one of claims 1 to 4, At least one of the transistors is composed of a bipolar transistor, A reference voltage circuit.

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