Delay control circuit

Abstract

To provide a delay control circuit that operates a plurality of external devices connected in parallel in a correctly synchronized manner.SOLUTION: An FPGA 30 includes a delay control circuit that delays PWM1, 2, 3 based on Sync1, 2, 3. The delay control circuit includes: a phase difference detection circuit 40 (phase difference detecting unit) that detects a phase difference of the Sync1, 2, 3 (input signals) input from a gate driver SiC 100; a phase difference time measurement circuit 50 (phase difference time measurement unit) that measures a phase difference time of the phase difference detected by the phase difference detection circuit 40; a correction factor integration circuit 60 (integration unit) that calculates an integrated value by adding and subtracting the phase difference time at the previous time to the phase difference time at this time measured by the phase difference time measurement circuit 50; a delay time determination circuit 70 (delay time determination unit) that determines a delay time of the PWM1, 2, 3 (output signals) based on the integrated value calculated by the correction factor integration circuit 60; and a delay circuit 80 (delay unit) that delays the PWM1, 2, 3 based on the determined delay time.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a delay control circuit.

Background Art

[0002] Patent Document 1 discloses a technique of driving external devices to be driven by a gate driver in parallel.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technique of parallel driving as in Patent Document 1, a technique that can correctly synchronize and drive a plurality of externally connected devices in parallel is desired.

[0005] Therefore, the present invention provides a delay control circuit that can correctly synchronize and drive a plurality of externally connected devices in parallel.

Means for Solving the Problems

[0006] The present invention employs the following solutions to solve the above problems. Note that the following solutions and the words in parentheses are merely examples, and the present invention is not limited thereto. Further, the present invention can be an invention including at least one of the invention specific matters shown in the following solutions. Furthermore, elements limiting the invention specific matters can be added to the invention specific matters shown in the following solutions to form a lower concept, and elements limiting the invention specific matters can also be deleted to form a higher concept.

[0007] Solution 1: The delay control circuit of this solution outputs an output signal to each of a plurality of externally connected devices connected in parallel, an input signal based on the output signal is input from each of the externally connected devices, and the output signal is delayed based on the input signal. The delay control circuit includes: a phase difference detection unit that detects a phase difference of the input signal input from each of the externally connected devices; a phase difference time measurement unit that measures a phase difference time of the phase difference detected by the phase difference detection unit; an integration unit that calculates an integrated value by adding and subtracting a previous phase difference time from the current phase difference time measured by the phase difference time measurement unit; a delay time determination unit that determines a delay time of the output signal based on the integrated value calculated by the integration unit; and a delay unit that delays the output signal based on the delay time determined by the delay time determination unit.

[0008] According to this solution, since the output signal is delayed based on the input signal, it is possible to suppress the variation in the phases of the externally connected devices and correctly synchronize and drive the plurality of externally connected devices.

[0009] Solution 2: The delay control circuit of this solution is the delay control circuit according to any of the above solutions, wherein the integration unit multiplies the current phase difference time measured by the phase difference time measurement unit by a predetermined correction rate.

[0010] According to this solution, since the correction rate is used, it is possible to gently synchronize the plurality of externally connected devices.

[0011] Solution 3: The delay control circuit of this solution is the delay control circuit according to any of the above solutions, wherein the phase difference time measurement unit uses a phase synchronization circuit.

[0012] According to this solution, since the phase synchronization circuit is used, it is possible to perform time measurement and signal delay with a resolution higher than the maximum operating frequency of the delay control circuit.

Advantages of the Invention

[0013] According to the present invention, a plurality of externally connected devices can be correctly synchronized and driven in parallel.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the drive circuit 10 of the embodiment. FIG. 1(A) shows an outline of the drive circuit 10, and FIG. 1(B) shows details of the dotted line portion in FIG. 1(A) and the circuit connected thereto. As shown in Fig. 1(A), the drive circuit 10 includes a power supply 11, a control board 12, three-phase power switching devices 13, 14, 15, and three coils 16. The three-phase power switching devices 13, 14, 15 are each composed of two power switching devices shown vertically.

[0016] In the drive circuit 10, the control board 12 operates by the power from the power supply 11, and the control board 12 drives a motor (not shown) by three coils 16 by gate-controlling the three-phase power switching devices 13, 14, 15. Note that although the drive circuit 10 drives a motor, it may be a circuit that drives a device other than the motor.

[0017] The dotted line portion in Fig. 1(A) is usually a single power switching device, but in the case where the current is insufficient, a plurality of power switching devices may be connected in parallel. The delay control circuit of the present embodiment is a circuit used when a plurality of power switching devices are connected in parallel in such a situation. The details of the delay control circuit will be described later.

[0018] As shown in Fig. 1(B), SiC1, SiC2, and SiC3 as power switching devices are connected in parallel. SiC is a power semiconductor using a compound silicon carbide semiconductor.

[0019] SiC1 is connected to the first gate driver 20a, and the first gate driver 20a is connected to an FPGA (Field Programmable Gate Array) 30. SiC2 is connected to the second gate driver 20b, and the second gate driver 20b is connected to the FPGA 30. SiC3 is connected to the third gate driver 20c, and the third gate driver 20c is connected to the FPGA 30.

[0020] PWM is input to the FPGA 30 from the control board 12 (upper side). The FPGA 30 outputs PWM1 to the first gate driver 20a, and Sync1 is input from the first gate driver 20a. The FPGA 30 outputs PWM2 to the second gate driver 20b, and Sync2 is input from the second gate driver 20b. The FPGA 30 outputs PWM3 to the third gate driver 20c, and Sync3 is input from the third gate driver 20c. PWM (Pulse Width Modulation) is a signal for controlling electrical components and the like using rectangular wave pulses. Sync (Synchronization) is a signal for taking the operation timing among various devices (synchronization signal).

[0021] The first gate driver 20a outputs Vgs1 to SiC1, and Vdsps1 is input from SiC1. The second gate driver 20b outputs Vgs2 to SiC2, and Vdsps2 is input from SiC2. The third gate driver 20c outputs Vgs3 to SiC3, and Vdsps3 is input from SiC3. SiC1, SiC2, and SiC3 output Ids1, Ids2, and Ids3 respectively. Vgs is the gate-source voltage. Vdsps is the voltage between the driver source and the power source of the SiC4 terminal device. Ids is the current flowing from the drain to the source.

[0022] Although not particularly shown, Ids1 output by SiC1 is also input to the first gate driver 20a, Ids2 output by SiC2 is also input to the second gate driver 20b, and Ids3 output by SiC3 is also input to the third gate driver 20c. And each gate driver is provided with a Sync detection circuit, and can detect Sync based on Vdsps (the potential difference between the driver source and the power source), Ids, etc. input to the Sync detection circuit, and output Sync1, 2, 3 to the FPGA 30.

[0023] The circuit that transmits PWM to the FPGA 30 and the first gate driver 20a, the second gate driver 20b, and the third gate driver 20c can be implemented as part of the control board 12. On the other hand, the FPGA 30 can be implemented as a function separate from the control board 12. The delay control circuit of this embodiment is incorporated in the FPGA 30.

[0024] Figure 2 is a diagram showing the relationship between Ids and PWM. Figure 2(A) shows the case without control by the delay control circuit, and Figure 2(B) shows the case with control by the delay control circuit. As shown in Figure 2(A), when there is no control by the delay control circuit, PWM is input from the control board 12 to the FPGA 30, and the FPGA 30 outputs PWM1, 2, and 3 to the power switching device at the same timing via the respective gate drivers. In this case, although PWM1, 2, and 3 are output at the same timing, Ids1, 2, and 3 (the current from the power switching device) have waveforms with shifted rising and falling timings. This variation is caused by individual differences in devices, temperature distribution of devices, aging deterioration of devices, etc.

[0025] On the other hand, as shown in Figure 2(B), when there is control by the delay control circuit, PWM is input from the control board 12 to the FPGA 30, and the FPGA 30 outputs PWM1, 2, and 3 to the power switching device at different timings via the respective gate drivers. In this case, although PWM1, 2, and 3 are output at different timings, Ids1, 2, and 3 have waveforms with no shifted rising and falling timings. The reason for this is that the output timings of PWM1, 2, and 3 are delayed based on the variation in Figure 2(A). In the control by the delay control circuit, control is performed to eliminate the variation as shown in Figure 2(A) and adjust the current balance as shown in Figure 2(B). That is, in the control by the delay control circuit, in order to eliminate the variation in current, PWM1, 2, and 3 are forcibly delayed to align the waveforms of Ids1, 2, and 3.

[0026] Figure 3 is a diagram showing the configuration of the power switching device. In this embodiment, a four-terminal power switching device is adopted. As the four-terminal power switching device, for example, SCT3040KR (manufactured by Rohm Co., Ltd.) can be used. The four terminals are drain T1, gate T2, driver source T3, and power source T4. In this embodiment, control is performed based on the potential difference (such as Vdsps) between the driver source T3 and the power source T4.

[0027] Generally, the Ls of the power switching device ranges from several nH to a dozen or so nH. When dI D / dt reaches several A / ns, an electromotive force V L of 10 V or more may be generated. Vdsps is the same signal as V L . By making the "Sync detection circuit" highly sensitive, it becomes possible to detect the initial operation of Id. In this embodiment, in order to match the shunt balance when power switching devices are connected in parallel, each signal is controlled so that the timings of the Vdsps signals match.

[0028] Figure 4 is a diagram showing the configuration of the delay control circuit. The delay control circuit is a circuit for three-parallel feedback control. Note that SiC1, 2, and 3 are vertically displayed for convenience, but in reality, they are connected in parallel (see Figure 1). The FPGA 30 detects the PWM by the detection circuit 91, generates PWM1, 2, and 3 by the first delay circuit 80a, the second delay circuit 80b, and the third delay circuit 80c, and outputs PWM1, 2, and 3 to the first gate driver 20a, the second gate driver 20b, and the third gate driver 20c.

[0029] Also, for the FPGA 30, Sync1, 2, and 3 are input from the first gate driver 20a, the second gate driver 20b, and the third gate driver 20c, and feedback control is performed in the time difference measurement circuit 90, the delay time determination circuit 70, and the three delay circuits (the first delay circuit 80a, the second delay circuit 80b, and the third delay circuit 80c). In the time difference measurement circuit 90, a 250 MHz four-phase shift PLL 51 is used. Also, in the time difference measurement circuit 90, a correction rate (such as 0.25, 0.50, 0.75, 1.00, etc.) can be applied. The correction rate is preferably a value of 1 or less.

[0030] Figure 5 is a diagram showing the timing of each signal of the FPGA. As shown in FIG. 5(A), the waveform of the PWM is a signal output from the control board 12 to the FPGA 30. As shown in FIG. 5(B), the FPGA 30 outputs PWM1, 2, and 3 based on the PWM. As shown in FIG. 5(C), when the FPGA 30 outputs PWM1, 2, and 3, Sync1, 2, and 3 are input to the FPGA 30.

[0031] Then, in the FPGA 30, the time differences of Sync1, 2, and 3 are monitored. The time differences of Sync1, 2, and 3 are reflected in the next PWM1, 2, and 3 (see arrow A1). This is the turn-on side (rising side), and similarly for the turn-off side (falling side), the time differences of Sync1, 2, and 3 are monitored and reflected in the next PWM1, 2, and 3 (see arrow A2).

[0032] When the processes of arrow A1 and arrow A2 are executed, Sync1, 2, and 3 are generally aligned, but there may be some deviation. Therefore, the same process is executed on the next turn-on side. And in this case, the signal is delayed with the sum of the previous delay and the current delay (see arrow A3). This is the same for the turn-off side (see arrow A4). And hereafter, such processes are continuously performed.

[0033] Figure 6 is a diagram showing the details of the delay control circuit. FPGA 30 outputs PWM1, 2, and 3 (output signals) to each gate driver SiC of a plurality of gate drivers SiC100 (external devices) connected in parallel, and Sync1, 2, and 3 (input signals) based on PWM1, 2, and 3 are input from each gate driver SiC. It is provided with a delay control circuit that delays PWM1, 2, and 3 based on Sync1, 2, and 3. Note that three gate drivers SiC100 are connected in parallel. The first one corresponds to the first gate driver 20a and SiC1, the second one corresponds to the second gate driver 20b and SiC2, and the third one corresponds to the third gate driver 20c and SiC3 (see Figure 1).

[0034] The delay control circuit of FPGA 30 includes a phase difference detection circuit 40 (phase difference detection unit), a phase difference time measurement circuit 50 (phase difference time measurement unit), a correction rate integration circuit 60 (integration unit), a delay time determination circuit 70 (delay time determination unit), and a delay circuit 80 (delay unit).

[0035] [(1) Phase difference detection circuit 40] The phase difference detection circuit 40 is a circuit that detects the phase difference of Sync1, 2, and 3 (input signals) input from each gate driver (each external device). Specifically, the phase difference detection circuit 40 detects the phase differences between Sync1 and Sync2, Sync2 and Sync3, and Sync3 and Sync1.

[0036] [(2) Phase difference time measurement circuit 50] The phase difference time measurement circuit 50 is a circuit that measures the phase difference time of the phase difference detected by the phase difference detection circuit 40. Also, it is preferable that the phase difference time measurement circuit 50 uses a PLL (phase-locked loop circuit). Specifically, the phase difference time measurement circuit 50 measures the phase difference with a resolution of 1 ns.

[0037] [(3) Correction rate integration circuit 60] The correction rate integration circuit 60 is a circuit that calculates an integrated value by adding or subtracting the previous phase difference time from the current phase difference time measured by the phase difference time measurement circuit 50. Further, it is preferable that the correction rate integration circuit 60 multiplies the current phase difference time measured by the phase difference time measurement circuit 50 by a predetermined correction rate. Specifically, the correction rate integration circuit 60 multiplies the current measured value by the correction rate and adds or subtracts it from the previous integrated value.

[0038] [(4) Delay time determination circuit 70] The delay time determination circuit 70 is a circuit that determines the delay times of PWM1, 2, 3 (output signals) based on the integrated value calculated by the correction rate integration circuit 60. Specifically, the delay time determination circuit 70 determines the delay times of PWM1, 2, 3 from the integrated value.

[0039] [(5) Delay circuit 80] The delay circuit 80 is a circuit that delays PWM1, 2, 3 based on the delay times determined by the delay time determination circuit 70. Specifically, the delay circuit 80 delays the respective delay times of PWM1, 2, 3 with respect to the PWM input signal.

[0040] PWM1, 2, 3 are output from the FPGA 30 to the gate driver·SiC100 (PWM1 → the first gate driver·SiC1, PWM2 → the second gate driver·SiC2, PWM3 → the third gate driver·SiC3). On the other hand, Sync1, 2, 3 are input from the gate driver·SiC100 to the FPGA 30. Note that the phase difference detection circuit 40, the phase difference time measurement circuit 50, and the correction rate integration circuit 60 correspond to the time difference measurement circuit 90 (see FIG. 1).

[0041] FIG. 7 is a diagram showing the details of the phase difference detection circuit 40. FIG. 7(A) shows the circuit configuration, and FIG. 7(B) shows the timing chart of each signal. As shown in Fig. 7(A), the phase difference detection circuit 40 is a circuit that receives Sync1, Sync2, and the PWM rising edge as inputs and outputs the results of phase detection and signs. Here, Sync1 and Sync2 are described as representatives, but the same applies to Sync2, 3 and Sync3, 1.

[0042] When Sync1 and Sync2 are input to the FPGA 30, Sync1 and Sync2 are input to the clock portions of the flip-flop circuits in the upper and middle stages. Also, the PWM rising edge is input to the flip-flop circuits in the upper and middle stages. Then, data A is output from the flip-flop circuit in the upper stage, data B is output from the flip-flop circuit in the middle stage, and by inputting data A and data B to the exclusive OR circuit, phase detection is performed (phase difference detection).

[0043] Also, Sync1 is input to the clock portion of the flip-flop circuit in the lower stage. Also, the value of data B is inverted by the inverter circuit and input to the flip-flop circuit in the lower stage. Then, a sign is output from the flip-flop circuit in the lower stage.

[0044] As shown in Fig. 7(B), Sync1 and Sync2 with different waveforms are input. In this case, when taking the exclusive OR of data A and data B, only the portion where Sync1 is High (1) and Sync2 is Low (0) becomes High, so this is regarded as the phase detection (the length of AB). Also, the sign is High in the case shown in the figure, which means that Sync1 rises first and Sync2 rises later. Note that when Sync2 rises first and Sync1 rises later, the sign remains Low.

[0045] Fig. 8 is a diagram showing the details of the phase difference time measurement circuit 50. Fig. 8(A) shows the circuit configuration, Fig. 8(B) shows the timing chart of each signal in the first example, and Fig. 8(C) shows the timing chart of each signal in the second example. As shown in Fig. 8(A), the phase difference time measurement circuit 50 is a circuit that receives a phase difference and a clock and outputs a phase difference time. A phase difference (the pulse of phase detection in Fig. 7) is input to the phase difference time measurement circuit 50. Counters 0 to 3 are controlled by CLK0 to CLK3 generated by the PLL 51, and data 0 to data 3 are added by the addition circuit 52 to measure the phase difference time. Also, in the phase difference time measurement circuit 50, a pulse of the phase difference is measured (resolved) in a time of 1 ns using a 4-phase shift PLL 51 of 250 MHz.

[0046] The PLL 51 uses a function (circuit) provided in the FPGA. By using the PLL 51, the clock is increased up to 250 ns and a 4-phase shift is performed. Thereby, a continuous clock waveform at 250 MHz can be generated. CLK0 to CLK3 are waveforms shifted by 90 degrees from each other. CLK1 is shifted by 90 degrees with respect to CLK0, CLK2 is shifted by 90 degrees with respect to CLK1, CLK3 is shifted by 90 degrees with respect to CLK2, and CLK0 is shifted by 90 degrees with respect to CLK3. Since 250 MHz corresponds to 4 ns, a 90-degree shift means that each clock has a shift of 1 ns.

[0047] One grid of the vertical lines shown in Fig. 8(B)(C) corresponds to 1 ns. As shown in Fig. 8(B), assume that the waveform of the phase difference becomes High only for a short time. In this case, since the waveform of the phase difference becomes High only when CLK1 becomes High, the counter 1 corresponding to CLK1 is set to 1. After that, since the waveform of the phase difference becomes Low, this state continues. The values counted by each counter are added by the final addition circuit 52. Thereby, in the example of Fig. 8(B), the phase difference time is 1 (ns).

[0048] As shown in Fig. 8(C), assume that the waveform of the phase difference becomes High over a longer period of time than in Fig. 8(B). In this case, since the waveform of the phase difference is High for all of CLK0 to CLK3, counters 0 to 3 corresponding to CLK0 to CLK3 count respectively. Specifically, counter 0 corresponding to CLK0 counts 4, counter 1 corresponding to CLK1 counts 4, counter 2 corresponding to CLK2 counts 5, and counter 3 corresponding to CLK3 counts 4. After that, since the waveform of the phase difference becomes Low, this state continues. The values counted by each counter are added by the last adder circuit 52. As a result, in the example of Fig. 8(C), the phase difference time is 4 + 4 + 5 + 4 = 17 (ns). Each counter is configured to count up when the input signal is High when the pulse of its own clock becomes High.

[0049] Fig. 9 is a diagram showing details of the correction rate integration circuit 60. Fig. 9(A) shows the circuit configuration, and Fig. 9(B) shows the timing chart of each signal. As shown in Fig. 9(A), the correction rate integration circuit 60 is a circuit that receives a correction rate, a phase difference time, and a sign and outputs an integrated value. The correction rate has the role of delaying the phase difference time gradually instead of delaying it all at once. In the correction rate integration circuit 60, the correction rate and the current phase difference time are multiplied, the current phase difference time is added to or subtracted from the previous phase difference time, and the sign is added to output the integrated value.

[0050] For example, as shown in Fig. 9(B), PWM1, 2, and 3 are output. PWM1, 2, and 3 are in the initial state without delay. Here, the correction rate = 1 is used for explanation. On the other hand, Sync1, 2, and 3 are input with a shift as shown in the figure.

[0051] In this case, the phase difference time is as follows. (Sync1 → Sync2): Phase difference time of Sync2 as seen from Sync1: +3 (Sync2 → Sync3): Phase difference time of Sync3 as seen from Sync2: +1 (Sync3→Sync1): Phase difference time of Sync1 as seen from Sync3: -4

[0052] And in order to reflect the deviation of each Sync in the following PWM1, 2, 3, since it is difficult to speed up the slower Sync, the faster Sync is slowed down. In the illustrated example, since Sync3 is the slowest, Sync1 and 2 are adjusted to Sync3. Specifically, the PWM1 corresponding to Sync1 is delayed by 4, and the PWM2 corresponding to Sync2 is delayed by 1. The PWM3 corresponding to Sync3 remains unchanged. Then, in response to the result of delaying each PWM, the next Sync1, 2, 3 are input again.

[0053] In this case, the phase difference time is as follows. (Sync1→Sync2): Phase difference time of Sync2 as seen from Sync1: +2 (Sync2→Sync3): Phase difference time of Sync3 as seen from Sync2: -1 (Sync3→Sync1): Phase difference time of Sync1 as seen from Sync3: -1

[0054] In this case, the integrated value of (Sync1→Sync2) is 5 (=3 + 2), the integrated value of (Sync2→Sync3) is 0 (=1 - 1), and the integrated value of (Sync3→Sync1) is -5 (= -4 - 1).

[0055] Figure 10 is a diagram showing a part of the function of the correction rate integration circuit 60. Figure 10(A) shows a part of the circuit of the correction rate integration circuit 60, and Figure 10(B) shows the timing chart of each signal and the values of various data. As shown in FIG. 10(A), the addition / subtraction circuit receives the data A, the sign, and the value output from the flip-flop circuit (FF), and outputs the value obtained by adding and subtracting the value obtained by reflecting the sign on the data A and the value output from the flip-flop circuit. Further, the flip-flop circuit receives the value output from the addition / subtraction circuit and the CLK, outputs the value output from the addition / subtraction circuit as an integrated value, and outputs the value output from the addition / subtraction circuit to the addition / subtraction circuit. Note that the data A is the data obtained by multiplying the correction rate in FIG. 9 by the current phase difference time.

[0056] As shown in FIG. 10(B), the initial value of the data A is "0", the initial value of the sign is "+ (for example, 0)", and the initial value of the integrated value is "0". Also, for the data A and the sign, different values are input as time passes. Then, when the CLK is input to the flip-flop circuit, an operation is performed in the addition / subtraction circuit, and the integrated value is output from the flip-flop circuit. Examples of the output of the integrated value are as follows.

[0057] At the first rising edge of the CLK, since the data A is "0" and the sign is "+", the integrated value is output as "0 (0 + 0 = 0)". At the second rising edge of the CLK, since the data A is "2" and the sign is "+", the integrated value is output as "2 (0 + 2 = 2)". At the third rising edge of the CLK, since the data A is "1" and the sign is "+", the integrated value is output as "3 (2 + 1 = 3)". At the fourth rising edge of the CLK, since the data A is "2" and the sign is "- (for example, 1)", the integrated value is output as "1 (3 - 2 = 1)".

[0058] At the fifth rising edge of the CLK, since the data A is "1" and the sign is "+", the integrated value is output as "2 (1 + 1 = 2)". At the sixth rising edge of the CLK, since the data A is "2" and the sign is "-", the integrated value is output as "0 (2 - 2 = 0)". At the seventh rising edge of the CLK, since the data A is "1" and the sign is "-", the integrated value is output as "-1 (0 - 1 = -1)". At the eighth rising edge of the CLK, since the data A is "2" and the sign is "+", the integrated value is output as "1 (-1 + 2 = 1)". In this way, in the correction rate integration circuit 60, the previous phase difference time is held using a flip-flop circuit.

[0059] FIG. 11 is a diagram showing the details of the delay time determination circuit 70. FIG. 11(A) shows the circuit configuration, and FIG. 11(B) shows a specific calculation example. As shown in FIG. 11(A), the delay time determination circuit 70 is a circuit that receives the integrated values of (Sync1 → Sync2), (Sync2 → Sync3), and (Sync3 → Sync1) and outputs the PWM1 delay time, PWM2 delay time, and PWM3 delay time.

[0060] In the delay time determination circuit 70, first, the sign of the integrated value is inverted. Next, the positive value remains as the positive value, and the negative value is converted to 0. Finally, the values are compared and the larger value is output, which is used as the delay time for each PWM.

[0061] As shown in FIG. 11(B), for example, the integrated value of (Sync1 → Sync2) is 5, the integrated value of (Sync2 → Sync3) is 0, and the integrated value of (Sync3 → Sync1) is -5. By inverting the plus / minus sign, the integrated value of (Sync1 → Sync3) becomes 5, the integrated value of (Sync2 → Sync1) becomes -5, and the integrated value of (Sync3 → Sync2) becomes 0.

[0062] Next, when the previous integrated values are processed such that the positive value remains as the positive value and the negative value is converted to 0, the following results are obtained. (Sync1 → Sync2): Sync2 seen from Sync1: 5 → 5 (Sync1 → Sync3): Sync3 seen from Sync1: 5 → 5 (Sync2→Sync1): Sync1 as seen from Sync2: -5 → 0 (Sync2→Sync3): Sync3 as seen from Sync2: 0 → 0 (Sync3→Sync1): Sync1 as seen from Sync3: -5 → 0 (Sync3→Sync2): Sync2 as seen from Sync3: 0 → 0

[0063] And finally, when a comparison is made and the larger value is output, the delay time is as follows. The reason for setting negative values to 0 and selecting the larger value is to align the remaining Syncs with the slowest Sync. PWM1 delay time: 5 PWM2 delay time: 0 PWM3 delay time: 0

[0064] Figure 12 is a diagram showing the concept of the processing content (in the case of two Syncs) of the delay time determination circuit 70. For example, assume that Sync1 and Sync2 with waveforms as shown in Figure 12(A) are input to the FPGA 30. (1) Sync1 is 5 steps ahead of Sync2 (Sync1→Sync2: 5). In this situation, to align Sync1 and Sync2, PWM1 needs to be delayed by 5 compared to PWM2. (2) On the other hand, Sync2 is 5 steps behind Sync1 (Sync2→Sync1: -5). In this situation, to align Sync1 and Sync2, PWM2 needs to be advanced by 5 compared to PWM1.

[0065] (3) Even if both (1) and (2) are executed, only Sync1 and Sync2 will be swapped, so it is necessary to execute either (1) or (2). However, since it is difficult to advance PWM2 in (2), this is not executed, and the process of delaying PWM1 in (1) is executed. As a result, the delay time of PWM1 = 5 and the delay time of PWM2 = 0. Then, as shown in FIG. 12(B), PWM1 is delayed by 5 and PWM2 remains unchanged (PWM2 is not delayed). Setting the negative value to 0 in FIG. 11 means leaving the PWM unchanged (not delaying it).

[0066] FIG. 13 is a diagram showing the concept of the processing content of the delay time determination circuit 70 (in the case of three Syncs). For example, assume that Sync1, Sync2, and Sync3 with waveforms as shown in FIG. 13(A) are input to the FPGA 30. Here, Sync2 and Sync3 are delayed by the same amount of time with respect to Sync1. The relationship of each Sync is as follows. (Sync1→Sync2): Sync2 as seen from Sync1: 5 (Sync1→Sync3): Sync3 as seen from Sync1: 5 (Sync2→Sync1): Sync1 as seen from Sync2: -5 (Sync2→Sync3): Sync3 as seen from Sync2: 0 (Sync3→Sync1): Sync1 as seen from Sync3: -5 (Sync3→Sync2): Sync2 as seen from Sync3: 0

[0067] The relationship of each PWM is as follows. (PWM1→PWM2): PWM2 as seen from PWM1: -5 (PWM1→PWM3): PWM3 as seen from PWM1: -5 (PWM2→PWM1): PWM1 as seen from PWM2: 5 (PWM2→PWM3): PWM3 as seen from PWM2: 0 (PWM3→PWM1): PWM1 as seen from PWM3: 5 (PWM3→PWM2): PWM2 as seen from PWM3: 0

[0068] From these relationships, assume that the delay time of PWM1 = 5, the delay time of PWM2 = 0, and the delay time of PWM3 = 0. Then, PWM1 is delayed by 5, while PWM2 and PWM3 remain unchanged (PWM2 and 3 are not delayed).

[0069] Also, for example, assume that waveforms Sync1, Sync2, and Sync3 as shown in FIG. 13(B) are input to FPGA 30. Here, Sync2 and Sync3 are delayed from Sync1 by different times. The relationship of each Sync is as follows. (Sync1→Sync2): Sync2 as seen from Sync1: 5 (Sync1→Sync3): Sync3 as seen from Sync1: 5 (Sync2→Sync1): Sync1 as seen from Sync2: -5 (Sync2→Sync3): Sync3 as seen from Sync2: -2 (Sync3→Sync1): Sync1 as seen from Sync3: -3 (Sync3→Sync2): Sync2 as seen from Sync3: -2

[0070] The relationship of each PWM is as follows. (PWM1→PWM2): PWM2 as seen from PWM1: -5 (PWM1→PWM3): PWM3 as seen from PWM1: -3 (PWM2→PWM1): PWM1 as seen from PWM2: 5 (PWM2→PWM3): PWM3 as seen from PWM2: 2 (PWM3→PWM1): PWM1 as seen from PWM3: 3 (PWM3→PWM2): PWM2 as seen from PWM3: -2

[0071] From these relationships, assume that the delay time of PWM1 = 5, the delay time of PWM2 = 0, and the delay time of PWM3 = 2. Then, PWM1 is delayed by 5, PWM2 remains unchanged (PWM2 is not delayed), and PWM3 is delayed by 2.

[0072] FIG. 14 is a diagram showing the details of the delay circuit 80. The delay circuit 80 is a circuit that receives PWM, CLK0 to 3, and the PWM1 delay time as inputs and outputs PWM1. The delay circuit 80 includes a PWM rising delay circuit 81 and a PWM falling delay circuit 82, and the output results of both circuits are latched (combined) and output. The difference between the PWM rising delay circuit 81 and the PWM falling delay circuit 82 is that only the PWM rising CLK selection is changed to the PWM falling CLK selection, so the detailed description of the PWM falling delay circuit 82 is omitted. Also, the illustrated circuit is the delay circuit 80 for PWM1, but there are also delay circuits 80 for PWM2 and delay circuits 80 for PWM3. Note that for the delay circuit 80 for PWM2 and the delay circuit 80 for PWM3, only the PWM1 part of the illustrated circuit is changed to PWM2 or PWM3, so the detailed description is omitted.

[0073] In the upper circuit of the PWM rising delay circuit 81, PWM and CLK0 to 3 are input to the PWM rising CLK selection circuit to detect the rising edge of PWM. The PWM rising CLK selection circuit selects the clock (CLK0 / CLK1 / CLK2 / CLK3) to which the PWM signal first responds. Then, the detection result is encoded and added to the lower 2 bits of the delay time to form the address of the multiplexer.

[0074] In the lower circuit of the PWM rising delay circuit 81, the edge of PWM is detected by edge detectors 0 to 3, the upper 2 bits of the PWM1 delay time are used to rotate counters 0 to 3, and the edge of the carry signal thereof is detected by edge detectors 0 to 3 to output a pulse to the multiplexer. It is the upper circuit that determines which of the pulses output to the multiplexer is selected. The rising pulse output from the multiplexer is latched with the falling pulse output from the multiplexer of the falling delay circuit, and finally, PWM1 with the reflected delay time is output.

[0075] Figure 15 is a diagram showing a simplified delay circuit 80 of Figure 14. In the PWM detection circuit for each clock, a PWM signal is detected by each clock. In the multiplexer address calculation circuit, the address of the multiplexer is calculated. In the PWM delay circuit for each clock, pulses are output to the multiplexer based on each clock.

[0076] Then, the delay circuit 80 latches the rising pulse output from the multiplexer and the falling pulse output from the multiplexer of the PWM falling delay circuit, and outputs PWM1 with the delay time reflected. Note that the upper circuit in the PWM rising delay circuit 81 in FIG. 14 corresponds to the PWM detection circuit and the multiplexer address calculation circuit for each clock in FIG. 15, and the lower circuit in the PWM rising delay circuit 81 in FIG. 14 corresponds to the PWM delay circuit and the multiplexer for each clock in FIG. 15.

[0077] FIG. 16 is a sequence diagram when PWM is detected by CLK1 in the delay circuit 80. In the illustrated example, after PWM rises, CLK1 rises first. Then, the delay time is determined based on the clock (CLK1 in this example) that first detects the PWM signal.

[0078] When the counter counts 1 (the output value when the counter is set to 1) is as follows. Counter 0_1 count carry: Delay 3 ns Counter 1_1 count carry: Delay 0 ns Counter 2_1 count carry: Delay 1 ns Counter 3_1 count carry: Delay 2 ns

[0079] When the counter counts 2 (the output value when the counter is set to 2) is as follows. Note that when a delay of 8 ns or more is desired, counters 3 and above are used. Counter 0_2 count carry: Delay 7 ns Counter 1_2 count carry: Delay 4 ns Counter 2_2 Count Carry: Delay 5 ns Counter 3_2 Count Carry: Delay 6 ns

[0080] When the result of the delay time determination is PWM1 delay time = 5 ns, PWM2 delay time = 0 ns, and PWM3 delay time = 0 ns, for the PWM1 delay time = 5 ns, PWM1 is delayed and output until it corresponds to "Counter 2_2 Count Carry: Delay 5 ns". Also, for the PWM2 delay time = 0 ns and PWM3 delay time = 0 ns, PWM2 and PWM3 are output at the timing corresponding to "Counter 1_1 Count Carry: Delay 0 ns".

[0081] Note that the timing of the reference "Counter 1_1 Count Carry: Delay 0 ns" can be the timing delayed by 4 ns × N (N is an integer of 1 or more) from the timing when CLK1 detects PWM, although it also depends on the processing time of the circuit.

[0082] Figure 17 is a sequence diagram when PWM is detected by CLK2 in the delay circuit 80. In the illustrated example, after PWM rises, first CLK2 rises. And the delay time is determined based on the clock that first detects the PWM signal (CLK2 in this example).

[0083] When the counter counts 1, it is as follows. Counter 0_1 Count Carry: Delay 2 ns Counter 1_1 Count Carry: Delay 3 ns Counter 2_1 Count Carry: Delay 0 ns Counter 3_1 Count Carry: Delay 1 ns

[0084] When the counter counts 2, it is as follows. Counter 0_2 Count Carry: Delay 6 ns Counter 1_2 Count Carry: Delay 7 ns Counter 2_2 Count Carry: Delay 4 ns Counter 3_2 Count Carry: Delay 5 ns

[0085] When the result of the delay time determination is PWM1 delay time = 5 ns, PWM2 delay time = 0 ns, and PWM3 delay time = 0 ns, for the PWM1 delay time = 5 ns, PWM1 is delayed and output until it corresponds to "Counter 3_2 Count Carry: Delay 5 ns". Also, for the PWM2 delay time = 0 ns and PWM3 delay time = 0 ns, PWM2 and PWM3 are output at the point corresponding to "Counter 2_1 Count Carry: Delay 0 ns".

[0086] Note that the timing of the reference "Counter 2_1 Count Carry: Delay 0 ns" depends on the processing time of the circuit, but it can be set to the timing delayed by 4 ns × N (N is an integer of 1 or more) from the timing when CLK2 detects PWM.

[0087] Figure 18 is a diagram showing the details of the PWM rising edge CLK selection circuit. Note that the PWM falling edge CLK selection circuit is omitted because only the rising edge processing is changed to the falling edge processing. The PWM rising edge CLK selection circuit is a circuit that receives PWM and CLR (clear signal) as inputs and outputs SC0 to SC3. The PWM rising edge CLK selection circuit includes a flip-flop circuit, an AND circuit, an OR circuit, etc. It latches with each CLK, and after latching, it executes processing by a predetermined logic (for example, AND of the inversions of CLK0 and CLK3), and outputs with SC0 to 3 which CLK latched the rising edge of PWM based on PWM and CLK0 to 3.

[0088] CKL0 corresponds to SC0, CKL1 corresponds to SC1, CKL2 corresponds to SC2, and CKL3 corresponds to SC3. For example, when PWM is latched with CLK1, SC1 corresponding to CLK1 becomes High.

[0089] Figure 19 is a diagram showing each signal related to the PWM rising edge CLK selection circuit. CLK0 to CLK3 are displayed in the upper part of the figure, and the vertical dotted line corresponds to 1 ns. When PWM is input to FPGA30, it is latched by CLK0 to CLK3. Then, the output values of (1) to (4) and SC0 to SC3 become the values shown in the figure. For example, in the waveforms of (1) to (4) of the PWM rising edge CLK selection circuit, only (2) rises to High for a moment. This is because (2) becomes High when the CLK1 latch is High and the CLK0 latch is Low. On the other hand, in the case of CLK1 and CLK2, since the CLK2 latch is always High and there is no case where the CLK1 latch is Low, it is always Low. The same applies to other CLKs.

[0090] And, although it is desired to hold the rising state of (2), the timing for holding is when (2) falls and SC1 is set to High. "SC1 = High (1)" means that the CLK1 corresponding to SC1 first detects PWM. Note that although the circuit actually operates at 250 MHz, in order to operate it normally, it is preferable to ensure a frequency band of at least 333 MHz (= 250 MHz × 4 / 3) considering a certain margin, etc.

[0091] Figure 20 is a diagram showing the actual signals related to the PWM rising edge CLK selection circuit. The signals shown in Figure 19 are ideal graphs. In flip - flops and other circuits, data is output at the same timing with respect to the clock, but in reality, delays occur. Therefore, the actual waveform becomes the waveform shown by the solid line in Figure 20. And even with such a waveform, in the PWM rising edge CLK selection circuit of Figure 18, data can be output as "SC1 = High (1)" without problems. Note that since the FPGA of this embodiment operates at 500 MHz, the delay is considered to be 2 ns or less. Even if such a delay occurs, only SC1 can be correctly set to High.

[0092] Figure 21 is a conceptual diagram showing part of the processing content of the delay circuit 80. The delay circuit 80 encodes SC0~3. The content of the encoded value is as follows. SC0 = 1, SC1 = 0, SC2 = 0, SC3 = 0 → Encoded value 00 SC0 = 0, SC1 = 1, SC2 = 0, SC3 = 0 → Encoded value 01 SC0 = 0, SC1 = 0, SC2 = 1, SC3 = 0 → Encoded value 10 SC0 = 0, SC1 = 0, SC2 = 0, SC3 = 1 → Encoded value 11

[0093] The delay circuit 80 converts the delay time into a binary value. Specifically, it is as follows. Delay time 0ns → 0000 Delay time 1ns → 0001 Delay time 2ns → 0010 Delay time 3ns → 0011 Delay time 4ns → 0100 Delay time 5ns → 0101 Delay time 6ns → 0110 Delay time 7ns → 0111

[0094] The delay circuit 80 adds the lower 2 bits of the binary delay time and the encoded value to obtain the address of the multiplexer. Also, the delay circuit 80 adds the upper 2 bits (bits other than the lower 2 bits) of the binary delay time and the fixed value "01" to obtain the counter data. The fixed value is a predefined value, and it is set to "01" to increment the counter at least once.

[0095] For example, when looking at the case where the delay time is 0ns, the address of the multiplexer is 01 and the counter is 01, so it corresponds to the location of counter 1-1 (see Figure 16). Also, for example, when looking at the case where the delay time is 5ns, the address of the multiplexer is 10 and the counter is 10, so it corresponds to the location of counter 2-2 (see Figure 16).

[0096] The reason for splitting the upper bits and the lower bits is that the clock has a 4n cycle at 250 MHz, and 4n is equivalent to 2 to the power of 2. Considering 4n as the reference, a decimal point will be in the second digit position. Then, it determines which address to select in the decimal part and determines the counter data in the integer part.

[0097] Figure 22 is a diagram showing the circuit configuration of an FPGA with 3 - parallel feedback control. As the phase - difference detection circuits, there are a first phase - difference detection circuit 40a, a second phase - difference detection circuit 40b, and a third phase - difference detection circuit 40c. As the phase - difference time measurement circuits, there are a first phase - difference time measurement circuit 50a, a second phase - difference time measurement circuit 50b, and a third phase - difference time measurement circuit 50c. As the correction rate integration circuits, there are a first correction rate integration circuit 60a, a second correction rate integration circuit 60b, and a correction rate integration circuit 60c. There is only one delay time determination circuit 70 provided. As the delay circuits, there are a first delay circuit 80a, a second delay circuit 80b, and a third delay circuit 80c.

[0098] In the FPGA 30 with 3 - parallel feedback control, in phase - difference detection, the phase - differences are detected between Sync1 and Sync2, Sync2 and Sync3, and Sync3 and Sync1, the respective phase - difference times are measured, correction rate integration is performed, the delay time is determined by the delay time determination circuit 70, and finally, PWM1, 2, and 3 are output by the individual delay circuits. PWM1 is output to the first gate driver · SiC1_101, PWM2 is output to the second gate driver · SiC2_102, and PWM3 is output to the third gate driver · SiC3_103.

[0099] Figure 23 is a diagram showing the circuit configuration of an FPGA with 2 - parallel feedback control. As the phase - difference detection circuit, there is a first phase - difference detection circuit 40a. As the phase - difference time measurement circuit, there is a first phase - difference time measurement circuit 50a. As the correction rate integration circuit, there is a first correction rate integration circuit 60a. Only one delay time determination circuit 70 is provided. As the delay circuits, there are a first delay circuit 80a and a second delay circuit 80b.

[0100] In the 2-parallel feedback control FPGA 30, in phase difference detection, the phase difference is detected between Sync1 and Sync2, the phase difference time is measured, correction rate integration is performed, the delay time is determined by the delay time determination circuit 70, and finally PWM is output by the individual delay circuits. PWM1 is output to the first gate driver SiC1_101, and PWM2 is output to the second gate driver SiC2_102.

[0101] Figure 24 is a diagram showing the circuit configuration of the multi-parallel feedback control FPGA. As the phase difference detection circuits, there are a first phase difference detection circuit 40a, a second phase difference detection circuit 40b, a third phase difference detection circuit 40c,..., an nth phase difference detection circuit 40n. As the phase difference time measurement circuits, there are a first phase difference time measurement circuit 50a, a second phase difference time measurement circuit 50b, a third phase difference time measurement circuit 50c,..., an nth phase difference time measurement circuit 50n. As the correction rate integration circuits, there are a first correction rate integration circuit 60a, a second correction rate integration circuit 60b, a correction rate integration circuit 60c,..., a correction rate integration circuit 60n. Only one delay time determination circuit 70 is provided. As the delay circuits, there are a first delay circuit 80a, a second delay circuit 80b, a third delay circuit 80c,..., an nth delay circuit 80n.

[0102] In the multi-parallel feedback control FPGA 30, in phase difference detection, the phase difference is detected between Sync1 and Sync2, Sync2 and Sync3, Syncn - 1 and Syncn, Syncn and Sync1, the respective phase difference times are measured, correction rate integration is performed, the delay time is determined by the delay time determination circuit 70, and finally PWM is output by the individual delay circuits. PWM1 is output to the first gate driver, SiC1_101, PWM2 is output to the second gate driver, SiC2_102, PWM3 is output to the third gate driver, SiC3_103, and PWMn is output to the nth gate driver, SiCn_100n.

[0103] FIG. 25 is a diagram showing a modified example of the phase difference time measurement circuit 50. As shown in FIG. 25, the phase difference time measurement circuit 50A is a circuit that receives a phase difference and a clock and outputs a phase difference time. The phase difference time measurement circuit 50A receives a phase difference (the pulse of the phase detection in FIG. 7), controls counters 0 to 7 with CLK0 to CLK7 generated by the PLL 51A, and adds data 0 to data 7 in the addition circuit 52A to measure the phase difference time. Further, in the phase difference time measurement circuit 50A, a phase difference pulse is measured (resolved) in a time of 0.5 ns using an 8-phase shift PLL 51A of 250 MHz. As a result, the resolution of the phase difference time measurement circuit 50A can be set to 0.5 ns, which is twice that of FIG. 8.

[0104] FIG. 26 is a diagram showing the configuration of the operation evaluation circuit for three-parallel feedback control. The FPGA 30 shown on the left side in the figure has the same configuration as that in FIG. 4. The FPGA delay jig 200 shown on the right side in the figure is a jig for evaluating the FPGA 30. The FPGA delay jig 200 includes a first delay circuit 201a, a second delay circuit 201b, a third delay circuit 201c, and a PLL 202.

[0105] The first delay circuit 201a is a circuit that receives PWM1 and outputs Vdsps1 delayed by a first delay time that can be arbitrarily set by a switch or the like. The second delay circuit 201b is a circuit that receives PWM2 and outputs Vdsps2 delayed by a second delay time that can be arbitrarily set by a switch or the like. The third delay circuit 201c is a circuit that receives PWM3 and outputs Vdsps3 delayed by a third delay time that can be arbitrarily set by a switch or the like. The first delay circuit 201a, the second delay circuit 201b, and the third delay circuit 201c can each set a delay time. The setting range is 0 to 63 ns in 1 ns units. The PLL 202 receives a 100 MHz clock and operates with a 250 MHz four-phase shift.

[0106] Vdsps 1 to 3 are converted by the FPGA delay jig 200 to Sync 1 to 3 and input to the FPGA 30. PWM 1 to 3 and Sync 1 to 3 are measured with an oscilloscope.

[0107] Figure 27 is a diagram showing an overview of the correction rate process. As shown in Figure 27(A), the phase difference time (delay time change amount) can be made into the corrected phase difference time (control delay time) by integrating the correction rate.

[0108] For example, as shown in Figure 27(B), there are Sync 1 and Sync 2 at the same timing, and if one of the Sync 2 is 10 delayed from Sync 1, the phase difference time is 10 ns. When the correction rate is 1.0, subsequent calculations are advanced based on this 10 ns, but when the correction rate is 0.5, subsequent calculations are advanced based on 5 ns obtained by multiplying this 10 ns by the correction rate.

[0109] Therefore, as shown in Figure 27(C), assuming that the phase difference time decreases by half over time from 10 ns, when the correction rate is 0.5, the corrected phase difference time can gradually decrease the control amount (corrected phase difference time) such as "5 ns (= 10 ns × 0.5)" → "2.5 ns (= 5 ns × 0.5)" → "1.25 ns (= 2.5 ns × 0.5)".

[0110] Figure 28 is a diagram showing the measurement results when the correction rate is 1.0. The delay times in the FPGA delay jig 200 are set to PWM1: 0 ns, PWM2: 16 ns, and PWM3: 32 ns. The delay time is set only once at the start of a plurality of pulses. Then, at the rising edge of the first pulse, Sync2 is significantly delayed with respect to Sync1, and Sync3 is significantly delayed with respect to Sync2 as seen from Sync1. However, with this delay, delay control of PWM1 to 3 is performed. Specifically, PWM1 and 2 are delayed so as to align with PWM3 corresponding to the most delayed Sync3 (see arrow B1).

[0111] At the rising edge of the second pulse, Sync1 to 3 are almost aligned. However, since there is some deviation, delay control of PWM1 to 3 is performed to adjust for the deviation (see arrow B2).

[0112] At the rising edge of the third pulse, Sync1 to 3 are almost aligned. However, since there is some deviation, delay control of PWM1 to 3 is performed to adjust for the deviation. In this way, with a correction rate of 1.0, the deviation of Sync1 to 3 is generally eliminated by the third pulse rising edge.

[0113] Figure 29 is a diagram showing the measurement results when the correction rate is 0.5. The measurement conditions other than the correction rate are the same as those in Figure 28. When the correction rate is 0.5, at the rising edge of the first pulse, Sync2 is significantly delayed with respect to Sync1, and Sync3 is significantly delayed with respect to Sync2 as seen from Sync1. With this delay, delay control of PWM1 to 3 is performed. Specifically, PWM1 and 2 are delayed so as to align with PWM3 corresponding to the most delayed Sync3 (see arrow C1).

[0114] At the rising edge of the second pulse, Sync2 is delayed with respect to Sync1, and Sync3 is delayed with respect to Sync2. With this delay, delay control of PWM1 to 3 is performed. Specifically, PWM1 and 2 are delayed so as to align with PWM3 corresponding to the most delayed Sync3 (see arrow C2).

[0115] In the rising edge of the 3rd pulse, Sync2 lags slightly behind Sync1 as seen from Sync1, and Sync3 lags slightly behind Sync2 as seen from Sync2. Based on this delay, the delay control of PWM1 - 3 is performed. Specifically, PWM1 and 2 are delayed so as to align with PWM3 which is the most delayed (see arrow C3).

[0116] In the rising edge of the 4th pulse, Sync2 lags slightly behind Sync1 as seen from Sync1, and Sync3 lags slightly behind Sync2 as seen from Sync2. Based on this delay, the delay control of PWM1 - 3 is performed. Specifically, PWM1 and 2 are delayed so as to align with PWM3 which is the most delayed (see arrow C4).

[0117] In the rising edge of the 5th pulse, Sync1 - 3 are almost aligned. However, since there is a slight deviation, the delay control of PWM1 - 3 is performed to adjust the slight deviation. In this way, with a correction rate of 0.5, the deviation of Sync1 - 3 is gradually eliminated by the 5th pulse rising edge. In this way, when the value of the correction rate is decreased, it takes time for the Sync to align, but the Sync can be gradually aligned slowly.

[0118] Figure 30 is a diagram showing the measurement results of jitter. Here, each signal is overwritten based on PWM1, and the jitter is measured. As shown in Figure 30(A), when the correction rate = 1.0, a deviation of 5 ns occurs as jitter. On the other hand, as shown in Figure 30(B), when the correction rate = 0.5, a deviation of 2.5 ns occurs as jitter.

[0119] In this way, when the correction rate is decreased, the width of the jitter becomes smaller. This indicates that there are variations in the circuit, and if direct control is applied to it, it will be controlled in the wrong direction and that will be amplified. And such an increase in the width of the jitter can be prevented by setting the correction rate. Therefore, even when there are large changes (even when the phase difference time is large), by changing it little by little (by decreasing the phase difference time little by little), the width of the jitter can be decreased.

[0120] The correction rate may be a predetermined fixed value, or it may be a variable value that increases the correction rate at the start of control and decreases the correction rate as the control becomes stable. Also, in some cases, the correction rate may be decreased at the start of control and increased as the control becomes stable.

[0121] FIG. 31 is a diagram showing the configuration of the correction limiter. The circuit configuration is basically the same as that in FIG. 26, but the delay time determination circuit 70 has the function of setting the correction limiter. The correction limiter is a limiter that determines the maximum value of the delay time. The correction limiter can be a fixed value (for example, 15 ns, etc.). And here, the FPGA delay jig 200 delays Sync1 by 32 ns for evaluation.

[0122] FIG. 32 is a diagram showing the measurement results of the correction limiter. In FIG. 32, only Sync1 and 2 are displayed for PWM1, 2, and 3. At the timing of No.0, Sync1 has a delay of 0, and at the timing of No.1, Sync1 is forcibly delayed by 32 ns using the FPGA delay jig 200.

[0123] FIG. 33 is a diagram showing the details of the measurement results of the correction limiter. At the timing of No.0, Sync1 has a delay of 0. In this case, PWM1, 2, and 3 are aligned. Sync1 is delayed by 40 ns with respect to PWM1 due to internal processing, etc. At timing No.1, Sync1 is forced to be delayed by 32 ns. Specifically, it becomes 40 ns + 32 ns, and Sync1 is delayed by 72 ns with respect to PWM1. At this point, PWM1, 2, and 3 are aligned.

[0124] At timing No.2, the correction limiter is in a controlled state. Normally, in order to align Sync2 with the delayed Sync1, it would be desirable to significantly delay PWM2 and 3 (by 16 ns or more), but due to the correction limiter, PWM2 and 3 are only delayed by a maximum of 15 ns. Similarly, at timing No.3, the correction limiter is in a controlled state. For this reason, PWM2 and 3 are only delayed by a maximum of 15 ns. By using the function of such a correction limiter, rapid changes in PWM1, 2, and 3 can be avoided.

[0125] As described above, according to this embodiment, there are the following effects. (1) Since the operating frequency of FPGA30 is up to several hundred MHz, the resolution of time measurement is several nanoseconds. Therefore, it is difficult to measure time with a resolution higher than the operating frequency (less than 4 ns). Thus, in this embodiment, a circuit configuration using a PLL can provide a circuit that improves the resolution (a circuit capable of measuring time with a 1 - nsec resolution).

[0126] (2) Since the operating frequency of FPGA30 is up to several hundred MHz, the time unit of signal delay is several nanoseconds. Therefore, it is difficult to ensure a time unit of signal delay higher than the operating frequency (less than 4 ns). Thus, in this embodiment, a circuit configuration using a PLL can provide a circuit that improves the time unit of signal delay (a circuit capable of delaying a signal (PWM) in 1 - nsec units).

[0127] (3) According to this embodiment, since PWM1, 2, 3 (output signals) are delayed based on Sync1, 2, 3 (input signals), the phase variation of the gate driver SiC can be suppressed, and the gate driver SiC (a plurality of external devices) can be correctly synchronized and driven.

[0128] (4) According to this embodiment, since the correction rate is used, the gate driver SiC (a plurality of external devices) can be gently synchronized.

[0129] (5) According to this embodiment, since the PLL (phase-locked loop) is used, time measurement and signal delay with a resolution higher than the maximum operating frequency of the delay control circuit (4 ns) (resolution of 1 ns or less) are possible.

[0130] 〔Modifications〕 The present invention can be variously modified and implemented without being limited to the above-described embodiments. (1) The output signal is described by way of example of PWM1, 2, 3, but it may be other signals. The input signal is described by way of example of Sync1, 2, 3, but it may be other signals. (2) The correction rate and correction limiter may not be adopted.

[0131] (3) The phase difference time measurement unit may not use a phase-locked loop. (4) SiC is described by way of example of a four-terminal device, but it may be a three-terminal device. When the terminal of the driver source T3 is missing in the three-terminal device, a shunt resistor can be arranged next to the coil 16 or the motor, and a waveform (input signal) replacing Sync can be output to the FPGA from the waveform of the shunt resistor.

[0132] (5) Although there are parts where the description is omitted among the rising edge, falling edge, PWM1, 2, 3, Sync1, 2, 3, the control content of one process can be changed and diverted to the control content suitable for another process.

[0133] (6) In addition, the structures and circuit configurations illustrated in the embodiments are merely preferred examples, and various elements can be added to the basic structure, some configurations can be replaced, or some configurations can be deleted.

Description of Reference Numerals

[0134] 10 Drive circuit 11 Power supply 12 Control board 13, 14, 15 Power switching device 16 Coil 20a First gate driver 20b Second gate driver 20c Third gate driver 30 FPGA 40 Phase difference detection circuit 50 Phase difference time measurement circuit 51 PLL 60 Correction rate integration circuit 70 Delay time determination circuit 80 Delay circuit 90 Time difference measurement circuit 91 Detection circuit 100 Gate driver·SiC

Claims

1. A delay control circuit that outputs an output signal to each of a plurality of externally connected external devices, receives an input signal based on the output signal from each of the external devices, and delays the output signal based on the input signal, comprising: a phase difference detection unit that detects a phase difference of the input signal input from each of the external devices; a phase difference time measurement unit that measures a phase difference time of the phase difference detected by the phase difference detection unit; an integration unit that calculates an integrated value by adding or subtracting a previous phase difference time from the current phase difference time measured by the phase difference time measurement unit; a delay time determination unit that determines a delay time of the output signal based on the integrated value calculated by the integration unit; a delay unit that delays the output signal based on the delay time determined by the delay time determination unit; A delay control circuit comprising the above.

2. In the delay control circuit according to Claim 1, the integration unit multiplies the current phase difference time measured by the phase difference time measurement unit by a predetermined correction rate. A delay control circuit characterized by this.

3. In the delay control circuit according to Claim 1, the phase difference time measurement unit uses a phase-locked loop circuit. A delay control circuit characterized by this.

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