Semiconductor device, memory system and operating method thereof

Abstract

The invention provides a semiconductor device, a memory system and an operating method thereof. The semiconductor device includes: a delay-locked loop (DLL) configured to output a first correction value corresponding to a single period of a clock; and a duty cycle correction circuit including a frequency divider configured to divide the clock into half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty cycle of 5: 5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2024-0061865, filed on May 10, 2024, and Korean Patent Application No. 10-2024-0200109, filed on December 30, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure described herein relate to a memory system, and more specifically, to a semiconductor device or memory system including a duty cycle correction circuit and a method of operating the semiconductor device or memory system. Background Technology

[0004] A data processing system comprising a memory system or data storage device has been developed to store larger amounts of data in the data storage device, store data faster in the data storage device, and retrieve data stored in the data storage device more quickly. The data storage device may include non-volatile memory cells and / or volatile memory cells for storing data. In input and output (I / O) interface schemes that transmit data synchronously with a clock frequency, such as data transfer between a memory device and a memory controller in a memory system, precise time synchronization between the clock and data may be required as the load on the bus (or data path) increases and the frequency of data transfer increases. Summary of the Invention

[0005] Embodiments of this disclosure may provide an apparatus and method for transmitting and receiving electrical signals such as data, addresses, and commands within a memory system.

[0006] Furthermore, embodiments of this disclosure may provide a memory device, a memory system including the memory device, a controller included in the memory system, or a data processing device including the memory system, configured to transmit and receive electrical signals.

[0007] Embodiments of this disclosure may provide an apparatus and method that adaptively compensate for variations in clock duty cycle caused by process deviations during manufacturing and by temperature and voltage variations that occur during the use of a semiconductor device, memory device, or memory system, thereby maintaining a constant clock duty cycle (e.g., 5:5) amidst changes in the operating environment.

[0008] In embodiments of this disclosure, the semiconductor device may include: a delay phase-locked loop (DLL) configured to output a first correction value corresponding to a single cycle of a clock; and a duty cycle correction circuit configured to divide the clock in half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock with a duty cycle of 5:5 based on the divided clock and the delayed clock. The delay value may be adjusted based on the first correction value.

[0009] A delay phase-locked loop can be configured to detect clock delay within a semiconductor device based on at least one of changes in the operating environment and manufacturing process of the semiconductor device, and output a first correction value corresponding to a single cycle of the clock. The operating environment includes power supply and temperature.

[0010] The duty cycle correction circuit may include a frequency divider configured to select either the rising edge or the falling edge of the clock, such that the output value of the frequency divider transitions from a logic high level to a logic low level or from a logic low level to a logic high level based on the selected edge.

[0011] The duty cycle correction circuit may include: a first delay unit comprising N delay elements, where N is a positive integer, wherein each of the delay elements has a delay value corresponding to 1 / N of a single cycle of the clock. The first delay unit may be configured to delay the divided clock by using delay elements selected from the N delay elements, based on half of a first correction value.

[0012] The duty cycle correction circuit may include: a first inverter configured to invert the divided clock and transmit the inverted divided clock to a first delay unit.

[0013] The first delay unit can be configured to determine a delay value corresponding to a value obtained by subtracting the delay value of the first inverter from half of the first correction value.

[0014] The duty cycle correction circuit may include: a first logic gate configured to perform an XOR operation on a divided clock and a delayed clock; a second inverter configured to invert the output of the first logic gate; and a multiplexer configured to selectively output one of the output of the first logic gate and the output of the second inverter.

[0015] The duty cycle correction circuit may further include: a second delay unit configured to delay the output of the multiplexer and output a delayed output based on a second correction value of the delay phase-locked loop.

[0016] The semiconductor device may further include: a fixed-value filter configured to calculate the average value of a first correction value continuously output from a delay phase-locked loop and send the average value to a first delay unit.

[0017] The fixed value filter can be configured to calculate the average of the values ​​belonging to a preset deviation among the first correction values.

[0018] In another embodiment, the memory system may include: at least one memory device; and a controller coupled to the at least one memory device and configured to adjust the duty cycle of a clock when power is supplied to generate an adjusted clock and perform read or write training based on the adjusted clock. The controller may include: a delay phase-locked loop (DLL) configured to output a first correction value corresponding to a single cycle of the clock; and a duty cycle correction circuit configured to divide the clock in half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock with a 5:5 duty cycle based on the divided clock and the delayed clock.

[0019] The delay value of the first delay unit can be adjusted or changed based on the first correction value output from the delay phase-locked loop.

[0020] A delay phase-locked loop can be configured to detect clock delays within a memory system based on at least one of changes in the operating environment and manufacturing process of the memory system, and output a first correction value corresponding to a single clock cycle. The operating environment includes power supply and temperature.

[0021] The duty cycle correction circuit may include a frequency divider configured to select one of the rising and falling edges of the clock, such that the output value of the frequency divider transitions from a logic high level to a logic low level or from a logic low level to a logic high level based on the selected edge.

[0022] The duty cycle correction circuit may include: a first delay unit comprising N delay elements, where N is a positive integer, wherein each of the delay elements has a delay value corresponding to 1 / N of a single cycle of the clock. The first delay unit may be configured to delay the divided clock by using delay elements selected from the N delay elements, based on half of a first correction value.

[0023] The duty cycle correction circuit may include: a first inverter configured to invert the divided clock and transmit the inverted divided clock to a first delay unit.

[0024] The first delay unit can be configured to determine a delay value corresponding to a value obtained by subtracting the delay value of the first inverter from half of the first correction value.

[0025] The duty cycle correction circuit may include: a first logic gate configured to perform an XOR operation on a divided clock and a delayed clock; a second inverter configured to invert the output of the first logic gate; and a multiplexer configured to selectively output one of the output of the first logic gate and the output of the second inverter.

[0026] The controller may further include: a fixed-value filter configured to calculate the average value of a first correction value continuously output from a delay phase-locked loop (DLL) and send the average value to a first delay unit.

[0027] In another embodiment, the semiconductor device may include: a delay phase-locked loop (DLL) configured to output a first correction value corresponding to a single cycle of a clock; and a duty cycle correction circuit configured to, in the absence of a phase detection device for detecting the phase of the clock, divide the clock in half to generate a divided clock, delay the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generate an adjusted clock with a duty cycle of 5:5 based on the divided clock and the delayed clock.

[0028] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments and the accompanying drawings. Attached Figure Description

[0029] The description herein refers to the accompanying drawings, wherein the same reference numerals refer to the same parts throughout the drawings.

[0030] Figure 1 A data processing apparatus according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A first training process according to an embodiment of this disclosure is shown.

[0032] Figure 3 A second training process according to an embodiment of this disclosure is shown.

[0033] Figure 4 A first clock duty cycle control circuit according to an embodiment of the present disclosure is shown.

[0034] Figure 5 A second clock duty cycle control circuit according to an embodiment of the present disclosure is shown.

[0035] Figure 6 The operation method of a clock duty cycle control circuit according to an embodiment of the present disclosure is shown.

[0036] Figure 7 A third clock duty cycle control circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0037] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. In this disclosure, elements and features may be configured or arranged differently to form other embodiments, which may be any variations of the disclosed embodiments.

[0038] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in terms such as “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may be combined in the same embodiment or may not necessarily be combined in the same embodiment.

[0039] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0040] In this disclosure, various units, circuits, or other components may be described or claimed to be “configured to” perform one or more tasks. In this context, “configured to” is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when the specified block / unit / circuit / component is not currently operating, such as when it is not enabled or activated, it can be said that the block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits / components used with the “configured to” language include hardware, circuits, memory storing program instructions that can be executed to perform operations, etc. Additionally, “configured to” can include general structures, such as general-purpose circuits, that are manipulated by software and / or firmware, such as an FPGA or general-purpose processor running software, to be capable of performing the discussed task(s). “Configured to” can also include means, such as integrated circuits, that adapt manufacturing processes, such as semiconductor manufacturing facilities, to manufacture for performing or implementing one or more tasks.

[0041] As used in this disclosure, the terms “machine,” “circuit,” or “logic” refer to all of the following: (a) purely hardware circuit implementations, such as implementations in analog and / or digital circuits only; and (b) combinations of circuits with software and / or firmware, such as (if applicable): (i) combinations of (one or more) processors or (ii) portions of (one or more) processors / software that work together to cause a device such as a mobile phone or server to perform various functions; and (c) circuits such as (one or more) microprocessors or portions of (one or more) microprocessors that require software or firmware for operation even if the software or firmware is not physically present. The definition of “machine,” “circuit,” or “logic” is suitable for all applications of the term in this application, including its application in any claim. As a further example, as used in this application, the terms “machine,” “circuit,” or “logic” also cover implementations of processors or processors or portions of processors and their accompanying software and / or firmware. For example, the terms “machine,” “circuit,” or “logic” also cover integrated circuits, for example, for storage devices, if suitable for a particular claim element.

[0042] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering, such as spatial, temporal, logical, etc. The terms “first” and “second” do not necessarily imply that the first value must precede the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that otherwise has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0043] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that might influence the determination. That is, the determination can be based solely on those factors or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that the determination of A is also based on C. In other instances, A can be determined solely based on B.

[0044] Embodiments will now be described with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements.

[0045] Figure 1 A data processing apparatus according to an embodiment of the present disclosure is shown.

[0046] Reference Figure 1The data processing device may include a host 110 and a memory system 150. The host 110 and memory system 150 may include a Universal Flash Storage (UFS) electrical interface. The memory system 150 may have the characteristics of a UFS memory device. These characteristics may include low power consumption, high data throughput, low electromagnetic interference, and large memory subsystem efficiency optimization. The UFS electrical interface may be based on a differential interface recommended by the Mobile Industry Processor Interface (MIPI) M-PHY specification, which establishes and supports interconnection between the UFS interface and the MIPI Unified Protocol (UniPro) specification.

[0047] According to an embodiment, host 110 may be an entity or device having the characteristics of a computing device including one or more Small Computer System Interface (SCSI) initiator devices. Host 110 and memory system 150 may communicate data or send and receive data between them using a predetermined set of rules or procedures or a preset interface. Examples of the set of rules or procedures for data communication standards or interfaces supported by host 110 and memory system 150 for sending and receiving data include: Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, host 110 and memory system 150 may be interconnected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that ensures cost-effective, standard connectivity to peripherals such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video conferencing cameras, and more.

[0048] According to embodiments, the memory system 150 can be implemented as any of a variety of storage devices such as: solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), small form factor MMCs (RS-MMCs) or micro MMCs, secure digital cards (SDs) in the form of micro SDs, universal storage bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media cards, memory sticks, etc.

[0049] Host 110 may include a host central processing unit (CPU) 112, host memory 114, bus interface 116, host controller interface (HCI) 118, at least one controller IP core 120, and physical layer (M-PHY) 122. In this document, the controller IP core may include intellectual property blocks or pre-designed and pre-verified components used or embedded in a semiconductor chip or integrated circuit (IC). Host CPU 112 is capable of running at least one application. Host memory 114 may store data to be sent to host CPU 112 or data generated by host CPU 112. Bus interface 116 may be an interface for communication between components included in host 110. Host controller interface 118 may output data to or receive data from external devices (e.g., memory system 150) coupled to host 110. At least one controller IP core 120 may perform various functions such as data, command, or control signal transmission, error handling, power management, etc. Physical layer 122 may perform communication based on the MIPI M-PHY specification.

[0050] At least one controller IP core 120 can manage and control communication between host 110 and memory system 150. For example, controller IP core 120 can be used to send data from host 110 to memory system 150 and perform operations to detect and recover from errors in the data sent from memory system 150 to host 110.

[0051] Physical layer 122 can perform communication according to a serial communication protocol developed by the Mobile Industry Processor Interface (MIPI) organization. Physical layer 122 can be designed for high-speed data transmission used in mobile devices and other low-power devices. According to embodiments, physical layer 122 can be used for communication between various devices such as mobile displays, cameras, sensors, and memory. In particular, physical layer 122 can support low-power operation, enabling it to minimize power consumption and thus extend the lifespan of the battery embedded in the mobile device. Furthermore, physical layer 122 can provide high bandwidth and fast data transmission speeds via a parallel processing scheme using a multi-channel architecture, thereby meeting the demands of high-definition video and large file transfers.

[0052] The host controller interface 118 provides communication with at least one controller IP core 120 and other components connected via bus interface 116. For example, AMBA (Advanced Microcontroller Bus Architecture) is a bus-based communication protocol and interface developed by ARM Ltd. AMBA interfaces, including AXI (Advanced Extensible Interface), AHB (Advanced High Performance Bus), or APB (Advanced Peripheral Bus), can be used for communication between intellectual property (IP) cores in a system-on-a-chip (SoC) design. Bus interface 116 can also support the exchange of data or control signals between the various components included in host 110 and at least one controller IP core 120.

[0053] The physical layer 122 in the host 110 can send or receive reset signals (RST), reference clock (REF-CLK), input data or write data (DIN), and output data or read data (DOUT) to or from the memory system 150.

[0054] The memory system 150 may include a controller 160 and a memory device 180. In this document, the memory device 180 may include at least one data storage space, which may include volatile memory cells or non-volatile memory cells.

[0055] A controller 160, connected to memory device 180 via at least one channel (CH), can receive signals, commands, or data input from host 110 and perform operations in response to such signals, commands, or data. For example, when data is input from host 110, controller 160 can store the data in memory device 180. Controller 160 can also send data requested by host 110 and received from memory device 150 to host 110. Controller 160 may include a physical layer (M-PHY) 162, at least one controller IP core 164, a bus interface 166, and a memory controller 168.

[0056] The controller 160 included in the memory system 150 may include a physical layer 162 that is substantially similar to the physical layer 122 included in the host 110. Physical layer 162 may receive or transmit signals or data sent from or to the host 110. For example, physical layer 162 and physical layer 122 may operate as corresponding parts of each other.

[0057] According to one embodiment, at least one controller IP core 164 in the memory system 150 may be substantially the same as at least one controller IP core 120 in the host 110. In another embodiment, at least one controller IP core 164 may be different from at least one controller IP core 120. The configuration of at least one controller IP core 164 may be determined or established in response to a bus interface 166 that supports communication between the various components included in the memory system 150.

[0058] The memory controller 168 can be designed or configured based on the configuration of the memory device 180. For example, when the memory device 180 is flash memory, the memory controller 168 can support communication with flash memory such as NAND or NOR devices. For example, the memory controller 168 can support the communication schemes and protocols defined in ONFI (Open NAND Flash Interface). ONFI can use data paths (e.g., channels, paths, etc.) including signal lines that enable bidirectional transmission and reception of 8-bit or 16-bit data units between different components. Data communication between the controller 160 and the memory device 180 can be performed by means of an interface designed to support at least one of asynchronous SDR (Asynchronous Single Data Rate), synchronous DDR (Synchronous Double Data Rate), and switched DDR (Switched Double Data Rate).

[0059] Figure 2 A first training process according to an embodiment of this disclosure is illustrated. Specifically, Figure 2 A first training process is described, comprising multiple operations that can be sequentially performed by controller 160 or host 110 when powered. In this document, controller 160 or host 110 may be configured to send commands, signals, or data to and receive commands, signals, or data from memory device 180.

[0060] Reference Figure 2 When power is supplied (operation 252), the controller 160 or the host 110 can initialize various information or parameters for ZQ calibration, and then set completion information or parameters after ZQ calibration is completed (operation 254).

[0061] Following ZQ calibration (operation 254), controller 160 or host 110 may perform duty cycle correction (DCC) training (operation 256). DCC training may be intended or designed to optimize the input / output (I / O) performance of memory device 180 and improve the reliability of data transmission. DCC training is a technique for adjusting the duty cycle of signals (e.g., CLK, RE_t, RE_c) to improve the accuracy of data transmission. DCC training can increase the data transmission speed from or to controller 160 or host 110 and reduce signal distortion in data transmission from or to controller 160 or host 110.

[0062] Controller 160 or host 110 can perform DCC training by sending signals (e.g., preset commands or addresses) to memory device 180. For example, memory device 180 may include function address registers (e.g., feature address registers) for setting and controlling specific functions. Function address registers may include information preset to perform operations that optimize interaction with or within memory device 180 and improve the reliability of data transfer. Controller 160 or host 110 can determine whether to perform a specific function (e.g., whether to enable DCCE_EN) by enabling or disabling specific values ​​in the function address register. After setting or activating the function, controller 160 or host 110 can run a random data output command with a specific address (e.g., 00h) and send a signal with the page size to compensate for the phase of signals (e.g., RE_t or RE_c). The page size can be set differently based on the manufacturer or internal design of memory device 180. During the data output cycle generated by the switching of signals (e.g., RE_t, RE_c), the control signals being trained (e.g., DQ, DQS) may be driven based on the design and implementation, or may be in a high-impedance (Hi-Z) state. Controller 160 or host 110 may invalidate or ignore data exchanged or used during this training process. If a signal transmission is not detected normally (e.g., training failure), controller 160 or host 110 may repeat DCC training.

[0063] After performing DCC training 256, the controller 160 or host 110 can perform read training 258. Read training (or read DQ training) is an operation performed to adjust the timing of data signals (e.g., DQ) and / or control signals (e.g., DQS) to improve the accuracy of data transmission in the memory device 180 and ensure reliable data transmission. For example, the memory device 180 can output a preset data pattern of 16 bits or 32 bits to each DQ pin, and the controller 160 or host 110 can read data corresponding to a preset number of times. That is, this is an operation performed by the controller 160 or host 110 to optimize the timing of the data signal DQ. Read training can reduce errors that may occur during transmission when the controller 160 or host 110 reads data from the memory device 180. Therefore, read training can improve the reliability of data transmission.

[0064] The controller 160 or host 110 connected to the memory device 180 can perform write training (operations 260, 262). Similar to read training, the controller 160 or host 110 can perform write training (operations 260, 262) to optimize the timing of data signals, ensuring that the data to be stored in the memory device 180 can be accurately transmitted, thereby reducing potential errors in data transmission between the memory device 180 and the controller 160 or host 110. Here, write training can be divided into transmit (Tx) side training (operation 262) and receive (Rx) side training (operation 260). According to embodiments, receive-side training (operation 260) can be performed selectively or optionally.

[0065] After writing the training (operations 260, 262), the controller 160 or the host 110 can perform regular operations with the memory device 180 (e.g., data input / output operations, etc.) (operation 264).

[0066] After power is supplied, each of the aforementioned operations can be performed based on a clock signal or data transmission. When transmitting signals or data at high speed, the signals or data can be transmitted based on the rising or falling edge of the clock. To improve the reliability of signal or data transmission, maintaining a 5:5 duty cycle and a constant clock period can have significant advantages. Therefore, the controller 160 or host 110 may include, for example... Figures 4 to 7 The duty cycle correction circuit shown is shown.

[0067] Figure 3 A second training process according to an embodiment of this disclosure is shown. Figure 3 A second training process is described to improve the reliability of signal or data transmission during high-speed operation of the memory device 180. For convenience, the following description can focus on... Figure 2 and Figure 3The difference between the first and second training processes shown corresponds to the operation.

[0068] Reference Figure 3 It describes the process of performing various training operations between the controller 160 and the memory device 180 after the memory system 150 is powered on (operation 202).

[0069] Interface (I / F) initialization (operation 204) may include operations performed at a relatively slow interface speed, such as high-speed interface setup, driver strength setup, ZQ calibration, etc. Interface (I / F) initialization (operation 204) may be performed before multiple training iterations.

[0070] In the following text, controller 160 may perform DCC training (operation 206) before performing read / write DQ training (operations 208, 210, 212). Here, DCC training (operation 206) may correspond to Figure 2 DCC training (Operation 256) is described in the diagram. In memory system 150, controller 160 and memory device 180 can be interconnected via data paths and multiple channels. According to embodiments, each channel can connect multiple memory chips or dies. For example, controller 160 and memory device 180 in memory system 150 can be implemented with multiple semiconductor chips or dies. Semiconductor chips or dies can perform data transfer at speeds of 3.6 Gbps or higher. Therefore, maintaining the duty cycle of control signals (e.g., DQS, RE, etc.) may be critical, as these control signals may be used as the clock (CLK) between the interface circuitry of controller 160 and memory device 180. If the duty cycle of the control signals (e.g., DQS, RE, etc.) is not kept constant, the distortion of the duty cycle may make it impossible to guarantee the data transfer speed between controller 160 and memory device 180 implemented with individual chips or dies. Maintaining the duty cycle of control signals (e.g., DQS, RE, etc.) and maintaining the duty cycle of the clock CLK can be achieved in a substantially similar manner.

[0071] A scheme for adding a buffer chip between controller 160 and memory device 180 has been proposed. However, the expected performance may not be achieved due to duty cycle distortion of the control signal (DQS) used as the sampling clock for the DQ data line. This duty cycle distortion may be more severe because the distortion may occur inside the buffer chip rather than outside it. Therefore, to address this issue, it may be necessary to compensate for the duty cycle of the control signals (e.g., DQS, RE) used as clocks for data latches and signal processing within the system-on-chip (SoC) or memory system 150. In particular, the duty cycle of the clock CLK or control signals (e.g., DQS, RE, etc.) can vary based on changes in the operating environment (e.g., power or temperature) or manufacturing process of controller 160 and memory device 180. Therefore, it is necessary to adjust or compensate for the duty cycle of the clock CLK or control signals (e.g., DQS, RE, etc.) based on the current timing of memory system 150 operation.

[0072] Furthermore, even if data such as mismatched signals (e.g., mismatched DQS) and control signals such as clocks (DQS, RE) are transmitted with different timing sequences (e.g., time differences) supported by memory device 180, controller 160 and memory device 180 can compensate and / or delay the clock line to support the communication protocol. After duty cycle compensation or adjustment, the signal output of the clock line compensated or delayed by a specific value or greater can be used for data or signal transmission.

[0073] The most important reference value used during duty cycle recovery operations performed by a digitally based duty cycle correction (DCC) circuit can be a value corresponding to a single cycle (e.g., one cycle of a 1x clock) of the clock output after the operation is performed by a delay phase-locked loop (DLL). The output value of the DLL (e.g., the latch value) can be a single-cycle value during the operation of the memory system 150. Because the delay elements (e.g., delay cells) included in the delay line have delay values ​​that vary based on process, voltage, and temperature variations (i.e., PVT variations), the output value of the DLL (e.g., the latch value) can vary based on deviations and variations in temperature and voltage of the memory system 150.

[0074] According to an embodiment, to mitigate failures caused by errors in the output values ​​(e.g., DLL lock values) of a delay phase-locked loop (DLL) continuously measured during operation of the memory system 150, an average value can be calculated over a predetermined time period using a fixed-value filter (e.g., a lock value filter). The result (e.g., the average value) can be used to adjust the delay value in a duty cycle correction circuit (DCC) such that the DCC can adaptively follow changes in at least one of the process, voltage, and temperature (PVT) of the memory system 150 to generate or output a delayed output (e.g., a delayed clock).

[0075] Reference Figure 3 Reading the training (operation 208) can correspond to Figure 2 The read training (operation 258) described in the text, and the write training (operation 216) in the DQ training (operation 212) can correspond to Figure 2 Write training as described in the text (operations 260 and 262).

[0076] After reading the training (operation 208), controller 160 can perform an adjustment operation to adjust the duty cycle of the control signal (e.g., DQS) (operation 210). Based on changes in voltage and temperature of memory system 150, it can be monitored whether the finally obtained training settings (e.g., training result values) are sufficient to generate a low error rate at the interface between controller 160 and memory device 180. For example, the first interface training can set the allowable margin of the crossover points of the fast segment (e.g., X DAC) and slow segment (e.g., Y DAC) with respect to the control signals (e.g., DQSn, DQS), and set the gate point of the control signals (e.g., DQS / DQSn). When a trigger for monitoring the interface is present, controller 160 can attempt to obtain a training setting that brings the crossover points closer or delays them by a preset range and check the operational status of the interface. If the duty cycle adjustment is successful, controller 160 does not need to perform interface training again. On the other hand, if the duty cycle adjustment fails, controller 160 can perform interface training again.

[0077] During write training (operation 212), controller 160 can train the level of an internal data reference voltage (e.g., internal VrefQ) (operation 214), which serves as a reference for operations storing and retrieving data in memory device 180. For example, the internal data reference voltage (e.g., internal VrefQ) can be used to determine whether data stored or output in a memory cell is "0" or "1". When the internal data reference voltage (e.g., internal VrefQ) is set incorrectly, data errors may occur. Training the internal data reference voltage (e.g., internal VrefQ) (operation 214) can contribute to data stability, performance optimization, and reduced power consumption.

[0078] After training (operation 214) on an internal data reference voltage (e.g., internal VrefQ), controller 160 may perform write training (operation 216). If write training (operation 216) does not proceed correctly, controller 160 may perform training (operation 214) on the internal data reference voltage (e.g., internal VrefQ) again (repeated).

[0079] Furthermore, if the training (operation 212) does not proceed normally, the controller 160 may again perform the duty cycle adjustment operation of the control signal (e.g., DQS) (operation 210) (repeated). After the training (operation 212), the controller 160 or the host 110 may perform normal operations (e.g., data input / output operations, etc.) with the memory device 180 (operation 222).

[0080] Figure 4 A first clock duty cycle control circuit according to an embodiment of the present disclosure is shown. Here, the first clock duty cycle control circuit is shown as an example including an analog detector capable of detecting the phase of the clock (CLK_Out).

[0081] Reference Figure 4 The first clock duty cycle control circuit may include a duty cycle correction circuit (DCC) 402, a detection and sampling unit 404, a counter 406, and adjustment logic 408.

[0082] Duty cycle correction circuit 402 can be configured to receive an input clock Clk_In and generate an output clock Clk_Out. The input clock Clk_In may not have a 5:5 (i.e., 50%) duty cycle. Duty cycle is a value expressed as a percentage, for example, representing the proportion of time a signal is active (i.e., logic high) within a single cycle or period of the signal. The duty cycle of the input clock Clk_In can be less than 50% or greater than 50%. Duty cycle correction circuit 402 can increase or decrease the duty cycle of the input clock Clk_In to generate an output clock Clk_Out with a 50% duty cycle (i.e., a 5:5 duty cycle).

[0083] The detection and sampling unit 404 can be configured to detect the analog phase of the output clock Clk_Out output from the duty cycle correction circuit 402 and sample the detected phase. The counter 406 can be configured to convert the phase sampled by the detection and sampling unit 404 into a digital value.

[0084] Adjustment logic 408 can calculate the intermediate value between the power supply voltage VDD and the ground voltage GND. Adjustment logic 408 can calculate an adjustment value (e.g., a delay value) for adjusting the input clock Clk_In in response to a phase and digital value sampled based on the intermediate value (e.g., VDD / 2). Based on the adjustment value output from adjustment logic 408, duty cycle correction circuit 402 can determine the delay value (e.g., the amount of delay) of the input clock Clk_In and change the phase of the input clock Clk_In. Through this scheme, duty cycle correction circuit 402 can generate an output clock Clk_Out with a duty cycle of 50% (i.e., a duty ratio of 5:5).

[0085] Figure 4 The first clock duty cycle control circuit described herein can perform the operation of detecting the phase of the output clock Clk_Out using a sensing or detection device capable of detecting the analog phase of the signal, and calculate an adjustment value for the detected signal phase. The first clock duty cycle control circuit including a sensing or detection device can have the advantage of being able to accurately detect the phase of the signal (e.g., the output clock Clk_Out). However, the first clock duty cycle control circuit may spend relatively more (e.g., at least not less) processing time or resources adjusting the duty cycle of the signal (e.g., the clock). High-speed operating memory systems can preferably use devices capable of adjusting the clock duty cycle or duty rate faster than the first clock duty cycle control circuit, without degrading the data input / output (I / O) performance of the memory system.

[0086] The present invention provides a clock duty cycle control circuit that can eliminate or avoid duty cycle distortion in high-speed signal or data communication processes (e.g., high-speed interface operation of 3.6 Gbps or higher) between the controller 160 and the memory device 180 in a memory system 150 capable of storing or outputting large amounts of data. Furthermore, to address transmission processes where there is a time difference between the control signals (e.g., DQS, RE) and the data to be supported in the memory device 180 (e.g., DQ), the clock duty cycle control circuit can be implemented to support duty cycle compensation of the control signals (e.g., DQS, RE) and transmission delay via delay lines used for data gating between the controller 160 and the memory device 180.

[0087] Figure 5 A second clock duty cycle control circuit according to an embodiment of the present disclosure is shown.

[0088] Reference Figure 5 The second clock duty cycle control circuit may include a delay phase-locked loop (DLL) 302 and a duty cycle correction circuit 310.

[0089] A delay-locked loop (DLL) 302 is a feedback control system that can be used in electronic circuits for various purposes. The DLL 302 can be used to adjust the frequency and phase of an input signal so that the frequency and phase of the output signal match the frequency and phase of the input signal. The DLL 302 can be used for precise clock signal phase adjustment, frequency synthesis, or data transmission timing adjustment in any system. The DLL 302 can be configured to output a lock value, Lock_Value, which can correspond to a single cycle of the clock CLK.

[0090] The clock CLK can be generated internally or received from an external device. Due to variations in the operating environment (e.g., voltage, temperature) and manufacturing process of semiconductor devices or memory systems, unexpected distortions and deviations may occur in the lines transmitting or processing the clock CLK. The delay phase-locked loop 302 can output a lock value, Lock_Value, corresponding to a single cycle of the clock CLK, to compensate for distortions and deviations.

[0091] According to an embodiment, the lock value Lock_Value output from the delay phase-locked loop 302 can be used as the first correction value Delay_Value1 input to the duty cycle correction circuit 310.

[0092] The duty cycle correction circuit 310 may include a clock divider 304 configured to divide the input clock CLK by half (i.e., 1 / 2). The divider 304 may include a component that converts the output value based on one of the rising and falling edges of the clock CLK. In an embodiment, in Figure 5 In one embodiment, frequency divider 304 can convert the logic value of output Q0 from logic high to logic low based on the falling edge of clock CLK, or vice versa. In another embodiment, frequency divider 304 can convert the logic value of output Q0 from logic high to logic low based on the rising edge of clock CLK, or vice versa.

[0093] The duty cycle correction circuit 310 may include a first inverter 306 configured to invert a frequency divider clock, which is the output of the frequency divider 304.

[0094] The duty cycle correction circuit 310 may include a first delay unit 308 configured to delay the output of the first inverter 306. The first delay unit 308 may delay the output of the first inverter 306 by half a single cycle of a clock CLK in response to a first correction value Delay_Value1. In this case, half a cycle of the clock CLK may vary based on the operating environment (e.g., voltage, temperature, etc.) and manufacturing process of the semiconductor device or memory system. The first correction value Delay_Value1 is a lock value Lock_Value corresponding to a single cycle (i.e., 1 cycle) of the clock CLK output from the delay phase-locked loop 302. The first delay unit 308 may delay the output of the first inverter 306 by half of the first correction value Delay_Value1.

[0095] According to an embodiment, the first delay unit 308 may include a plurality of delay elements. Each delay element may include at least one delay unit (e.g., an inverter). For example, the first delay unit 308 may determine N delay elements among the plurality of delay elements corresponding to a single cycle (i.e., 1 cycle) of the clock CLK based on a first correction value Delay_Value1. Therefore, the delay amount of each of the N delay elements may be equal to N equal parts of a single cycle (i.e., 1 cycle) of the clock CLK. Alternatively, the first delay unit 308 may select N / 2 delay elements corresponding to half of a single cycle (i.e., 1 cycle) of the clock CLK in response to the first correction value Delay_Value1 to determine its delay amount. The output of the first inverter 306 may be delayed by the N / 2 delay elements selected corresponding to half of the delay amount set in the first delay unit 308.

[0096] According to an embodiment, the first delay unit 308 can determine the delay amount by reflecting the delay amount of the first inverter 306.

[0097] The duty cycle correction circuit 310 may include a logic gate 312 configured to perform an XOR operation on the output of the first delay unit 308 and the output of the frequency divider 304. The result of the XOR operation may be a signal having a single cycle corresponding to the lock value output by the delay phase-locked loop 302.

[0098] The duty cycle correction circuit 310 may include a second inverter 314 configured to invert the output of logic gate 312.

[0099] The duty cycle correction circuit 310 may include a multiplexer 316 configured to transmit either the output of logic gate 312 or the output of the second inverter 314. The output of logic gate 312 and the output of the second inverter 314 may be mutually inverted signals. One of the two signals can be selected for ease of use or to reduce latency based on the operating state of the semiconductor device or memory system. The output of the multiplexer 316 can be determined based on this selection.

[0100] The output of multiplexer 316 can be sent to another component as an output clock CLK_OUT with a duty cycle adjusted to 50%.

[0101] According to an embodiment, the semiconductor device or memory system can use the output clock CLK_OUT after an additional delayed output clock CLK_OUT. In this case, the duty cycle correction circuit 310 can be further configured to receive a second correction value Delay_value2 for the additional delay amount, delay the output clock CLK_OUT based on the second correction value Delay_value2, and output a delayed clock CLK_DELAYED.

[0102] In high-speed interface signal exchange, control signals (e.g., strobe signals) or clocks can maintain a 5:5 duty cycle in the transmitting device (e.g., controller 160). The receiving device (e.g., memory device 180) can transmit data based on the control signals or clocks. However, distortion may frequently occur due to the characteristics of the device during the transmission or reception of control signals or clocks through the channel or receiving device, or after the control signals or clocks are input to the receiving device. For these reasons, duty cycle correction functionality can be useful in semiconductor devices or memory systems. As the operating speed of semiconductor devices or memory systems increases, the ability to restore the duty cycle of control signals or clocks and the ability to restore it quickly may become increasingly critical or important. Furthermore, in protocols based on high-speed interface signal exchange, duty cycle correction functionality can be considered a prerequisite for data communication.

[0103] A system-on-a-chip (SoC) fabricated on a silicon substrate may vary due to process variations in the fabrication process (FAB) and the operating environment, including temperature and voltage changes that occur during the SoC's use after manufacturing. Therefore, it may be necessary to adjust a preset value for the 5:5 duty cycle of the first delay cell 308 based on these differences and variations. Without such adjustment, performance issues or inconveniences may arise in controlling the SoC (e.g., a semiconductor device or memory system) when adjusting the duty cycle based on the preset value.

[0104] To address these issues, unlike traditional analog sensing or detection schemes, a second clock duty cycle control circuit according to an embodiment of this disclosure can be implemented using digital operating logic. The second clock duty cycle control circuit can use one cycle of a clock detected and determined by a delay phase-locked loop (DLL), thereby reducing the impact of process, voltage, and temperature (PVT) deviations and variations. Through these methods, the second clock duty cycle control circuit can restore the duty cycle of the clock or control signal to converge to 5:5. Furthermore, compared to traditional analog sensing or detection schemes, the second clock duty cycle control circuit can achieve immediate or very fast recovery due to the characteristics of its implementation using digital operating logic.

[0105] Figure 6 The operation method of a clock duty cycle control circuit according to an embodiment of the present disclosure is shown.

[0106] Reference Figure 6 When the reset signal ( / RST) can be enabled as a logic low, the clock duty cycle control circuit (DCC) can be reset.

[0107] In the first operation (①), the clock duty cycle control circuit (DCC) can receive the clock signal ORG. Here, the clock signal ORG may not have a 5:5 duty cycle.

[0108] In the second operation (②), the clock duty cycle control circuit (DCC) can divide the clock signal by 1 / 2 to generate a 1 / 2 divided clock signal ORG / 2. According to the embodiment, the 1 / 2 divided clock signal can be generated based on the rising edge of the clock signal ORG.

[0109] In the third operation (③), the clock duty cycle control circuit (DCC) can invert the 1 / 2 divided clock signal ORG / 2 to generate an inverted 1 / 2 divided clock signal (inverted ORG / 2).

[0110] In the fourth operation (④), the clock duty cycle control circuit (DCC) can delay the inverted 1 / 2 divided clock signal (inverted ORG / 2) by half the lock value (1 / 2 lock value).

[0111] In the fifth operation (⑤), the clock duty cycle control circuit (DCC) performs an XOR operation on the 1 / 2 divided clock signal ORG / 2 generated in the second operation (②) and the delayed and inverted 1 / 2 divided clock signal generated in the fourth operation (④). Through the fifth operation (⑤), the clock duty cycle control circuit (DCC) can generate a clock signal with a 5:5 duty cycle.

[0112] In the sixth operation (⑥), the clock duty cycle control circuit (DCC) can invert the clock signal generated in the fifth operation (⑤).

[0113] The clock duty cycle control circuit according to embodiments of this disclosure can adjust the duty cycle of the clock signal through logical operations, so that the recovery time can be very short (fast recovery). According to embodiments, the signal for adjusting or restoring the duty cycle can be output within one cycle or time period before the clock signal ORG.

[0114] Figure 7 A third clock duty cycle control circuit according to an embodiment of the present disclosure is shown. Figure 7 The third clock duty cycle control circuit shown is... Figure 5 The second clock duty cycle control circuit shown is similar.

[0115] Reference Figure 7 The delay phase-locked loop (DLL) 352 and the latch value filter 380 can be configured to measure a single cycle of the input clock CLK during operation of the semiconductor device or memory system and output the value of the measured cycle as the latch value. To avoid or eliminate sudden changes in the latch value, the latch value filter 380 can be configured to perform filtering on the latch value. The clock divider 354 is configured to divide the input clock CLK, i.e., the clock requiring duty cycle correction, by half. A 1 / 2 speed clock can be generated based on the first inverter 356 configured to invert the clock and the first delay unit 358 configured to delay the inverted clock. Alternatively, the original 1 speed clock can be recovered through an XOR operation performed by logic gate 362. The polarity of the output clock can be selected using the second inverter 364 and the multiplexer 366. A clock delayed by a preset amount compared to the original clock can be output through the second delay unit 368.

[0116] and Figure 5Unlike the second clock duty cycle control circuit, the third clock duty cycle control circuit may include a lock value filter 380. The delay phase-locked loop (DLL) can continuously monitor the clock CLK and continuously output lock values ​​(Lock_Value). In this case, filtering can be performed to mitigate sudden changes in the use of the continuously output values. For example, because lock values ​​deviating from a preset deviation or range have a higher probability of error, the lock value filter 380 cannot be used to restore the duty cycle of the clock CLK.

[0117] According to an embodiment, the lock value filter 380 can be configured to calculate an average value of the lock value based on a time axis (e.g., a preset time range) and output the average value to the duty cycle correction circuit 360 to mitigate malfunctions caused by errors in the continuously measured lock values ​​in the delay phase-locked loop (DLL). In this way, the duty cycle correction circuit (DCC) 360 in the third clock duty cycle control circuit can adaptively track and reflect the delay amount of the first delay unit 358 based on variations in the process, voltage, and temperature (PVT) of the semiconductor device or memory system. Furthermore, the delay amount of the second delay unit 368, used to reflect an additionally set delay amount, can also be determined based on the correction values ​​output from the delay phase-locked loop (DLL) 352 and the lock value filter 380.

[0118] As described above, the characteristics and operation of semiconductor devices or memory systems vary based on process, voltage, and temperature conditions. This is particularly true in clock-related fields. Compared to methods that rigidly adjust the duty cycle with a preset delay value based on memory, a clock duty cycle control circuit according to an embodiment of this disclosure can actively or adaptively track a locked value that fluctuates or changes based on process, voltage, and temperature (PVT) variations during the operation of the semiconductor device. Therefore, the clock or control signal used in the semiconductor device or memory system can maintain a 5:5 duty cycle independently of changes in the surrounding environment.

[0119] Furthermore, unlike devices employing conventional analog detection schemes, the clock duty cycle control circuit according to embodiments of this disclosure can use a frequency divider configured to halve the clock frequency through several logic operations and a delay unit having a delay amount that adaptively reflects a value corresponding to half a cycle of the clock to generate a control signal (or clock) with a 50% duty cycle. Additionally, the clock duty cycle control circuit according to embodiments of this disclosure can use a delay phase-locked loop (DLL) configured to continuously monitor the clock cycle, which varies according to changes in voltage and temperature (VT), during operation of the semiconductor device or memory system. Furthermore, the clock duty cycle control circuit can use a duty cycle correction circuit (DCC) configured to determine a half-cycle delay value based on a value obtained by filtering the locked value output from the delay phase-locked loop (DLL).

[0120] As described above, a memory device or memory system according to an embodiment of the present disclosure can maintain a constant clock duty cycle, thereby reducing errors that may occur during the transmission and reception of data or signals, even when the operating environment changes.

[0121] Furthermore, the duty cycle correction circuit according to embodiments of the present disclosure may include digital logic that operates based on digital delay values ​​to simplify internal configuration and improve the speed of clock duty cycle correction or recovery.

[0122] The methods, processes, and / or operations described herein can be executed by code or instructions that run on a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein, or other computers, processors, controllers, or other signal processing devices besides those described herein. Because the algorithms underlying the methods or operations of the computer, processor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0123] Furthermore, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be volatile or non-volatile memory or other storage device that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device to execute the code or instructions to perform the operations of the method or apparatus embodiments described herein.

[0124] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features disclosed in the embodiments herein can be implemented, for example, with non-transitory logic that may include hardware, software, or both. When at least partially implemented in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features can be any of various integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0125] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or any other element besides those described herein. Because the algorithms underlying the methods or operations of the computer, processor, microprocessor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0126] Although embodiments of the present disclosure have been described and illustrated with reference to specific examples, it will be apparent to those skilled in the art that, in view of the present disclosure, various changes and modifications may be made without departing from the scope and range of the present disclosure as defined by the appended claims. Furthermore, embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A delay-locked loop (DLL) outputs a first correction value corresponding to a single clock cycle. as well as The duty cycle correction circuit divides the clock frequency in half to generate a pre-divided clock, delays the pre-divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generates an adjusted clock with a duty cycle of 5:5 based on the pre-divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

2. The semiconductor device according to claim 1, wherein, The delay phase-locked loop detects the delay of a clock within the semiconductor device based on at least one of changes in the operating environment and manufacturing process of the semiconductor device, and outputs a first correction value corresponding to a single cycle of the clock. The operating environment includes power supply and temperature.

3. The semiconductor device according to claim 2, wherein, The duty cycle correction circuit includes a frequency divider that selects one of the rising and falling edges of the clock, such that the output value of the frequency divider changes from a logic high level to a logic low level or from a logic low level to a logic high level based on the selected edge.

4. The semiconductor device according to claim 2, wherein, The duty cycle correction circuit includes: a first delay unit comprising N delay elements, where N is a positive integer, each of the delay elements having a delay value corresponding to 1 / N of a single cycle of the clock, and The first delay unit delays the frequency division clock based on half of the first correction value by using a delay element selected from the N delay elements.

5. The semiconductor device according to claim 4, wherein, The duty cycle correction circuit includes: a first inverter, which inverts the frequency-divided clock and transmits the inverted frequency-divided clock to the first delay unit.

6. The semiconductor device according to claim 5, wherein, The first delay unit determines a delay value corresponding to the value obtained by subtracting the delay value of the first inverter from half of the first correction value.

7. The semiconductor device according to claim 1, wherein, The duty cycle correction circuit includes: The first logic gate performs an XOR operation on the frequency-divided clock and the delayed clock. The second inverter inverts the output of the first logic gate; and The multiplexer selectively outputs one of the outputs of the first logic gate and the second inverter.

8. The semiconductor device according to claim 7, wherein, The duty cycle correction circuit further includes: a second delay unit, which delays the output of the multiplexer and outputs a delayed output based on the second correction value of the delay phase-locked loop.

9. The semiconductor device according to claim 1, further comprising: A fixed-value filter calculates the average value of the first correction value continuously output from the delay phase-locked loop and sends the average value to the first delay unit.

10. The semiconductor device according to claim 9, wherein, The fixed-value filter calculates the average value of the first correction value that belongs to the preset deviation.

11. A memory system, comprising: At least one memory device; as well as A controller, connected to the at least one memory device, adjusts the clock duty cycle to generate an adjusted clock when power is supplied and performs read or write training based on the adjusted clock. The controller includes: A delay-locked loop (DLL) outputs a first correction value corresponding to a single cycle of the clock; and The duty cycle correction circuit divides the clock frequency by half to generate a divided clock, delays the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generates an adjusted clock with a duty cycle of 5:5 based on the divided clock and the delayed clock.

12. The memory system according to claim 11, wherein, The delay value is adjusted or changed based on the first correction value.

13. The memory system according to claim 12, wherein, The delay phase-locked loop detects the clock delay within the memory system based on at least one of changes in the operating environment and manufacturing process of the memory system, and outputs a first correction value corresponding to a single cycle of the clock. The operating environment includes power supply and temperature.

14. The memory system of claim 13, wherein, The duty cycle correction circuit includes a frequency divider that selects one of the rising and falling edges of the clock, such that the output value of the frequency divider changes from a logic high level to a logic low level or from a logic low level to a logic high level based on the selected edge.

15. The memory system according to claim 13, wherein, The duty cycle correction circuit includes: a first delay unit comprising N delay elements, where N is a positive integer, each of the delay elements having a delay value corresponding to 1 / N of a single cycle of the clock, and The first delay unit delays the frequency division clock based on half of the first correction value by using a delay element selected from the N delay elements.

16. The memory system according to claim 15, wherein, The duty cycle correction circuit includes: a first inverter, which inverts the frequency-divided clock and transmits the inverted frequency-divided clock to the first delay unit.

17. The memory system according to claim 16, wherein, The first delay unit determines a delay value corresponding to the value obtained by subtracting the delay value of the first inverter from half of the first correction value.

18. The memory system according to claim 11, wherein, The duty cycle correction circuit includes: The first logic gate performs an XOR operation on the frequency-divided clock and the delayed clock. The second inverter inverts the output of the first logic gate; and The multiplexer selectively outputs one of the outputs of the first logic gate and the second inverter.

19. The memory system according to claim 11, wherein, The controller further includes: A fixed-value filter calculates the average value of the first correction value continuously output from the delay phase-locked loop and sends the average value to the first delay unit.

20. A semiconductor device, comprising: A delay-locked loop (DLL) outputs a first correction value corresponding to a single clock cycle. as well as The duty cycle correction circuit, in the absence of a phase detection device for detecting the phase of the clock, divides the clock into half to generate a divided clock, delays the divided clock by a delay value corresponding to half a cycle of the clock to generate a delayed clock, and generates an adjusted clock with a duty cycle of 5:5 based on the divided clock and the delayed clock.

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