Doherty amplifier circuit and semiconductor device

Abstract

To provide a Doherty amplifier circuit capable of improving characteristics.SOLUTION: A Doherty amplifier circuit includes a distributor 16 that distributes an input signal into a first signal and a second signal, a main amplifier 10 that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier 12 that amplifies the second signal and outputs the amplified signal as a fifth signal, a combiner that combines the fourth signal and the fifth signal and outputs the combined signal as an output signal to an output terminal, a first matching circuit 30 connected between the distributor and the main amplifier, and a second matching circuit 31 connected between the distributor and the first peak amplifier. In an operating band, the absolute value of a return loss seen as viewed from the distributor to the second matching circuit is greater than the absolute value of a return loss as viewed from the distributor to the first matching circuit.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device.

Background Art

[0002] An N (N is 3 or more)-way Doherty amplifier circuit using a main amplifier and two or more peak amplifiers is known (for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in a Doherty amplifier circuit, it is required to improve efficiency and suppress distortion.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to improve characteristics.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a distributor that distributes an input input signal into a first signal and a second signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a synthesizer that synthesizes the fourth signal and the fifth signal and outputs the synthesized signal to an output terminal as an output signal, a first matching circuit connected between the distributor and the main amplifier, and a second matching circuit connected between the distributor and the first peak amplifier. In the operating band, the absolute value of the return loss seen from the distributor to the second matching circuit is greater than the absolute value of the return loss seen from the distributor to the first matching circuit, which is a Doherty amplifier circuit.

[0007] One embodiment of the present disclosure is a package including a base, a first input lead, and a second input lead, a first semiconductor chip mounted on the base and including a main amplifier that amplifies a first signal to which an input signal is distributed, a second semiconductor chip mounted on the base and including a first peak amplifier that amplifies a second signal to which the input signal is distributed, a first capacitor mounted on the base and having a first end electrically connected to the base, a second capacitor mounted on the base and having a first end electrically connected to the base, a third capacitor mounted on the base and having a first end electrically connected to the base, a first inductor having a first end electrically connected to the first input lead and a second end electrically connected to a second end of the first capacitor, a second inductor having a first end electrically connected to the second end of the first capacitor and a second end electrically connected to a second end of the second capacitor, a third inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the first semiconductor chip, a fourth inductor having a first end electrically connected to the second input lead and a second end electrically connected to the second end of the third capacitor, and a fifth inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the second semiconductor chip, which is a semiconductor device for a Doherty amplifier circuit.

Advantages of the Invention

[0008] According to the present disclosure, the characteristics can be improved.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

[0010] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a distributor that distributes an input input signal into a first signal and a second signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a synthesizer that synthesizes the fourth signal and the fifth signal and outputs the synthesized signal to an output terminal as an output signal, a first matching circuit connected between the distributor and the main amplifier, and a second matching circuit connected between the distributor and the first peak amplifier. In the operating band, the absolute value of the return loss seen from the distributor to the second matching circuit is greater than the absolute value of the return loss seen from the distributor to the first matching circuit. This is a Doherty amplifier circuit. Thereby, since the gain of the first peak amplifier can be improved, distortion can be suppressed. Therefore, the characteristics can be improved. (2) In the above (1), the impedance seen from the main amplifier to the first matching circuit at a frequency twice the center frequency of the operating band may be capacitive, and the impedance seen from the first peak amplifier to the second matching circuit at a frequency twice the center frequency may be inductive. Thereby, since the efficiency is improved, the characteristics can be further improved. (3) In the above (2), the first matching circuit includes a first inductor having a first end electrically connected to the distributor and a second end electrically connected to the first node, a second inductor having a first end electrically connected to the first node and a second end electrically connected to the second node, a third inductor having a first end electrically connected to the second node and a second end electrically connected to the main amplifier, a first capacitor shunt-connected to the first node, and a second capacitor shunt-connected to the second node, and is a two-stage matching circuit. The second matching circuit may include a fourth inductor having a first end electrically connected to the distributor and a second end electrically connected to the third node, a fifth inductor having a first end electrically connected to the third node and a second end electrically connected to the first peak amplifier, and a third capacitor shunt-connected to the third node, which is a one-stage matching circuit. Thereby, the characteristics can be further improved. (4) In the above (3), in the operating band, when the ratio of the absolute value of the second impedance seen from the first inductor to the first node to the absolute value of the first impedance seen from the third inductor to the main amplifier is defined as the first ratio, the ratio of the absolute value of the third impedance seen from the distributor to the first inductor to the absolute value of the second impedance is defined as the second ratio, the ratio of the absolute value of the fifth impedance seen from the fourth inductor to the third node to the absolute value of the fourth impedance seen from the fifth inductor to the first peak amplifier is defined as the third ratio, and the ratio of the absolute value of the sixth impedance seen from the distributor to the fourth inductor to the absolute value of the fifth impedance is defined as the fourth ratio, the ratio of the first ratio to the second ratio may be greater than the ratio of the third ratio to the fourth ratio. Thereby, the gain of the peak amplifier can be improved. (5) In the above (4), the second ratio may be greater than the first ratio. Thereby, the efficiency of the main amplifier can be improved. (6) In any of (1) to (5) above, a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal, and a third matching circuit connected between the distributor and the second peak amplifier, wherein the input power of the input signal when the second peak amplifier is turned on is greater than the input power when the first peak amplifier is turned on, the distributor distributes the input signal into the first signal, the second signal, and the third signal, and the synthesizer synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal as the output signal to the output terminal. Thereby, when there are two or more peak amplifiers, the characteristics can be improved. (7) In (6) above, in the operating band, the absolute value of the return loss seen from the distributor to the third matching circuit may be greater than the absolute value of the return loss seen from the distributor to the first matching circuit. Thereby, distortion can be further suppressed. (8) In (7) above, at a frequency twice the center frequency of the operating band, the impedance seen from the main amplifier to the first matching circuit is capacitive, the impedance seen from the first peak amplifier to the second matching circuit at a frequency twice the center frequency is inductive, and the impedance seen from the second peak amplifier to the third matching circuit at a frequency twice the center frequency may be inductive. Thereby, distortion can be further suppressed. (9) In (6) above, in the operating band, the absolute value of the return loss seen from the distributor to the third matching circuit may be smaller than the absolute value of the return loss seen from the distributor to the second matching circuit. Thereby, the efficiency can be improved. (10) In (9) above, at a frequency twice the center frequency of the operating band, the impedance seen from the main amplifier to the first matching circuit is capacitive, the impedance seen from the first peak amplifier to the second matching circuit at a frequency twice the center frequency is inductive, and the impedance seen from the second peak amplifier to the third matching circuit at a frequency twice the center frequency may be capacitive. Thereby, the efficiency can be further improved. (11)One embodiment of the present disclosure includes a package including a base, a first input lead, and a second input lead, a first semiconductor chip mounted on the base and including a main amplifier that amplifies a first signal to which an input signal is distributed, a second semiconductor chip mounted on the base and including a first peak amplifier that amplifies a second signal to which the input signal is distributed, a first capacitor mounted on the base and having a first end electrically connected to the base, a second capacitor mounted on the base and having a first end electrically connected to the base, a third capacitor mounted on the base and having a first end electrically connected to the base, a first inductor having a first end electrically connected to the first input lead and a second end electrically connected to a second end of the first capacitor, a second inductor having a first end electrically connected to the second end of the first capacitor and a second end electrically connected to a second end of the second capacitor, a third inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the first semiconductor chip, a fourth inductor having a first end electrically connected to the second input lead and a second end electrically connected to the second end of the third capacitor, and a fifth inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the second semiconductor chip. A semiconductor device for a Doherty amplifier circuit is provided. Thereby, characteristics can be improved.

[0011] [Details of Embodiments of the Present Disclosure] Specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] [Example 1] As a Doherty amplifier circuit, a high-output high-frequency amplifier circuit used in a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 20 GHz or less. FIG. 1 is a block diagram of the Doherty amplifier circuit according to Example 1.

[0013] As shown in FIG. 1, in Doherty amplifier circuit 100, main amplifier 10, peak amplifier 12 (first peak amplifier), and 14 (second peak amplifier) are connected in parallel between distributor 16 and combiner 18. In this way, Doherty amplifier circuit 100 is a 3-way amplifier circuit. The Doherty amplifier circuit may be an N-way Doherty amplifier circuit having one or three or more peak amplifiers.

[0014] A high-frequency signal is input as input signal Sin to input terminal Tin. Distributor 16 distributes input signal Sin input to input terminal Tin into signal S1 (first signal), S2 (second signal), and S3 (third signal). Distributor 16 is, for example, a Wilkinson type distributor.

[0015] The path through which signal S1 is input includes matching circuit 30, bias circuit 36, main amplifier 10, bias circuit 39, and matching circuit 33. The path through which signal S2 is input includes matching circuit 31, bias circuit 37, peak amplifier 12, and matching circuit 34. The path through which signal S3 is input includes matching circuit 32, bias circuit 38, peak amplifier 14, and matching circuit 35.

[0016] Matching circuits 30 to 32 match the impedance seen from distributor 16 to matching circuits 30 to 32 with the impedance seen from matching circuits 30 to 32 to main amplifier 10, peak amplifiers 12 and 14, respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to gates G of main amplifier 10, peak amplifiers 12 and 14, respectively, to suppress leakage of signals S1 to S3 to the bias terminals.

[0017] The main amplifier 10, peak amplifiers 12 and 14 amplify signals S1, S2 and S3 respectively, and output amplified signals S4 (the fourth signal), S5 (the fifth signal) and S6 (the sixth signal) respectively. The bias circuit 39 supplies a drain bias voltage VD to the drains D of the main amplifier 10, peak amplifiers 12 and 14, and suppresses leakage of the signal S4 to the bias terminal. The matching circuits 33 to 35 match the impedances seen from the main amplifier 10, peak amplifiers 12 and 14 to the impedances seen from the matching circuits 33 to 35 to the synthesizer 18 respectively. The synthesizer 18 synthesizes the signals S4 to S6, and outputs the synthesized signal as an output signal Sout to the output terminal Tout.

[0018] The main amplifier 10, peak amplifiers 12 and 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), and are, for example, GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, signals S1 to S3 are input to the gates G respectively, and signals S4 to S6 are output from the drains D respectively.

[0019] When the input power of the input signal Sin increases, the main amplifier 10 starts to operate. Until the input power at which the main amplifier 10 begins to saturate, the peak amplifiers 12 and 14 do not operate, and the main amplifier 10 amplifies the input signal. At the input power at which the main amplifier 10 begins to saturate, the peak amplifier 12 starts to operate. Until the input power at which the peak amplifier 12 begins to saturate, the peak amplifier 14 does not operate, and the main amplifier 10 and the peak amplifier 12 amplify the input signal. At the input power at which the peak amplifier 12 begins to saturate, the peak amplifier 14 starts to operate. Thereafter, the main amplifier 10, the peak amplifiers 12 and 14 amplify the input signal Sin. Thus, the input power at which the peak amplifier 12 turns on is greater than the input power at which the main amplifier 10 turns on, and the input power at which the peak amplifier 14 turns on is greater than the input power at which the peak amplifier 12 turns on. The main amplifier 10 is, for example, a class A or AB amplifier, and the peak amplifiers 12 and 14 are, for example, class C amplifiers.

[0020] In the first embodiment, the absolute value of the return loss when viewing the matching circuit 30 from the distributor 16 is smaller than the absolute value of the return loss when viewing the matching circuit 31 from the distributor 16. Thereby, the gain of the main amplifier 10 is lower than the gain of the peak amplifier 12. On the other hand, the efficiency of the main amplifier 10 is higher than the efficiency of the peak amplifier 12. The absolute value of the return loss when viewing the matching circuit 32 from the distributor 16 is larger than the absolute value of the return loss when viewing the matching circuit 30 from the distributor 16. Note that the return loss RL when viewing the matching circuits 30 to 32 from the distributor 16 is expressed as RL = 20log 10 |Γ| [dB] using the reflection coefficient |Γ| when viewing the matching circuits 30 to 32 from the distributor 16 in the operating band. Here, the reflection coefficient |Γ| is |Γ| = |(Z - Zo) / (Z + Zo)| where Z is the impedance when viewing the matching circuits 30 to 32 from the distributor 16 in the operating band and Zo is the reference impedance, and corresponds to the absolute value |S11| of the S parameter S11.

[0021] [Examples of matching circuits] As examples of the integrated circuits 30 to 32, the two-stage integrated circuit 30a and the single-stage integrated circuit 30b will be described. The two-stage integrated circuit 30a and the single-stage integrated circuit 30b are merely examples, and the circuit configurations of the two-stage integrated circuit 30a and the single-stage integrated circuit 30b are not limited thereto.

[0022] FIG. 2 is a circuit diagram of the two-stage integrated circuit in the first embodiment. Terminal T1 is the output terminal of the distributor 16 in FIG. 1. Terminal T2 is the output terminal of the transistors Q (corresponding to transistors Q1 to Q3 in FIG. 1) used for the main amplifier 10, the peak amplifiers 12 and 14. The source S of the transistor Q is grounded, and the drain D is electrically connected to the terminal T2.

[0023] The two-stage integrated circuit 30a includes a transmission line TL1, inductors L1 to L3, and capacitors C1 and C2. The transmission line TL1 corresponds to, for example, a line provided on a circuit board. The first end of the inductor L1 (first inductor) is electrically connected to the terminal T1 via the transmission line TL1, and the second end is electrically connected to a node N1 (first node). The first end of the inductor L2 (second inductor) is electrically connected to the node N1, and the second end is electrically connected to a node N2 (second node). The first end of the inductor L3 (third inductor) is electrically connected to the node N2, and the second end is electrically connected to the gate G of the transistor Q. The capacitor C1 (first capacitor) is shunt-connected to the node N1. The capacitor C2 (second capacitor) is shunt-connected to the node N2.

[0024] Let the impedances of the fundamental wave (signal in the operating band) from the terminal T1, the inductor L1, the node N1, the inductor L2, the node N2, and the inductor L3 to the transistor Q be Z1(f), Z2(f), Z3(f), Z4(f), Z5(f), and Z6(f), respectively. Let the impedances of the second harmonic wave (signal having a frequency twice that of the operating band) from the gate G, the inductor L3, the node N2, the inductor L2, and the transmission line TL1 to the terminal T1 be Z6(2f), Z5(2f), Z4(2f), Z3(2f), and Z1(2f), respectively.

[0025] FIG. 3 is a circuit diagram of the first-stage matching circuit in the first embodiment. The first-stage matching circuit 30b includes a transmission line TL2, inductors L4 and L5, and a capacitor C3. The transmission line TL2 corresponds to, for example, a line provided on a circuit board. The first end of the inductor L4 (the fourth inductor) is electrically connected to the terminal T1 via the transmission line TL2, and the second end is electrically connected to the node N3 (the third node). The first end of the inductor L5 (the fifth inductor) is electrically connected to the node N3, and the second end is electrically connected to the gate G of the transistor Q. The capacitor C3 (the third capacitor) is shunt-connected to the node N3.

[0026] Let the fundamental wave impedances when looking from the terminal T1, the inductor L4, the node N3, and the inductor L5 toward the transistor Q be Z1(f), Z7(f), Z8(f), and Z6(f), respectively. Let the second harmonic impedances when looking from the gate G, the inductor L5, and the transmission line TL2 toward the terminal T1 be Z6(2f), Z8(2f), and Z1(2f), respectively.

[0027] [Explanation of impedance matching by the matching circuit] The impedance matching will be described using the two-stage matching circuit 30a and the first-stage matching circuit 30b. The method of impedance matching is not limited to the method described below.

[0028] Figure 4 is a Smith chart showing the fundamental wave impedance matching using the single-stage matching circuit in Example 1. For ease of viewing Figure 1, for convenience, the reference impedance Z0 is set to 5 Ω. The impedance Z1(f) seen from the terminal T1 to the single-stage matching circuit 30b is 50 Ω and is located almost on the real axis. In an example where a GaN HEMT is used as the transistor Q, the absolute value of the impedance Z6(f) seen from the gate G from the single-stage matching circuit 30b is 0.15 Ω and is capacitive. The inductor L5 converts the impedance Z6(f) to Z8(f). The capacitor C3 converts the impedance Z8(f) to an impedance Z7(f) almost on the real axis. The transmission line TL2 and the inductor L4 convert the impedance Z7(f) to the impedance Z1(f).

[0029] For example, in a GaN HEMT with an operating band of 2 GHz and a maximum output power of 200 W, the absolute value of the impedance Z6(f) is 0.15 Ω. Thus, the absolute value of the input impedance of a transistor with a large output power is low. On the other hand, the impedance Z1(f) corresponding to the output impedance of the distributor 16 is 50 Ω. Thus, the absolute value of the impedance Z1(f) with respect to the absolute value of the impedance Z6(f) is about 300 times.

[0030] As a method for converting the impedance Z6(f) to the impedance Z1(f), it is conceivable to convert the impedance Z6(f) to an impedance on the real axis with an almost unchanged absolute value and then use a 1 / 4 wavelength line impedance converter to convert 0.15 Ω to 50 Ω. However, when converting from 0.15 Ω to 50 Ω using a 1 / 4 wavelength line, the impedance conversion ratio becomes about 300 times, making it difficult to match in a wide band.

[0031] Therefore, in the single-stage matching circuit 30b, the impedance Z7(f) is set to approximately 3 Ω on the real axis. In this way, Z7(f) is set to approximately √(Z6(f) × Z1(f)). By doing so, the conversion from the impedance Z6(f) to Z1(f) via Z7(f) is realized by performing impedance conversion of approximately 20 times, twice, from 0.15 Ω through 3 Ω to 50 Ω. When the absolute values of the impedances Z6(f), Z7(f), and Z1(f) are 0.15 Ω, 3 Ω, and 50 Ω respectively, the impedance conversion ratios are |Z6(f)| / |Z7(f)| = 20 and |Z7(f)| / |Z1(f)| = 16.7. In this way, since the impedance conversion ratios |Z6(f)| / |Z7(f)| and |Z7(f)| / |Z1(f)| can be reduced, the bandwidth can be broadened.

[0032] FIG. 5 is a Smith chart of the second harmonic using the single-stage matching circuit in Example 1. As shown in FIG. 5, it is required that the second harmonic signal does not leak to the distributor 16 side. For this reason, the impedance Z1(2f) is almost open. The transmission line TL2, the inductor L4, and the capacitor C3 convert the impedance Z1(2f) to Z8(2f) on the outer periphery of the Smith chart. Further, the inductor L5 converts the impedance Z8(2f) to Z6(2f) on the outer periphery of the Smith chart. The impedance Z6(2f) becomes inductive.

[0033] FIG. 6 is a diagram showing the efficiency with respect to the phase of the impedance Z6(2f) as seen from the gate of the transistor looking at the previous stage. A GaN HEMT with an operating band in the 2 GHz band and a maximum output power of 200 W is taken as an example. The phase of the impedance Z6(2f) on the horizontal axis is the phase on the Smith chart of FIG. 5. The open position has a phase of 0°, and it shows that as the phase increases from 0°, the impedance Z6(2f) rotates counterclockwise around the center of the Smith chart. It shows that as the phase decreases from 0°, the impedance Z6(2f) rotates clockwise around the center of the Smith chart. The phases at the short positions are 180° and -180°. The efficiency on the vertical axis is the drain efficiency.

[0034] As shown in Fig. 6, the efficiency is the lowest when the phase is around 130°, the highest when the phase is around 150°, and the efficiency increases as the phase passes from 130° to -180° and heads towards 150°. In the range R1 where the phase is from 20° to around 70°, the efficiency decreases. On the other hand, in the range R2 where the phase is from -90° to -180°, the efficiency improves. Thus, in order to improve the efficiency, as shown in Fig. 4, it is important not only to match the impedance of the fundamental wave but also to adjust the phase of the second harmonic wave.

[0035] Therefore, the improvement in efficiency by using the two-stage matching circuit 30a will be explained below. Fig. 7 is a Smith chart of the second harmonic wave using the two-stage matching circuit in Example 1. As shown in Fig. 7, the transmission line TL1, inductor L1, and capacitor C1 convert the impedance Z1(2f) at the open position to Z3(2f) on the outer periphery of the Smith chart. Further, the inductor L2 converts the impedance Z3(2f) to Z4(2f) on the outer periphery of the Smith chart. The position of the impedance Z4(2f) is almost the same as the position of the impedance Z6(2f) in Fig. 5. The capacitor C2 converts the impedance Z4(2f) to Z5(2f) on the outer periphery of the Smith chart. The inductor L3 converts the impedance Z5(2f) to Z6(2f) on the outer periphery of the Smith chart. Thus, by providing the capacitor C2 and the inductor L3, the impedance Z6(2f) can be made capacitive. Thereby, the efficiency can be improved.

[0036] FIG. 8 is a Smith chart showing the fundamental wave impedance matching using the two-stage matching circuit in Example 1. As shown in FIG. 8, in the two-stage matching circuit 30a, the inductor L3 in FIG. 2 converts the impedance Z6(f) to Z5(f). The capacitor C2 converts the impedance Z5(f) to Z4(f). The inductor L2 converts the impedance Z4(f) to Z3(f). The capacitor C1 converts the impedance Z3(f) to Z2(f). The transmission line TL1 and the inductor L1 convert the impedance Z2(f) to Z1(f). Thus, the impedance Z6(f) can be converted to Z1(f).

[0037] When the second harmonic impedance Z6(2f) is capacitive as shown in FIG. 7 and the fundamental wave impedance Z6(f) is converted to Z1(f) as shown in FIG. 8, the inductor L3 and the capacitor C2 are made small so that the impedances Z5(f) and Z4(f) are not moved much from the impedance Z6(f). By increasing the inductor L2, the impedance Z4(2f) in FIG. 7 rotates greatly, but the impedance Z3(f) in FIG. 8 also rotates near the outer circumference. When the impedance Z2(f) is converted onto the real axis from the impedance Z3(f) using the capacitor C1, the impedance Z2(f) comes close to the impedance Z1(f). In one example, the impedance Z2(f) is 30 Ω.

[0038] When the absolute values of the impedances Z6(f), Z2(f), and Z1(f) are 0.15 Ω, 30 Ω, and 50 Ω, respectively, the impedance conversion ratios are |Z6(f)| / |Z2(f)| = 200 and |Z2(f)| / |Z1(f)| = 1.7. Thus, the impedance conversion ratios become unbalanced. Therefore, it becomes difficult to achieve broadband.

[0039] As described above, when using the two-stage matching circuit 30a, the efficiency is high but the bandwidth becomes narrow. When attempting to obtain gain across the entire operating bandwidth using the two-stage matching circuit 30a, the overall gain is adjusted to decrease, resulting in a reduction in gain. When using the single-stage matching circuit 30b, the efficiency is low but the bandwidth is wide. Therefore, it is easy to obtain gain across the entire operating bandwidth, and the gain improves.

[0040] [Simulation] S11 and S21 at terminals T1 and T2 were simulated when using the two-stage matching circuit 30a in Fig. 2 and the single-stage matching circuit 30b in Fig. 3 as the matching circuits. The simulation conditions are as follows. Transistor Q: GaN HEMT Two-stage matching circuit 30a: Transmission line TL1: Characteristic impedance: 19Ω, Electrical length: 87° Inductors L1, L2, L3: 0.1nH, 0.2nH, 0.022nH Capacitors C1, C2: 42pF, 20pH Single-stage matching circuit 30b: Transmission line TL2: Characteristic impedance: 8Ω, Electrical length: 83° Inductors L4, L5: 0.1nH, 0.137nH Capacitor C3: 108pH Operating bandwidth: 1.8Hz to 2.2GHz The electrical length is converted to the phase at 2GHz.

[0041] Fig. 9 is a diagram showing S11 with respect to frequency in the simulation. The frequency on the horizontal axis is the frequency of the high-frequency signal input to terminal T1. The S11 on the vertical axis is the absolute value of the S-parameter S11 of terminal T1, corresponding to the absolute value of the reflection coefficient. Also, S11 corresponds to the return loss. When S11 is close to 0dB, the absolute value of the return loss is small, and when S11 is close to 0, that is, when the negative dB value is large, the absolute value of the return loss is large. It shows the case of using the two-stage matching circuit 30a and the case of using the single-stage matching circuit 30b.

[0042] FIG. 10 is a diagram showing S21 with respect to frequency in the simulation. S21 on the vertical axis is the absolute value of the S-parameter S21 from terminal T1 to terminal T2, which is the passing characteristic. S21 corresponds to the gain, and the larger S21 is, the larger the gain is.

[0043] As shown in FIG. 9, when the two-stage matching circuit 30a is used, the absolute value of the return loss is larger than that in the case where the one-stage matching circuit 30b is used. For this reason, as shown in FIG. 10, the gain is 1 dB or more larger over the entire operating band.

[0044] [Comparison between Comparative Example and Example] FIGS. 11, 12, 13, and 14 are circuit diagrams of a part of Doherty amplifier circuits according to Comparative Example 1, Comparative Example 2, Example 1, and Example 2, respectively. In FIGS. 11 to 14, a distributor 16, matching circuits 30 to 32, a main amplifier 10, and peak amplifiers 12 and 14 are illustrated.

[0045] As shown in FIG. 11, in the Doherty amplifier circuit 110 of Comparative Example 1, the matching circuits 30 to 32 are the two-stage matching circuit 30a having inductors L1 to L3, capacitors C1 and C2.

[0046] As shown in FIG. 12, in the Doherty amplifier circuit 112 of Comparative Example 2, the matching circuit 30 is the one-stage matching circuit 30b having inductors L4 and L5 and capacitor C3. The matching circuits 31 and 32 are the two-stage matching circuit 30a having inductors L1 to L3, capacitors C1 and C2.

[0047] As shown in FIG. 13, in the Doherty amplifier circuit 102 of Example 1, the matching circuit 30 is the two-stage matching circuit 30a having inductors L1 to L3, capacitors C1 and C2. The matching circuits 31 and 32 are the one-stage matching circuit 30b having inductors L4 and L5 and capacitor C3.

[0048] As shown in FIG. 14, in the Doherty amplifier circuit 104 of Embodiment 2, the matching circuits 30 and 32 are two-stage matching circuit 30a having inductors L1 to L3, and capacitors C1 and C2. The matching circuit 31 is a one-stage matching circuit 30b having inductors L4, L5, and capacitor C3.

[0049] FIG. 15 is a diagram showing the gain with respect to the input power in Comparative Examples 1 and 2, and Embodiments 1 and 2. The horizontal axis corresponds to the input power Pin of the input signal Sin. The gain on the vertical axis is the power gain, which is different from the small-signal S21 in FIG. 10, but the larger the S21, the larger the power gain. The solid line indicates the gain of the main amplifier 10, peak amplifiers 12 and 14, and the sum of the broken lines indicates the gain of the entire main amplifier 10, peak amplifiers 12 and 14.

[0050] As shown in FIG. 15, in the Doherty amplifier circuit 110 of Comparative Example 1, in order to increase the efficiency, a two-stage matching circuit 30a is used as the matching circuits 30 to 32 as shown in FIG. 11. In the range where the input power Pin is up to the power P1, the gain of the main amplifier 10 is almost constant. When the input power Pin becomes larger than the power P1, the main amplifier 10 saturates and the gain of the main amplifier 10 decreases.

[0051] Near the power P1, the peak amplifier 12 starts to operate. When the input power Pin becomes larger than the power P1, the gain of the peak amplifier 12 gradually increases and saturates at the power P2. The gain when the peak amplifier 12 saturates is smaller than that of the main amplifier 10. When the input power becomes larger than the power P2, the peak amplifier 12 saturates and the gain of the peak amplifier 12 decreases.

[0052] Near the power P2, the peak amplifier 14 starts to operate. When the input power Pin becomes larger than the power P2, the gain of the peak amplifier 14 gradually increases and saturates at the power P3. The gain when the peak amplifier 14 saturates is smaller than that of the main amplifier 10. When the input power becomes larger than the power P3, the peak amplifier 14 saturates and the gain of the peak amplifier 14 decreases.

[0053] The reason why the gain behaviors of the main amplifier 10, peak amplifiers 12 and 14 are different is that the main amplifier 10 is an AB - class operation amplifier, and the peak amplifiers 12 and 14 are C - class operation amplifiers.

[0054] The total gain is almost constant in the range where the input power Pin is up to the power P1. When the input power Pin becomes larger than the power P1, the total gain decreases with the decrease in the gain of the main amplifier 10, and then increases with the increase in the gain of the peak amplifier 12 and becomes almost constant. When the input power Pin becomes larger than the power P2, the total gain decreases with the decrease in the gain of the peak amplifier 12, and then increases with the increase in the gain of the peak amplifier 14 and becomes almost constant. When the input power Pin becomes larger than the power P3, the total gain decreases with the decrease in the gain of the peak amplifier 14.

[0055] In Comparative Example 1, due to the difference in gain between the main amplifier 10, peak amplifiers 12 and 14, a step ΔG1 is formed in the total gain. When the gain is constant with respect to the input power Pin, the linearity such as AM (Amplitude - Modulation) / AM characteristics is good. In Comparative Example 1, since the step ΔG1 is formed, the AM / AM characteristics deteriorate and the distortion characteristics deteriorate.

[0056] In the Doherty amplifier circuit 112 of Comparative Example 2, as shown in FIG. 12, a single - stage matching circuit 30b is used as the matching circuit 30, and a two - stage matching circuit 30a is used as the matching circuits 31 and 32. As shown in FIG. 15, the gain of the main amplifier 10 is larger than that of the Doherty amplifier circuit 110 of Comparative Example 1. As a result, the step ΔG2 of the total gain in the vicinity of the power P2 of the input power Pin becomes larger than ΔG1. Therefore, the AM / AM characteristics deteriorate more than those of the Doherty amplifier circuit 110 of Comparative Example 1. Furthermore, by using a single - stage matching circuit 30b for the matching circuit 30, the efficiency of the main amplifier 10 decreases.

[0057] In the Doherty amplifier circuit 102 of Embodiment 1, as shown in FIG. 13, a two-stage matching circuit 30a is used as the matching circuit 30, and a one-stage matching circuit 30b is used as the matching circuits 31 and 32. As shown in FIG. 15, the gains of the peak amplifiers 12 and 14 are larger than those of the Doherty amplifier circuit 110 of Comparative Example 1. As a result, the step of the total gain in the vicinity of the input power Pin being the power P2 becomes smaller. Therefore, the AM / AM characteristic is improved compared to the Doherty amplifier circuit 110 of Comparative Example 1. By using the one-stage matching circuit 30b for the matching circuits 31 and 32, the efficiencies of the peak amplifiers 12 and 14 decrease. However, since the main amplifier 10 mainly amplifies the input signal Sin, the influence of the decrease in the efficiencies of the peak amplifiers 12 and 14 is small when viewed as the entire Doherty amplifier circuit.

[0058] In the Doherty amplifier circuit 104 of Embodiment 2, as shown in FIG. 14, two-stage matching circuits 30a are used as the matching circuits 30 and 32, and a one-stage matching circuit 30b is used as the matching circuit 31. As shown in FIG. 15, the gain of the peak amplifier 12 is larger than that of the Doherty amplifier circuit 110 of Comparative Example 1. As a result, the step of the total gain in the vicinity of the input power Pin being the power P2 becomes smaller. A step ΔG3 of the total gain occurs in the vicinity of the power P3. Therefore, the AM / AM characteristic deteriorates compared to the Doherty amplifier circuit 102 of Embodiment 1. However, by using the two-stage matching circuit 30a for the matching circuit 32, the efficiency of the peak amplifier 14 is improved, and the efficiency as a whole is improved compared to the Doherty amplifier circuit 104 of Embodiment 1.

[0059] Table 1 is a table showing the characteristics (efficiency, distortion, and phase difference) of each Doherty amplifier circuit 110, 112, 102, and 104. 30 to 32 are the number of stages of the matching circuits 30 to 32. 1 indicates the one-stage matching circuit 30b, and 2 indicates the two-stage matching circuit 30a. The efficiency is the drain efficiency, the distortion is the AM / AM characteristic, and the phase difference is the phase difference between the matching circuits 31 and 32. A for each characteristic indicates that the characteristic is good. B indicates that the characteristic is good although not as good as A. B- indicates that the characteristic is slightly worse than B. C indicates that the characteristic is bad. D indicates that the characteristic is very bad.

Table 1

[0060] As shown in Table 1, in the Doherty amplifier circuit 110 of Comparative Example 1, since the two-stage matching circuit 30a is used for the matching circuits 30 to 32, the efficiency is A. The distortion is C. Since the matching circuits 30 to 32 are the same, there is almost no phase difference between the matching circuits 30 to 32, and the phase difference is A.

[0061] In the Doherty amplifier circuit 112 of Comparative Example 2, the efficiency and distortion are worse than those of the Doherty amplifier circuit 110 and are D. Since the number of stages of the matching circuits 30 to 32 is different, the phase difference becomes worse than that of the Doherty amplifier circuit 110. However, since it can be phase-adjusted, it is not at a problematic level.

[0062] In the Doherty amplifier circuit 102 of Example 1, the efficiency is worse than that of the Doherty amplifier circuit 110 and is B-, but the distortion is A. The phase difference is B. In the Doherty amplifier circuit 104 of Example 2, the efficiency is slightly better than that of the Doherty amplifier circuit 102 of Example 1 and is B. The distortion is slightly worse than that of the Doherty amplifier circuit 102 but better than that of the Doherty amplifier circuit 110.

[0063] [Description of Embodiments] According to Examples 1 and 2, the matching circuit 30 (first matching circuit) is connected between the distributor 16 and the main amplifier 10. The matching circuit 31 (second matching circuit) is connected between the distributor 16 and the peak amplifier 12. As shown in FIG. 9, in the operating band, the absolute value of the return loss RL2 seen from the distributor 16 to the matching circuit 31 is larger than the absolute value of the return loss RL1 seen from the distributor 16 to the matching circuit 30. Thereby, as shown in FIG. 10, the gain of the peak amplifier 12 can be improved. Therefore, as shown in FIG. 15, the step of the total gain can be reduced and the distortion can be suppressed. Therefore, the characteristics can be improved.

[0064] The absolute value of the return loss RL2 may be greater than the absolute value of the return loss RL1 at any frequency within the operating band. At any frequency within the operating band, the absolute value of the return loss RL2 can be made 1 dB or more greater than the absolute value of the return loss RL1, and can be made 5 dB or more greater. Thereby, the gain of the peak amplifier 12 can be further improved. If the absolute value of the return loss RL1 is too small, the gain of the main amplifier 10 deteriorates too much. From this perspective, the absolute value of the return loss RL1 can be made 3 dB or more at any frequency within the operating band.

[0065] As shown in FIGS. 5 to 7, at the frequency 2f which is twice the center frequency of the operating band, the impedance seen from the main amplifier 10 to the matching circuit 30 is capacitive. The impedance seen from the peak amplifier 12 to the matching circuit 31 is inductive. Thereby, the efficiency of the main amplifier 10 can be improved, and thus the overall efficiency is improved. Therefore, the characteristics can be further improved.

[0066] In the Smith chart, when the angle counterclockwise from the open position is defined as the phase, the phase of the impedance Z6(2f) seen from the main amplifier 10 to the matching circuit 30 can be set to -180° or more and -20° or less, and can be set to -180° or more and -90° or less. Thereby, the efficiency of the main amplifier 10 can be improved. The phase of the impedance Z6(2f) seen from the peak amplifier 12 to the matching circuit 31 can be set to 0° or more and 90° or less, and can be set to 20° or more and 70° or less. Thereby, the gain of the peak amplifier 12 can be improved.

[0067] The peak amplifier 14 may be a 2-way Doherty amplifier circuit that is not provided. In the case of a 3-way Doherty amplifier circuit including the peak amplifier 14 and the matching circuit 32 (third matching circuit), the balance between efficiency and distortion becomes important. Therefore, the absolute value of the return loss RL2 can be made greater than the absolute value of the return loss RL1. Thereby, the characteristics can be improved in the 3-way Doherty amplifier circuit.

[0068] In the Doherty amplifier circuit 102 of Embodiment 1, the absolute value of the return loss RL3 as seen from the distributor 16 to the matching circuit 32 is larger than the absolute value of the return loss RL1 as seen from the distributor 16 to the matching circuit 30. Thereby, as shown in FIG. 10, the gain of the peak amplifier 14 can be improved. Therefore, as shown in FIG. 15, the step of the total gain can be reduced and distortion can be suppressed.

[0069] At any frequency in the operating band, the absolute value of the return loss RL3 can be made 1 dB or more larger than the absolute value of the return loss RL1, and can be made 5 dB or more larger. At any frequency in the operating band, the absolute value of the return loss RL1 can be made 3 dB or more.

[0070] At the frequency 2f, the impedance seen from the peak amplifier 14 to the matching circuit 32 is inductive. Thereby, distortion can be further suppressed.

[0071] In the Doherty amplifier circuit 104 of Embodiment 2, the absolute value of the return loss RL3 as seen from the distributor 16 to the matching circuit 32 is smaller than the absolute value of the return loss RL2 as seen from the distributor 16 to the matching circuit 31. Thereby, the efficiency of the peak amplifier 14 can be improved.

[0072] The absolute value of the return loss RL3 may be smaller than the absolute value of the return loss RL2 at any frequency in the operating band. At any frequency in the operating band, the absolute value of the return loss RL3 can be made 1 dB or more smaller than the absolute value of the return loss RL2, and can be made 5 dB or more smaller. At any frequency in the operating band, the absolute value of the return loss RL3 can be made 3 dB or more.

[0073] At the frequency 2f, the impedance seen from the peak amplifier 14 to the matching circuit 32 is capacitive. Thereby, the efficiency can be further improved.

[0074] The circuit configurations of the matching circuits 30 to 32 are not limited to the configurations of FIGS. 2 and 3, and any configuration may be used as long as the return loss becomes a desired value. As the matching circuit 30, a two-stage matching circuit 30a is used, and as the matching circuit 31, a one-stage matching circuit 30b is used. Thereby, the absolute value of the return loss RL2 can be made larger than the absolute value of the return loss RL1. Also, at the frequency f2, the impedance seen from the main amplifier 10 to the matching circuit 30 can be capacitive, and the impedance seen from the peak amplifier 12 to the matching circuit 31 can be inductive. Therefore, the characteristics can be further improved.

[0075] Like the Doherty amplifier circuit 102 of the first embodiment, the matching circuit 32 may use a one-stage matching circuit 30b. Thereby, the absolute value of the return loss RL3 can be made larger than the absolute value of the return loss RL1. Also, at the frequency f2, the impedance seen from the peak amplifier 14 to the matching circuit 32 can be made inductive.

[0076] Like the Doherty amplifier circuit 104 of the second embodiment, the matching circuit 32 may use a two-stage matching circuit 30a. Thereby, the absolute value of the return loss RL3 can be made smaller than the absolute value of the return loss RL2. Also, at the frequency f2, the impedance seen from the peak amplifier 14 to the matching circuit 32 can be made capacitive.

[0077] As shown in Fig. 8, in the two-stage matching circuit 30a, at the center frequency of the operating band, let the absolute value of the impedance Z6(f) (the first impedance) seen from the inductor L1 to the gate G be |Z6(f)|. Let the absolute value of the impedance Z2(f) (the second impedance) seen from the inductor L1 to the node N1 be |Z2(f)|. Let the absolute value of the impedance Z1(f) (the third impedance) seen from the distributor 16 to the inductor L1 be |Z1(f)|. Let the ratio |Z2(f)| / |Z6(f)| of |Z2(f)| to |Z6(f)| be the first ratio R1. Let the ratio |Z1(f)| / |Z2(f)| of |Z1(f)| to |Z2(f)| be the second ratio R2. When |Z6(f)|, |Z2(f)|, and |Z1(f)| are 0.15 Ω, 30 Ω, and 50 Ω respectively, the first ratio R1 = 200, the second ratio R2 = 1.67, and the ratio R1 / R2 of the first ratio R1 to the second ratio R2 is approximately 120.

[0078] As shown in Fig. 4, in the one-stage matching circuit 30b, at the center frequency of the operating band, let the absolute value of the impedance Z6(f) (the fourth impedance) seen from the inductor L5 to the gate G be |Z6(f)|. Let the absolute value of the impedance Z7(f) (the fifth impedance) seen from the inductor L4 to the node N3 be |Z7(f)|. Let the absolute value of the impedance Z1(f) (the sixth impedance) seen from the distributor 16 to the inductor L4 be |Z1(f)|. Let the ratio |Z7(f)| / |Z6(f)| of |Z7(f)| to |Z6(f)| be the third ratio R3. Let the ratio |Z1(f)| / |Z7(f)| of |Z1(f)| to |Z7(f)| be the fourth ratio R4. When |Z6(f)|, |Z7(f)|, and |Z1(f)| are 0.15 Ω, 3 Ω, and 50 Ω respectively, the third ratio R3 = 20, the fourth ratio R4 = 16.7, and the ratio R3 / R4 of the third ratio R3 to the fourth ratio R4 is approximately 1.20.

[0079] As described above, the ratio R1 / R2 is made larger than the ratio R3 / R4. Thereby, the efficiency of the main amplifier 10 in which the matching circuit 30 is a two-stage matching circuit 30a can be improved, and the gain of the peak amplifier 12 in which the matching circuit 31 is a single-stage matching circuit 30b can be improved. The ratio R1 / R2 can be set to be two times or more, ten times or more, and fifty times or more the ratio R3 / R4. From the viewpoint of not making the ratio R1 / R2 too large, the ratio R1 / R2 can be set to be 1000 times or less the ratio R3 / R4.

[0080] In the two-stage matching circuit 30a, the first ratio R1 is larger than the second ratio R2. Thereby, the efficiency of the main amplifier 10 in which the matching circuit 30 is a two-stage matching circuit 30a can be improved. The first ratio R1 can be set to be two times or more, ten times or more, and one hundred times or more the second ratio R2. From the viewpoint of not making the first ratio R1 too large, the first ratio R1 can be set to be 1000 times or less the second ratio R2.

[0081] In FIG. 7, from the viewpoint of rotating the phase from the impedance Z3(2f) to Z4(2f) and, in FIG. 8, reducing the movement from the impedance Z6(f) to Z5(f), the inductance of the inductor L2 can be made larger than the inductance of the inductor L3 and can be made two times or more. In FIG. 8, from the viewpoint of reducing the movement from the impedance Z5(f) to Z4(f) and moving from the impedance Z3(f) to Z2(f), the capacitance of the capacitor C1 can be made larger than the capacitance of the capacitor C2 and can be made 1.5 times or more.

[0082] In the single-stage matching circuit 30b, the third ratio R3 can be set to be 0.1 times or more and 10 times or less, 0.2 times or more and 5 times or less, and 0.5 times or more and 2 times or less the fourth ratio R4. Thereby, the gain of the peak amplifier 12 in which the matching circuit 31 is a single-stage matching circuit 30b can be improved.

[0083] [Example 3] Example 3 and its modification 1 are examples of semiconductor devices for Doherty amplifier circuits of Examples 1 and 2. FIG. 16 is a plan view of the semiconductor device according to Example 3. In FIG. 16, the lid of the package 40 is not shown. The thickness direction of the base 41 of the package 40 is the Z direction, the direction from the leads 44a to 44c to the leads 45a to 45c is the X direction, and the direction orthogonal to the X direction and the Z direction is the Y direction.

[0084] As shown in FIG. 16, in the semiconductor device 106 of Example 3, the package 40 has a base 41 at least on the upper surface of which is conductive, a frame 42, and leads 44a to 44c and 45a to 45c. The base 41 is a conductor substrate such as a laminated substrate of copper and molybdenum, for example. A reference potential such as a ground potential is supplied to the base 41. Semiconductor chips 50a to 50c and capacitive components 55a to 55c are mounted on the base 41. A frame 42 is provided on the base 41 so as to surround the semiconductor chips 50a to 50c and the capacitive components 55a to 55c. The frame 42 is a dielectric layer made of a resin such as a glass epoxy resin or a ceramic, for example.

[0085] Leads 44a to 44c are provided on one side in the X direction of the frame 42. Leads 45a to 45c are provided on the + side in the X direction of the frame 42. The leads 44a to 44c and 45a to 45c are a metal layer or a metal plate made of copper, for example. Signals S1 to S3 are respectively input to the leads 44a to 44c, and signals S4 to S6 are respectively output from the leads 45a to 45c.

[0086] Semiconductor chips 50a to 50c each include a semiconductor substrate 51, pads 52 and 53 provided on the upper surface of the semiconductor substrate 51, and electrodes provided on the lower surface of the semiconductor substrate 51. The electrodes on the lower surfaces of the pads 52, 53 and the semiconductor substrate 51 are a gate electrode, a drain electrode and a source electrode respectively, and the pads 52 and 53 are an input pad and an output pad respectively. Transistors Q1 to Q3 shown in FIG. 1 are provided on the semiconductor substrate 51. When the transistors Q1 to Q3 are GaN HEMTs, the semiconductor substrate 51 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOS, the semiconductor substrate 51 is, for example, a silicon (Si) substrate. The pads 52, 53 and the electrodes are metal layers such as a gold layer, for example.

[0087] Capacitive components 55a to 55c include a dielectric substrate 56, an electrode 57 provided on the upper surface of the dielectric substrate 56, and an electrode provided on the lower surface of the dielectric substrate 56. The electrode 57 and the lower electrode sandwiching the dielectric substrate 56 form a capacitor. The dielectric substrate 56 is, for example, an alumina substrate or a barium titanate substrate. The electrode 57 is a metal layer such as a gold layer, for example.

[0088] Two capacitive components 55a and 55b are provided between the lead 44a and the semiconductor chip 50a. One capacitive component 55c is provided between each of the leads 44b and 44c and the semiconductor chips 50b and 50c.

[0089] Bonding wire 61 electrically connects lead 44a and electrode 57 of capacitive component 55a. Bonding wire 62 electrically connects electrode 57 of capacitive component 55a and electrode 57 of capacitive component 55b. Bonding wire 63 electrically connects electrode 57 of capacitive component 55b and pad 52 of semiconductor chip 50a. Bonding wire 64 electrically connects lead 44b (and 44c) and electrode 57 of capacitive component 55c. Bonding wire 65 electrically connects electrode 57 of capacitive component 55c and pad 52 of semiconductor chip 50b (and 50c). Bonding wire 66 electrically connects pads 53 of semiconductor chips 50a to 50c and leads 45a to 45c, respectively. Bonding wires 61 to 66 are metal wires such as gold wires or aluminum wires, for example.

[0090] Bonding wires 61 to 65 respectively correspond to inductors L1 to L5 in FIG. 13. Capacitive components 55a to 55c respectively correspond to capacitors C1 to C3 in FIG. 13. Thereby, bonding wires 61 to 63, capacitive components 55a and 55b form a two-stage matching circuit 30a, and bonding wires 64, 65 and capacitive component 55c form a one-stage matching circuit 30b.

[0091] [Modification Example 1 of Embodiment 3] FIG. 17 is a plan view of a semiconductor device according to Modification Example 1 of Embodiment 3. As shown in FIG. 17, in semiconductor device 108 of Modification Example 1 of Embodiment 3, capacitive components 55a and 55b are provided between lead 44c and semiconductor chip 50c. Bonding wire 61 electrically connects lead 44c and electrode 57 of capacitive component 55a. Bonding wire 63 electrically connects electrode 57 of capacitive component 55b and pad 52 of semiconductor chip 50c. Other configurations are the same as those in FIG. 16 of Embodiment 1 and the description thereof is omitted.

[0092] According to Example 3 and Modification 1 thereof, as shown in FIGS. 16 and 17, the semiconductor chip 50a (first semiconductor chip) includes the main amplifier 10, the semiconductor chip 50b (second semiconductor chip) includes the peak amplifier 12, and the semiconductor chip 50c (third semiconductor chip) includes the peak amplifier 14.

[0093] Capacitors C1 to C3 respectively correspond to capacitive components 55a to 55c, are mounted on the base 41, and the first ends are electrically connected to the base 41. Inductor L1 corresponds to bonding wire 61, the first end is electrically connected to the lead 44a (first input lead), and the second end is electrically connected to the second end of capacitor C1. Inductor L2 corresponds to bonding wire 62, the first end is electrically connected to the second end of capacitor C1, and the second end is electrically connected to the second end of capacitor C2. Inductor L3 corresponds to bonding wire 63, the first end is electrically connected to the second end of capacitor C2, and the second end is electrically connected to the pad 52 (input pad) of the semiconductor chip 50a. Inductor L4 corresponds to bonding wire 64, the first end is electrically connected to the lead 44b (second input lead), and the second end is electrically connected to the second end of capacitor C3. Inductor L5 corresponds to bonding wire 65, the first end is electrically connected to the second end of capacitor C3, and the second end is electrically connected to the pad 52 (input pad) of the semiconductor chip 50b.

[0094] Thereby, the matching circuit 30 can be a two-stage matching circuit 30a, and the matching circuit 31 can be a single-stage matching circuit 30b. Therefore, the characteristics of the Doherty amplifier circuits 102 and 104 of Examples 1 and 2 can be improved.

[0095] Although the 3-way Doherty amplifier circuit has been described as an example, a 2-way Doherty amplifier circuit without the peak amplifier 14 and the matching circuit 32 may also be used. Further, an N-way Doherty amplifier circuit where N is 4 or more may be used. In this case, N - 1 peak amplifiers may be provided.

[0096] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Explanation of Reference Numerals

[0097] 10 Main amplifier 12 (First peak amplifier), 14 (Second peak amplifier) Peak amplifiers 16 Distributor 18 Combiner 30 (First integrated circuit), 31 (Second integrated circuit), 32 (Third integrated circuit), 33, 34, 35 Integrated circuits 36, 37, 38, 39 Bias circuits 40 Package 41 Base 42 Frame 44a (First input lead), 44b (Second input lead), 44c, 45a, 45b, 45c Leads 50a (First semiconductor chip), 50b (Second semiconductor chip), 50c Semiconductor chips 51 Semiconductor substrate 52, 53 Pads 55a, 55b, 55c Capacitive components 56 Dielectric substrate 57 Electrode 61, 62, 63, 64, 65, 66 Bonding wires 100, 102, 104, 110, 112 Doherty amplifier circuits 106, 108 Semiconductor devices L1 (First inductor), L2 (Second inductor), L3 (Third inductor), L4 (Fourth inductor), L5 (Fifth inductor) Inductors C1 (First capacitor), C2 (Second capacitor), C3 (Third capacitor) Capacitors N1 (First node), N2 (Second node), N3 (Third node) Nodes S1 (First Signal), S2 (Second Signal), S3 (Third Signal), S4 (Fourth Signal), S5 (Fifth Signal), S6 (Sixth Signal) signals Sin Input Signal Sout Output Signal Tin Input Terminal Tout Output Terminal

Claims

1. A distributor that distributes an input signal into a first signal and a second signal, a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal, a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal, a synthesizer that synthesizes the fourth signal and the fifth signal and outputs the synthesized signal to an output terminal as an output signal, a first matching circuit connected between the distributor and the main amplifier, a second matching circuit connected between the distributor and the first peak amplifier, comprising: A Doherty amplifier circuit in which, in an operating band, the absolute value of the return loss seen from the distributor to the second matching circuit is greater than the absolute value of the return loss seen from the distributor to the first matching circuit.

2. At a frequency twice the center frequency of the operating band, the impedance seen from the main amplifier to the first matching circuit is capacitive, The Doherty amplifier circuit according to claim 1, wherein at a frequency twice the center frequency, the impedance seen from the first peak amplifier to the second matching circuit is inductive.

3. The first matching circuit is a two-stage matching circuit comprising a first inductor having a first end electrically connected to the distributor and a second end electrically connected to a first node, a second inductor having a first end electrically connected to the first node and a second end electrically connected to a second node, a third inductor having a first end electrically connected to the second node and a second end electrically connected to the main amplifier, a first capacitor shunt-connected to the first node, and a second capacitor shunt-connected to the second node. The second matching circuit is a one-stage matching circuit comprising a fourth inductor having a first end electrically connected to the distributor and a second end electrically connected to a third node, a fifth inductor having a first end electrically connected to the third node and a second end electrically connected to the first peak amplifier, and a third capacitor shunt-connected to the third node. The Doherty amplifier circuit according to claim 1 or claim 2.

4. In the operation band, a ratio of an absolute value of a second impedance seen from the first inductor to the first node to an absolute value of a first impedance seen from the third inductor to the main amplifier is defined as a first ratio, a ratio of an absolute value of a third impedance seen from the first inductor to the distributor to an absolute value of the second impedance is defined as a second ratio, a ratio of an absolute value of a fifth impedance seen from the fourth inductor to the third node to an absolute value of a fourth impedance seen from the fifth inductor to the first peak amplifier is defined as a third ratio, and a ratio of an absolute value of a sixth impedance seen from the fourth inductor to the distributor to an absolute value of the fifth impedance is defined as a fourth ratio. The Doherty amplifier circuit according to claim 3, wherein a ratio of the first ratio to the second ratio is greater than a ratio of the third ratio to the fourth ratio.

5. The Doherty amplifier circuit according to claim 4, wherein the second ratio is greater than the first ratio.

6. A second peak amplifier that amplifies a third signal and outputs the amplified signal as a sixth signal; A third matching circuit connected between the distributor and the second peak amplifier; Comprising: An input power of the input signal at which the second peak amplifier turns on is greater than an input power of the input signal at which the first peak amplifier turns on. The distributor distributes the input signal into a first signal, a second signal, and a third signal. The Doherty amplifier circuit according to claim 1 or claim 2, wherein the synthesizer synthesizes the fourth signal, the fifth signal, and the sixth signal, and outputs the synthesized signal as the output signal to the output terminal.

7. The Doherty amplifier circuit according to claim 6, wherein an absolute value of a return loss seen from the distributor to the third matching circuit in the operation band is greater than an absolute value of a return loss seen from the distributor to the first matching circuit.

8. An impedance seen from the main amplifier to the first matching circuit at a frequency twice the center frequency of the operation band is capacitive. An impedance seen from the first peak amplifier to the second matching circuit at a frequency twice the center frequency is inductive. The Doherty amplifier circuit according to claim 7, wherein an impedance seen from the second peak amplifier to the third matching circuit at a frequency twice the center frequency is inductive.

9. In the operating band, the absolute value of the return loss seen from the distributor to the third matching circuit is smaller than the absolute value of the return loss seen from the distributor to the second matching circuit. The Doherty amplifier circuit according to claim 6.

10. At a frequency twice the center frequency of the operating band, the impedance seen from the main amplifier to the first matching circuit is capacitive. At a frequency twice the center frequency, the impedance seen from the first peak amplifier to the second matching circuit is inductive. At a frequency twice the center frequency, the impedance seen from the second peak amplifier to the third matching circuit is capacitive. The Doherty amplifier circuit according to claim 9.

11. A package including a base, a first input lead, and a second input lead. A first semiconductor chip mounted on the base and including a main amplifier that amplifies a first signal to which an input signal is distributed. A second semiconductor chip mounted on the base and including a first peak amplifier that amplifies a second signal to which the input signal is distributed. A first capacitor mounted on the base and having a first end electrically connected to the base. A second capacitor mounted on the base and having a first end electrically connected to the base. A third capacitor mounted on the base and having a first end electrically connected to the base. A first inductor having a first end electrically connected to the first input lead and a second end electrically connected to a second end of the first capacitor. A second inductor having a first end electrically connected to the second end of the first capacitor and a second end electrically connected to a second end of the second capacitor. A third inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the first semiconductor chip. A fourth inductor having a first end electrically connected to the second input lead and a second end electrically connected to the second end of the third capacitor. A fifth inductor having a first end electrically connected to the second end of the third capacitor and a second end electrically connected to an input pad of the second semiconductor chip. A semiconductor device for a Doherty amplifier circuit including the above components.

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