Electronic device and data storage method

Abstract

To provide an electronic device in which the number of storage parts provided to be connectable to a logic circuit can be reduced, and a data storage method.SOLUTION: An image forming device comprises: a plurality of storage parts 64A that respectively store a plurality of configuration data in which combinations of corresponding functions are different from each other; a switching part 65 that can switch a connection object to be connected to a field programmable gate array (FPGA) 63, between the plurality of storage parts 64A; an obtaining processing part 51A that obtains the configuration data from a storing part 54; and a storage processing part 51B that stores, in an unconnected storage part, the configuration data obtained by the obtaining processing part 51A, in stead of the configuration data stored in the unconnected storage part not connected to the FPGA 63.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an electronic device and a data storage method.

Background Art

[0002] There is known an electronic device including a logic circuit such as an FPGA (Field-Programmable Gate Array) that can reconfigure an internal logic configuration so as to be able to realize one or more functions by reading configuration data corresponding to the one or more functions. Further, there is known as a related art an electronic device including a plurality of storage units that individually store a plurality of the configuration data, and capable of switching a connection target to the logic circuit among the plurality of storage units (see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the electronic device according to the above-described related art, the larger the number of functions to be realized in the logic circuit, the larger the number of storage units provided so as to be connectable to the logic circuit.

[0005] An object of the present invention is to provide an electronic device and a data storage method capable of reducing the number of storage units provided so as to be connectable to a logic circuit.

Means for Solving the Problems

[0006] An electronic device according to one aspect of the present invention includes a logic circuit, a plurality of first storage units, a switching unit, an acquisition processing unit, and a storage processing unit. The logic circuit can reconfigure its internal configuration based on configuration data corresponding to one or more functions. The plurality of first storage units are each provided so as to be connectable to the logic circuit, and individually store a plurality of pieces of the configuration data corresponding to different functions or combinations of functions. The switching unit can switch a connection target connected to the logic circuit among the plurality of first storage units. The acquisition processing unit acquires the configuration data from a second storage unit different from the first storage unit. The storage processing unit stores, in the first storage unit, the configuration data acquired by the acquisition processing unit in place of the configuration data stored in the first storage unit not connected to the logic circuit.

[0007] A data storage method according to another aspect of the present invention is executed by an electronic device including a logic circuit capable of reconfiguring its internal configuration based on configuration data corresponding to one or more functions, a plurality of first storage units each provided so as to be connectable to the logic circuit and individually storing a plurality of pieces of the configuration data corresponding to different functions or combinations of functions, and a switching unit capable of switching a connection target connected to the logic circuit among the plurality of first storage units, and includes an acquisition step and a storage step. In the acquisition step, the configuration data is acquired from a second storage unit different from the first storage unit. In the storage step, the configuration data acquired in the acquisition step is stored in the first storage unit in place of the configuration data stored in the first storage unit not connected to the logic circuit.

Advantages of the Invention

[0008] According to the present invention, it is possible to reduce the number of storage units provided so as to be connectable to the logic circuit.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the following embodiments are merely examples of embodying the present invention and do not limit the technical scope of the present invention.

[0011] [Configuration of Image Forming Apparatus 100] First, with reference to FIGS. 1 to 3, the configuration of an image forming apparatus 100 according to an embodiment of the present invention will be described. Here, FIG. 1 is a cross-sectional view showing the configuration of the image forming apparatus 100. Further, FIG. 2 is a plan view showing the configuration of the image forming unit 3 and the conveyance unit 4. Further, FIG. 3 is a block diagram showing the configuration of the first control unit 5 and the second control unit 6. In FIG. 1, a sheet conveyance path R11 is indicated by a two-dot chain line.

[0012] The image forming apparatus 100 is a printer capable of forming an image on a sheet by an inkjet method. The image forming apparatus 100 is an example of an electronic device of the present invention. Note that the present invention is applicable to electronic devices such as scanners, facsimile machines, copiers, multifunction devices, personal computers, televisions, air conditioners, refrigerators, microwave ovens, and washing machines.

[0013] As shown in FIGS. 1 and 3, the image forming apparatus 100 includes a housing 1, a sheet conveyance unit 2, an image forming unit 3, a conveyance unit 4, a first control unit 5, and a second control unit 6.

[0014] The housing 1 houses each component of the image forming apparatus 100. A paper feed cassette 11 is detachably provided in the housing 1. The paper feed cassette 11 houses sheets on which images are to be formed. A paper discharge tray 12 is provided on the outer surface of the housing 1. Sheets on which images are formed by the image forming unit 3 are discharged onto the paper discharge tray 12. Inside the housing 1, the sheets housed in the paper feed cassette 11 are conveyed along a sheet conveyance path R11 (see FIG. 1) that reaches the paper discharge tray 12 via the image forming position by the image forming unit 3.

[0015] The sheet conveyance unit 2 conveys the sheets housed in the paper feed cassette 11 along the sheet conveyance path R11 (see FIG. 1). As shown in FIG. 1, the sheet conveyance unit 2 includes a pickup roller 21 and a plurality of conveyance rollers 22. The pickup roller 21 picks up the uppermost sheet in the stack of sheets housed in the paper feed cassette 11 and feeds the sheet onto the sheet conveyance path R11. The plurality of conveyance rollers 22 are arranged side by side along the sheet conveyance path R11. Each of the conveyance rollers 22 conveys the sheet along the sheet conveyance path R11. Each of the conveyance rollers 22 conveys the sheet in the conveyance direction D11 (see FIG. 1) from the paper feed cassette 11 toward the paper discharge tray 12.

[0016] The image forming unit 3 forms an image based on image data on the sheet supplied from the sheet conveyance unit 2. As shown in FIG. 1, the image forming unit 3 includes line heads 31 to 34 and a head frame 35.

[0017] As shown in FIG. 2, each of the line heads 31 to 34 is long in the width direction D12 orthogonal to the conveyance direction D11. Specifically, each of the line heads 31 to 34 has a length corresponding to the width of the largest-sized sheet that can be housed in the paper feed cassette 11 in the width direction D12. Each of the line heads 31 to 34 is arranged at equal intervals along the conveyance direction D11.

[0018] As shown in FIG. 2, each of the line heads 31 to 34 has a plurality of recording heads 30. The recording head 30 discharges ink toward a sheet conveyed by the conveying unit 4. Specifically, a large number of nozzles 36 (see FIG. 2) used for discharging the ink are provided on the surface of the recording head 30 facing the sheet. Each of the recording heads 30 provided in the line head 31 discharges the black ink. Each of the recording heads 30 provided in the line head 32 discharges the cyan ink. Each of the recording heads 30 provided in the line head 33 discharges the magenta ink. Each of the recording heads 30 provided in the line head 34 discharges the yellow ink.

[0019] In the present embodiment, in the line head 31, three recording heads 30 are arranged in a staggered pattern along the width direction D12. Also, in each of the other line heads 32 to 34, three recording heads 30 are arranged in a staggered pattern along the width direction D12, similar to the line head 31. Note that FIG. 2 shows a state in which the image forming unit 3 is viewed from the upper side of FIG. 1.

[0020] The head frame 35 supports the line heads 31 to 34. The head frame 35 is supported by the housing 1. Note that the number of line heads provided in the image forming unit 3 may be one or more. Also, the number of recording heads 30 provided in each of the line heads 31 to 34 does not have to be limited to three.

[0021] As shown in FIG. 1, the conveyance unit 4 is disposed below the line heads 31 to 34. The conveyance unit 4 conveys the sheet while facing it to the recording head 30. For example, each time the ink is ejected by the recording head 30, the conveyance unit 4 conveys the sheet by a predetermined conveyance amount. Further, the conveyance unit 4 stops the conveyance of the sheet while the ink is being ejected by the recording head 30. As shown in FIG. 1, the conveyance unit 4 includes a conveyance belt 41 on which the sheet is placed, a first tension roller 42, a second tension roller 43, and a third tension roller 44 that stretch the conveyance belt 41, and a conveyance frame 45 that supports these. Note that the gap between the conveyance belt 41 and the recording head 30 is adjusted so that the gap between the surface of the sheet and the recording head 30 during image formation becomes a predetermined distance (for example, 1 mm).

[0022] The first tension roller 42 is rotationally driven by a rotational driving force supplied from a motor (not shown). Thereby, the conveyance belt 41 rotates in a direction in which the sheet can be conveyed in the conveyance direction D11 (see FIG. 1). Note that the conveyance unit 4 is also provided with a suction unit (not shown) that sucks air from a large number of through holes formed in the conveyance belt 41 in order to adsorb the sheet to the conveyance belt 41. Further, a pressure roller 46 for pressing the sheet against the conveyance belt 41 and conveying it is provided above the first tension roller 42.

[0023] The first control unit 5 comprehensively controls the image forming apparatus 100. As shown in FIG. 3, the first control unit 5 includes a CPU 51, a RAM 52, a network I / F 53, a storage unit 54, and an image output I / F 55. In the first control unit 5, the CPU 51, the RAM 52, the network I / F 53, the storage unit 54, and the image output I / F 55 are connected to each other communicably by a bus 56 shown in FIG. 3.

[0024] The CPU 51 is a processor that executes various arithmetic processes. The CPU 51 comprehensively controls the image forming apparatus 100 by executing a control program stored in a ROM (not shown) provided in the first control unit 5.

[0025] The RAM 52 is a volatile memory device. The CPU 51 uses the RAM 52 as a temporary storage memory (working area) for various processes it executes.

[0026] The network I / F 53 is an interface that communicably connects the image forming apparatus 100 and a communication device external to the image forming apparatus 100.

[0027] The storage unit 54 is a non-volatile memory device. For example, the storage unit 54 is a non-volatile memory such as a flash memory. The storage unit 54 has a larger storage capacity than the storage unit 64 (see FIG. 3) provided in the second control unit 6. Note that the storage unit 54 may be an SSD (Solid State Drive) or an HDD (Hard Disk Drive).

[0028] The image output I / F 55 is an interface that communicably connects the first control unit 5 and the second control unit 6 via the data transmission path 71 (see FIG. 3). The data transmission path 71 is a serial transmission path. The data transmission path 71 is used for transmitting image data from the first control unit 5 to the second control unit 6. For example, the image output I / F 55 converts the image data to be transmitted into a serial signal according to a predetermined interface standard such as FPD-Link and V-by-One, and outputs the converted serial signal to the data transmission path 71.

[0029] The second control unit 6 controls the operations of the sheet conveyance unit 2, the image forming unit 3, and the conveyance unit 4. As shown in FIG. 3, the second control unit 6 includes a CPU 61, a RAM 62, an FPGA (Field Programmable Gate Array) 63, a storage unit 64, and a switching unit 65. In the second control unit 6, the CPU 61, the RAM 62, the FPGA 63, and the storage unit 64 are communicably connected to each other by a bus 66 shown in FIG. 3.

[0030] The CPU 61 is a processor that executes various arithmetic operations. The CPU 61 controls the operations of the sheet conveyance unit 2, the image forming unit 3, and the conveyance unit 4 by executing a control program stored in a ROM (not shown) provided in the second control unit 6.

[0031] In the image forming apparatus 100, inter-CPU communication is executed between the CPU 51 and the CPU 61. The inter-CPU communication is a data communication that is slower than the data communication using the data transmission path 71.

[0032] The RAM 62 is a volatile storage device. The CPU 61 uses the RAM 62 as a temporary storage memory (working area) for various processes that it executes.

[0033] The FPGA 63 is an electronic circuit whose internal logic configuration can be reconfigured so as to be able to realize one or more functions by reading configuration data corresponding to the one or more functions. The FPGA 63 is an example of the logic circuit of the present invention. Note that the logic circuit in the present invention is not limited to the FPGA, and any electronic circuit whose internal logic configuration can be reconfigured based on the configuration data may be used.

[0034] The FPGA 63 is used for image processing on image data. Specifically, as shown in FIG. 3, the FPGA 63 includes an image input I / F 63A and an image processing unit 63B. The FPGA 63 functions as the image input I / F 63A and the image processing unit 63B by reading the configuration data stored in the storage unit 64A (see FIG. 3) connected to the FPGA 63.

[0035] The image input I / F 63A is an interface that communicably connects the first control unit 5 and the second control unit 6 via the data transmission path 71. The image input I / F 63A converts the serial signal input from the data transmission path 71 into image data according to the interface standard and outputs the converted image data.

[0036] The image processing unit 63B executes image processing on the image data transmitted from the first control unit 5. The image processing unit 63B executes image processing corresponding to the configuration data read by the FPGA 63.

[0037] Incidentally, an electronic device including a plurality of storage units that individually store the plurality of configuration data and capable of switching a connection target connected to the FPGA 63 among the plurality of storage units is known as a related art.

[0038] However, in the electronic device according to the above-described related art, the larger the number of functions to be realized by the FPGA 63, the larger the number of the storage units provided to be connectable to the FPGA 63. Therefore, the configuration of the second control unit 6 becomes complicated.

[0039] On the other hand, in the image forming apparatus 100 according to the embodiment of the present invention, as described below, the number of the storage units provided to be connectable to the FPGA 63 can be reduced.

[0040] In the image forming apparatus 100, a plurality of the configuration data in which corresponding functions or combinations of functions are different are stored in the storage unit 54 of the first control unit 5. For example, the first configuration data, the second configuration data, and the third configuration data are stored in the storage unit 54.

[0041] The first configuration data can cause the FPGA 63 to function as an image input I / F 63A and an image processing unit 63B that executes first image processing. For example, the first image processing is image processing corresponding to a first image forming mode in which image data is printed in color and with high image quality.

[0042] The second configuration data can cause the FPGA 63 to function as an image input I / F 63A and an image processing unit 63B that executes second image processing. For example, the second image processing is image processing corresponding to a second image forming mode in which image data is printed in color and at high speed. The second image forming mode is an image forming mode with a higher printing speed and lower print quality than the first image forming mode.

[0043] The third configuration data can cause the FPGA 63 to function as an image input I / F 63A and an image processing unit 63B that executes third image processing. For example, the third image processing is image processing corresponding to a third image forming mode in which image data is printed in monochrome.

[0044] Note that the number of the configuration data stored in the storage unit 54 may be four or more. Also, the configuration data stored in the storage unit 54 may be updated by update data acquired from a server outside the image forming apparatus 100.

[0045] The storage unit 64 stores a plurality of the configuration data having different corresponding functions or combinations of functions individually. As shown in FIG. 3, the storage unit 64 includes two storage units 64A. The two storage units 64A are an example of a plurality of first storage units of the present invention. Note that the storage unit 64 may include three or more storage units 64A.

[0046] Each of the storage units 64A is a nonvolatile storage device. For example, each of the storage units 64A is a flash memory. Each of the storage units 64A is provided so as to be connectable to the FPGA 63. Any of the configuration data stored in the storage unit 54 of the first control unit 5 is stored in each of the storage units 64A.

[0047] Note that the storage unit 64 may be one or a plurality of storage devices. In this case, each of the storage units 64A may be a storage area set in the storage unit 64.

[0048] The switching unit 65 can switch the connection target connected to the FPGA 63 between two storage units 64A. For example, the switching unit 65 is a multiplexer capable of switching the connection target. Note that the switching unit 65 may be a mechanical switch, a relay, or the like.

[0049] As shown in FIG. 3, the CPU 51 of the first control unit 5 includes an acquisition processing unit 51A, a storage processing unit 51B, a job execution unit 51C, and a determination processing unit 51D.

[0050] Specifically, an operation control program for causing the CPU 51 to function as each of the above-described functional units is stored in advance in the ROM of the first control unit 5. Then, the CPU 51 functions as each of the above-described functional units by executing the operation control program stored in the ROM.

[0051] Note that the operation control program is recorded on a computer-readable recording medium such as a CD, a DVD, or a flash memory, and may be read from the recording medium and stored in a storage device such as the storage unit 54. Also, a part or all of each of the above-described functional units may be configured by an electronic circuit such as an integrated circuit (ASIC). Further, the operation control program may be a program for causing a plurality of processors to function as each of the above-described functional units.

[0052] The acquisition processing unit 51A acquires the configuration data from the storage unit 54 (an example of the second storage unit of the present invention).

[0053] The storage processing unit 51B stores the configuration data acquired by the acquisition processing unit 51A in the non-connected storage unit in place of the configuration data stored in the non-connected storage unit that is not connected to the FPGA 63 among the two storage units 64A.

[0054] For example, the storage processing unit 51B transmits the configuration data acquired by the acquisition processing unit 51A to the second control unit 6 using the data transmission path 71. Further, the storage processing unit 51B instructs the CPU 61 of the second control unit 6 to store the configuration data transmitted from the first control unit 5 in the non-connection storage unit.

[0055] The job execution unit 51C executes an image formation job for forming an image based on the image data.

[0056] For example, an image formation job including designation information for designating any one of the first image formation mode, the second image formation mode, and the third image formation mode is input to the image forming apparatus 100 from an external information processing apparatus.

[0057] When the image formation job is input from an external information processing apparatus, the job execution unit 51C executes the input image formation job according to the designated image formation mode.

[0058] Here, when the image formation job is executed, the FPGA 63 is reconfigured so that image processing corresponding to the image formation mode can be executed using the configuration data corresponding to the image formation mode of the image formation job to be executed.

[0059] Specifically, when the configuration data corresponding to the image formation mode of the image formation job to be executed is stored in the non-connection storage unit, the CPU 51 uses the switching unit 65 to switch the connection target and restart the FPGA 63.

[0060] Further, when the configuration data corresponding to the image forming mode of the image forming job to be executed is not stored in any of the storage units 64A, the acquisition processing unit 51A acquires the configuration data corresponding to the image forming mode of the image forming job to be executed from the storage unit 54. Further, the storage processing unit 51B stores the configuration data acquired by the acquisition processing unit 51A in the non-connected storage unit instead of the configuration data stored in the non-connected storage unit. Then, the CPU 51 uses the switching unit 65 to switch the connection target and restart the FPGA 63.

[0061] Note that the FPGA 63 instructed to restart from the CPU 51 first executes a reset process to reset itself, then reads the configuration data from the connection target, and then executes a configuration process to reconfigure the internal logic configuration based on the read data.

[0062] When there is an image forming job in the standby state during the execution of the image forming job, the determination processing unit 51D determines whether the configuration data corresponding to the image forming mode of the image forming job in the standby state is stored in any of the plurality of storage units 64A.

[0063] For example, when there is an image forming job in the standby state during the execution of the image forming job, the determination processing unit 51D determines whether the image forming mode of the first image forming job being executed is the same as the image forming mode of the second image forming job to be executed next.

[0064] Here, if the image forming mode of the first image forming job is the same as the image forming mode of the second image forming job, the determination processing unit 51D determines that the configuration data corresponding to the image forming mode of the second image forming job is stored in the storage unit 64A connected to the FPGA 63.

[0065] Further, if the image formation mode of the first image formation job is not the same as the image formation mode of the second image formation job, the determination processing unit 51D determines whether the image formation mode of a third image formation job executed immediately before the first image formation job is the same as the image formation mode of the second image formation job. Then, if the image formation mode of the third image formation job is the same as the image formation mode of the second image formation job, the determination processing unit 51D determines that the configuration data corresponding to the image formation mode of the second image formation job is stored in the non-connection storage unit. Further, if the image formation mode of the third image formation job is not the same as the image formation mode of the second image formation job, the determination processing unit 51D determines that the configuration data corresponding to the image formation mode of the second image formation job is not stored in any of the plurality of storage units 64A.

[0066] Here, when the acquisition processing unit 51A determines that the configuration data corresponding to the image formation mode of the image formation job in the standby state is not stored in any of the plurality of storage units 64A by the determination processing unit 51D, the acquisition processing unit 51A acquires the configuration data corresponding to the image formation mode of the image formation job in the standby state from the storage unit 54 during the execution of the image formation job.

[0067] For example, the acquisition processing unit 51A acquires the configuration data corresponding to the image formation mode of the second image formation job from the storage unit 54 during the execution of the first image formation job.

[0068] Further, the storage processing unit 51B stores the configuration data acquired by the acquisition processing unit 51A in the non-connection storage unit during the execution of the image formation job.

[0069] For example, the storage processing unit 51B stores the configuration data corresponding to the image formation mode of the second image formation job acquired by the acquisition processing unit 51A in the non-connection storage unit during the execution of the first image formation job.

[0070] Here, the configuration data corresponding to the image formation mode of the image formation job in the standby state is transmitted from the first control unit 5 to the second control unit 6 using the data transmission path 71 during a non-transmission period in which image data is not transmitted using the data transmission path 71 during the execution of the image formation job. Thereby, the configuration data can be transmitted from the first control unit 5 to the second control unit 6 during the execution of the image formation job without interfering with the execution of the image formation job.

[0071] [Logical Circuit Reconfiguration Processing] Hereinafter, with reference to FIG. 4, an example of the procedure of the logical circuit reconfiguration process executed by the CPU 51 of the first control unit 5 in the image forming apparatus 100 will be described together with the data storage method of the present invention. Here, steps S11, S12,... represent the numbers of the processing procedures (steps) executed by the CPU 51. The logical circuit reconfiguration process is executed when there is an image formation job in the standby state during the execution of the image formation job. That is, the logical circuit reconfiguration process is executed when the first image formation job and the second image formation job exist.

[0072] <Step S11> First, in step S11, the CPU 51 determines whether the image formation mode of the first image formation job is the same as the image formation mode of the second image formation job.

[0073] Here, when the CPU 51 determines that the image forming mode of the first image forming job is the same as the image forming mode of the second image forming job (Yes side in S11), the CPU 51 ends the logic circuit reconfiguration process. Also, if the image forming mode of the first image forming job is not the same as the image forming mode of the second image forming job (No side in S11), the CPU 51 causes the process to shift to step S12.

[0074] <Step S12> In step S12, the CPU 51 determines whether the image forming mode of the third image forming job executed immediately before the first image forming job is the same as the image forming mode of the second image forming job. Here, the processes of step S11 and step S12 are executed by the determination processing unit 51D.

[0075] Here, when the CPU 51 determines that the image forming mode of the third image forming job is the same as the image forming mode of the second image forming job (Yes side in S12), the CPU 51 causes the process to shift to step S15. Also, if the image forming mode of the third image forming job is not the same as the image forming mode of the second image forming job (No side in S12), the CPU 51 causes the process to shift to step S13.

[0076] <Step S13> In step S13, during the execution of the first image forming job, the CPU 51 acquires the configuration data corresponding to the image forming mode of the second image forming job from the storage unit 54. Here, the process of step S13 is an example of the acquisition step of the present invention and is executed by the acquisition processing unit 51A.

[0077] <Step S14> In step S14, the CPU 51 stores the configuration data acquired by the process of step S13 in the non-connection storage unit during the execution of the first image forming job. Here, the process of step S14 is an example of the storage step of the present invention and is executed by the storage processing unit 51B.

[0078] Specifically, the CPU 51 uses the data transmission path 71 during the inter-sheet time from when the transmission of the image data printed on one sheet ends until the transmission of the image data printed on the next sheet starts, and transmits the configuration data acquired by the acquisition processing unit 51A to the second control unit 6. Further, the CPU 51 instructs the CPU 61 of the second control unit 6 to store the configuration data transmitted from the first control unit 5 in the non-connection storage unit.

[0079] <Step S15> In step S15, the CPU 51 determines whether or not the first image forming job has ended.

[0080] Here, when the CPU 51 determines that the first image forming job has ended (Yes side of S15), the process proceeds to step S16. Also, if the first image forming job has not ended (No side of S15), the CPU 51 waits for the end of the first image forming job in step S15.

[0081] <Step S16> In step S16, the CPU 51 restricts the execution of the image forming job by the job execution unit 51C.

[0082] <Step S17> In step S17, the CPU 51 switches the connection target using the switching unit 65. As a result, the FPGA 63 is connected to the storage unit 64A in which the configuration data corresponding to the image forming mode of the second image forming job is stored.

[0083] <Step S18> In step S18, the CPU 51 restarts the FPGA 63. As a result, the FPGA 63 is reconfigured so that the FPGA 63 corresponds to the image forming mode of the second image forming job.

[0084] <Step S19> In step S19, the CPU 51 releases the execution restriction of the image forming job by the job execution unit 51C. As a result, the job execution unit 51C starts executing the second image forming job.

[0085] In this way, in the image forming apparatus 100, instead of the configuration data stored in the non-connection storage unit, the configuration data acquired from the storage unit 54 is stored in the non-connection storage unit. As a result, without increasing the number of storage units 64A provided to be connectable to the FPGA 63, it is possible to increase the number of functions realized by the FPGA 63. Therefore, the number of storage units 64A provided to be connectable to the FPGA 63 can be reduced.

[0086] Also, in the image forming apparatus 100, when the configuration data corresponding to the image forming mode of the second image forming job is not stored in any of the storage units 64A, during the execution of the first image forming job, the configuration data corresponding to the image forming mode of the second image forming job is stored in the non-connection storage unit. As a result, compared with the configuration in which the configuration data corresponding to the image forming mode of the second image forming job is stored in one of the storage units 64A after the end of the first image forming job, it is possible to shorten the waiting time of the user waiting for the start of the execution of the second image forming job.

[0087] In the image forming apparatus 100, the configuration data corresponding to the image forming mode of the second image forming job is transmitted from the first control unit 5 to the second control unit 6 using the data transmission path 71 during the non-transmission period while the first image forming job is being executed. As a result, for example, compared with a configuration in which the configuration data corresponding to the image forming mode of the second image forming job is transmitted by the inter-CPU communication executed between the CPU 51 and the CPU 61 while the first image forming job is being executed, it is possible to transmit the configuration data to the second control unit 6 earlier.

[0088] Note that it is conceivable that the configuration data is damaged during the transfer of the configuration data. If the FPGA 63 is reconfigured based on the damaged configuration data, the operation of the image input I / F 63A may be hindered, and data transmission from the first control unit 5 to the second control unit 6 using the data transmission path 71 may become impossible.

[0089] In this case, the CPU 51 may restart the FPGA 63 by switching the connection target using the switching unit 65. Thereby, as long as the configuration data stored in the non-connection storage unit is not damaged, it is possible to restore the function of the image input I / F 63A.

[0090] Also, when the CPU 51 cannot restore the function of the image input I / F 63A even after restarting the FPGA 63, the configuration data may be transmitted from the first control unit 5 to the second control unit 6 by the inter-CPU communication.

[0091] [Supplementary Note of the Invention] Hereinafter, the outline of the invention extracted from the above-described embodiment will be appended. Note that each configuration and each processing function described in the following supplementary note can be arbitrarily combined by selection.

[0092] [Supplementary Note 1] A logic circuit whose internal configuration can be reconfigured based on configuration data corresponding to one or more functions, a plurality of first storage units each provided so as to be connectable to the logic circuit and individually storing a plurality of the configuration data in which corresponding functions or combinations of functions are different from each other, a switching unit capable of switching a connection target connected to the logic circuit among the plurality of first storage units, an acquisition processing unit that acquires the configuration data from a second storage unit different from the first storage unit, and a storage processing unit that stores the configuration data acquired by the acquisition processing unit in the first storage unit in place of the configuration data stored in the first storage unit not connected to the logic circuit. An electronic device comprising.

[0093] <Appendix 2> Comprising a job execution unit that executes an image forming job for forming an image based on image data, wherein when the image forming job is executed, the logic circuit is reconfigured so that the configuration data corresponding to the image forming mode of the executed image forming job is used to execute image processing corresponding to the image forming mode, and the electronic device, when there is an image forming job in a standby state during the execution of the image forming job, determines whether the configuration data corresponding to the image forming mode of the image forming job in the standby state is stored in any of the plurality of first storage units. The acquisition processing unit, when it is determined by the determination processing unit that the configuration data corresponding to the image forming mode of the image forming job in the standby state is not stored in any of the plurality of first storage units, acquires the configuration data corresponding to the image forming mode of the image forming job in the standby state from the second storage unit during the execution of the image forming job, and the storage processing unit stores the configuration data acquired by the acquisition processing unit in the first storage unit during the execution of the image forming job. The electronic device according to Appendix 1.

[0094] <Appendix 3> A first control unit having the second storage unit, a second control unit having the logic circuit, a plurality of the first storage units, and the switching unit, and a data transmission path used for transmitting the image data from the first control unit to the second control unit. The configuration data corresponding to the image formation mode of the image formation job in the standby state is transmitted from the first control unit to the second control unit using the data transmission path during a non-transmission period in which transmission of the image data using the data transmission path is not performed during execution of the image formation job. The electronic device according to Appendix 2.

[0095] <Appendix 4> A logic circuit capable of reconfiguring an internal configuration based on configuration data corresponding to one or more functions, a plurality of first storage units each provided so as to be connectable to the logic circuit and individually storing a plurality of pieces of the configuration data in which corresponding functions or combinations of functions are different from each other, and a switching unit capable of switching a connection target connected to the logic circuit among the plurality of first storage units. A data storage method executed by an electronic device, the method including: an acquisition step of acquiring the configuration data from a second storage unit different from the first storage unit; and a storage step of storing, in the first storage unit, the configuration data acquired in the acquisition step in place of the configuration data stored in the first storage unit not connected to the logic circuit.

Explanation of Signs

[0096] 1 Housing 2 Sheet Conveying Unit 3 Image Forming Unit 4 Conveying Unit 5 First Control Unit 6 Second Control Unit 51 CPU 51A Acquisition Processing Unit 51B Storage Processing Unit 51C Job Execution Unit 51D Judgment Processing Unit 52 RAM 53 Network I / F 54 Memory unit 55 Image output I / F 56 Bus 61 CPU 62 RAM 63 FPGA 63A Image input I / F 63B Image processing unit 64 Memory unit 64A Storage unit 65 Switching unit 66 Bus 71 Data transmission path 100 Image forming apparatus

Claims

1. A logic circuit capable of reconfiguring its internal configuration based on configuration data corresponding to one or more functions, A plurality of first storage units each provided so as to be connectable to the logic circuit and individually storing a plurality of the configuration data in which corresponding functions or combinations of functions are different from each other, A switching unit capable of switching a connection target connected to the logic circuit among the plurality of first storage units, An acquisition processing unit that acquires the configuration data from a second storage unit different from the first storage unit, A storage processing unit that stores the configuration data acquired by the acquisition processing unit in the first storage unit in place of the configuration data stored in the first storage unit not connected to the logic circuit, An electronic device comprising the above.

2. Comprising a job execution unit that executes an image formation job for forming an image based on image data, When the image formation job is executed, the logic circuit is reconfigured so that image processing corresponding to the image formation mode can be executed using the configuration data corresponding to the image formation mode of the executed image formation job, The electronic device, Comprises a determination processing unit that determines whether or not the configuration data corresponding to the image formation mode of the image formation job in the standby state is stored in any of the plurality of first storage units when there is an image formation job in the standby state during the execution of the image formation job, When the acquisition processing unit determines that the configuration data corresponding to the image formation mode of the image formation job in the standby state is not stored in any of the plurality of first storage units by the determination processing unit, the acquisition processing unit acquires the configuration data corresponding to the image formation mode of the image formation job in the standby state from the second storage unit during the execution of the image formation job, The storage processing unit stores the configuration data acquired by the acquisition processing unit in the first storage unit during the execution of the image formation job. The electronic device according to Claim 1.

3. A first control unit having the second storage unit, A second control unit having the logic circuit, the plurality of first storage units, and the switching unit, A data transmission path used for transmitting the image data from the first control unit to the second control unit, Comprising the above. The configuration data corresponding to the image forming mode of the image forming job in the standby state is transmitted from the first control unit to the second control unit using the data transmission path during a non-transmission period in which transmission of the image data using the data transmission path is not performed during execution of the image forming job. The electronic device according to claim 2.

4. A data storage method executed by an electronic device, comprising: a logic circuit capable of reconfiguring an internal configuration based on configuration data corresponding to one or more functions; a plurality of first storage units each provided so as to be connectable to the logic circuit and individually storing a plurality of pieces of the configuration data having different corresponding functions or combinations of functions; and a switching unit capable of switching a connection target connected to the logic circuit among the plurality of first storage units. An acquisition step of acquiring the configuration data from a second storage unit different from the first storage unit. A storage step of storing the configuration data acquired in the acquisition step in the first storage unit in place of the configuration data stored in the first storage unit not connected to the logic circuit. A data storage method including the above.

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