Detection circuit, semiconductor integrated circuit device, detection system, and vehicle

Abstract

To provide a detection circuit for detecting an operation limit of a band gap circuit when a power source voltage supplied to the band gap circuit becomes low, and to provide a semiconductor integrated circuit device, a detection system, and a vehicle.SOLUTION: In a motor system (SYS1), a detection circuit (28) of a gate drive device (2) detects an operation limit of a band gap circuit, based on a first current (I1) output from a constant-current source (26), a second current (I2) consumed by a band gap circuit (27), and a third current (I3) obtained by subtracting the second current from the first current.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The invention disclosed in this specification relates to a detection circuit, a semiconductor integrated circuit device, a detection system, and a vehicle.

Background Art

[0002] A bandgap circuit is a circuit that generates a reference voltage with a stable voltage value against temperature fluctuations and power supply voltage fluctuations by utilizing the bandgap voltage, which is a physical property of a semiconductor material. The bandgap circuit is also called a bandgap reference circuit, a bandgap type constant voltage circuit, etc.

[0003] The reference voltage output from the bandgap circuit is used in various applications. For example, the reference voltage output from the bandgap circuit is used in a UVLO (Under Voltage Lock Out) circuit (see, for example, Patent Document 1).

[0004] A UVLO circuit that uses the reference voltage output from the bandgap circuit needs to prevent the protected circuit (such as a drive circuit) from being turned on in order to prevent unexpected problems caused by the protected circuit not operating properly when the monitored voltage drops below the reference voltage output from the bandgap circuit.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] [Summary] However, when the power supply voltage supplied to the bandgap circuit becomes low and the bandgap circuit reaches its operating limit, there is a possibility that the UVLO circuit that uses the reference voltage output from the bandgap circuit also reaches its operating limit and cannot execute normal control.

[0007] For this reason, for example, a series circuit composed of a bipolar transistor and a plurality of diodes may be used for both the UVLO circuit and the bandgap circuit. In this case, when the power supply voltage supplied to the bandgap circuit falls below the sum of the saturation voltage between the collector and emitter of the bipolar transistor and the total forward voltage of the plurality of diodes, a measure is taken to mask the output of the UVLO circuit. The sum of the saturation voltage between the collector and emitter of the bipolar transistor and the total forward voltage of the plurality of diodes is set to a value of the power supply voltage slightly before the bandgap circuit reaches its operating limit.

[0008] However, since the forward voltage of the diode has temperature characteristics and large manufacturing variations, it has been difficult to bring the sum of the saturation voltage between the collector and emitter of the bipolar transistor and the total forward voltage of the plurality of diodes close to the value of the power supply voltage at which the bandgap circuit reaches its operating limit. Therefore, when the difference between the value of the reference voltage output from the bandgap circuit and the value of the power supply voltage at which the bandgap circuit reaches its operating limit is small, there is a problem that the above-described measure of masking the output of the UVLO circuit cannot be implemented.

[0009] In the detection circuit disclosed in this specification, the first current (I1) is the current output from the current source, the second current (I2) is the current consumed by the bandgap circuit, and based on the third current (I3) obtained by subtracting the second current from the first current, it is configured to detect the operating limit of the bandgap circuit.

[0010] The semiconductor integrated circuit device disclosed in this specification includes the detection circuit having the above configuration and the bandgap circuit.

[0011] The detection system disclosed in this specification includes the detection circuit having the above configuration and the bandgap circuit.

[0012] The vehicle disclosed in this specification includes the semiconductor integrated circuit device having the above configuration or the detection system having the above configuration.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0014] [Detailed Description] FIG. 1 is a diagram showing a schematic configuration of a motor system according to an embodiment. The motor system SYS1 shown in FIG. 1 includes an MCU (Micro Controller Unit) 1, a gate drive device 2, a first half-bridge circuit including switching elements M1 and M2, a second half-bridge circuit including switching elements M3 and M4, and a motor 3. A motor drive circuit constituted by the gate drive device 2, the first half-bridge circuit, and the second half-bridge circuit drives the motor 3.

[0015] In the present embodiment, the switching elements M1 to M4 are N-channel type MOSFETs. The switching element M2 is connected in series with the switching element M1 and is provided on the lower potential side than the switching element M1. The switching element M4 is connected in series with the switching element M3 and is provided on the lower potential side than the switching element M3.

[0016] The MCU 1 supplies a first PWM (Pulse Width Modulation) signal to the terminal PWM1 of the gate drive device 2 and supplies a second PWM signal to the terminal PWM2 of the gate drive device 2.

[0017] The gate driving device 2 is a semiconductor integrated circuit device. FIG. 2 is an external perspective view of the gate driving device 2. The gate driving device 2 is an electronic component formed by encapsulating a semiconductor integrated circuit chip in a housing (package) made of resin. A plurality of external terminals are provided on the housing of the gate driving device 2 so as to be exposed, and the plurality of external terminals include the terminals PWM1, PWM2, EN, VB, VCC, GND, VCP, G1H, S1H, G1L, S1L, G2H, S2H, G2L, and S2L shown in FIG. 1. Note that the number of external terminals of the gate driving device 2 shown in FIG. 2 and the appearance of the gate driving device 2 are merely examples.

[0018] The gate driving device 2 includes a control logic unit 20, gate driving circuits 21 to 24, an internal power supply circuit 25, a constant current source 26, a bandgap circuit 27, a detection circuit 28, and an UVLO circuit 29. The gate driving device 2 further includes the terminals PWM1, PWM2, EN, VB, VCC, GND, VCP, G1H, S1H, G1L, S1L, G2H, S2H, G2L, and S2L.

[0019] The control logic unit 20 supplies signals based on the first PWM signal supplied to the terminal PWM1 to the gate driving circuits 21 and 22. The control logic unit 20 supplies signals based on the second PWM signal supplied to the terminal PWM2 to the gate driving circuits 23 and 24.

[0020] The gate driving circuit 21 includes switching elements Q1 and Q2. The switching element Q1 is a P-channel type MOSFET. The switching element Q2 is an N-channel type MOSFET. By the control logic unit 20, the switching elements Q1 and Q2 are switched between on and off complementarily. The switching element Q1 is a current source unit configured to flow current into the gate of the switching element M1. The switching element Q2 is a current sink unit configured to draw current from the gate of the switching element M1.

[0021] The source of the switching element Q1 is connected to the terminal VCP. Outside the gate drive device 2, a voltage Vcp is applied to the terminal VCP. A voltage VB is applied to the drain of the switching element M1. The voltage Vcp is higher than the voltage VB. The drain of the switching element Q1 and the drain of the switching element Q2 are connected to the terminal G1H. Outside the gate drive device 2, the gate of the switching element M1 is connected to the terminal G1H. The source of the switching element Q2 is connected to the terminal S1H. Outside the gate drive device 2, the source of the switching element M1, the drain of the switching element M2, and the first end of the motor 3 are connected to the terminal S1H.

[0022] The gate drive circuit 22 includes switching elements Q3 and Q4. The switching element Q3 is a P-channel type MOSFET. The switching element Q4 is an N-channel type MOSFET. By the control logic unit 20, the switching elements Q3 and Q4 are switched on and off complementarily. The switching element Q3 is a current source unit configured to supply current to the gate of the switching element M2. The switching element Q4 is a current sink unit configured to draw current from the gate of the switching element M2.

[0023] An internal power supply voltage VREG1 is applied to the source of the switching element Q3. The drain of the switching element Q3 and the drain of the switching element Q4 are connected to the terminal G1L. Outside the gate drive device 2, the gate of the switching element M2 is connected to the terminal G1L. The source of the switching element Q4 is connected to the terminal S1L. Outside the gate drive device 2, the source of the switching element M2 and the ground potential are connected to the terminal S1L.

[0024] The gate drive circuit 23 includes switching elements Q5 and Q6. The switching element Q5 is a P-channel MOSFET. The switching element Q6 is an N-channel MOSFET. By the control logic unit 20, the switching elements Q5 and Q6 are complementarily switched between on and off. The switching element Q5 is a current source unit configured to supply current to the gate of the switching element M3. The switching element Q6 is a current sink unit configured to draw current from the gate of the switching element M3.

[0025] The source of the switching element Q5 is connected to the terminal VCP, similar to the source of the switching element Q1. The drain of the switching element Q5 and the drain of the switching element Q6 are connected to the terminal G2H. Outside the gate drive device 2, the gate of the switching element M3 is connected to the terminal G2H. The source of the switching element Q6 is connected to the terminal S2H. Outside the gate drive device 2, the source of the switching element M3, the drain of the switching element M4, and the second end of the motor 3 are connected to the terminal S2H.

[0026] The gate drive circuit 24 includes switching elements Q7 and Q8. The switching element Q7 is a P-channel MOSFET. The switching element Q8 is an N-channel MOSFET. By the control logic unit 20, the switching elements Q7 and Q8 are complementarily switched between on and off. The switching element Q7 is a current source unit configured to supply current to the gate of the switching element M4. The switching element Q8 is a current sink unit configured to draw current from the gate of the switching element M4.

[0027] The internal power supply voltage VREG1 is applied to the source of the switching element Q7. The drains of the switching element Q7 and the switching element Q8 are connected to the terminal G2L. Outside the gate driver 2, the gate of the switching element M4 is connected to the terminal G2L. The source of the switching element Q8 is connected to the terminal S2L. Outside the gate driver 2, the source of the switching element M4 and the ground potential are connected to the terminal S2L.

[0028] The internal power supply circuit 25 converts the reference voltage VREF output from the bandgap circuit 27 into the internal power supply voltage VREG1. When the enable signal supplied to the terminal EN is at the first level (for example, low level), the control logic unit 20 and the internal power supply circuit 25 are in the enabled state. On the other hand, when the enable signal supplied to the terminal EN is at the second level (for example, high level), the control logic unit 20 and the internal power supply circuit 25 are in the disabled state.

[0029] The constant current source 26 outputs a constant current I1. The constant current I1 is set to a value larger than the current required for driving the bandgap circuit 27. Note that, instead of the constant current source 26, a current source that is not a constant current source may be used. Even when a current source that is not a constant current source is used, the current output from the current source that is not a constant current source is set to a value larger than the current required for driving the bandgap circuit 27.

[0030] The bandgap circuit 27 generates the reference voltage VREF by using the bandgap voltage which is a physical property of the semiconductor material.

[0031] The detection circuit 28 detects the operating limit of the bandgap circuit 27. Specifically, the detection circuit 28 detects the operating limit of the bandgap circuit 27 based on the third current I3 obtained by subtracting the second current I2 consumed by the bandgap circuit 27 from the first current I1 output from the constant current source 26. Note that the detection circuit 28 may have a small margin in detecting the operating limit of the bandgap circuit 27.

[0032] When the voltage Vcc, which is the voltage to be monitored, drops below the reference voltage VREF output from the bandgap circuit 27, the UVLO circuit 29 prevents the circuit to be protected (for example, the control logic unit 20) from turning on in order to prevent unexpected problems caused by the abnormal operation of the circuit to be protected.

[0033] FIG. 3 is a diagram showing a configuration example of the bandgap circuit 27 and the detection circuit 28. The detection system SYS2 is constituted by the constant current source 26, the bandgap circuit 27, and the detection circuit 28. Note that the constant current source 26 may be provided outside the detection system SYS2. That is, the detection system SYS2 may be constituted only by the bandgap circuit 27 and the detection circuit 28. In the present embodiment, the constant current source 26 is provided inside the gate drive device 2 as shown in FIG. 1, but the constant current source 26 may be provided outside the gate drive device 2.

[0034] The bandgap circuit 27 of the configuration example shown in FIG. 3 includes resistors R1 to R3 and NPN bipolar transistors Q11 to Q13. The first end of resistor R1, the first end of resistor R2, and the emitter of a PNP bipolar transistor Q14 (described later) are connected to the output end of the constant current source 26. The first end of a current source CS1 (not shown in FIG. 1) provided inside the gate driving device 2 is connected to the terminal VCC. The second end of the current source CS1 is connected to the collector of the NPN bipolar transistor Q13. In the present embodiment, the current source CS1 is provided inside the gate driving device 2, but the current source CS1 may be provided outside the gate driving device 2. The second end of resistor R1 is connected to the collector and base of the NPN bipolar transistor Q11, and the base of the NPN bipolar transistor Q12. The second end of resistor R2 is connected to the collector of the NPN bipolar transistor Q12 and the base of the NPN bipolar transistor Q13. The emitter of the NPN bipolar transistor Q12 is connected to the first end of resistor R3. The emitter of the NPN bipolar transistor Q11, the second end of resistor R3, and the emitter of the NPN bipolar transistor Q13 are connected to the terminal GND, the sources of NMOS transistors (N-channel MOSFETs) Q15 and Q16 (described later), and the second end of a capacitor C1 (described later).

[0035] The reference voltage VREF output from the bandgap circuit 27 of the configuration example shown in FIG. 3 is represented by the following equation. Here, V BE1 is the base-emitter voltage of the NPN bipolar transistor Q11, R1 is the resistance value of the resistor R1, R3 is the resistance value of the resistor R3, V T is the thermal voltage, and N is the size ratio (more specifically, the emitter size ratio) of the NPN bipolar transistor Q12 with respect to the NPN bipolar transistor Q11. VREF = V BE1 + (R1 / R3) V T ln N

[0036] The detection circuit 28 of the configuration example shown in FIG. 3 includes a PNP transistor Q14, NMOS transistors Q15 and Q16, a resistor R4, a capacitor C1, and an inverter INV1. The emitter of the PNP bipolar transistor Q14 is connected to the output terminal of the constant current source 26 together with the first terminal of the resistor R1 and the first terminal of the resistor R2. The base of the PNP bipolar transistor Q14 is connected to the collector of the NPN bipolar transistor Q13. The collector of the PNP bipolar transistor Q14 is connected to the drain and gate of the NMOS transistor Q15 and the gate of the NMOS transistor Q16. A voltage Vcc is applied to the first terminal of the resistor R4. The second terminal of the resistor R4 is connected to the input terminal of the inverter INV1, the drain of the NMOS transistor Q16, and the first terminal of the capacitor C1. The sources of the NMOS transistors Q15 and Q16 and the second terminal of the capacitor C1 are connected to the emitter of the NPN bipolar transistor Q11, the second terminal of the resistor R3, the emitter of the NPN bipolar transistor Q13, and the terminal GND.

[0037] When the bandgap circuit 27 is driving, that is, when the bandgap circuit 27 has not reached its operating limit, the value of the third current I3 is configured not to become zero. Note that the third current I3 is the current obtained by subtracting the second current I2 (the total current of the current I2a flowing through the resistor R1 and the current I2b flowing through the resistor R2) consumed by the bandgap circuit 27 from the first current I1 output from the constant current source 26. Since the third current I3 is a current not consumed by the bandgap circuit 27, it is also called a waste current.

[0038] The third current I3 is folded back by a current mirror circuit composed of the NMOS transistors Q15 and Q16, and a mirror current corresponding to the third current I3 flows through the resistor R4. As a result, the first voltage V1 applied to the input terminal of the inverter INV1 becomes a low level, and the second voltage V2 output from the inverter INV1 becomes a high level.

[0039] On one hand, when the first current I1 output from the constant current source 26 saturates due to the decrease in the voltage Vcc, and the current I2a flowing through the resistor R1 and the current I2b flowing through the resistor R2 are not sufficiently supplied, resulting in the reduction of the reference voltage VREF, that is, when the bandgap circuit 27 reaches its operating limit, the value of the third current I3 becomes zero or less. As a result, the value of the mirror current corresponding to the third current I3 also becomes zero, the first voltage V1 applied to the input terminal of the inverter INV1 becomes high level, and the second voltage V2 output from the inverter INV1 becomes low level. That is, the detection circuit 28 in the configuration example shown in FIG. 3 detects the operating limit of the bandgap circuit 27 when the third current I3 is equal to or less than the threshold value (zero). In the configuration example shown in FIG. 3, the threshold value is zero, but the threshold value may be a positive value other than zero. In the gate drive device 2, the output of the UVLO circuit is masked by the low-level second voltage V2.

[0040] The filter circuit composed of the resistor R4 and the capacitor C1 suppresses the transition of the first voltage V1 from the low level to the high level due to external noise. That is, the filter circuit composed of the resistor R4 and the capacitor C1 suppresses the transition from the state where the operating limit of the bandgap circuit 27 is not detected to the state where the operating limit of the bandgap circuit 27 is detected. Thereby, even when the voltage Vcc applied to the first terminal of the resistor R4 fluctuates due to external noise, it is possible to suppress the misdetection of the operating limit of the bandgap circuit 27.

[0041] <Application Example> FIG. 4 is a diagram showing the appearance of a vehicle. The vehicle X1 shown in FIG. 4 includes the motor system SYS1 described above.

[0042] The motor system SYS1 can be applied to various in-vehicle systems provided in the vehicle X1. Here, an example of applying the motor system SYS1 to a power window system as an example of an in-vehicle system will be described.

[0043] FIG. 5 is a schematic diagram showing a configuration example of a power window system to which the motor system SYS1 is applied. The power window system Y1 shown in FIG. 5 is a system for driving the window Y2, and includes the window Y2, the motor system Y3, and the regulator Y4.

[0044] The regulator Y4 is a so-called arm-type regulator, and is a mechanism for moving the window Y2 up and down by the rotational drive of the motor included in the motor system Y3. Note that the regulator is not limited to this, and may be, for example, a so-called wire-type regulator. The window Y2 is disposed, for example, before and after on both side surfaces of the vehicle X1.

[0045] In-vehicle systems to which the motor system SYS1 can be applied include, for example, a wide variety such as a power sunroof system and a power sliding door system.

[0046] The system to which the motor system SYS1 is applied is not limited to in-vehicle systems. The motor system SYS1 can be applied to, for example, a louver position adjustment system of an air conditioner, an opening / closing system of a shutter, and the like.

[0047] <Others> The configuration of the invention disclosed in this specification can be variously modified within the scope not departing from the gist of the invention in addition to the above-described embodiments. The above-described embodiments should be considered as illustrative in all respects and not restrictive, and the technical scope of the invention disclosed in this specification is shown not by the description of the above-described embodiments but by the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0048] For example, in the above-described embodiment, the motor was a two-phase motor, but the motor may be a three-phase motor. When the motor is a three-phase motor, the motor system may have a configuration including three half-bridge circuits.

[0049] A circuit that utilizes the reference voltage output from the bandgap circuit is not limited to the UVLO circuit. For example, the reference voltage output from the bandgap circuit may be utilized by an error amplifier provided in a power supply device, a light-emitting element driving device, etc. Therefore, a semiconductor integrated circuit device including a detection circuit and a bandgap circuit is not limited to a gate driving device, and may be, for example, a control device that controls a switching element of a switching power supply device, a control device that controls an output transistor of a linear power supply device, a light-emitting element driving device that drives a light-emitting element, etc.

[0050] Unlike the above-described embodiments, a part of a detection system including a detection circuit and a bandgap circuit may not be integrated and may be configured by discrete components.

[0051] <Appendix> An appendix is provided for the present disclosure in which specific configuration examples are shown in the above-described embodiments.

[0052] The detection circuit (28) of the present disclosure has a configuration (first configuration) in which a first current (I1) is a current output from a current source (26), a second current (I2) is a current consumed by a bandgap circuit (26), and based on a third current (I3) obtained by subtracting the second current from the first current, the operation limit of the bandgap circuit is detected.

[0053] According to the detection circuit of the first configuration, the operation limit of the bandgap circuit can be detected.

[0054] In the detection circuit of the first configuration, it may have a configuration (second configuration) in which the operation limit of the bandgap circuit is detected when the third current is equal to or less than a threshold value.

[0055] In the detection circuit having the first or second configuration, a filter circuit (R4, C1) may be provided which is configured to suppress a transition from a state in which the operating limit of the bandgap circuit is not detected to a state in which the operating limit of the bandgap circuit is detected (a third configuration).

[0056] The semiconductor integrated circuit device (2) of the present disclosure has a configuration (a fourth configuration) including a detection circuit having any of the first to third configurations and the bandgap circuit.

[0057] In the semiconductor integrated circuit device having the fourth configuration, a configuration including the current source (a fifth configuration) may be provided.

[0058] In the semiconductor integrated circuit device having the fifth configuration, a configuration in which the current source is a constant current source (a sixth configuration) may be provided.

[0059] The detection system (SYS2) of the present disclosure has a configuration (a seventh configuration) including a detection circuit having any of the first to third configurations and the bandgap circuit.

[0060] In the detection system having the seventh configuration, a configuration including the current source (an eighth configuration) may be provided.

[0061] In the detection system having the eighth configuration, a configuration in which the current source is a constant current source (a ninth configuration) may be provided.

[0062] The vehicle (X1) of the present disclosure has a configuration (a tenth configuration) including the semiconductor integrated circuit device having any of the fourth to sixth configurations or the detection system having any of the seventh to ninth configurations.

Explanation of Reference Numerals

[0063] 1 MCU 2 Gate driving device 20 Control logic unit 21 to 24 Gate driving circuit 25 Internal power supply circuit 26 Constant current source 27 Bandgap Circuit 28 Detection Circuit 29 UVLO Circuit 3 Motor C1 Capacitor CS1 Current Source INV1 Inverter M1~M4, Q1~Q8 Switching Elements Q11~Q13 NPN Bipolar Transistors Q14 PNP Bipolar Transistor Q15, Q16 NMOS Transistors R1~R4 Resistors SYS1 Motor System SYS2 Detection System X1 Vehicle Y1 Power Window System Y2 Window Y3 Motor System Y4 Regulator PWM1, PWM2, EN, VB, VCC, GND, VCP Terminals G1H, S1H, G1L, S1L, G2H, S2H, G2L, S2L Terminals

Claims

1. The first current is the current output from a current source, and the second current is the current consumed by a bandgap circuit. Based on a third current obtained by subtracting the second current from the first current, a detection circuit is configured to detect an operating limit of the bandgap circuit.

2. The detection circuit according to claim 1, wherein the detection circuit is configured to detect an operating limit of the bandgap circuit when the third current is equal to or less than a threshold value.

3. The detection circuit according to claim 1, further comprising a filter circuit configured to suppress a transition from a state where the operating limit of the bandgap circuit is not detected to a state where the operating limit of the bandgap circuit is detected.

4. A semiconductor integrated circuit device, comprising: the detection circuit according to claim 1; and the bandgap circuit.

5. The semiconductor integrated circuit device according to claim 4, further comprising the current source.

6. The semiconductor integrated circuit device according to claim 5, wherein the current source is a constant current source.

7. A detection system, comprising: the detection circuit according to claim 1; and the bandgap circuit.

8. The detection system according to claim 7, further comprising the current source.

9. The detection system according to claim 8, wherein the current source is a constant current source.

10. A vehicle, comprising the semiconductor integrated circuit device according to any one of claims 4 to 6 or the detection system according to any one of claims 7 to 9.

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