Semiconductor device and method for manufacturing the same

Abstract

To improve reliability of a semiconductor device.SOLUTION: A pad PD is formed on an interlayer insulating film IL, and an insulating film PA is formed to cover the interlayer insulating film IL and pad PD. An opening OP is formed in the insulating film PA to expose a portion of the pad PD. In the opening OP, a nickel plating film PL1 is formed on the pad PD, a gold plating film PL2a is formed on the nickel plating film PL1, and a gold plating film PL2b is formed on the gold plating film PL2a. The phosphorus concentration in the nickel plating film PL1 is equal to or more than 2 mass percent and equal to or less than 7 mass percent.SELECTED DRAWING: Figure 25

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having electrode pads and a method for manufacturing the same.

Background Art

[0002] An OPM (Over Pad Metal) film is formed on the electrode pads of a semiconductor device. Japanese Patent Application Laid-Open No. 2020-120133 (Patent Document 1) describes a technique using a laminated film of a nickel plating layer and a gold plating layer as the OPM film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device having pads and an OPM film, it is desired to improve the reliability.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes an electrode pad, a nickel plating film formed on the electrode pad at an opening of a passivation film, a first gold plating film formed on the nickel plating film, and a second gold plating film formed on the first gold plating film. The phosphorus concentration of the nickel plating film is 2 mass percent or more and 7 mass percent or less.

Effects of the Invention

[0007] According to one embodiment, the reliability of a semiconductor device can be improved.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Embodiments for Carrying Out the Invention

[0009] In the following embodiments, when necessary for convenience, the description may be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not independent of each other, and one is related to a part or all of the other as a modification, detail, supplementary explanation, etc. Further, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified or clearly considered otherwise in principle, it includes those substantially approximated or similar to the shape, etc. This also applies to the above numerical values and ranges.

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Also, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0011] Also, in the drawings used in the embodiments, hatching may be omitted even in sectional views for easy viewing of the drawings. Also, hatching may be added even in plan views for easy viewing of the drawings.

[0012] (Embodiment 1) <Regarding the structure of the semiconductor device> The semiconductor device of the present embodiment will be described with reference to the drawings.

[0013] FIG. 1 is a top view of the semiconductor device CP of the present embodiment. FIG. 2 is a bottom view of the semiconductor device CP of the present embodiment. FIGS. 3 and 4 are cross-sectional views of main parts of the semiconductor device CP of the present embodiment. The cross-sectional view taken along line A-A in FIG. 1 substantially corresponds to FIG. 3, and the cross-sectional view taken along line B-B in FIG. 1 substantially corresponds to FIG. 4.

[0014] As shown in FIGS. 1 to 4, the semiconductor device CP of the present embodiment includes a semiconductor substrate SB, an interlayer insulating film IL, a back surface electrode BE, a source pad PDS, a gate pad PDG, a gate wiring portion GEW, an insulating film PA, and a plating film PL. The semiconductor device CP further includes a trench gate electrode TG, an n-type semiconductor region NR formed in the semiconductor substrate SB, and a p-type semiconductor region PR formed in the semiconductor substrate SB.

[0015] The semiconductor substrate SB is made of, for example, n-type single-crystalline silicon into which an n-type impurity such as arsenic (As) has been introduced. A semiconductor substrate (so-called epitaxial wafer) having a substrate body made of an n-type single-crystalline silicon substrate and an epitaxial layer made of n-type single-crystalline silicon formed on the substrate body can also be used as the semiconductor substrate SB.

[0016] The semiconductor substrate SB has a main surface and a back surface located opposite to the main surface. An interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB, and a back surface electrode BE is formed on the back surface of the semiconductor substrate SB.

[0017] In the semiconductor substrate SB, a trench gate type MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) is formed. The trench gate type MISFET has a trench type gate structure. The trench type gate structure corresponds to a gate electrode structure embedded in a groove formed in the substrate.

[0018] The specific configuration of the trench gate type MISFET formed in the semiconductor substrate SB will be described below.

[0019] On the main surface of a semiconductor substrate SB, a trench gate type MISFET that constitutes a power transistor (power semiconductor device) is formed. Specifically, a plurality of unit transistor cells Q1 are formed on the main surface of the semiconductor substrate SB, and one power transistor is formed by connecting the plurality of unit transistor cells Q1 formed in the semiconductor substrate SB in parallel. Each unit transistor cell Q1 is composed of a trench gate type MISFET. Here, in the main surface of the semiconductor substrate SB, a planar region where a plurality of unit transistor cells Q1 that constitute the power transistor are formed is referred to as a transistor cell region.

[0020] The semiconductor substrate SB has a function as a drain region of the unit transistor cell Q1. A back surface electrode BE for the drain is formed on the back surface of the semiconductor substrate SB. The back surface electrode BE is formed over the entire back surface of the semiconductor substrate SB. The back surface electrode BE functions as a drain terminal. The back surface electrode BE is composed of, for example, a laminated film of a titanium (Ti) film in contact with the semiconductor substrate SB, a nickel (Ni) film on the titanium film, and a gold (Au) film or a silver (Ag) film on the nickel film.

[0021] A p-type semiconductor region PR is formed in the semiconductor substrate SB in the transistor cell region. The p-type semiconductor region PR has a function as a channel formation region of the unit transistor cell Q1.

[0022] An n-type semiconductor region (source region) NR is formed in the semiconductor substrate SB on the p-type semiconductor region PR. The n-type semiconductor region NR has a function as a source region of the unit transistor cell Q1. The p-type semiconductor region PR exists under the n-type semiconductor region NR. The semiconductor substrate SB intervening between the p-type semiconductor region PR and the back surface electrode BE maintains an n-type conductivity type and has a function as a drain region of the unit transistor cell Q1.

[0023] A groove (trench) TR is formed on the main surface of a semiconductor substrate SB, and a trench gate electrode TG is embedded in the groove TR via a gate insulating film GF. The trench gate electrode TG is made of a conductor film embedded in the groove TR of the semiconductor substrate SB, and is made of, for example, a doped polysilicon film. The gate insulating film GF is formed on the bottom surface and the side surface of the groove TR. The gate insulating film GF is made of, for example, a silicon oxide film. Although not shown, on the main surface of the semiconductor substrate SB, the grooves TR are formed, for example, in a striped or grid pattern in plan view.

[0024] Note that when referring to the plan view of the components of the semiconductor device CP, it corresponds to the case of viewing in a plane substantially parallel to the main surface of the semiconductor substrate SB constituting the semiconductor device CP.

[0025] The groove TR is formed so as to penetrate through the n-type semiconductor region NR and the p-type semiconductor region PR from the main surface of the semiconductor substrate SB. The bottom surface of the groove TR is deeper than the bottom surface of the n-type semiconductor region NR and deeper than the bottom surface of the p-type semiconductor region PR.

[0026] Next, the structure above the semiconductor substrate SB will be described.

[0027] An interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB so as to cover the trench gate electrode TG. The interlayer insulating film IL is made of, for example, a silicon oxide film.

[0028] The trench gate electrodes TG of the plurality of unit transistor cells Q1 are integrally connected in a region not shown in the cross-sectional views of FIGS. 3 and 4. A gate lead-out portion TGL formed integrally with the trench gate electrode TG is formed on the main surface of the semiconductor substrate SB outside the groove TR via the gate insulating film GF (see FIG. 4).

[0029] Contact holes CT1 and CT2 are formed in the interlayer insulating film IL. The contact hole CT1 is a contact hole for the source. In plan view, the contact hole CT1 is arranged between adjacent grooves TR.

[0030] Contact hole CT2 is a contact hole for the gate. Contact hole CT2 is disposed on gate lead-out portion TGL. A part of gate lead-out portion TGL is exposed from contact hole CT2.

[0031] On interlayer insulating film IL, source pad (electrode pad for source) PDS, gate pad (electrode pad for gate) PDG, and gate wiring portion GEW are formed. Source pad PDS, gate pad PDG, and gate wiring portion GEW are formed by patterned conductor film CD. Conductor film CD is made of a metal film mainly composed of aluminum (Al), specifically, an aluminum film or an aluminum alloy film.

[0032] Gate pad PDG and gate wiring portion GEW are integrally formed. Therefore, gate pad PDG and gate wiring portion GEW are electrically connected to each other. Source pad PDS is separated from gate pad PDG and gate wiring portion GEW.

[0033] A part of source pad PDS is embedded in contact hole CT1 for source. The portion of source pad PDS embedded in contact hole CT1 for source is referred to as the source via portion.

[0034] A part of gate wiring portion GEW is embedded in contact hole CT2 for gate. The portion of gate wiring portion GEW embedded in contact hole CT2 for gate is referred to as the gate via portion.

[0035] The gate via portion is in contact with gate lead-out portion TGL and is electrically connected. Gate pad PDG is electrically connected to trench gate electrodes TG of a plurality of unit transistor cells Q1 via gate wiring portion GEW, the gate via portion, and gate lead-out portion TGL.

[0036] In a plan view, the source pad PDS is formed so as to cover the transistor cell region.

[0037] The contact hole CT1 for the source penetrates the interlayer insulating film IL and the n-type semiconductor region NR and reaches the p-type semiconductor region PR. Therefore, the via portion for the source embedded in the contact hole CT1 for the source penetrates the interlayer insulating film IL and the n-type semiconductor region NR and reaches the p-type semiconductor region PR. Since the via portion for the source is in contact with both the n-type semiconductor region NR and the p-type semiconductor region PR, it is electrically connected to both the n-type semiconductor region NR and the p-type semiconductor region PR.

[0038] The source regions (n-type semiconductor regions NR) and channel formation regions (p-type semiconductor regions PR) of the plurality of unit transistor cells Q1 arranged in the transistor cell region are electrically connected to a common source pad PDS via a plurality of via portions for the source. In this case, the source pad PDS also serves as a source wiring for electrically connecting the source regions (n-type semiconductor regions NR) of the plurality of unit transistor cells Q1 to each other. It is also possible to form a source wiring for electrically connecting the source regions (n-type semiconductor regions NR) of the plurality of unit transistor cells Q1 to each other on the interlayer insulating film IL and form the source pad PDS in a layer above the source wiring. Similarly, a gate wiring portion GEW can be formed on the interlayer insulating film IL, and a gate pad PDG can be formed in a layer above the gate wiring portion GEW.

[0039] An insulating film PA is formed as a passivation film so as to cover a part of the source pad PDS, a part of the gate pad PDG, and the gate wiring portion GEW on the interlayer insulating film IL. The insulating film PA is the uppermost protective film of the semiconductor device CP. The insulating film PA is made of a resin film such as a polyimide resin, for example.

[0040] Openings OPS and OPG are formed in the insulating film PA. At least a part of the source pad PDS is exposed from the opening OPS of the insulating film PA. At least a part of the gate pad PDG is exposed from the opening OPG of the insulating film PA. A plating film PL is formed on the source pad PDS exposed from the opening OPS of the insulating film PA and on the gate pad PDG exposed from the opening OPG of the insulating film PA, respectively.

[0041] The plating film PL is an OPM film. The upper surface of the insulating film PA and the upper surface of the plating film PL constitute the upper surface of the semiconductor device CP. The surface of the back electrode BE constitutes the back surface of the semiconductor device CP. The gate wiring portion GEW is not exposed from the insulating film PA, and the entire gate wiring portion GEW is covered with the insulating film PA. The plating film PL is not formed on the gate wiring portion GEW.

[0042] The plating film PL is selectively formed on the source pad PDS exposed from the opening OPS of the insulating film PA and on the gate pad PDG exposed from the opening OPG. That is, in the opening OPS, the plating film PL is formed on the source pad PDS, and in the opening OPG, the plating film PL is formed on the gate pad PDG. The plating film PL is not formed on the source pad PDS covered with the insulating film PA and on the gate pad PDG covered with the insulating film PA.

[0043] The plating film PL is composed of a laminated film of a nickel (Ni) plating film PL1 and a gold (Au) plating film PL2 formed on the nickel plating film PL1.

[0044] The nickel plating film PL1 is formed in the opening OPS on the source pad PDS so as to be in contact with the source pad PDS, and in the opening OPG on the gate pad PDG so as to be in contact with the gate pad PDG. The gold plating film PL2 is formed on the nickel plating film PL1 so as to be in contact with the nickel plating film PL1.

[0045] The nickel plating film PL1 contains phosphorus (P). The phosphorus (P) concentration of the nickel plating film PL1 is 2 mass percent or more and 7 mass percent or less, preferably 2 mass percent or more and 5.7 mass percent or less, and more preferably 2 mass percent or more and 4.0 mass percent or less. Note that mass percent may also be referred to as weight percent.

[0046] The gold plating film PL2 is composed of a laminated film of a gold (Au) plating film PL2a formed on the nickel plating film PL1 and a gold (Au) plating film PL2b formed on the gold plating film PL2a. The gold plating film PL2a is a substitutional gold plating film formed by a substitutional Au (gold) plating process. The gold plating film PL2b is a reduction gold plating film formed by a reduction Au (gold) plating process. The gold plating film PL2a is formed on the nickel plating film PL1 so as to be in contact with the nickel plating film PL1. The gold plating film PL2b is formed on the gold plating film PL2a so as to be in contact with the gold plating film PL2a.

[0047] Therefore, the plating film PL is composed of a laminated film of the nickel plating film PL1, the gold plating film PL2a formed on the nickel plating film PL1, and the gold plating film PL2b formed on the gold plating film PL2a. The gold plating film PL2b is located at the uppermost layer of the plating film PL. The upper surface of the gold plating film PL2b constitutes the upper surface of the plating film PL.

[0048] In plan view, the source pad PDS is formed so as to cover the transistor cell region. For this reason, the area of the source pad PDS is larger than the area of the gate pad PDG. Therefore, the area of the opening OPS is larger than the area of the opening OPG. The planar shape of each of the openings OPG and OPS is, for example, rectangular.

[0049] The whole combination of the source pad PDS and the plating film PL on the source pad PDS is referred to as the bonding pad for source BPS. The whole combination of the gate pad PDG and the plating film PL on the gate pad PDG is referred to as the bonding pad for gate BPG.

[0050] Among the plating films PL, the nickel plating film PL1 has a function as a barrier layer (solder barrier layer) that prevents the components of the solder from diffusing through the plating film PL to the conductor film CD when performing solder connection to the bonding pad. The nickel plating film PL1 also has a function of ensuring the bonding strength of the solder. The gold plating film PL2 among the plating films PL is provided to prevent the oxidation of the nickel plating film PL1 and to improve the wettability of the solder.

[0051] When performing wire bonding to the bonding pad, the gold plating film PL2 has a function of facilitating the connection of the wire.

[0052] In the semiconductor device CP having such a configuration, the operating current of the power transistor flows between the source pad PDS and the back electrode BE for drain. That is, the operating current of the trench gate type MISFET formed in the transistor cell region flows in the thickness direction of the semiconductor substrate SB. For this reason, the trench gate type MISFET formed in the transistor cell region is a vertical transistor. Here, the vertical transistor corresponds to a transistor in which the operating current flows in the thickness direction of the semiconductor substrate SB.

[0053] In the present embodiment, the case where a trench gate type MISFET is applied as the semiconductor element formed on or in the semiconductor substrate SB has been described, but the present invention is not limited thereto, and other types of semiconductor elements can also be formed on or in the semiconductor substrate SB.

[0054] For example, a trench gate type IGBT can be formed on the semiconductor substrate SB instead of a trench gate type MISFET. When a trench gate type IGBT is applied, a p-type semiconductor region for a collector is formed near the back surface of the semiconductor substrate SB. When a trench gate type IGBT is applied, the back surface electrode BE functions as a collector electrode, the n-type semiconductor region NR functions as an n-type semiconductor region for an emitter, and the source pad PDS functions as an emitter pad (electrode pad for an emitter). The back surface electrode BE is composed of, for example, a laminated film of an aluminum silicon alloy (AlSi) film in contact with the semiconductor substrate SB, a nickel (Ni) film on the aluminum silicon alloy (AlSi) film, and a gold (Au) film or a silver (Ag) film on the nickel film.

[0055] An LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) can also be formed on the semiconductor substrate SB instead of a trench gate type MISFET.

[0056] The semiconductor device CP can also have bonding pads other than the source bonding pad BPS and the gate bonding pad BPG. In that case, each bonding pad is composed of a pad (electrode pad) made of the conductor film CD and the plating film PL formed on the pad.

[0057] When a wiring structure (multilayer wiring structure) including a plurality of wiring layers is formed on the main surface of the semiconductor substrate SB, the present embodiment can also be applied. In this case, pads are formed on the uppermost wiring layer among the plurality of wiring layers included in the wiring structure.

[0058] <Regarding the manufacturing process of the semiconductor device> The manufacturing process of the semiconductor device CP according to this embodiment will be described with reference to FIGS. 5 to 18. FIGS. 5 to 15, 17, and 18 are cross-sectional views of the main parts during the manufacturing process of the semiconductor device CP according to this embodiment. FIG. 16 is an explanatory diagram of the substitution reaction that occurs during the substitution Au plating process. In addition, in FIGS. 5, 6, 7, 8, 10, 12, 14, and 17, cross-sections corresponding to FIG. 3 above are shown. In FIGS. 9, 11, 13, 15, and 18, cross-sections corresponding to FIG. 4 above are shown.

[0059] As shown in FIG. 5, a semiconductor substrate SB (semiconductor wafer) made of, for example, n-type single-crystalline silicon is prepared. As the semiconductor substrate SB, an epitaxial wafer can also be used.

[0060] Next, as shown in FIG. 5, a groove TR is formed on the main surface of the semiconductor substrate SB. The groove TR can be formed using photolithography technology and etching technology.

[0061] Next, a gate insulating film GF made of a thin silicon oxide film or the like is formed on the side surfaces and bottom surface of the groove TR and on the main surface of the semiconductor substrate SB using, for example, the thermal oxidation method.

[0062] Next, a conductor film PS made of a polycrystalline silicon film or the like is formed on the main surface of the semiconductor substrate SB so as to fill the groove TR using a CVD method or the like.

[0063] Next, after forming a photoresist pattern (not shown) on a part of the conductor film PS, the conductor film PS is etched back using anisotropic etching technology. By this etch-back, the conductor film PS is left in the groove TR and under the photoresist pattern, and the other conductor film PS is removed. Then, the photoresist pattern is removed. As a result, as shown in FIG. 6, a trench gate electrode TG made of the conductor film PS remaining in the groove TR is formed. The gate lead-out portion TGL is formed by the conductor film PS remaining under the photoresist pattern.

[0064] Next, as shown in FIG. 7, a p-type semiconductor region PR is formed in the semiconductor substrate SB using an ion implantation method.

[0065] Next, an n-type semiconductor region NR is formed in the semiconductor substrate SB using an ion implantation method. The depth of the bottom surface of the p-type semiconductor region PR is shallower than the depth of the bottom surface of the trench TR. The depth of the bottom surface of the n-type semiconductor region NR is shallower than the depth of the bottom surface of the p-type semiconductor region PR. Therefore, the trench TR penetrates through the n-type semiconductor region NR and the p-type semiconductor region PR.

[0066] Next, as shown in FIG. 7, an interlayer insulating film IL is formed on the main surface of the semiconductor substrate SB so as to cover the trench gate electrode TG and the gate lead-out portion TGL.

[0067] Next, as shown in FIG. 8, by using a photoresist pattern (not shown) formed on the interlayer insulating film IL as an etching mask to etch the interlayer insulating film IL and the semiconductor substrate SB, a contact hole CT1 for the source is formed. The p-type semiconductor region PR and the n-type semiconductor region NR are exposed from the contact hole CT1 for the source.

[0068] Next, as shown in FIG. 9, by using another photoresist pattern (not shown) formed on the interlayer insulating film IL as an etching mask to etch the interlayer insulating film IL, a contact hole CT2 for the gate is formed. The gate lead-out portion TGL is exposed from the contact hole CT2 for the gate.

[0069] Next, as shown in FIGS. 8 and 9, a conductor film CD mainly composed of aluminum (Al) is formed in the contact holes CT1 and CT2 and on the interlayer insulating film IL using a sputtering method or the like.

[0070] Next, as shown in FIGS. 10 and 11, by patterning the conductor film CD using photolithography technology and etching technology, a source pad PDS, a gate pad PDG, and a gate wiring portion GEW are formed. The gate pad PDG and the gate wiring portion GEW are connected to each other and are integrally formed.

[0071] The source pad PDS is formed on the interlayer insulating film IL, and a part of the source pad PDS (source via portion) fills the inside of the contact hole CT1 for the source. The gate pad PDG and the gate wiring portion GEW are formed on the interlayer insulating film IL, and a part of the gate wiring portion GEW (gate via portion) fills the inside of the contact hole CT2 for the gate.

[0072] The source via portion can be formed in a process different from the source pad PDS forming process, and the gate via portion can be formed in a process different from the gate pad PDG forming process. In that case, after the contact holes CT1 and CT2 forming process and before the conductor film CD forming process, a conductive plug that fills the contact holes CT1 and CT2 is formed.

[0073] Next, as shown in FIGS. 10 and 11, an insulating film PA is formed as a passivation film so as to cover the source pad PDS, the gate pad PDG, and the gate wiring portion GEW on the interlayer insulating film IL.

[0074] Next, as shown in FIGS. 12 and 13, openings OPG and OPS are formed in the insulating film PA. For example, after forming the insulating film PA made of a photosensitive resin film, the openings OPG and OPS can be formed by exposing and developing the insulating film PA. Alternatively, after forming the insulating film PA made of a resin film, the insulating film PA can be etched using a photoresist pattern (not shown) on the insulating film PA as an etching mask to form the openings OPG and OPS.

[0075] Next, as shown in FIGS. 14 and 15, a plating film PL is formed on the source pad PDS exposed from the opening OPS of the insulating film PA and on the gate pad PDG exposed from the opening OPG of the insulating film PA by using a plating method.

[0076] The plating film PL is composed of a laminated film of a nickel plating film PL1, a gold plating film PL2a on the nickel plating film PL1, and a gold plating film PL2b on the gold plating film PL2a. Therefore, the plating film PL forming step includes a nickel plating film PL1 forming step, a gold plating film PL2a forming step, and a gold plating film PL2b forming step. The gold plating film PL2a forming step is performed after the nickel plating film PL1 forming step, and the gold plating film PL2b forming step is performed after the gold plating film PL2a forming step. The nickel plating film PL1, the gold plating film PL2a, and the gold plating film PL2b are each formed by using a plating method, specifically, by using an electroless plating method.

[0077] The nickel plating film PL1 is formed on the source pad PDS in contact with the source pad PDS at the opening OPS, and is formed on the gate pad PDG in contact with the gate pad PDG at the opening OPG.

[0078] The nickel plating film PL1 contains phosphorus (P). Therefore, the plating solution used in the nickel plating film PL1 forming step contains a nickel compound and a phosphorus compound. By adjusting the composition of the plating solution to be used, etc., the phosphorus (P) concentration of the nickel plating film PL1 can be controlled. The phosphorus (P) concentration of the nickel plating film PL1 is 2 mass percent or more and 7 mass percent or less, preferably 2 mass percent or more and 5.7 mass percent or less, and more preferably 2 mass percent or more and 4.0 mass percent or less.

[0079] The gold plating film PL2a is formed by a displacement Au (gold) plating process. In the gold plating film PL2a forming step, a plating solution for displacement Au plating is used. When the surface of the nickel plating film PL1 comes into contact with the plating solution for displacement Au plating, the gold plating film PL2a is formed on the surface of the nickel plating film PL1.

[0080] In the displacement Au plating process, the Au (gold) ions in the plating solution receive electron supply by substitution with the nickel (Ni) contained in the nickel plating film PL1, and are deposited as a gold (Au) film on the surface of the nickel plating film PL1, thereby forming the gold plating film PL2a.

[0081] FIG. 16 is an explanatory diagram of the substitution reaction that occurs in the displacement Au plating process. As shown in the reaction formula shown in FIG. 16, the nickel (Ni) contained in the nickel plating film PL1 dissolves into the plating solution to become nickel (Ni) ions, and the Au (gold) ions in the plating solution are reduced by the electrons generated therewith. The reduced gold (Au) is deposited as a film on the nickel plating film PL1, thereby forming the gold plating film PL2a.

[0082] The gold plating film PL2b is formed by a reduction Au (gold) plating process. In the gold plating film PL2b forming step, a plating solution for reduction Au plating is used. When the surface of the gold plating film PL2a comes into contact with the plating solution for reduction Au plating, the gold plating film PL2b is formed on the surface of the gold plating film PL2a.

[0083] In the reduction Au plating process, the Au (gold) ions in the plating solution receive electron supply from the reducing agent in the plating solution, and are deposited as a gold (Au) film on the surface of the gold plating film PL2a, thereby forming the gold plating film PL2b.

[0084] Next, if necessary, the back surface of the semiconductor substrate SB is ground or polished to reduce the thickness of the semiconductor substrate SB.

[0085] Next, as shown in FIGS. 17 and 18, a back electrode BE is formed on the back surface of the semiconductor substrate SB. The back electrode BE can be formed, for example, by using a sputtering method.

[0086] Thereafter, the semiconductor substrate SB is cut by dicing. In this way, a semiconductor device CP as a semiconductor chip can be manufactured.

[0087] <Regarding the structure of the semiconductor package> FIG. 19 is a cross-sectional view showing an example of a semiconductor package PKG in which the semiconductor device CP is used.

[0088] The semiconductor chip CP1 used in the semiconductor package PKG shown in FIG. 19 is the same as the semiconductor device CP shown in FIGS. 1 to 4 above. Therefore, here, the repeated description of the configuration of the semiconductor chip CP1 will be omitted.

[0089] As shown in FIG. 19, the semiconductor package PKG includes a semiconductor chip CP1, a die pad DP, a metal plate (conductor plate, clip) MP, leads LD, conductive wires (bonding wires) WA, and a sealing portion (sealing resin portion) MR.

[0090] The sealing portion MR is made of a resin material such as a thermosetting resin material and may contain a filler or the like.

[0091] The leads LD are made of a metal material such as copper (Cu) or a copper alloy. A part (inner lead portion) of the leads LD is sealed within the sealing portion MR, and another part (outer lead portion) of the leads LD protrudes outside the sealing portion MR from the side surface of the sealing portion MR.

[0092] Note that the semiconductor package PKG of this embodiment has a structure in which the outer lead portion of the lead LD protrudes from the side surface of the sealing portion MR. Although the following description is based on this structure, it is not limited to this structure. For example, a configuration (QFN type configuration) in which the lead LD hardly protrudes from the side surface of the sealing portion MR and a part of the lead LD is exposed on the lower surface of the sealing portion MR can also be adopted.

[0093] A semiconductor chip CP1 is mounted on the upper surface of the die pad DP. The die pad DP is a chip mounting portion for mounting the semiconductor chip CP1. The die pad DP is made of a metal material such as copper (Cu) or a copper alloy.

[0094] The semiconductor chip CP1 is disposed on the upper surface of the die pad DP via a conductive bonding material (die bonding material) BD1 such that the back surface electrode BE of the semiconductor chip CP1 faces the upper surface of the die pad DP via the bonding material BD1. The bonding material BD1 is made of, for example, solder, silver (Ag) paste, or sintered Ag (sintered silver). Therefore, the back surface electrode BE of the semiconductor chip CP1 is electrically connected to the die pad DP via the conductive bonding material BD1. The semiconductor chip CP1 is sealed within the sealing portion MR and is not exposed from the sealing portion MR.

[0095] The bonding pad BPG for the gate of the semiconductor chip CP1 and the inner lead portion of the lead LD are electrically connected via a wire WA which is a conductive connection member. Specifically, one end of the wire WA is connected to the bonding pad BPG for the gate of the semiconductor chip CP1, and the other end of the wire WA is connected to the inner lead portion of the lead LD. For this reason, one end of the wire WA is connected to the gold plating film PL2b of the uppermost layer of the bonding pad BPG for the gate. The outer lead portion of the lead LD functions as an external terminal electrically connected to the bonding pad BPG for the gate of the semiconductor chip CP1. The wire WA is a conductive wire, and preferably made of a metal wire such as a gold (Au) wire, a copper (Cu) wire, or an aluminum (Al) wire. The wire WA is sealed within the sealing portion MR and is not exposed from the sealing portion MR.

[0096] A metal plate MP is joined and fixed to the bonding pad BPS for the source of the semiconductor chip CP1 via a conductive joining material BD2. The joining material BD2 is made of, for example, solder. The metal plate MP is electrically connected to the bonding pad BPS for the source of the semiconductor chip CP1 via the conductive joining material BD2. For this reason, the metal plate MP is connected to the gold plating film PL2b of the uppermost layer of the bonding pad BPS for the source via the joining material BD2.

[0097] A part of the metal plate MP is exposed from the sealing portion MR. The metal plate MP exposed from the sealing portion MR functions as an external terminal electrically connected to the bonding pad BPS for the source of the semiconductor chip CP1.

[0098] The metal plate MP is made of a metal material such as copper (Cu) or a copper (Cu) alloy. The metal plate MP can also be formed of aluminum (Al), an aluminum (Al) alloy, silver (Ag) or a silver (Ag) alloy. The width of the metal plate MP is larger than the diameter of the wire WA. Therefore, the resistance of the metal plate MP is larger than the resistance of the wire WA. Since the metal plate MP is connected to the source bonding pad BPS of the semiconductor chip CP1, the on-resistance of the power transistor formed in the semiconductor chip CP1 can be reduced. Accordingly, in the semiconductor package PKG, the conduction loss can be reduced.

[0099] The semiconductor package PKG further has a source lead (not shown), and the metal plate MP can also be electrically connected to the source lead via a conductive bonding material. In that case, the source lead functions as an external terminal electrically connected to the source bonding pad BPS of the semiconductor chip CP1. In this case, the metal plate MP is not exposed from the sealing portion MR.

[0100] The lower surface of the die pad DP is exposed from the lower surface of the sealing portion MR. The sealing portion MR exposed from the lower surface of the sealing portion MR functions as an external terminal electrically connected to the back surface electrode BE of the semiconductor chip CP1. The conduction current (on-current) of the power transistor formed in the semiconductor chip CP1 mainly flows between the metal plate MP and the die pad DP, but by using the metal plate MP in the conduction path, the conduction loss can be reduced.

[0101] The heat generated during the operation of the semiconductor chip CP1 can be mainly dissipated to the outside of the semiconductor package PKG through the bonding material BD1 and the die pad DP from the back surface of the semiconductor chip CP1.

[0102] <Regarding the manufacturing process of the semiconductor package> The manufacturing process of the semiconductor package PKG will be described.

[0103] Prepare a lead frame integrally having a die pad DP and a lead LD. In the lead frame, the die pad DP and the lead LD are integrally connected to a frame (not shown) of the lead frame, respectively.

[0104] Next, perform a die bonding process to mount a semiconductor chip CP1 on the upper surface of the die pad DP of the lead frame via a conductive bonding material BD1. Thereby, the back electrode BE of the semiconductor chip CP1 is bonded to the upper surface of the die pad DP via the conductive BD1. The bonding material BD1 is a die bonding material. Solder, silver (Ag) paste, or sintered Ag (sintered silver) can be used as the bonding material BD1.

[0105] The die bonding process includes a heat treatment process. When the bonding material BD1 is solder, the heat treatment process is a solder reflow process. When the bonding material BD1 is silver paste, the heat treatment process is a heat treatment process for curing or sintering the silver paste.

[0106] Next, perform a wire bonding process to connect between the gate bonding pad BPG of the semiconductor chip CP1 and the lead LD of the lead frame via a wire WA. At this time, one end of the wire WA is connected to the uppermost gold plating film PL2b of the gate bonding pad BPG. Note that the wire bonding process can also be performed after a process of bonding a metal plate MP to the source bonding pad BPS of the semiconductor chip CP1.

[0107] Next, bond a metal plate MP to the source bonding pad BPS of the semiconductor chip CP1 via a conductive bonding material BD2. The metal plate MP is connected to the uppermost gold plating film PL2b of the source bonding pad BPS via the bonding material BD2.

[0108] Next, a molding process is performed to form the sealing portion MR. Thereafter, the die pad DP and the lead LD are separated from the lead frame, and the outer lead portion of the lead LD is bent as necessary. Thus, the semiconductor package PKG can be manufactured.

[0109] Although the case where the semiconductor package PKG has one semiconductor chip CP1 has been described, the present invention is not limited thereto, and the semiconductor package PKG may have a plurality of semiconductor chips.

[0110] <Regarding the process of consideration> The inventor is considering using a laminated film of a nickel plating film and a gold plating film as the OPM film formed on the pad. Compared with the case of using a laminated film of a nickel plating film, a palladium plating film, and a gold plating film as the OPM film, when using a laminated film of a nickel plating film and a gold plating film, advantages such as suppressing the formation cost of the OPM film can be obtained. In addition, as the die bonding material, a bonding material (silver paste) having a sintering temperature of a high temperature (about 260 degrees Celsius to 300 degrees Celsius) is being considered. For this reason, an OPM film that can withstand heat treatment at a high temperature of about 300 degrees Celsius is being considered.

[0111] FIG. 20 is a cross-sectional view of a main part of a semiconductor device according to a first study example studied by the inventor.

[0112] In FIG. 20 and FIGS. 21, 22, 23, 24, 25, 28, and 29 described later, a pad (electrode pad) PD mainly made of aluminum (Al) is formed on the interlayer insulating film IL, and an insulating film (passivation film) PA is formed so as to cover the interlayer insulating film IL and the pad PD. An opening OP is formed in the insulating film PA so as to expose a part of the pad PD. The pad PD corresponds to the source pad PDS or the gate pad PDG, and the opening OP corresponds to the opening OPS or the opening OPG.

[0113] In the case of the first study example, as shown in FIG. 20, on the pad PD at the opening OP of the insulating film PA, an OPM film PL100 is formed. The OPM film PL100 is a laminated film composed of a nickel plating film PL101 formed on the pad PD and a gold plating film PL102 formed on the nickel plating film PL101. The nickel plating film PL101 has a higher phosphorus concentration than the nickel plating film PL1 of the present embodiment. For example, the phosphorus concentration of the nickel plating film PL101 is about 9 mass percent.

[0114] According to the study by the present inventor, in the case of the first study example, it was found that the following problems occur.

[0115] Due to various heating processes performed after the formation process of the OPM film, there is a risk of cracks occurring in the nickel plating film PL101. FIG. 21 shows a state in which cracks CR have occurred in the nickel plating film PL101 in the semiconductor device of the first study example.

[0116] The reason for the occurrence of cracks CR in the nickel plating film PL101 is that when the nickel plating film PL101 is heated to a high temperature, an Ni3P alloy is generated in the nickel plating film PL101, making the nickel plating film PL101 brittle and prone to cracks CR. The high-temperature heating processes that cause the occurrence of cracks CR include the sputtering process for forming the back electrode BE, the heat treatment process for improving the bonding property between the semiconductor substrate SB and the back electrode BE, the die bonding process for mounting the semiconductor chip on the die pad, or the bonding process for bonding the bonding pad BPS for the source and the metal plate MP with solder or the like. The occurrence of cracks CR in the nickel plating film PL101 reduces the reliability of the semiconductor device.

[0117] <Regarding the main features and effects> The inventor of the present invention studied the phosphorus concentration of the nickel plating film constituting the OPM film. As a result, by reducing the phosphorus concentration of the nickel plating film, even when the nickel plating film is heated to a high temperature, the formation of the Ni3P alloy in the nickel plating film can be suppressed or prevented, so that it was found that the generation of cracks in the nickel plating film can be suppressed or prevented.

[0118] Therefore, in the present embodiment, the phosphorus concentration of the nickel plating film PL1 is lowered. Specifically, the phosphorus concentration of the nickel plating film PL1 is 2 mass percent or more and 7 mass percent or less, preferably 2 mass percent or more and 5.7 mass percent or less, and more preferably 2 mass percent or more and 4.0 mass percent or less.

[0119] Thereby, due to various heating processes performed after the formation process of the OPM film, the formation of the Ni3P alloy in the nickel plating film PL1 can be suppressed or prevented. As a result, the occurrence of cracks in the nickel plating film PL1 can be suppressed or prevented. Therefore, the reliability of the semiconductor device can be improved.

[0120] However, according to the study by the inventor of the present invention, when the phosphorus concentration of the nickel plating film PL1 is lowered, it was found that a low-density layer (nickel low-density layer) LW is formed in the nickel plating film PL1 near the interface between the nickel plating film PL1 and the gold plating film on the nickel plating film PL1.

[0121] FIGS. 22 and 23 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of the second study example studied by the inventor of the present invention. FIG. 22 shows a state before forming a gold plating film on the nickel plating film PL1 after forming the nickel plating film PL1. FIG. 23 shows a state in which a gold plating film PL202 is formed on the nickel plating film PL1.

[0122] In the case of the second study example, as can also be seen from FIGS. 22 and 23, in the opening OP of the insulating film PA, an OPM film PL200 is formed on the pad PD. The OPM film PL200 is composed of a laminated film of a nickel plating film PL1 formed on the pad PD and a gold plating film PL202 formed on the nickel plating film PL1. The gold plating film PL202 is formed by a displacement Au plating process. In the case of the second study example, after forming the gold plating film PL202 by the displacement Au plating process, a gold plating film by a reduction Au treatment is not formed on the gold plating film PL202.

[0123] As shown in FIG. 23, in the vicinity of the interface between the nickel plating film PL1 and the gold plating film PL202, a low-density layer LW is formed in a layered (continuous) manner in the nickel plating film PL1. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1 under the low-density layer LW. As shown in FIG. 22, at the stage of forming the nickel plating film PL1 by the nickel plating process, the low-density layer LW is not formed. When forming a gold plating film by a reduction Au plating process on the nickel plating film PL1, the low-density layer LW is formed. The reason for the formation of the low-density layer LW is that during the reduction Au plating process, nickel atoms elute from the surface layer portion of the nickel plating film PL1 into the plating solution to become nickel ions. Due to the elution of nickel from the surface layer portion of the nickel plating film PL1 into the plating solution, a low-density layer LW with a low density of nickel atoms is formed in the surface layer portion of the nickel plating film PL1.

[0124] The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. Therefore, as in the first study example above, when the phosphorus concentration of the nickel plating film PL101 is high, nickel is less likely to elute from the nickel plating film PL101 into the plating solution during the reduction Au plating process for forming a gold plating film on the nickel plating film PL101. Therefore, as in the first study example above, when the phosphorus concentration of the nickel plating film PL101 is high, it is difficult to form a low-density layer LW in the nickel plating film PL101 in the vicinity of the interface between the nickel plating film PL101 and the gold plating film PL102.

[0125] However, when the phosphorus concentration of the nickel plating film PL1 is low as in the present embodiment and the second study example described above, nickel is likely to elute from the nickel plating film PL1 into the plating solution during the reduction Au plating process for forming the gold plating film on the nickel plating film PL1. As a result, the low-density layer LW is likely to be formed in the surface layer portion of the nickel plating film PL1.

[0126] The wire WA or the metal plate MP is connected to the bonding pad including the pad PD and the OPM film. When the low-density layer LW is formed in the OPM film, the connection strength of the wire WA or the metal plate MP may decrease. For example, peeling starting from the low-density layer LW may cause the wire WA or the metal plate MP connected to the bonding pad to peel off. This reduces the reliability of the semiconductor device. This peeling is more likely to occur as the thickness of the low-density layer LW increases. Therefore, it is desirable to suppress the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 during the reduction Au plating process for forming the gold plating film on the nickel plating film PL1.

[0127] In order to suppress the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1, it is effective to suppress the thickness of the gold plating film formed on the nickel plating film PL1 by the reduction Au plating process. If the thickness of the gold plating film formed by the reduction Au plating process is small, the amount of nickel eluting from the nickel plating film PL1 into the plating solution during the reduction Au plating process decreases, so that the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 becomes thin.

[0128] FIG. 24 is a cross-sectional view of a main part of a semiconductor device according to a third study example examined by the present inventor.

[0129] In the case of the third study example, as shown in FIG. 24, on the pad PD at the opening OP of the insulating film PA, an OPM film PL300 is formed. The OPM film PL300 is composed of a laminated film of a nickel plating film PL1 formed on the pad PD and a gold plating film PL302 formed on the nickel plating film PL1. Similar to the gold plating film PL202 in the second study example, the gold plating film PL302 in the third study example is also formed by a substitution Au plating process. However, the thicknesses of the gold plating film PL202 in the second study example and the gold plating film PL302 in the third study example are different from each other, and the thickness of the gold plating film PL302 is smaller than the thickness of the gold plating film PL202. Similar to the second study example, also in the third study example, after forming the gold plating film PL302 by the substitution Au plating process, a gold plating film by a reduction Au treatment is not formed on the gold plating film PL302.

[0130] Reflecting that the thickness of the gold plating film PL302 in the third study example is smaller than the thickness of the gold plating film PL202 in the second study, the thickness of the low-density layer LW formed in the third study example (FIG. 24) is smaller than the thickness of the low-density layer LW formed in the second study example (FIG. 23). For this reason, compared with the second study example (FIG. 23), in the third study example (FIG. 24), the occurrence of peeling starting from the low-density layer LW can be suppressed, and a decrease in the connection strength of the wire WA or the metal plate MP due to the low-density layer LW can be prevented.

[0131] However, reflecting that the thickness of the gold plating film PL302 in the third study example is smaller than the thickness of the gold plating film PL202 in the second study, in the third study example (FIG. 24), in various heating processes performed after the formation process of the OPM film, there is a concern that nickel (Ni) in the nickel plating film PL1 passes through the gold plating film PL302 and gushes out onto the surface of the gold plating film PL302. As the high-temperature heating process that causes nickel to gush out onto the surface of the gold plating film PL302, there are the sputtering process for forming the back electrode BE, or the die bonding process for mounting the semiconductor chip on the die pad. When nickel gushes out onto the surface of the gold plating film PL302, the connection strength of the wire WA or the metal plate MP to the bonding pad decreases.

[0132] Therefore, in the case of the second study example (FIG. 23) in which a thick gold plating film PL202 is formed on the nickel plating film PL1, a thick low-density layer LW is formed in the surface layer portion of the nickel plating film PL1, whereby the connection strength of the wire WA or the metal plate MP decreases. On the other hand, in the case of the third study example (FIG. 24) in which a thin gold plating film PL302 is formed on the nickel plating film PL1, nickel gushes out onto the surface of the gold plating film PL302, whereby the connection strength of the wire WA or the metal plate MP decreases. Therefore, in both the case of the second study example (FIG. 23) and the case of the third study example (FIG. 24), the connection strength of the wire WA or the metal plate MP decreases. This reduces the reliability of the semiconductor device.

[0133] FIG. 25 is a cross-sectional view of the main part of the semiconductor device of the present embodiment. Also in the present embodiment, as shown in FIG. 25, in the vicinity of the interface between the nickel plating film PL1 and the gold plating film PL2a, a low-density layer LW is formed in a layer-like (continuous) manner in the nickel plating film PL1. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1 below the low-density layer LW.

[0134] In the present embodiment, a gold plating film PL2a is formed on a nickel plating film PL1 by a substitution Au plating process, and a gold plating film PL2b is formed on the gold plating film PL2a by a reduction Au plating process. By forming the gold plating film PL2 on the nickel plating film PL1 as a laminate film of the gold plating film PL2a and the gold plating film PL2b, the thickness of the gold plating film PL2 can be increased while suppressing the thickness of the gold plating film PL2a. By being able to suppress the thickness of the gold plating film PL2a, the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 can be suppressed, and by being able to increase the thickness of the gold plating film PL2 by forming the gold plating film PL2b, the emergence of nickel onto the surface of the gold plating film PL2 can be suppressed or prevented. Thereby, when the wire WA or the metal plate MP is connected to the bonding pad composed of the pad PD and the plating film PL, the connection strength of the wire WA or the metal plate MP can be improved. As a result, the reliability of the semiconductor device can be improved.

[0135] For example, assume that the thickness of the gold plating film PL2a in the present embodiment (FIG. 25) is the same as the thickness of the gold plating film PL302 in the third study example, and the thickness of the gold plating film PL2 in the present embodiment (FIG. 25) is the same as the thickness of the gold plating film PL202 in the third study example. In this case, in the third study example (FIG. 24) and the present embodiment (FIG. 25), the thicknesses of the low-density layers LW formed in the surface layer portion of the nickel plating film PL1 are the same as each other. Therefore, compared with the second study example (FIG. 23), in the present embodiment (FIG. 25), the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film PL1 can be suppressed, so that the occurrence of peeling starting from the low-density layer LW can be suppressed, and the decrease in the connection strength of the wire WA or the metal plate MP due to the low-density layer LW can be prevented. Further, compared with the third study example (FIG. 24), in the present embodiment (FIG. 25), the total thickness of the gold plating film formed on the nickel plating film PL1 can be increased, so that the emergence of nickel on the surface of the gold plating film can be suppressed, and the decrease in the connection strength of the wire WA or the metal plate MP due to the emergence of nickel can be prevented. As a result, compared with the second study example (FIG. 23) and the third study example (FIG. 24), in the present embodiment (FIG. 25), when the wire WA or the metal plate MP is connected to the bonding pad composed of the pad PD and the OPM film, the connection strength of the wire WA or the metal plate MP can be improved. As a result, the reliability of the semiconductor device can be improved.

[0136] If it were possible to directly form a reduced Au plating film on the nickel plating film PL1 without forming a substitution Au plating film on the nickel plating film PL1, the formation of the low-density layer LW in the surface layer portion of the nickel plating film PL1 could be prevented. However, it is difficult to directly form a reduced Au plating film on the nickel plating film PL1.

[0137] Therefore, the gold plating film PL2a formed to contact the nickel plating film PL1 is formed by a displacement Au plating process. Thereby, the gold plating film PL2a can be easily and accurately formed on the nickel plating film PL1. Then, a gold plating film PL2b is formed on the gold plating film PL2a by a reduction plating process. Thereby, the gold plating film PL2b can be easily and accurately formed on the gold plating film PL2a, and the thickness of the gold plating film PL2 can be increased. The gold plating film PL2b is formed to increase the thickness of the entire gold plating film PL2 without increasing the thickness of the low-density layer LW. By forming the gold plating film PL2b on the gold plating film PL2a, the thickness of the gold plating film PL2 can be increased while suppressing the thickness of the low-density layer LW, so that the connection strength of the wire WA or the metal plate MP can be improved. As a result, the reliability of the semiconductor device can be improved.

[0138] In the present embodiment, the gold plating film PL2a is formed by a displacement Au plating process so as to be directly formed on the nickel plating film PL1. However, since the low-density layer LW is formed during the formation of the gold plating film PL2a, it is preferable that the gold plating film PL2a is not thick. On the other hand, since the gold plating film PL2b is formed to ensure the thickness of the gold plating film PL2, it is preferable that the gold plating film PL2b is thick. Therefore, in the present embodiment, it is preferable to allocate more than half of the thickness of the gold plating film PL2 to the gold plating film PL2b and allocate less than half of the thickness of the gold plating film PL2 to the gold plating film PL2a. In other words, the thickness of the gold plating film PL2b is preferably equal to or greater than the thickness of the gold plating film PL2a. Thereby, the thickness of the gold plating film PL2 can be increased while suppressing the thickness of the low-density layer LW, so that the connection strength of the wire WA or the metal plate MP can be improved. As a result, the reliability of the semiconductor device can be improved.

[0139] The reason for thinning the gold plating film PL2a is to reduce the thickness of the low-density layer LW formed during the formation of the gold plating film PL2a. The thinner the gold plating film PL2a, the thinner the low-density layer LW. In order to improve the connection strength of the wire WA or the metal plate MP to the bonding pad, the thickness of the low-density layer LW is preferably 20 nanometers or less. Therefore, it is preferable to set the thickness of the gold plating film PL2a so that the thickness of the low-density layer LW becomes 20 nanometers or less.

[0140] However, if the thickness of the gold plating film PL2a is too small, it becomes difficult to form the gold plating film PL2b by the reduction Au plating treatment after the formation of the gold plating film PL2a. From this perspective, the thickness of the gold plating film PL2a is preferably 10 nanometers or more.

[0141] If the thickness of the gold plating film PL2 is too small, there is a concern that nickel (Ni) in the nickel plating film PL1 may pass through the gold plating film PL2 and emerge on the surface of the gold plating film PL2 in various heating processes performed after the plating film PL forming process. From this perspective, the thickness of the gold plating film PL2 is preferably 40 nanometers or more. On the other hand, if the thickness of the gold plating film PL2 is too large, the time required for the gold plating film PL2 forming process becomes long, and the cost for forming the gold plating film PL2 also increases. From this perspective, the thickness of the gold plating film PL2 is preferably 100 nanometers or less.

[0142] Therefore, the thickness of the gold plating film PL2b is preferably equal to or greater than the thickness of the gold plating film PL2a. However, the thickness of the gold plating film PL2a is more preferably 10 nanometers or more. More preferably, the total thickness of the gold plating film PL2a and the gold plating film PL2b is 40 nanometers or more and 100 nanometers or less. The thickness of the gold plating film PL2a depends on the total thickness of the gold plating film PL2, but is preferably about 10 nanometers or more and 35 nanometers or less.

[0143] The thickness of the nickel plating film PL1 is larger than that of the gold plating film PL2, preferably 1 micrometer or more and 6 micrometers or less.

[0144] FIG. 26 is a graph showing the correlation between the thickness of the low-density layer LW formed in the surface layer portion of the nickel plating film and the phosphorus concentration of the nickel plating film when a 50-nanometer replacement gold plating film is formed on the nickel plating film by replacement gold plating treatment. A reduction gold plating film is not formed on the replacement gold plating film. The horizontal axis of the graph in FIG. 26 corresponds to the phosphorus concentration of the nickel plating film. The vertical axis of the graph in FIG. 26 corresponds to the thickness of the low-density layer LW formed in the surface layer portion (near the interface between the nickel plating film and the gold plating film) of the nickel plating film.

[0145] From the graph in FIG. 26, it can be seen that as the phosphorus concentration of the nickel plating film decreases, the thickness of the low-density layer LW tends to increase, and when the phosphorus concentration of the nickel plating film is 7 mass% or less, the thickness of the low-density layer LW exceeds 20 nanometers. When the thickness of the low-density layer LW exceeds 20 nanometers, the connection strength between the wire or metal plate and the bonding pad decreases, and there is a risk of peeling of the wire or metal plate. Therefore, it is desirable that the thickness of the low-density layer LW be 20 nanometers or less.

[0146] In this embodiment, by configuring the gold plating film constituting the OPM film as a laminated film of a replacement gold plating film (PL2a) and a reduction gold plating film (PL2b), even when the phosphorus concentration of the nickel plating film is 7 mass% or less, the thickness of the low-density layer LW can be suppressed, and the thickness of the low-density layer LW can be suppressed to 20 nanometers or less. For example, even when the thickness of the nickel plating film is 50 nanometers and the phosphorus concentration of the nickel plating film is 7 mass% or less, the thickness of the low-density layer LW can be suppressed to 20 nanometers or less. Therefore, when the phosphorus concentration of the nickel plating film is 7 mass% or less, applying this embodiment has a great effect.

[0147] Figure 27 is a table showing the correlation between the phosphorus concentration of the nickel plating film and the heat resistance of the nickel plating film in the case of using an OPM film composed of a laminated film of a nickel plating film and a gold plating film on the nickel plating film. In the table of Figure 27, for each of the cases where the phosphorus concentration of the nickel plating film is 9 mass%, the phosphorus concentration of the nickel plating film is 5.7 mass%, and the phosphorus concentration of the nickel plating film is 4 mass%, the results of examining the heat resistance of the nickel plating film are shown. In the table of Figure 27, when the OPM film is heat-treated at various heat treatment temperatures, a cross mark indicates the case where a crack occurs in the OPM film when a needle is applied to the OPM film, and a circle mark indicates the case where no crack occurs in the OPM film. The presence or absence of cracks was confirmed by observation with a microscope.

[0148] From the table in Figure 27, it can be seen that when the phosphorus concentration of the nickel plating film is 9 mass%, cracks in the nickel plating film can be prevented during heat treatment if the heat treatment temperature is 290 °C or lower. Also, when the phosphorus concentration of the nickel plating film is 5.7 mass%, it can be seen that cracks in the nickel plating film can be prevented during heat treatment if the heat treatment temperature is 315 °C or lower. Also, when the phosphorus concentration of the nickel plating film is 4 mass%, it can be seen that cracks in the nickel plating film can be prevented during heat treatment if the heat treatment temperature is 330 °C or lower. That is, the lower the phosphorus concentration of the nickel plating film, the better the heat resistance of the nickel plating film. The reason is that by reducing the phosphorus concentration of the nickel plating film, even when the nickel plating film is heated to a high temperature, the formation of the Ni3P alloy in the nickel plating film can be suppressed, thereby suppressing the generation of cracks in the nickel plating film.

[0149] The inventor is considering using a bonding material (silver paste) with a sintering temperature of high temperature (about 260 degrees Celsius to 300 degrees Celsius) as the die bonding material (bonding material BD1). For this reason, an OPM film that can withstand heat treatment at a high temperature of about 300 degrees Celsius is being considered. When the phosphorus concentration of the nickel plating film is 5.7 mass percent, even if heat treatment at 315 degrees Celsius is performed, ensuring a 5 percent margin with respect to 300 degrees Celsius, which is the maximum temperature of the heat treatment, no cracks will occur in the nickel plating film. When the phosphorus concentration of the nickel plating film is 4.0 mass percent, even if heat treatment at 330 degrees Celsius is performed, ensuring a 10 percent margin with respect to 300 degrees Celsius, which is the maximum temperature of the heat treatment, no cracks will occur in the nickel plating film. Further, by improving the heat resistance of the OPM film, in addition to the die bonding process and the bonding process of the bonding pad for the source, the occurrence of cracks in the sputtering process for forming the back electrode BE and the heat treatment process for improving the bonding property between the semiconductor substrate and the back electrode BE can be suppressed, and the yield can be improved.

[0150] Therefore, the phosphorus concentration of the nickel plating film PL1 is preferably 5.7 mass percent or less, and more preferably 4.0 mass percent. Thereby, the heat resistance of the nickel plating film PL1 can be improved, and the occurrence of cracks in the nickel plating film PL1 during heat treatment can be accurately prevented. It also becomes possible to use a bonding material (bonding material BD1) with a sintering temperature of high temperature (about 260 degrees Celsius to 300 degrees Celsius) as the die bonding material (bonding material BD1).

[0151] On the other hand, if the phosphorus concentration of the nickel plating film PL1 is too low, it becomes difficult to stably form the nickel plating film PL1. Therefore, the phosphorus concentration of the nickel plating film PL1 is preferably 2 mass percent or more. Thereby, the nickel plating film PL1 can be easily and accurately formed.

[0152] (Embodiment 2) Figs. 28 and 29 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of Embodiment 2. Fig. 28 shows a state before forming a gold plating film on the nickel plating film PL1 after forming the nickel plating film PL1. Fig. 29 shows a state where a gold plating film PL2 is formed on the nickel plating film PL1.

[0153] The semiconductor device of Embodiment 2 is different from the semiconductor device of Embodiment 1 in the following points.

[0154] In the semiconductor device of Embodiment 2, as shown in Figs. 28 and 29, the nickel plating film PL1 is composed of a laminated film of a nickel plating film PL1a formed on the pad PD and a nickel plating film PL1b formed on the nickel plating film PL1a at the opening OP of the insulating film PA. The phosphorus (P) concentration of the nickel plating film PL1a is higher than the phosphorus (P) concentration of the nickel plating film PL1b. Therefore, the nickel plating film PL1 forming step in Embodiment 2 includes a step of forming the nickel plating film PL1a on the pad PD and, after this step, a step of forming the nickel plating film PL1b on the plating film PL1a. Except for the nickel plating film PL1, the semiconductor device of Embodiment 2 has the same configuration as the semiconductor device of Embodiment 1.

[0155] In Embodiment 2, as shown in Fig. 28, at the opening OP of the insulating film PA, the nickel plating film PL1a is formed on the pad PD so as to be in contact with the pad PD. The nickel plating film PL1b is formed on the nickel plating film PL1a so as to be in contact with the nickel plating film PL1a. As shown in Fig. 29, the gold plating film PL2a is formed on the nickel plating film PL1b by a displacement Au plating process so as to be in contact with the nickel plating film PL1b. The gold plating film PL2b is formed on the gold plating film PL2a by a reduction Au plating process so as to be in contact with the gold plating film PL2a.

[0156] Also in the second embodiment, as shown in FIG. 29, a low-density layer LW is formed during the substitution Au plating process for forming the gold plating film PL2a. The low-density layer LW is formed in a layered (continuous) manner within the nickel plating film PL1b in the vicinity of the interface between the nickel plating film PL1b and the gold plating film PL2a. That is, the low-density layer LW is formed within the surface layer portion of the nickel plating film PL1b. The density of nickel (Ni) atoms in the low-density layer LW is lower than the density of nickel (Ni) atoms in the nickel plating film PL1b below the low-density layer LW.

[0157] The phosphorus concentration of each of the nickel plating films PL1a and PL1b is 2 mass percent or more and 7 mass percent or less, preferably 2 mass percent or more and 5.7 mass percent or less, and more preferably 2 mass percent or more and 4.0 mass percent or less. Thereby, due to various heating processes performed after the formation process of the plating film PL, the generation of the Ni3P alloy in the nickel plating film PL1 can be suppressed or prevented. As a result, the occurrence of cracks in the nickel plating film PL1 can be suppressed or prevented. Therefore, the reliability of the semiconductor device can be improved.

[0158] The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. For this reason, the corrosion resistance of the nickel plating film PL1a is higher than the corrosion resistance of the nickel plating film PL1b. Since the pad PD is composed of the above conductor film CD, it contains aluminum (Al) as a main component.

[0159] After the step of forming the nickel plating film PL1, there is a possibility that moisture or a gold plating solution may penetrate along the interface between the pad PD and the nickel plating film PL1. If moisture or a gold plating solution penetrates along the interface between the pad PD and the nickel plating film PL1, there is a concern that the nickel plating film PL1 may corrode near the interface between the pad PD and the nickel plating film PL1. If the nickel plating film PL1 corrodes near the interface between the pad PD and the nickel plating film PL1, peeling is likely to occur at the interface between the pad PD and the nickel plating film PL1, so that the reliability of the semiconductor device decreases. There is also a possibility that the electrical resistance between the wire WA or the metal plate MP and the pad PD increases.

[0160] In the present embodiment, the nickel plating film PL1 is composed of a laminated film of a nickel plating film PL1a and a nickel plating film PL1b on the nickel plating film PL1a, and the phosphorus concentration of the nickel plating film PL1a in contact with the pad PD is made higher than the phosphorus concentration of the nickel plating film PL1b. The higher the phosphorus concentration of the nickel plating film, the higher the corrosion resistance of the nickel plating film. Therefore, by making the phosphorus concentration of the nickel plating film PL1a higher than the phosphorus concentration of the nickel plating film PL1b, it is possible to suppress or prevent the nickel plating film PL1a from corroding near the interface between the pad PD and the nickel plating film PL1a. And, the lower the phosphorus concentration of the nickel plating film, the higher the heat resistance of the nickel plating film. Therefore, by making the phosphorus concentration of the nickel plating film PL1b on the nickel plating film PL1a lower than the phosphorus concentration of the nickel plating film PL1a, the heat resistance of the nickel plating film PL1b can be improved. As a result, it is possible to suppress or prevent cracks from occurring in the nickel plating film PL1 due to various heating steps performed after the step of forming the plating film PL.

[0161] For this reason, in the second embodiment, it is possible to suppress or prevent the nickel plating film PL1 from corroding near the interface between the pad PD and the nickel plating film PL1 and cracks from occurring in the nickel plating film PL1. Therefore, the reliability of the semiconductor device can be further improved.

[0162] Similar to the first embodiment, in the second embodiment, by forming the gold plating film PL2 as a laminated film of the gold plating film PL2a and the gold plating film PL2b on the gold plating film PL2a, the thickness of the low-density layer LW can be suppressed, and the thickness of the gold plating film PL2 can be increased. As a result, when the wire WA or the metal plate MP is connected to the bonding pad composed of the pad PD and the plating film PL, the connection strength of the wire WA or the metal plate MP can be improved. Therefore, the reliability of the semiconductor device can be improved.

[0163] As described above, the invention made by the present inventor has been specifically described based on its embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0164] BD1, BD2 Bonding material BE Back surface electrode CD Conductor film CP Semiconductor device CP1 Semiconductor chip CR Crack CT1, CT2 Contact hole DP Die pad GEW Gate wiring portion GF Gate insulating film LD Lead LW Low-density layer MP Metal plate MR Sealing portion NR n-type semiconductor region OP, OPG, OPS Opening PD Pad PDG Gate pad PDS Source pad PKG Semiconductor package PL Plating film PL1, PL1a, PL1b, PL101 Nickel plating film PL2, PL2a, PL2b, PL102, PL202, PL302 Gold plating film PL100, PL200, PL300 OPM film PR p-type semiconductor region PS conductor film Q1 unit transistor cell SB semiconductor substrate TG trench gate electrode TGL gate lead-out part TR groove WA wire

Claims

1. A semiconductor substrate, An interlayer insulating film formed on the main surface of the semiconductor substrate, An electrode pad mainly composed of aluminum formed on the interlayer insulating film, A passivation film formed so as to cover the interlayer insulating film and the electrode pad, An opening formed in the passivation film so as to expose a part of the electrode pad, A nickel plating film formed on the electrode pad in the opening, A first gold plating film formed on the nickel plating film, A second gold plating film formed on the first gold plating film, And having, The phosphorus concentration of the nickel plating film is 2 mass percent or more and 7 mass percent or less, a semiconductor device.

2. In the semiconductor device according to Claim 1, The first gold plating film is a substitution gold plating film, The second gold plating film is a reduction gold plating film, a semiconductor device.

3. In the semiconductor device according to Claim 1, The phosphorus concentration of the nickel plating film is 2 mass percent or more and 5.7 mass percent or less, a semiconductor device.

4. In the semiconductor device according to Claim 1, The phosphorus concentration of the nickel plating film is 2 mass percent or more and 4.0 mass percent or less, a semiconductor device.

5. In the semiconductor device according to Claim 1, The thickness of the second gold plating film is equal to or greater than the thickness of the first gold plating film, a semiconductor device.

6. In the semiconductor device according to Claim 5, The sum of the thickness of the first gold plating film and the thickness of the second gold plating film is 40 nanometers or more and 100 nanometers or less, a semiconductor device.

7. In the semiconductor device according to Claim 6, The thickness of the first gold plating film is 10 nanometers or more, a semiconductor device.

8. In the semiconductor device according to Claim 1, The thickness of the nickel plating film is 1 micrometer or more and 6 micrometers or less, a semiconductor device.

9. In the semiconductor device according to Claim 2, The first gold plating film is formed by Au ions receiving electron supply by substitution with Ni and depositing as a gold film on the nickel plating film. A semiconductor device.

10. In the semiconductor device according to Claim 2, The second gold plating film is formed by Au ions receiving electron supply from a reducing agent and depositing as a gold film on the nickel plating film. A semiconductor device.

11. In the semiconductor device according to claim 2, in the nickel plating film, a nickel low-density layer is formed near the interface between the nickel plating film and the first gold plating film, the density of nickel atoms in the nickel low-density layer is lower than the density of nickel atoms in the nickel plating film below the nickel low-density layer, the semiconductor device, wherein the thickness of the nickel low-density layer is 20 nanometers or less.

12. In the semiconductor device according to claim 11, the semiconductor device, wherein the nickel low-density layer is continuously formed at the interface between the nickel plating film and the first gold plating film.

13. In the semiconductor device according to claim 1, the nickel plating film is a laminated film of a first nickel plating film formed on the electrode pad and a second nickel plating film formed on the first nickel plating film, the semiconductor device, wherein the phosphorus concentration of the first nickel plating film is higher than the phosphorus concentration of the second nickel plating film.

14. In the semiconductor device according to claim 1, the semiconductor device, further comprising a wire or a metal plate connected to the second gold plating film.

15. In the semiconductor device according to claim 1, the semiconductor device further includes a semiconductor element formed on or in the semiconductor substrate, the semiconductor device, wherein the semiconductor element is a MISFET or an IGBT.

16. (a) A step of forming an interlayer insulating film on the main surface of a semiconductor substrate, (b) A step of forming an electrode pad mainly composed of aluminum on the interlayer insulating film, (c) A step of forming a passivation film so as to cover the interlayer insulating film and the electrode pad, (d) A step of forming an opening in the passivation film so as to expose a part of the electrode pad, (e) A step of forming a nickel plating film on the electrode pad in the opening, (f) A step of forming a first gold plating film on the nickel plating film by a substitution Au plating treatment, (g) A step of forming a second gold plating film on the first gold plating film by a reduction Au plating treatment, The semiconductor device manufacturing method includes: the semiconductor device manufacturing method, wherein the phosphorus concentration of the nickel plating film is 2 mass% or more and 7 mass% or less.

17. In the semiconductor device manufacturing method according to claim 16, the semiconductor device manufacturing method, wherein the phosphorus concentration of the nickel plating film is 2 mass% or more and 5.7 mass% or less.

18. In the method of manufacturing a semiconductor device according to claim 16, The phosphorus concentration of the nickel plating film is 2 mass percent or more and 4.0 mass percent or less, a method of manufacturing a semiconductor device.

19. In the method of manufacturing a semiconductor device according to claim 16, The thickness of the second gold plating film formed in the step (f) is equal to or greater than the thickness of the first gold plating film formed in the step (g), a method of manufacturing a semiconductor device.

20. In the method of manufacturing a semiconductor device according to claim 16, The nickel plating film formed in the step (e) is a laminated film of a first nickel plating film formed on the electrode pad and a second nickel plating film formed on the first nickel plating film, The phosphorus concentration of the first nickel plating film is higher than the phosphorus concentration of the second nickel plating film, a method of manufacturing a semiconductor device.

Images