Semiconductor device and manufacturing method thereof

Abstract

To improve the balance between operating speed and power consumption while suppressing costs in a semiconductor device including a logic gate.SOLUTION: A semiconductor device includes three types of cells as a plurality of logic gates. The first cell includes a p-type MOSFET having a first threshold voltage HVTP and an n-type MOSFET having a second threshold voltage HVTN. The second cell includes a p-type MOSFET having a third threshold voltage LVTP and an n-type MOSFET having a fourth threshold voltage LVTN. The third cell includes a p-type MOSFET having a third threshold voltage LVTP and an n-type MOSFET having a second threshold voltage HVTN. The absolute value of the first threshold voltage HVTP is higher than the absolute value of the third threshold voltage LVTP, and the absolute value of the second threshold voltage HVTN is higher than the absolute value of the fourth threshold voltage LVTN.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device including a logic gate including a p-channel MOSFET and an n-channel MOSFET is known. Patent Document 1 describes a semiconductor device including a logic gate including a p-channel MOSFET and an n-channel MOSFET.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device including a logic gate, further speeding up of the operation speed of the logic gate and further reduction of power consumption are required.

[0005] Generally, in a semiconductor device including a logic gate including a p-channel MOSFET and an n-channel MOSFET, in order to increase the operation speed, that is, the switching operation, it is necessary to lower the gate threshold voltage of the FET. On the other hand, in an FET having a low gate threshold voltage, since the leakage current at the off state is relatively large, the power consumption increases.

[0006] As described above, the operation speed and the power consumption in a logic gate including a p-channel MOSFET and an n-channel MOSFET are usually in a trade-off relationship. And, in order to further improve the operation speed and the power consumption, for example, when developing a new device, the monetary and time costs increase.

[0007] In a semiconductor device including logic gates, it is required to improve the balance between the operating speed and the power consumption while suppressing the cost.

Means for Solving the Problem

[0008] In a typical embodiment, the semiconductor device includes three types of cells as a plurality of logic gates. The first cell includes a p-channel MOSFET having a first threshold voltage and an n-channel MOSFET having a second threshold voltage. The second cell includes a p-channel MOSFET having a third threshold voltage and an n-channel MOSFET having a fourth threshold voltage. The third cell includes the p-channel MOSFET having the third threshold voltage and the n-channel MOSFET having the second threshold voltage. The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, and the absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage.

Effect of the Invention

[0009] According to one embodiment, in a semiconductor device including logic gates, it is possible to improve the balance between the operating speed and the power consumption while suppressing the cost.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] (Background of the Study by the Present Inventors) Semiconductor devices equipped with digital logic circuits are known. A digital logic circuit is composed of a plurality of logic gates. A logic gate includes a p-channel type MOSFET connected to a line on the high potential side of the power supply and an n-channel type MOSFET connected to a line on the low potential side of the same power supply. Such a semiconductor device is, for example, an integrated circuit, and a specific example is a semiconductor chip obtained by dicing a semiconductor wafer.

[0012] Generally, the mask layout design of a digital logic circuit, for example, a CMOS digital logic circuit, is performed by combining basic circuits that have been standardized and prepared in advance. This basic circuit is usually called a cell. A cell is a logic gate or a circuit combining logic gates. Cells include, for example, logic gates such as NOT (INV), NAND, NOR, AOI (AND-OR-INV), and OAI (OR-AND-INV). In addition, cells also include, for example, basic logic circuits such as flip-flops and multiplexers, and auxiliary circuits such as gated clocks, buffers, and delay circuits.

[0013] The set of cells prepared in advance as described above is called a "cell library". In the design of a digital logic circuit, a cell selected from this cell library is laid out on a semiconductor substrate, and these cells are connected by wiring to design a desired digital logic circuit.

[0014] FIG. 1 shows a configuration example of a NOT (INV) type cell 21, a NAND type cell 22, and a NOR type cell 23. In FIG. 1, Vdd indicates a line on the high potential side of the power supply. Vss or GND indicates a line on the low potential side of the same power supply. Also, A and B indicate input terminals, and Y indicates an output terminal. As shown in FIG. 1, the logic gate includes a p-channel type MOSFET connected to the line Vdd on the high potential side of the power supply and an n-channel type MOSFET connected to the line Vss or GND on the low potential side of the same power supply.

[0015] In this specification and the drawings, the p-channel type MOSFET may sometimes be described as a p-type MOSFET or a pFET. Also, the n-channel type MOSFET may sometimes be described as an n-type MOSFET or an nFET.

[0016] The logic gate is a basic component of the cell. Due to differences in purpose (function), size, operating speed, driving force, etc., many types of cells, for example, more than 1000 patterns of cells, are prepared as logic gates.

[0017] In recent years, in a semiconductor device including a digital logic circuit including such a logic gate, it has been required to achieve both high operating speed and low power consumption.

[0018] Generally, in order to increase the operating speed of a semiconductor device including cells, it is necessary to combine a p-type MOSFET having a low absolute value of the gate threshold voltage Vt and an n-type MOSFET having a low absolute value of the gate threshold voltage Vt to form a logic gate. However, when the absolute value of the gate threshold voltage Vt becomes low, the leakage current of the MOSFET at the off state increases, and the power consumption increases. That is, in a semiconductor device including a MOSFET, there is a trade-off relationship between the operating speed and the power consumption. The relationship between the leakage current and the operating speed in the MOSFET will be described below.

[0019] Here, the leakage current flowing into the cell is also referred to as cell leakage. Also, the current flowing through the MOSFET when it is on is also called the on-current, and the leakage current flowing through the MOSFET when it is off is also called the off-leakage.

[0020] Figure 2 shows an example of a NOT (INV) type cell 21, which is a typical cell in a CMOS circuit. As shown in Figure 2, when an on-signal is input to the input terminal A of the NOT type cell 21, the off-leakage 21L of the NOT type cell 21 is determined by the off-leakage value IoffP of the p-type MOSFET. On the other hand, when an off-signal is input to the input terminal A, the off-leakage 21L of the NOT type cell 21 is determined by the off-leakage value IoffN of the n-type MOSFET. Assuming that the time when an on-signal is input to the input terminal A and the time when an off-signal is input are almost the same in the operation of the NOT type cell 21, the average leakage current Ileak_ave per unit time can be expressed as in the following equation (1).

[0021]

Equation

[0022] Figure 3 shows an example of the rise time Traise when an on-signal is output to the output terminal Y of the NOT type cell and an example of the fall time Tfall when an off-signal is output to the output terminal Y of the NOT type cell. When the rise time Traise is short, the slope of the rise becomes steep, and when the rise time Traise is long, the slope of the rise becomes gentle. When the fall time Tfall is short, the slope of the fall becomes steep, and when the fall time Tfall is long, the slope of the fall becomes gentle.

[0023] As shown in FIG. 3, considering the operating speed in a NOT-type cell, the rise time Traise is determined by the on-current value IonP of the p-type MOSFET. When the circuit load is Cload, it is proportional to the load capacitance Cload / IonP. On the other hand, the fall time Tfall is determined by the on-current value IonN of the n-type MOSFET and is proportional to the load capacitance Cload / IonN. The load capacitance is the value obtained by dividing the circuit load Cload by the on-current, that is, time. The average circuit operating speed in this case, that is, the average switching time Tpd, can be expressed as in the following equation (2).

[0024]

Equation

[0025] By the way, semiconductor device manufacturers generally often have four types of design models for the gate threshold voltage Vt of MOSFETs. Specifically, for the gate threshold voltage Vt designed for p-type MOSFETs, there are a high threshold voltage HVTP and a low threshold voltage LVTP. The absolute value of the low threshold voltage LVTP is lower than the absolute value of the high threshold voltage HVTP. Also, for the gate threshold voltage Vt designed for n-type MOSFETs, there are a high threshold voltage HVTN and a low threshold voltage LVTN. The absolute value of the low threshold voltage LVTN is lower than the absolute value of the high threshold voltage HVTN.

[0026] Semiconductor device manufacturers use these four types of gate threshold voltage design models to design two types of logic gates with different balances between operating speed and leakage current. The first type of logic gate is a high-speed operation / high-leakage current type logic gate. The second type of logic gate is a low-speed operation / low-leakage current type logic gate.

[0027] The high-speed operation and high-leakage current type logic gate includes a p-type MOSFET having a threshold voltage LVTP and an n-type MOSFET having a threshold voltage LVTN. In this specification, the cell, which is this high-speed operation and high-leakage type logic gate, is also referred to as an LVT cell. Further, the low-speed operation and low-leakage current type logic gate includes a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HVTN. In this specification, the cell, which is this low-speed operation and low-leakage current type logic gate, is also referred to as an HVT cell.

[0028] As understood from FIG. 3, generally, when the absolute value of the gate threshold voltage Vt of the MOSFETs constituting the cell increases, that is, when the on-current of the cell decreases, the rise time and fall time of the signal output Y of the cell become longer, and the rise and fall become slower. Conversely, when the gate threshold voltage Vt of the FETs constituting the cell decreases, that is, when the on-current of the cell increases, the rise time and fall time of the signal output Y of the cell become shorter, and the rise and fall become faster. That is, as indicated by arrows SH31 and SH32 in FIG. 3, the slopes of the rise and fall of the signal output Y become steeper. Further, when comparing the rise time of the p-type MOSFET and the fall time of the n-type MOSFET having equal on-currents, the rise time by the p-type MOSFET is longer than the fall time of the n-type MOSFET.

[0029] As shown in FIG. 4, when comparing the LVT cell and the HVT cell having the same driving force, it can be seen that the cell leakage of the LVT cell is about 16 times that of the HVT cell.

[0030] The semiconductor device manufacturer uses the LVT cell in places where high-speed operation is required and uses the HVT cell in places where high-speed operation like that of the LVT cell is not required. Thereby, a semiconductor device is designed that suppresses cell leakage as much as possible while ensuring the required operating speed.

[0031] However, in reality, among the digital circuit parts using high-speed operation and high-leakage current type LVT cells, there are parts where an operation speed intermediate between the operation speeds of LVT cells and HVT cells is sufficient.

[0032] Therefore, in a semiconductor device, as one method for further suppressing power consumption while ensuring the operation speed, it is conceivable to newly add and design an MVT cell having characteristics intermediate between an LVT cell and an HVT cell in terms of the balance between the operation speed and the leakage current.

[0033] As shown in FIG. 5, when comparing an LVT cell, an HVT cell, and an MVT cell having the same driving force, it can be seen that the cell leakage of the MVT cell is approximately in the middle between the cell leakage of the LVT cell and the cell leakage of the HVT cell.

[0034] To design an MVT cell, an intermediate threshold voltage MVTP is added as a design model for the gate threshold voltage of a p-type MOSFET, and an intermediate threshold voltage MVTN is added as a design model for the gate threshold voltage of an n-type MOSFET. The absolute value of the threshold voltage MVTP is higher than the absolute value of the threshold voltage LVTP and lower than the absolute value of the threshold voltage HVTP. Also, the absolute value of the threshold voltage MVTN is higher than the absolute value of the threshold voltage LVTN and lower than the absolute value of the threshold voltage HVTN. Then, a new MVT cell is prepared by combining a p-type MOSFET having the threshold voltage MVTP and an n-type MOSFET having the threshold voltage MVTN.

[0035] A semiconductor device manufacturer appropriately uses three types of cells, namely, LVT cells, HVT cells, and MVT cells, for each logic gate in the digital circuit part of the semiconductor device according to the required operation speed. Here, this method will be referred to as the reference method.

[0036] According to such a standard method, in the digital circuit portion of a semiconductor device, among the locations where LVT cells had to be used until now, locations where the operating speed is acceptable even with MVT cells can be replaced with MVT cells that have a lower leakage current than LVT cells. As a result, in a semiconductor device including a digital circuit, it becomes possible to suppress power consumption more than before while ensuring the required operating speed.

[0037] However, there are also problems with this standard method. In the manufacturing process of a semiconductor device, a process of implanting impurities into a channel located directly under a gate in a well in a semiconductor substrate is included. This process is also called channel doping. The content of the channel doping process varies depending on the difference in the channel type (p-type / n-type) of the MOSFET and the difference in the designed gate threshold voltage. In the channel doping process, the gate threshold voltage of the MOSFET can be adjusted by adjusting the type or amount of the impurities to be implanted and the diffusion state.

[0038] A mask is used in the channel doping process. The mask has an opening corresponding to the region where impurities are to be implanted. Therefore, in order to add MVT cells as cells used in the digital circuit, a mask for p-type MOSFETs having a threshold voltage MVTP and a mask for n-type MOSFETs having a threshold voltage MVTN are newly required. That is, when MVT cells are added as cells used in the digital circuit, the number of masks used in manufacturing increases, the number of manufacturing steps also increases, and the financial and time costs increase.

[0039] The inventors have devised a method that can reduce power consumption more while suppressing costs and ensuring the required operating speed in a semiconductor device including a digital circuit.

[0040] (Embodiment 1) Embodiment 1 is a semiconductor device including a digital circuit and a method for designing and manufacturing the semiconductor device. In Embodiment 1, in the semiconductor device, in addition to the HVT cell and the LVT cell, a cell having intermediate characteristics between the HVT cell and the LVT cell and having a configuration different from that of the MVT cell is used. Note that the HVT cell is an example of the "first cell" in the present application, and the LVT cell is an example of the "second cell" in the present application. In addition, the cell having intermediate characteristics between the HVT cell and the LVT cell and having a configuration different from that of the MVT cell is an example of the "third cell" in the present application. In each of the following embodiments, it is assumed that the thickness of the gate layer of the MOSFET constituting the cell is constant, and the size of the cell is proportional to the size of a well or the like that occupies the substrate surface of the semiconductor substrate.

[0041] The semiconductor device 100 according to Embodiment 1 is, for example, an integrated circuit, that is, a so-called semiconductor chip. As shown in FIG. 6, the semiconductor device 100 includes a digital circuit portion 101 and non-digital circuit portions 102 and 103. The non-digital circuit portion 102 is, for example, an analog circuit portion. The non-digital circuit portion 103 is, for example, an I / O (Input / Output) circuit portion.

[0042] Three types of cells are used in the digital circuit portion 101. That is, in addition to the HVT cell as the first cell and the LVT cell as the second cell, which have been conventionally used, a third cell is prepared. Then, the digital circuit portion 101 is designed by combining these three types of cells.

[0043] The third cell includes a p-type MOSFET connected to the first potential and an n-type MOSFET connected to the second potential. The second potential is lower than the first potential. The threshold voltage Vt of the p-type MOSFET constituting the third cell is the same threshold voltage LVTP as that of the p-type MOSFET constituting the LVT cell. Also, the threshold voltage Vt of the n-type MOSFET constituting the third cell is the same threshold voltage HVTN as that of the n-type MOSFET constituting the HVT cell. That is, the feature of the third cell is that the threshold voltage of the p-type MOSFET is set to a relatively low threshold voltage LVTP as a p-type, and the threshold voltage of the n-type MOSFET is set to a relatively high threshold voltage HVTN as an n-type.

[0044] Here, the threshold voltage HVTP is an example of the "first threshold voltage" in the present application, and the threshold voltage HVTN is an example of the "second threshold voltage" in the present application. Also, the threshold voltage LVTP is an example of the "third threshold voltage" in the present application, and the threshold voltage LVTN is an example of the "fourth threshold voltage" in the present application.

[0045] Generally, the leakage current of an LVT cell composed of MOSFETs having a low absolute value of the threshold voltage Vt corresponds to ten to dozens of times the leakage current of an HVT cell composed of MOSFETs having a high absolute value of the threshold voltage Vt. Also, due to the physical properties of silicon, the on-current of an n-type MOSFET corresponds to about several times the on-current of a p-type MOSFET. Here, consider comparing the rise time of the output of the p-type MOSFET and the fall time of the output of the n-type MOSFET with the same on-current (load). In this case, the rise time of the p-type MOSFET becomes longer than the fall time of the n-type MOSFET. The operating speed of the cell can be considered to be approximately the reciprocal of the time required for switching composed of the rise and fall of the output of the cell.

[0046] Therefore, the threshold voltage Vt of the n-type MOSFET is set as a high threshold voltage HVTN with a relatively high absolute value as an n-type, and the threshold voltage Vt of the p-type MOSFET is set as a low threshold voltage LVTP with a relatively low absolute value as a p-type. This increases the on-current of the p-type MOSFET and shortens the rise time. By designing in this way, it is possible to reduce the leakage current and increase the operating speed in the cell.

[0047] Figure 7 shows a configuration example of a NOT (INV) type cell 31 which is an example of a logic gate. In the NOT type cell 31, a p-type MOSFET 311 connected to the line Vdd and an n-type MOSFET 312 connected to the line Vss (GND) are connected in series. The potential of the line Vdd is the first potential on the high potential side of the power supply, and the potential of the line Vss is the second potential on the low potential side of the same power supply. The gate of the p-type MOSFET 311 and the gate of the n-type MOSFET 312 are connected, and the connection point serves as the input terminal A. Also, the source of the p-type MOSFET 311 and the drain of the n-type MOSFET 312 are connected, and the connection point serves as the output terminal Y.

[0048] In the NOT type cell 31, the p-type MOSFET 311 is a p-type MOSFET having a threshold voltage LVTP (hereinafter also referred to as LVT(p)), and the n-type MOSFET 312 is an n-type MOSFET having a threshold voltage HVTN (hereinafter also referred to as HVT(n)). In this specification, a cell including a p-type MOSFET having a threshold voltage HVTP, that is, HVT(p), and an n-type MOSFET having a threshold voltage LVTN, that is, HVT(n), will be referred to as an LVT(p)&HVT(n) cell.

[0049] Figure 8 shows a graph representing the relationship between the driving force and the cell leakage for each cell size for an LVT cell, an HVT cell, and an LVT(p)&HVT(n) cell, and an MVT cell by a reference method for comparison.

[0050] The driving force of a cell is correlated with the operating speed of the cell. Also, cell leakage is correlated with the power consumption of the cell. That is, the higher the driving force, the faster the operating speed, and the smaller the cell leakage, the lower the power consumption. As shown in FIG. 8, in the relationship between the driving force of the cell and the cell leakage, the LVT(p)&HVT(n) cell newly added in Embodiment 1 has characteristics intermediate between those of the existing LVT cells and HVT cells, and is close to the characteristics of the MVT cells by the standard method. That is, the LVT(p)&HVT(n) cell can be used instead of the MVT cell.

[0051] That is, in the digital circuit design method according to Embodiment 1, the operating speed or driving force of the LVT cell is not required, but for the part where the operating speed or driving force of the HVT cell is insufficient, the LVT(p)&HVT(n) cell is used for the part where an intermediate operating speed or driving force between the LVT cell and the HVT cell is sufficient. Therefore, according to Embodiment 1, a digital circuit can be provided that reduces the power consumption due to leakage current while ensuring the required operating speed.

[0052] Also, in the digital circuit design method according to Embodiment 1, the LVT(p)&HVT(n) cell is used instead of the MVT cell as the cell having characteristics intermediate between those of the LVT cell and the HVT cell. Therefore, in Embodiment 1, only the design models of LVTP and HVTN, which are the existing design models of the gate threshold voltage, can be directly used for the formation of the cell, and there is no need to newly develop a new design model of the gate threshold voltage. Also, in Embodiment 1, there is no need to newly develop a new design model of the gate threshold voltage. Therefore, in the manufacturing process of the digital circuit, in the process of implanting impurities into the channel or well in the semiconductor substrate for gate threshold voltage control, a new mask is not required, and only the existing mask is sufficient.

[0053] Further, according to Embodiment 1, there is no need to newly develop a design model for the gate threshold voltage. Also, there is no need to fabricate a new mask for use in the process of implanting impurities for gate threshold voltage control. Furthermore, the process of using that mask is also unnecessary. That is, according to Embodiment 1, a semiconductor device with an improved balance between operating speed and power consumption can be realized at reduced monetary and time costs.

[0054] <Estimation of the effect of reducing cell leakage by cell replacement> FIG. 9 shows a table representing the relationship between the usage ratio of cell types in a digital circuit and cell leakage. The left table in FIG. 9 shows the relationship between the usage ratio of HVT cells and LVT cells and cell leakage (conventional example). The right table in FIG. 9 shows the relationship between HVT cells, the usage ratio of HVT cells, HVT(N)&LVT(P) cells, and LVT cells in a digital circuit, and cell leakage. Here, it is assumed that all cell sizes are the same. Also, in these tables, cell leakage is shown as a cell leakage ratio, which is the ratio when the cell leakage when all cells are HVT cells is set to 1.

[0055] For example, as shown in FIG. 9, in the conventional example, when the usage ratio of HVT cells and LVT cells is 0.5:0.5, the cell leakage ratio is 12.4. On the other hand, in the example of Embodiment 1, when the usage ratio of HVT cells, LVT(p)&HVT(n) cells, and LVT cells is 0.5:0.5:0.0, the cell leakage ratio is 4.4. Also, in the example of Embodiment 1, when the usage ratio of HVT cells, LVT(p)&HVT(n) cells, and LVT cells is 0.5:0.4:0.1, the cell leakage ratio is 6.0. Therefore, in the case of a digital circuit where the usage rate of HVT cells and LVT cells is 0.5:0.5, by replacing all or about 80% of the LVT cells with LVT(p)&HVT(n) cells, the cell leakage can be reduced to about 1 / 2 to about 1 / 3 times.

[0056] <Relationship between cell driving force and leakage current> Figure 10 shows a graph representing the relationship between driving force and cell leakage for LVT cells, HVT cells, MVT cells, and LVT(p)&HVT(n) cells. Also, in the graph shown in Figure 10, curves (close to straight lines) representing the characteristics when the threshold voltages Vt of both p-type MOSFETs and n-type MOSFETs are simultaneously adjusted in the same positive or negative direction in cells of the same size are drawn with dashed lines for each cell size. Note that in the graph shown in Figure 10, "X160", "X240", and "X320" represent the cell sizes, and the larger the number, the larger the cell size. The physical height of the MOSFETs constituting the cells is the same, but the occupied area is different.

[0057] As shown in Figure 10, the ratio of cell leakage to driving force in HVT cells is relatively small. The ratio of cell leakage to driving force in LVT cells is relatively large. The ratio of cell leakage to driving force in MVT cells has characteristics intermediate between those of HVT cells and LVT cells. The ratio of cell leakage to driving force in LVT(p)&HVT(n) cells is slightly larger than that in the case of MVT cells, but has characteristics close to those of MVT cells.

[0058] Here, in the graph shown in Figure 10, the curve corresponding to the LVT(p)&HVT(n) cell is compared with the curves corresponding to the HVT cell, LVT cell, and MVT. Then, it can be seen that the curve corresponding to the LVT(p)&HVT(n) cell is shifted to the right overall compared to the other curves. This means that the cell leakage with respect to the driving force in the LVT(p)&HVT(n) cell is smaller than that in the case of other cells. That is, when comparing cells of the same size and having the same driving force, the cell leakage of the LVT(p)&HVT(n) cell is less than that of other cells, and it can be seen that the LVT(p)&HVT(n) cell is more performant than the MVT cell.

[0059] <Relationship between cell operating speed and leakage current> FIG. 11 shows a graph representing the relationship between the operating speed and cell leakage for each cell. In the graph shown in FIG. 11, plot P1 shows the relationship between the operating speed and cell leakage in an HVT cell. Plot P2 shows the relationship between the operating speed and cell leakage in an LVT cell. Also, plot P3 shows the relationship between the operating speed and cell leakage in an LVT(p)&HVT(n) cell. Further, in the graph shown in FIG. 11, for a cell fabricated by simultaneously changing the threshold voltages Vt of n-type FETs and p-type FETs, a curve (close to a straight line) L1 showing the relationship between the operating speed and cell leakage is drawn in dashed lines. In the graph shown in FIG. 11, the region below the dashed line L1 (diagonally lower right) indicates a region where the balance between the operating speed and cell leakage is further improved.

[0060] In the graph shown in FIG. 11, plot P3 corresponding to the LVT(p)&HVT(n) cell is located below the dashed line L1. Therefore, the LVT(p)&HVT(n) cell not only has intermediate characteristics between the LVT cell and the HVT cell, but also has an improved balance between the operating speed and cell leakage compared to the LVT cell and the HVT cell. This point is also a characteristic point of the LVT cell and the HVT cell that is different from the MVT cell.

[0061] <Method of manufacturing a cell> As shown in FIG. 12, in step (process) S0, a step of preparing a semiconductor substrate is performed. In step S1, a step of forming a well is performed. The details of the step of forming the well in step S1 will be described later. In step S2, a step of forming a trench is performed. In step S3, a step of filling the trench is performed. In step S4, a step of forming a gate is performed. The details of the step of forming the gate in step S4 will be described later.

[0062] In step S5, a process of forming an LDD (Lightly Doped Drain) is performed. In step S6, a process of forming sidewall spacers is performed. In step S7, a process of forming a source and a drain is performed. In step S8, a process of forming an interlayer film and contacts is performed. In step S9, a process of forming metal wiring is performed. In step S10, a process of wiring multilayer metal and a process of forming a passivation film are performed.

[0063] Note that, as shown in FIG. 12, performing the processes of steps S1 to S7 is substantially equivalent to performing the processes of steps T1 to T6 below. Step T1 is a process of forming a first p-type MOSFET of an HVT cell. Step T2 is a process of forming a first n-type MOSFET of an HVT cell. Step T3 is a process of forming a second p-type MOSFET of an HVT cell. Step T4 is a process of forming a second n-type MOSFET of an HVT cell. Step T5 is a process of forming a third p-type MOSFET of an LVT(p)&HVT(n) cell. Step T6 is a process of forming a third n-type MOSFET of an LVT(p)&HVT(n) cell.

[0064] As shown in FIG. 13, in step S11, a first p-type well, a second p-type well, and a third p-type well are formed by implanting p-type impurities into the semiconductor substrate 10. Also, in step S12, a first n-type well, a second n-type well, and a third n-type well are formed by implanting n-type impurities into the semiconductor substrate 10.

[0065] Here, the first p-type well is the well of the n-type MOSFET that constitutes the HVT cell. The second p-type well is the well of the n-type MOSFET that constitutes the HVT cell. The third n-type well is the well of the n-type MOSFET that constitutes the LVT(p)&HVT(n) cell. Also, the first n-type well is the well of the p-type MOSFET that constitutes the HVT cell. The second n-type well is the well of the p-type MOSFET that constitutes the HVT cell. The third n-type well is the well of the p-type MOSFET that constitutes the LVT(p)&HVT(n) cell.

[0066] Next, as shown in FIG. 14, in step S41, an element isolation structure is formed. First, a trench is formed in the semiconductor substrate, and an oxide film is formed on the semiconductor substrate so as to fill the trench. Then, the element isolation structure is formed by removing the oxide film formed outside the trench.

[0067] In step S42, a process of forming a gate insulating film is performed. For example, by oxidizing the semiconductor substrate, a gate insulating film (oxide film) is formed. Thereby, the first p-type MOSFET and the first n-type MOSFET that constitute the HVT cell 11 as the first cell have the first gate insulating film. Also, the second p-type MOSFET and the second n-type MOSFET that constitute the LVT cell 12 as the second cell have the second gate insulating film. Further, the third p-type MOSFET and the third n-type MOSFET that constitute the LVT(p)&HVT(n) cell 13 as the third cell have the third gate insulating film. Note that the thickness of the first gate insulating film, the thickness of the second gate insulating film, and the thickness of the third gate insulating film are the same as each other. However, the fact that the thicknesses of the gate insulating films are the same as each other does not mean that their thicknesses are exactly the same, but means that their thicknesses are the same in design, and manufacturing errors and the like are allowed.

[0068] In step S43, a process of injecting impurities for threshold voltage adjustment is performed. Specifically, three types of cells are laid out on a semiconductor substrate. For each individual cell of each type, impurities are injected into the channel located directly under the gate in the well to adjust the threshold voltage of each of the p-type MOSFET and n-type MOSFET that make up the cell. The adjustment of the threshold voltage is performed by changing the amount of impurities to be injected, the concentration of impurities in the channel, the degree of diffusion, and the like. P-type impurities are injected into the channel in the p-type well of the n-type MOSFET. N-type impurities are injected into the channel in the n-type well of the p-type MOSFET. The n-type impurities are, for example, phosphorus (P), arsenic (As), antimony (Sb), etc. The p-type impurities are, for example, boron (B), indium (In), aluminum (Al), etc.

[0069] In this example, by performing the process of injecting impurities for threshold voltage adjustment, each MOSFET of each cell has a channel having an impurity concentration as described below.

[0070] The first p-type MOSFET constituting the HVT cell 11 as the first cell has a channel having a first impurity concentration corresponding to the threshold voltage HVTP. Also, the first n-type MOSFET constituting the HVT cell 11 as the first cell has a channel having a second impurity concentration corresponding to the threshold voltage HVTN.

[0071] The second p-type MOSFET constituting the LVT cell 12 as the second cell has a channel having a third impurity concentration corresponding to the threshold voltage LVTP. Also, the second n-type MOSFET constituting the LVT cell 12 as the second cell has a channel having a fourth impurity concentration corresponding to the threshold voltage LVTN.

[0072] The third p-type MOSFET that constitutes the LVT(p)&HVT(n) cell 13 as the third cell has a channel with a third impurity concentration corresponding to the threshold voltage LVTP. Also, the third n-type MOSFET that constitutes the LVT(p)&HVT(n) cell 13 as the third cell has a channel with a second impurity concentration corresponding to the threshold voltage HVTN.

[0073] Note that when the impurity concentration in the channel of a MOSFET increases, the absolute value of the threshold voltage of that MOSFET increases. Conversely, when the impurity concentration in the channel of a MOSFET decreases, the absolute value of the threshold voltage of that MOSFET decreases.

[0074] Therefore, in a p-type MOSFET, the impurity concentration in the channel of the first n-type well corresponding to the threshold voltage HVTP is higher than the impurity concentration in the channel of the second n-type well corresponding to the threshold voltage LVTP and the impurity concentration in the channel of the third n-type well. Also, in an n-type MOSFET, the impurity concentration in the channel of the first p-type well corresponding to the threshold voltage HVTN and the impurity concentration in the channel of the third p-type well are higher than the impurity concentration in the channel of the second p-type well corresponding to the threshold voltage LVTN.

[0075] In an n-type MOSFET, the impurity concentration in the channel of the first p-type well corresponding to the threshold voltage HVTN and the impurity concentration in the channel of the third p-type well corresponding to the threshold voltage HVTN are the same as each other. Also, in a p-type MOSFET, the impurity concentration in the channel of the second n-type well corresponding to the threshold voltage LVTP and the impurity concentration in the channel of the third n-type well corresponding to the threshold voltage LVTP are the same as each other. Note that the fact that the impurity concentrations are the same as each other means that the designed concentrations are the same as each other, and errors that occur in actual manufacturing are tolerated.

[0076] Here, for example, as shown in FIG. 15, consider a design in which HVT cells 11, LVT cells 12, and LVT(p)&HVT(n) cells 13 are laid out on a semiconductor substrate 10. The HVT cell 11 includes a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HVTN. The LVT cell 12 includes a p-type MOSFET having a threshold voltage LVTP and an n-type MOSFET having a threshold voltage LVTN. Further, the LVT(p)&HVT(n) cell 13 includes a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage LVTN.

[0077] The types of impurities to be implanted in the p-type MOSFET are different from the types of impurities to be implanted in the n-type MOSFET. That is, the impurity implantation conditions corresponding to the threshold voltage HVTP and the threshold voltage LVTP are different from the impurity implantation conditions corresponding to the threshold voltage HVTN and the threshold voltage LVTN. Also, even when comparing the same p-type MOSFETs or the same n-type MOSFETs, if the absolute value of the threshold voltage to be adjusted is different, the impurity implantation amount or diffusion state is different, and the impurity implantation conditions are different. Therefore, in step S43, four types of masks are used.

[0078] Specifically, as shown in FIG. 16, the above four types of masks include a mask 111 for the threshold voltage HVTP, a mask 112 for the threshold voltage HVTN, a mask 113 for the threshold voltage LVTP, and a mask 114 for the threshold voltage LVTN.

[0079] As shown in FIG. 16, the mask 111 for the threshold voltage HVTP covers the wells of the MOSFETs that should have the threshold voltage HVTN, the threshold voltage LVTP, and the threshold voltage LVTN, and has an opening 111h that exposes the channel of the p-type MOSFET that should have the threshold voltage HVTP. Specifically, the mask 111 for the threshold voltage HVTP covers the wells in the n-type MOSFET of the HVT cell 11, the p-type MOSFET and the n-type MOSFET of the LVT cell 12, and the p-type MOSFET and the n-type MOSFET of the LVT(p)&HVT(n) cell 13, and is formed to expose the channel of the p-type MOSFET of the HVT cell 11.

[0080] As shown in FIG. 16, the mask 112 for the threshold voltage HVTN covers the wells of the MOSFETs that should have the threshold voltage HVTP, the threshold voltage LVTP, and the threshold voltage LVTN, and has an opening 112h that exposes the channel of the n-type MOSFET that should have the threshold voltage HVTN. Specifically, the mask 112 for the threshold voltage HVTN covers the wells in the p-type MOSFET of the HVT cell 11, the p-type MOSFET and the n-type MOSFET of the LVT cell 12, and the p-type MOSFET of the LVT(p)&HVT(n) cell 13, and is formed to expose the channels of the n-type MOSFET of the HVT cell 11 and the n-type MOSFET of the LVT(p)&HVT(n) cell 13.

[0081] As shown in FIG. 16, the mask 113 for the threshold voltage LVTP covers the wells of the MOSFETs that should have the threshold voltage HVTP, the threshold voltage HVTN, and the threshold voltage LVTN, and has an opening 113h that exposes the channel of the p-type MOSFET that should have the threshold voltage LVTP. Specifically, the mask 113 for the threshold voltage LVTP covers the wells in the p-type MOSFET and the n-type MOSFET of the HVT cell 11, the n-type MOSFET of the LVT cell 12, and the n-type MOSFET of the LVT(p)&HVT(n) cell 13, and is formed to expose the channels of the p-type MOSFET of the LVT cell 12 and the p-type MOSFET of the LVT(p)&HVT(n) cell 13.

[0082] As shown in FIG. 16, the mask 114 for the threshold voltage LVTN covers the wells of the MOSFETs that should have the threshold voltage HVTP, the threshold voltage HVTN, and the threshold voltage LVTP, and has an opening 114h that exposes the channels of the n-type MOSFETs that should have the threshold voltage HVTN. Specifically, the mask 114 for the threshold voltage LVTN is formed to cover the wells in the p-type MOSFET and n-type MOSFET of the HVT cell 11, the p-type MOSFET of the LVT cell 12, and the p-type MOSFET and n-type MOSFET of the LVT(p)&HVT(n) cell 13, and to expose the channels of the n-type MOSFETs of the LVT cell 12.

[0083] As shown in FIG. 17, first, in step S431, the mask 111 for the threshold voltage HVTP is formed (arranged) on the semiconductor substrate 10. Then, in step S432, using the mask 111 for the threshold voltage HVTP, a step of implanting n-type impurities for the threshold voltage HVTP into the channels of the n-type wells corresponding to the threshold voltage HVTP in the semiconductor substrate 10 is performed. Here, the "mask for the threshold voltage HVTP" is an example of the "first mask film" in the present application. Also, the "n-type well corresponding to the threshold voltage HVTP" is an example of the "first n-type well" in the present application.

[0084] Next, in step S433, the mask 112 for the threshold voltage HVTN is formed (arranged) on the semiconductor substrate 10. Then, in step S434, using the mask 112 for the threshold voltage HVTN, a step of implanting p-type impurities for the threshold voltage HVTN into the channels of the p-type wells corresponding to the threshold voltage HVTN in the semiconductor substrate 10 is performed. Here, the "mask for the threshold voltage HVTN" is an example of the "second mask film" in the present application. Also, the "p-type well corresponding to the threshold voltage HVTN" is an example of the "first p-type well" in the present application and an example of the "third p-type well" in the present application.

[0085] Next, in step S435, a mask 113 for the threshold voltage LVTP is formed (arranged) on the semiconductor substrate 10. Thereafter, in step S436, a process of implanting n-type impurities for the threshold voltage LVTP into the channel of the n-type well corresponding to the threshold voltage LVTP in the semiconductor substrate 10 is performed using the mask 113 for the threshold voltage LVTP. Here, the "mask for the threshold voltage LVTP" is an example of the "third mask film" in the present application. Also, the "n-type well corresponding to the threshold voltage LVTP" is an example of the "second n-type well" in the present application and an example of the "third n-type well".

[0086] Next, in step S437, a mask 114 for the threshold voltage LVTN is formed (arranged) on the semiconductor substrate 10. Thereafter, in step S438, a process of implanting p-type impurities for the threshold voltage LVTN into the channel corresponding to the threshold voltage LVTN in the semiconductor substrate 10 is performed using the mask 114 for the threshold voltage LVTN. Here, the "mask for the threshold voltage LVTN" is an example of the "fourth mask film" in the present application. Also, the "p-type well corresponding to the threshold voltage LVTN" is an example of the "second p-type well" in the present application.

[0087] Here, step S431 and step S432 performed after step S431 are defined as process A. Step S433 and step S434 performed after step S433 are defined as process B. Step S435 and step S436 performed after step S435 are defined as process C. Also, step S437 and step S438 performed after step S437 are defined as process D. As described above, an example in which processes A, B, C, and D are performed in this order has been described, but the order in which processes A to D are performed is not limited to this. For example, they may be performed in the order of process A, process C, process B, process D, or in the order of process D, process C, process B, process A.

[0088] Also, when forming a digital circuit using the HVT cells 11, LVT cells 12, and LVT(p)&HVT(n) cells 13 by the method of Embodiment 1, to inject impurities for threshold voltage adjustment, as described above, four masks are sufficient as in the conventional case. On the other hand, when forming a digital circuit using the HVT cells 11, LVT cells 12, and MVT cells by the standard method, to inject impurities for threshold voltage adjustment, two additional masks, i.e., the mask for the threshold voltage MVTP and the mask for the threshold voltage MVTN, are required, and a total of six masks are needed.

[0089] <Effect of Embodiment 1> According to such Embodiment 1, in the digital circuit portion of the semiconductor device, by replacing at least a part of the LVT cells with LVT(p)&HVT(n) cells, in the digital circuit portion, it is possible to reduce cell leakage, i.e., power consumption, while ensuring the required operating speed. Further, according to Embodiment 1, under the condition that the cell leakage is the same compared to the cells according to the standard method, the operating speed of the cells can be improved.

[0090] Furthermore, according to Embodiment 1, when forming a semiconductor device including a digital circuit portion, compared to the standard method, there is no need to add masks used for impurity implantation. Therefore, there is no additional manufacturing cost for the masks and no increase in the process of implanting impurities, and the cost can be suppressed.

[0091] Furthermore, according to Embodiment 1, by lowering only the absolute value of the gate threshold voltage Vt of the p-type MOSFET, the driving force of the cell is improved under the condition that the off-leakage is the same. Also, as understood from FIG. 10, the LVT(p)&HVT(n) cell is a cell with lower leakage and higher driving force than the MVT cell. Also, as understood from FIG. 3, for any cell size, the driving force ratio with respect to cell leakage is the highest for the LVT(p)&HVT(n) cell.

[0092] Furthermore, according to Embodiment 1, in the digital circuit portion of a semiconductor device having a digital circuit portion and a non-digital circuit portion, the three types of cells according to Embodiment 1 can be selectively used according to the required operating speed or driving force. As a result, it is possible to provide a semiconductor device that suppresses power consumption while ensuring the required operating speed. That is, according to Embodiment 1, in a semiconductor device including a digital circuit, the balance between the operating speed and the power consumption can be improved.

[0093] (Embodiment 2) Embodiment 2 is a modification of the HVT(n)&LVT(p) cell according to Embodiment 1. In Embodiment 2, the threshold voltage Vt is changed without changing the relative magnitude relationship of the absolute values of the respective threshold voltages Vt of the p-type MOSFET and the n-type MOSFET constituting the cell.

[0094] The NOT (INV) type cell 31a shown in FIG. 18 represents an HVT(p)&HHVT(n) cell formed by a combination of a p-type MOSFET having a threshold voltage HVTP and an n-type MOSFET having a threshold voltage HHVTN. The absolute value of the threshold voltage HHVTN is larger than the absolute value of the threshold voltage HVTN. Such an HVT(p)&HHVT(n) cell has lower off-leakage and higher operating speed compared to an LVT(p)&HVT(n) cell. The HVT(p)&HHVT(n) cell is suitable, for example, as a cell to be used in a circuit portion where the required operating speed is not as high as that of an LVT cell but is insufficient for an LVT(p)&HVT(n) cell. Note that the "threshold voltage HHVTN" is an example of the "fifth threshold voltage" in the present application.

[0095] The NOT (INV) type cell 31b shown in FIG. 18 represents an LLVT(p)&LVT(n) cell which is a combination of a p-type MOSFET having a threshold voltage LLVTP and an n-type MOSFET having a threshold voltage LVTN. The absolute value of the threshold voltage LVTN is larger than the absolute value of the threshold voltage LLVTN. Such an LLVT(p)&LVT(n) cell becomes a cell with lower off-leakage and higher operating speed compared to the LVT(p)&HVT(n) cell. The LLVT(p)&LVT(n) cell is suitable, for example, as a cell to be used in a circuit portion where the required operating speed is not as high as that of the LVT cell but is insufficient at the operating speed of the LVT(p)&HVT(n) cell.

[0096] FIG. 19 shows a graph in which a plot P1 showing the relationship between the operating speed and cell leakage corresponding to the HVT cell, and a plot P2 showing the relationship between the operating speed and cell leakage corresponding to the LVT cell are drawn. Further, in the graph shown in FIG. 19, a plot P3 showing the relationship between the operating speed and cell leakage corresponding to the LVT(p)&HVT(n) cell is drawn. Furthermore, in the graph shown in FIG. 19, a plot P4 showing the relationship between the operating speed and cell leakage corresponding to the HVT(p)&HHVT(n) cell and a plot P5 showing the relationship between the operating speed and cell leakage corresponding to the LLVT(p)&LVT(n) cell are drawn. In the graph shown in FIG. 19, a curve (close to a straight line) L1 showing the relationship between the operating speed and cell leakage is drawn with a broken line for cells formed by changing the threshold voltages Vt of the n-type MOSFET and the p-type MOSFET simultaneously. In the graph shown in FIG. 19, the region below the broken line L1 (diagonally lower right) indicates a region where the balance between the operating speed and cell leakage is further improved.

[0097] As can be understood from the graph shown in FIG. 19, the HVT(p)&HHVT(n) cells and the LLVT(p)&LVT(n) cells are located below the dashed line L1. Therefore, similar to the LVT(p)&HVT(n) cells, the balance between the operating speed and the cell leakage of the HVT(p)&HHVT(n) cells and the LLVT(p)&LVT(n) cells is improved compared to the LVT cells and the HVT cells. The HVT(p)&HHVT(n) cells are suitable, for example, as cells to be used in places where reducing cell leakage is emphasized rather than the operating speed of the cells, compared to the HVT cells. On the other hand, the LLVT(p)&LVT(n) cells are suitable, for example, as cells to be used in places where the operating speed of the cells is emphasized rather than the cell leakage, compared to the LVT cells. "Threshold voltage LLVTN" is an example of the "sixth threshold voltage" in the present application.

[0098] In addition to the two types of conventional cells or the three types of cells according to Embodiment 1, when manufacturing HVT(p)&HHVT(n) cells, a new mask for HHVT is required (a total of 5 masks are needed). Also, in addition to the two types of conventional cells or the three types of cells according to Embodiment 1, when newly manufacturing LLVT(p)&LVT(n) cells, a new mask for LLVT is required (a total of 5 masks are needed). However, in either case of the HVT(p)&HHVT(n) cells and the LLVT(p)&LVT(n) cells, the increase in the number of masks is only one. That is, it is not necessary to add two new masks as in the case of the MVT cells (a total of 6 masks are needed).

[0099] (Embodiment 3) Embodiment 3 is an example in which, among the combinational circuits connected between flip-flop circuits, not only LVT cells but also LVT(p)&HVT(n) cells are used in combinational circuits that require relatively high-speed operation.

[0100] Generally, the time delays that occur in combinational circuits vary. Conventionally, among combinational circuits where the resulting delay is relatively large or short delays are required, the use of cells that operate at high speed has been demanded. Therefore, conventionally, in such combinational circuits that require short delays, cells with high operating speed but large leakage current had to be used. That is, in such circuits, it was necessary to use cells with high driving force. Specifically, among the HVT cell 11 and the LVT cell 12, it was necessary to use the LVT cell 12 with high-speed operation and high driving force.

[0101] On the other hand, in Embodiment 3, among such combinational circuits that require short delays, for those where the operation speed and driving force are sufficient with the medium-speed operation and medium-driving force LVT(p)&HVT(n) cell 13, the LVT(p)&HVT(n) cell 13 is used. By doing so, in the combinational circuit, it is possible to suppress the leakage current while ensuring the required operation speed. Hereinafter, Embodiment 3 will be described using specific examples with reference to the drawings.

[0102] FIG. 20 shows a configuration example of a conventional combinational circuit, and FIG. 21 shows a configuration example of the combinational circuit according to Embodiment 3. In FIGS. 20 and 21, the flip-flop circuit is represented by "FF".

[0103] As shown in FIGS. 20 and 21, a part of the circuit 51 included in the digital circuit portion 101 includes a first flip-flop circuit FF1, a second flip-flop circuit FF2, a third flip-flop circuit FF3, a first combinational circuit KC1, and a second combinational circuit KC2. The first flip-flop circuit FF1, the second flip-flop circuit FF2, and the third flip-flop circuit FF3 operate in synchronization with the same clock signal CLK. The first combinational circuit KC1 is connected between the first flip-flop circuit FF1 and the second flip-flop circuit FF2. The second combinational circuit KC2 is connected between the second flip-flop circuit FF2 and the third flip-flop circuit FF3.

[0104] Here, for the sake of simplicity, the time delays caused by the operation of the combinational circuit are represented in three levels: large, medium, and small, and the required operating speeds are represented in three levels: high, medium, and low. The delay occurring in the first combinational circuit KC1 is small, and the required operating speed is low. The delay occurring in the second combinational circuit KC2 is medium, and the required operating speed is medium. Also, the operating speeds of the cells are represented in three levels: high, medium, and low. In this case, the operating speed of the HVT cell 11 is low, the operating speed of the LVT cell 12 is low, and the operating speed of the LVT(p)&HVT(n) cell 13 is medium.

[0105] FIG. 20 shows an example of using the conventional HVT cell 11 and LVT cell 12 in a combinational circuit. Also, FIG. 21 shows an example of using the HVT cell 11 and LVT(p)&HVT(n) cell 13 in a combinational circuit.

[0106] Conventionally, as shown in FIG. 20, for the first combinational circuit KC1 with a small delay and a low required operating speed, the HVT cell 11 with a low operating speed is used. Also, for the second combinational circuit KC2 with a medium delay and a medium required operating speed, the LVT cell 12 with a high operating speed has to be used.

[0107] On the other hand, in Embodiment 3, as shown in FIG. 21, for the first combinational circuit KC1 with a small delay and a low required operating speed, the HVT cell 11 with a low operating speed is used. However, for the second combinational circuit KC2 with a medium delay and a medium required operating speed, the LVT(p)&HVT(n) cell 13 with a medium operating speed is used.

[0108] That is, among the combinational circuits connected between flip-flop circuits, for combinational circuits with a relatively large resulting time delay (for example, long physical wiring or a large number of circuits), high-speed operating LVT cells 12 are used. For combinational circuits with a medium resulting delay that can be handled by the operating speed of LVT(p)&HVT(n) cells 13, LVT(p)&HVT(n) cells 13 are used. For combinational circuits with a relatively small resulting delay that do not require the operating speed up to LVT(p)&HVT(n) cells 13, low-speed HVT cells 11 are used.

[0109] Thus, in Embodiment 3, for the second combinational circuit KC2 that requires a medium operating speed, instead of high-speed high-leakage type LVT cells, medium-speed medium-leakage type LVT(p)&HVT(n) cells 13 are used. Therefore, according to Embodiment 3, in a digital circuit including a flip-flop circuit and a combinational circuit, cell leakage can be reduced while ensuring the required operating speed.

[0110] In the above specific example, cells are selectively used based on the required operating speed, but cells may also be selectively used based on the required driving force. For example, LVT cells 12 with a high driving force may be used in locations where a high driving force is required, HVT cells 11 with a small driving force may be used in locations where a small driving force is required, and LVT(p)&HVT(n) cells 13 with a medium driving force may be used in locations where a medium driving force is required.

[0111] (Embodiment 4) Embodiment 4 is an example of a NAND circuit type cell used in the digital circuit portion included in the semiconductor device.

[0112] As shown in FIG. 22, the NAND circuit type cell 41 according to the fourth embodiment includes a plurality of p-type MOSFETs and a plurality of n-type MOSFETs. The plurality of p-type MOSFETs are connected to the line Vdd on the high potential side of the power supply, which is the first potential, and are connected in parallel. The plurality of n-type MOSFETs are connected to the line Vss (GND) on the low potential side of the power supply, which is the second potential, and are connected in series. In the example of FIG. 22, the NAND circuit type cell 41 has a configuration in which three p-type MOSFETs connected in parallel and three n-type MOSFETs connected in series are connected. That is, the NAND circuit type cell 41 has three input terminals A, B, and C and one output terminal Y.

[0113] The p-type MOSFETs constituting the NAND circuit type cell 41 have a threshold voltage LVTP. The n-type MOSFETs constituting the NAND circuit type cell 41 have a threshold voltage HVTN. That is, the NAND circuit type cell 41 is an example of an LVT(p)&HVT(n) cell.

[0114] Here, consider the characteristics related to the on-current in the NAND circuit type cell 41. In a NAND circuit, when the number of input terminals increases, both the number of p-type MOSFETs connected in parallel and the number of n-type MOSFETs connected in series increase. Even if the number of p-type MOSFETs connected in parallel increases, the on-current of the entire p-type MOSFETs connected in parallel does not fall below the on-current of a single-stage p-type MOSFET. On the other hand, when the number of n-type MOSFETs connected in series, that is, the number of stacked stages, increases, the internal resistance of the entire n-type MOSFETs connected in series increases, and the on-current of the entire n-type MOSFETs connected in series, that is, stacked, decreases.

[0115] Therefore, if the number of input terminals of the NAND circuit type cell, that is, the number of stages of the n-type MOSFETs stacked vertically, is less than a certain number, the on-current of the n-type MOSFETs stacked vertically is greater than the on-current of a single-stage p-type MOSFET. However, if the number of input terminals, that is, the number of stages of the n-type MOSFETs stacked vertically, is equal to or more than a certain number, the on-current of the n-type MOSFETs stacked vertically becomes equal to or less than the on-current of a single-stage p-type MOSFET.

[0116] FIG. 23 shows a graph representing an example of the relationship between the vertical stacking number of n-type MOSFETs and the on-current in a NAND circuit type cell. In the example shown in FIG. 23, when the vertical stacking number GateN of the n-type MOSFETs becomes 3 or more, the on-current Ids of the vertically stacked n-type MOSFETs becomes smaller than the on-current of a single-stage p-type MOSFET. In this case, the operating speed of the NAND circuit type cell 41 is limited by the vertically stacked n-type MOSFETs. Therefore, it is more advantageous to apply an HVT(p)&LVT(n) cell rather than an LVT(p)&HVT(n) cell to the NAND circuit type cell 41 in terms of reducing the leakage current.

[0117] FIG. 24 shows an example in which an HVT(p)&LVT(n) cell is applied to a NAND circuit type cell. As shown in FIG. 24, the p-type MOSFETs constituting the NAND type cell 42 have a threshold voltage HVTP. Also, the n-type MOSFETs constituting the NAND type cell 42 have a threshold voltage LVTN. That is, the NAND type cell 42 is an example of an HVT(p)&LVT(n) cell.

[0118] Thus, in a NAND circuit type cell, it may be determined whether to apply an LVT(p)&HVT(n) cell or an HVT(p)&LVT(n) cell according to the vertical stacking number of the n-type MOSFETs so that the effect of reducing the leakage current is advantageous.

[0119] As described above, the invention made by the inventor of the present application has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications are possible within the scope not departing from the gist of the present invention. Also, the semiconductor device according to each embodiment is applicable to any product as long as it is a product using a digital circuit. A part of the content described in the above embodiments is described below.

[0120] [Appendix 1] A logic gate including a first cell including a first p-channel type MOSFET and a first n-channel type MOSFET, A logic gate, comprising a second cell including a second p-channel MOSFET and a second n-channel MOSFET, A logic gate, comprising a third cell including a third p-channel MOSFET and a third n-channel MOSFET, comprising The p-channel MOSFET of the first cell has a first threshold voltage, The n-channel MOSFET of the first cell has a second threshold voltage, The p-channel MOSFET of the second cell has a third threshold voltage, The n-channel MOSFET of the second cell has a fourth threshold voltage, The p-channel MOSFET of the third cell has the first threshold voltage, The n-channel MOSFET of the third cell has a sixth threshold voltage, The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, The absolute value of the sixth threshold voltage is higher than the absolute value of the first threshold voltage, A semiconductor device.

[0121] [Appendix 2] A logic gate, comprising a first cell including a first p-channel MOSFET and a first n-channel MOSFET, A logic gate, comprising a second cell including a second p-channel MOSFET and a second n-channel MOSFET, A logic gate, comprising a third cell including a third p-channel MOSFET and a third n-channel MOSFET, comprising The p-channel MOSFET of the first cell has a first threshold voltage, The n-channel MOSFET of the first cell has a second threshold voltage, The p-channel MOSFET of the second cell has a third threshold voltage, The n-channel MOSFET of the second cell has a fourth threshold voltage, The p-channel MOSFET of the third cell has the first threshold voltage, The n-channel MOSFET of the third cell has the fourth threshold voltage, The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, The third cell is a NAND gate having three or more input terminals, Semiconductor device.

Explanation of symbols

[0122] 10 Semiconductor substrate 11 HVT cell 12 LVT cell 13 LVT(p)&HVT(n) cell 21 NOT(INV) type cell 21L Off leakage 22, 41, 42 NAND type cells 23 NOR type cell 31, 31a, 31b NOT(INV) type cells 51 Part of the circuit 100 Semiconductor device 101 Digital circuit part 102, 103 Non-digital circuit parts 111 Mask for threshold voltage HVTP 112 Mask for threshold voltage HVTN 113 Mask for threshold voltage LVTP 114 Mask for threshold voltage LVTN 111h, 1112h, 1113h, 1114h Openings 311 p-type MOSFET 312 n-type MOSFET A, B, C Input terminals CLK Clock signal FF1 First flip-flop circuit FF2 The second flip-flop circuit FF3 The third flip-flop circuit KC1 The first combinational circuit KC2 The second combinational circuit Vdd The high-potential side line of the power supply Vss The low-potential side line of the power supply GND Ground Y Output terminal

Claims

1. A logic gate, comprising a first p-channel MOSFET connected to a first potential, and a first n-channel MOSFET connected to a second potential lower than the first potential, the first cell; A logic gate, comprising a second p-channel MOSFET connected to the first potential, and a second n-channel MOSFET connected to the second potential, the second cell; A logic gate, comprising a third p-channel MOSFET connected to the first potential, and a third n-channel MOSFET connected to the second potential, the third cell; Comprising The first p-channel MOSFET has a first threshold voltage; The first n-channel MOSFET has a second threshold voltage; The second p-channel MOSFET has a third threshold voltage; The second n-channel MOSFET has a fourth threshold voltage; The third p-channel MOSFET has the third threshold voltage; The third n-channel MOSFET has the second threshold voltage; The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage; The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage; A semiconductor device.

2. In the semiconductor device according to Claim 1, Each of the first p-channel MOSFET and the first n-channel MOSFET has a first gate insulating film; Each of the second p-channel MOSFET and the second n-channel MOSFET has a second gate insulating film; Each of the third p-channel MOSFET and the third n-channel MOSFET has a third gate insulating film; The thickness of the first gate insulating film, the thickness of the second gate insulating film, and the thickness of the third gate insulating film are the same as each other; A semiconductor device.

3. In the semiconductor device according to Claim 2, The first p-channel MOSFET has a channel having a first impurity concentration; The first n-channel MOSFET has a channel having a second impurity concentration; The second p-channel MOSFET has a channel having a third impurity concentration; The second n-channel MOSFET has a channel having a fourth impurity concentration; The third p-channel type MOSFET has a channel having the third impurity concentration, The third n-channel type MOSFET has a channel having the second impurity concentration, Semiconductor device.

4. In the semiconductor device according to claim 2, The first p-channel type MOSFET has a well having a first impurity concentration, The first n-channel type MOSFET has a well having a second impurity concentration, The second p-channel type MOSFET has a well having a third impurity concentration, The second n-channel type MOSFET has a well having a fourth impurity concentration, The third p-channel type MOSFET has a well having the third impurity concentration, The third n-channel type MOSFET has a well having the second impurity concentration, Semiconductor device.

5. In the semiconductor device according to claim 1, A first flip-flop circuit and a second flip-flop circuit that operate in synchronization with the same clock signal; A combinational circuit connected between the first flip-flop circuit and the second flip-flop circuit, The third cell is included in the combinational circuit, Semiconductor device.

6. A logic gate, a first cell including a first p-channel type MOSFET and a first n-channel type MOSFET; A logic gate, a second cell including a second p-channel type MOSFET and a second n-channel type MOSFET; A logic gate, a third cell including a third p-channel type MOSFET and a third n-channel type MOSFET; Comprising, The p-channel type MOSFET of the first cell has a first threshold voltage, The n-channel type MOSFET of the first cell has a second threshold voltage, The p-channel type MOSFET of the second cell has a third threshold voltage, The n-channel type MOSFET of the second cell has a fourth threshold voltage, The p-channel type MOSFET of the third cell has a fifth threshold voltage, The n-channel type MOSFET of the third cell has the fourth threshold voltage, The absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, The absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage, The absolute value of the fifth threshold voltage is smaller than the absolute value of the third threshold voltage. Semiconductor device.

7. In the semiconductor device according to claim 1, having a digital circuit portion and a non-digital circuit portion, the digital circuit portion includes the first cell, the second cell, and the third cell. Semiconductor device.

8. (a) A step of preparing a semiconductor substrate, (b) A step of forming a first p-channel MOSFET, a first n-channel MOSFET, a second p-channel MOSFET, a second n-channel MOSFET, a third p-channel MOSFET, and a third n-channel MOSFET on the semiconductor substrate, including, the first p-channel MOSFET and the first n-channel MOSFET constitute a first cell, the second p-channel MOSFET and the second n-channel MOSFET constitute a second cell, the third p-channel MOSFET and the third n-channel MOSFET constitute a third cell, the first p-channel MOSFET has a first threshold voltage and is connected to a first potential, the first n-channel MOSFET has a second threshold voltage and is connected to a second potential lower than the first potential, the second p-channel MOSFET has a third threshold voltage and is connected to the first potential, the second n-channel MOSFET has a fourth threshold voltage and is connected to the second potential, the third p-channel MOSFET has the third threshold voltage and is connected to the first potential, the third n-channel MOSFET has the second threshold voltage and is connected to the second potential, the absolute value of the first threshold voltage is higher than the absolute value of the third threshold voltage, the absolute value of the second threshold voltage is higher than the absolute value of the fourth threshold voltage. Method of manufacturing a semiconductor device.

9. In the method of manufacturing a semiconductor device according to claim 8, each of the first p-channel MOSFET and the first n-channel MOSFET has a first gate insulating film, each of the second p-channel MOSFET and the second n-channel MOSFET has a second gate insulating film, Each of the third p-channel MOSFET and the third n-channel MOSFET has a third gate insulating film. The method for manufacturing the semiconductor device is as follows. (c) After the step (a), a step of forming an insulating film on the semiconductor substrate; (d) A step of forming the first gate insulating film, the second gate insulating film, and the third gate insulating film by processing the insulating film; The method includes: A method for manufacturing a semiconductor device.

10. In the method for manufacturing a semiconductor device according to claim 9, (e) After the step (a), a step of forming a first p-well, a second p-well, and a third p-well by implanting p-type impurities into the semiconductor substrate; (f) A step of forming a first n-well, a second n-well, and a third n-well by implanting n-type impurities into the semiconductor substrate; (g) A step of forming a first mask film on the semiconductor substrate, which covers the second n-well, the third n-well, the first p-well, the second p-well, and the third p-well and exposes the channel of the first n-well; (h) After the step (g), a step of implanting n-type impurities into the channel of the first n-well using the first mask film; (i) A step of forming a second mask film on the semiconductor substrate, which covers the first n-well, the second n-well, the third n-well, and the second p-well and exposes the channels of the first p-well and the third p-well; (j) After the step (i), a step of implanting p-type impurities into the channels of the first p-well and the third p-well using the second mask film; (k) A step of forming a third mask film on the semiconductor substrate, which covers the first n-well, the first p-well, the second p-well, and the third p-well and exposes the channels of the second n-well and the third n-well; (l) After the step (k), a step of implanting n-type impurities into the channels of the second n-well and the third n-well using the third mask film; Step (m): Forming a fourth mask film on the semiconductor substrate, covering the first n-type well, the second n-type well, the third n-type well, the first p-type well, and the third p-type well, and exposing the channel of the second p-type well. Step (n): After the step (m), injecting p-type impurities into the channel of the second p-type well using the fourth mask film. The method includes: The first p-channel MOSFET has the first n-type well. The first n-channel MOSFET has the first p-type well. The second p-channel MOSFET has the second n-type well. The second n-channel MOSFET has the second p-type well. The third p-channel MOSFET has the third n-type well. The third n-channel MOSFET has the third p-type well. A method of manufacturing a semiconductor device.

11. In the method of manufacturing a semiconductor device according to Claim 10, the impurity concentration in the channel of the first n-type well is higher than the impurity concentration in the channel of the second n-type well and the impurity concentration in the channel of the third n-type well, and the impurity concentration in the channel of the first p-type well and the impurity concentration in the channel of the third p-type well are higher than the impurity concentration in the channel of the second p-type well. A method of manufacturing a semiconductor device.

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