Multilayer ceramic capacitor and mounting structure

Abstract

To provide a small-sized, thin multilayer ceramic capacitor that is excellent in electrical characteristics and reliability.SOLUTION: A multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 3. The laminate 2 is obtained by alternately laminating internal electrodes 6 and dielectric layers 7, and has a first surface 8a and a second surface 8b opposite to each other in a lamination direction. The external electrodes 3 include a first external electrode 3a and a second external electrode 3b, and the first external electrode 3a and the second external electrode 3b each include a main surface electrode part 30 that is located at least on the first surface 8a. The main surface electrode part 30 includes a first portion 31 and a second portion 32. The first portion 31 has a larger thickness than the second portion 32, and is located closer to a center part C of the laminate 2 on the main surface electrode part 30.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a mounting structure.

Background Art

[0002] In recent years, with the miniaturization and high functionality of electronic devices, miniaturization and thinning have also been promoted in electronic components such as multilayer ceramic capacitors mounted on electronic devices. However, when a multilayer ceramic capacitor is thinned, the strength of the laminate constituting the multilayer ceramic capacitor becomes insufficient, and the durability of the laminate tends to decrease.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor in which the durability of a laminate is enhanced by forming a free reinforcing layer inside the laminate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] As the multilayer ceramic capacitor becomes thinner, the conventional free reinforcement layer of the multilayer ceramic capacitor cannot ensure sufficient strength of the laminate, cracks may occur in the laminate, and the electrical characteristics and reliability of the laminate ceramic capacitor may deteriorate. In addition, multilayer ceramic capacitors are usually mounted on a substrate and used. However, in the case of a conventional multilayer ceramic capacitor, if the laminate has warpage, when the multilayer ceramic capacitor is pressed against the substrate, the laminate contacts the substrate, stress concentrates in a specific region of the laminate, and cracks may occur in the laminate. Alternatively, even if the conventional multilayer ceramic capacitor has no warpage in the laminate, when the multilayer ceramic capacitor is pressed against the substrate, warpage may occur in the substrate, stress may concentrate in a specific region of the laminate, and cracks may occur in the laminate.

Means for Solving the Problems

[0006] The multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, and has a first surface and a second surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the lamination direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the lamination direction and the length direction. And a laminate having a plurality of external electrodes, the plurality of internal electrodes have a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes are exposed on the first side surface, the plurality of second internal electrodes are exposed on the second side surface, the plurality of external electrodes have a first external electrode and a second external electrode, the first external electrode is located from the first side surface to at least the first surface and is connected to the plurality of first internal electrodes, the second external electrode is located from the second side surface to at least the first surface and is connected to the plurality of second internal electrodes, The first external electrode and the second external electrode each have a main surface electrode portion located at least on the first surface, and the main surface electrode portion has a first portion and a second portion. The first portion is thicker in the stacking direction than the second portion, and is located closer to the center of the laminate in the main surface electrode portion when viewed in the stacking direction.

[0007] The multilayer ceramic capacitor of the present disclosure is a substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately stacked, and has a first surface and a second surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the stacking direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the stacking direction and the length direction. It includes a plurality of external electrodes. The plurality of internal electrodes have a plurality of first internal electrodes and a plurality of second internal electrodes. The plurality of first internal electrodes are exposed at the corners extending from the first side surface to the third side surface and at the corners extending from the second side surface to the fourth side surface. The plurality of second internal electrodes are exposed at the corners extending from the first side surface to the fourth side surface and at the corners extending from the second side surface to the third side surface. The plurality of external electrodes include a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode. The first external electrode is located at least over the first surface from the corner extending from the first side surface to the third side surface, and is connected to the plurality of first internal electrodes. The second external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface, and is connected to the plurality of first internal electrodes. The third external electrode is located at least over the first surface from the corner extending from the first side surface to the fourth side surface, and is connected to the plurality of second internal electrodes. The fourth external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface, and is connected to the plurality of second internal electrodes. Each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode is a main surface electrode portion located at least on the first surface, and has a main surface electrode portion having a first portion and a second portion. The first portion is thicker than the second portion in the stacking direction, and is located closer to the center of the stacked body in the main surface electrode portion when viewed in the stacking direction.

[0008] The mounting structure of the present disclosure includes the above-described multilayer ceramic capacitor and a substrate having a mounting surface. The multilayer ceramic capacitor is mounted on the substrate such that the first surface of the stacked body faces the mounting surface.

Advantages of the Invention

[0009] According to the multilayer ceramic capacitor and the mounting structure of the present disclosure, even when the multilayer ceramic capacitor is thinned, cracking of the stacked body can be reduced when the multilayer ceramic capacitor is mounted on the substrate. As a result, deterioration of the electrical characteristics and reliability of the stacked body ceramic capacitor and the mounting structure can be reduced.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor and the mounting structure of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic, and the dimensional ratios on the drawings do not necessarily match the actual ones. In this specification, in some drawings, for convenience, a rectangular coordinate system XYZ is defined. The X-axis direction is also referred to as the first direction or the length direction. The Y-axis direction is also referred to as the second direction or the width direction. The Z-axis direction is also referred to as the third direction, the height direction, or the stacking direction. In this specification, a plan view means looking in the Z-axis direction.

[0012] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure, FIG. 2 is a plan view showing the multilayer ceramic capacitor of FIG. 1, and FIG. 3 is a cross-sectional view taken along the cutting plane line III-III of FIG. 2. FIG. 4 is a perspective view showing a mounting structure according to an embodiment of the present disclosure. FIGS. 5 to 7 are cross-sectional views showing a state in which the multilayer ceramic capacitor of FIG. 1 is mounted on a substrate using a mounting device. FIGS. 8 to 11 are cross-sectional views showing a part of the multilayer ceramic capacitor of FIG. 1 enlarged. FIG. 12 is a perspective view showing a multilayer ceramic capacitor according to another embodiment of the present disclosure, FIG. 13 is a plan view showing the multilayer ceramic capacitor of FIG. 12, FIG. 14 is a cross-sectional view taken along the cutting plane line XIV-XIV of FIG. 13, and FIG. 15 is a perspective view showing a laminate of the multilayer ceramic capacitor of FIG. 12. FIG. 16 is a perspective view showing a mounting structure according to another embodiment of the present disclosure. Note that the substrates shown in FIGS. 4 and 16 have wiring conductors, electronic components, etc. located on the substrate, but the wiring conductors, electronic components, etc. are omitted in FIGS. 4 and 16. Further, FIGS. 5 to 7 are diagrams for explaining the strength of the multilayer ceramic capacitor, so the wiring conductors, electronic components, solder paste, or conductive resin paste, etc. located on the substrate are omitted. Further, in FIG. 15, for ease of illustration, hatching is applied to the internal electrodes and dummy electrodes exposed on the surface of the laminate and shown.

[0013] A multilayer ceramic capacitor according to an embodiment of the present disclosure will be described. The multilayer ceramic capacitor 1 of this embodiment may be a thin multilayer ceramic capacitor. The thin multilayer ceramic capacitor may be, for example, a multilayer ceramic capacitor in which the ratio of the dimension in the length direction (X-axis direction) to the dimension in the height direction (Z-axis direction) is greater than 4. Hereinafter, the multilayer ceramic capacitor 1 may sometimes be simply referred to as the capacitor 1.

[0014] The multilayer ceramic capacitor 1 of this embodiment includes a laminate 2 and a plurality of external electrodes 3 as shown in FIG. 1.

[0015] The laminate 2 is configured by alternately laminating a plurality of internal electrodes 6 and a plurality of dielectric layers 7 in the lamination direction (Z-axis direction). As shown in FIG. 3, the laminate 2 may be configured to include a capacitance forming portion 4 and a pair of cover portions 5. The capacitance forming portion 4 is formed by alternately laminating a plurality of internal electrodes 6 and a plurality of dielectric layers 7 in the Z-axis direction to form capacitance. The cover portions 5 are respectively located at both ends of the capacitance forming portion 4 in the lamination direction.

[0016] The laminate 2 is substantially rectangular parallelepiped. The laminate 2 has a first surface 8a and a second surface 8b that face each other in the lamination direction. Hereinafter, the first surface 8a and the second surface 8b may be collectively referred to as the main surfaces 8a, 8b. Further, the laminate 2 has a first side surface 9a and a second side surface 9b that face each other in the length direction (X-axis direction) orthogonal to the lamination direction (Z-axis direction), and a third side surface 9c and a fourth side surface 9d that face each other in the width direction (Y-axis direction) orthogonal to the lamination direction (Z-axis direction) and the length direction (X-axis direction). Hereinafter, the first side surface 9a, the second side surface 9b, the third side surface 9c, and the fourth side surface 9d may be collectively referred to as the side surfaces 9a to 9d.

[0017] As shown in FIG. 3, the plurality of internal electrodes 6 include a plurality of first internal electrodes 6a and a plurality of second internal electrodes 6b. The first internal electrode 6a and the second internal electrode 6b have different polarities. In other words, when the first internal electrode 6a has a first polarity, the second internal electrode 6b has a second polarity different from the first polarity. The first internal electrode 6a and the second internal electrode 6b are alternately arranged with the dielectric layer 7 interposed therebetween in the lamination direction. The plurality of first internal electrodes 6a are exposed on the first side surface 9a of the laminate 2. The plurality of second internal electrodes 6b are exposed on the second side surface 9b of the laminate 2.

[0018] The internal electrode 6 is made of a conductive material. The internal electrode 6 may be made of a metal material mainly composed of a metal such as Ni (nickel), Cu (copper), Sn (tin), Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or an alloy thereof. Note that the main component refers to the component having the highest content ratio in the material or member of interest.

[0019] The dielectric layer 7 is made of a dielectric material. The dielectric layer 7 may be made of a ceramic material mainly composed of, for example, BaTiO3 (barium titanate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (barium zirconate), etc. The ceramic material constituting the dielectric layer 7 may contain, as secondary components with a lower content ratio than the main component, Mn (manganese) compounds, Mg (magnesium) compounds, Si (silicon) compounds, rare earth compounds, etc.

[0020] As shown in FIGS. 1 to 3, the plurality of external electrodes 3 include a first external electrode 3a and a second external electrode 3b. The first external electrode 3a is located from the first side surface 9a over at least the first surface 8a. The first external electrode 3a may be located from the first side surface 9a over the first surface 8a and the second surface 8b, or may be located from the first side surface 9a over the first surface 8a, the second surface 8b, the third side surface 9c, and the fourth side surface 9d. The first external electrode 3a is connected to the end of the first internal electrode 6a exposed on the first side surface 9a. The second external electrode 3b is located from the second side surface 9b over at least the first surface 8a. The second external electrode 3b may be located from the second side surface 9b over the first surface 8a and the second surface 8b, or may be located from the second side surface 9b over the first surface 8a, the second surface 8b, the third side surface 9c, and the fourth side surface 9d. The second external electrode 3b is connected to the end of the second internal electrode 6b exposed on the second side surface 9b.

[0021] The external electrode 3 is made of a conductive material. The external electrode 3 may be made of a metal material mainly composed of, for example, metals such as Ni, Cu, Sn, Pt, Pd, Ag, Au, or their alloys. The external electrode 3 may be formed by a thin film formation technique such as, for example, an electroplating method, a sputtering method, or a vapor deposition method, or may also be formed by a thick film formation technique such as, for example, an inkjet method, a dipping method, a screen printing method, or a gravure printing method. The electroplating method may be, for example, an electroless plating method, an electrolytic plating method, etc. The external electrode 3 may be configured to contain a conductive resin. The conductive resin may be, for example, an epoxy resin or a phenolic resin containing a metal powder such as Ag.

[0022] The external electrode 3 may be configured by laminating a plurality of conductor layers. The plurality of conductor layers may include a conductor layer formed by a thin film forming technique and a conductor layer formed by a thick film forming technique. Although details will be described later, the underlying layer of the external electrode 3 (i.e., the layer other than the outermost layer) may be configured to include at least one dielectric layer and at least one conductor layer. In this case, by adjusting at least one of the thickness and the number of layers of the dielectric layer, it becomes easy to partially change the thickness of the external electrode 3. The dielectric layer may be made of, for example, a ceramic material or a conductive resin. The ceramic material may be the same ceramic material as that constituting the dielectric layer 7.

[0023] As shown in FIGS. 1 to 3, the first external electrode 3a and the second external electrode 3b include at least a main surface electrode portion 30 located on the first surface 8a. When the first external electrode 3a and the second external electrode 3b are located on the first surface 8a and the second surface 8b, the first external electrode 3a and the second external electrode 3b may include main surface electrode portions 30 located on the first surface 8a and the second surface 8b. The main surface electrode portion 30 includes a first portion (also referred to as a thick portion) 31 and a second portion (also referred to as a thin portion) 32. The first portion 31 is thicker in the stacking direction (Z-axis direction) than the second portion 32. Further, as shown in FIG. 2, in a plan view, the first portion 31 is located closer to the center portion C of the laminate 2 in the main surface electrode portion 30. The center portion C may be the center (centroid) of the first surface 8a or the second surface 8b in a plan view.

[0024] As shown in FIG. 2, in a plan view, the first portion 31 may extend over the entire laminate 2 (the entire first surface 8a) in the width direction (Y-axis direction). As shown in FIGS. 2 and 3, for the first portion 31, it is sufficient that the location 31H where the height H from the second portion 32 is the highest is located closer to the center portion C than the center line M of the main surface electrode portion 30. The center line M may be a line that bisects the main surface electrode portion 30 in the length direction (X-axis direction). The first portion 31 may be located at an end on the center portion C side in the main surface electrode portion 30.

[0025] As described above, the laminate 2 may include a pair of cover portions 5. The cover portion 5 is made of a dielectric material. The cover portion 5 may be made of a ceramic material mainly composed of, for example, BaTiO3, CaTiO3, SrTiO3, BaZrO3, etc. The cover portion 5 may be composed of a plurality of dielectric layers laminated in the lamination direction (Z-axis direction). The dielectric layer constituting the cover portion 5 may be the dielectric layer 7 constituting the capacitance forming portion 4.

[0026] The cover portion 5 may include dummy electrodes 5a that do not contribute to the formation of capacitance. As shown in FIG. 3, the dummy electrodes 5a may be located at both ends of the cover portion 5 in the length direction (X-axis direction). The dummy electrode 5a on the first side surface 9a side may be exposed on the first side surface 9a, and the dummy electrode 5a on the second side surface 9b side may be exposed on the second side surface 9b. Note that the dummy electrode 5a on the first side surface 9a side and the dummy electrode 5a on the second side surface 9b side are not electrically connected. The dummy electrode 5a may be exposed on at least one of the first surface 8a and the second surface 8b as long as it is covered by the external electrode 3. The dummy electrode 5a may be exposed on the third side surface 9c and the fourth side surface 9d as long as it is covered by the external electrode 3. By including the dummy electrode 5a in the cover portion 5, the adhesion between the laminate 2 and the external electrode 3 can be enhanced, and the reliability of the capacitor 1 can be improved.

[0027] As shown in FIG. 4, the capacitor 1 may be mounted on a substrate (also referred to as a circuit board) 10. An electronic component formed by mounting the capacitor 1 on the substrate 10 is referred to as a mounting structure 20. The substrate 10 has a mounting surface 10a on which a first mounting electrode 11 and a second mounting electrode 12 are disposed. The capacitor 1 is mounted on the substrate 10 via a conductive bonding material CA such that the main surface electrode portions 30 of the first external electrode 3a and the second external electrode 3b are electrically connected to the first mounting electrode 11 and the second mounting electrode 12, respectively. The conductive bonding material CA may be, for example, solder, a conductive adhesive, or the like. When the main surface electrode portion 30 is located only on the first surface 8a of the laminate 2, the capacitor 1 is mounted on the substrate 10 such that the first surface 8a of the laminate 2 faces the mounting surface 10a. When the main surface electrode portion 30 is located on both the first surface 8a and the second surface 8b, the capacitor 1 is mounted on the substrate 10 such that either the first surface 8a or the second surface 8b faces the mounting surface 10a.

[0028] As shown in FIGS. 5 and 6, the capacitor 1 is mounted on the substrate 10 by pressing the capacitor 1 adsorbed by the suction nozzle 15 of the mounting device against the substrate 10 on which the conductive bonding material CA is applied to the first mounting electrode 11 and the second mounting electrode 12. In FIGS. 5 and 6, the first mounting electrode 11, the second mounting electrode 12, and the conductive bonding material CA are omitted. Here, if the main surface electrode portion 30 does not have the first portion 31 (that is, if the thickness of the main surface electrode portion 30 is substantially constant), when the laminate 2 is warped, the laminate 2 may come into contact with the substrate 10 when the capacitor 1 is pressed against the substrate 10. As a result, stress may concentrate in a specific region (for example, a region near the center C) of the laminate 2, and cracks may occur from the specific region.

[0029] Since the main surface electrode portion 30 of the capacitor 1 has the first portion 31, even if the laminate 2 is warped, when the capacitor 1 is pressed against the substrate 10, the first portion 31 comes into contact with the substrate 10, making it difficult for the end portion (end portion in the length direction) of the laminate 2 to come into contact with the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced.

[0030] When the first part 31 is located at the end on the center part C side in the main surface electrode part 30, regardless of the direction of the warp of the laminate 2, when the capacitor 1 is pressed against the substrate 10, stress concentration in a specific region (for example, a region near the center part C) of the laminate 2 can be reduced. As a result, generation of cracks from the specific region of the laminate 2 can be effectively reduced.

[0031] The main surface electrode part 30 (first part 31) may be located on both the first surface 8a and the second surface 8b. In this case, when mounting the capacitor 1 on the substrate 10, either the first surface 8a or the second surface 8b may be opposed to the mounting surface 10a, so that the labor of checking the surface on which the main surface electrode part 30 (first part 31) in the laminate 2 is located can be simplified. As a result, the manufacturing cost of the mounting structure 20 in which the capacitor 1 is mounted on the substrate 10 can be reduced.

[0032] When the total thickness of the laminate 2 in the stacking direction (Z-axis direction) is Ttot, the thickness of the center part C is Tc, and the height of the first part 31 with respect to the second part 32 (hereinafter, also simply referred to as the height of the first part 31) is H, the capacitor 1 may satisfy the following formula (1). Ttot - Tc < H …(1)

[0033] As shown in FIGS. 5 and 6, the total thickness Ttot in formula (1) may be the length between the upper end and the lower end of the laminate 2 in the stacking direction (Z-axis direction). The left side of formula (1) represents the warp of the laminate 2. Since the height H of the first part 31 is larger than the warp of the laminate 2, even if the laminate 2 has a warp, when the capacitor 1 is pressed against the substrate 10, the laminate 2 can be prevented from contacting the substrate 10, and the first part 31 can be brought into contact with the substrate 10. As a result, stress concentration in a specific region (for example, a region near the center part C) of the laminate 2 can be reduced, and generation of cracks in the laminate 2 can be reduced. Consequently, deterioration of the electrical characteristics and reliability of the capacitor 1 and the mounting structure 20 can be reduced.

[0034] The height H of the first portion 31 may be, for example, less than 10 μm. In the case of the small multilayer ceramic capacitor 1, for example, the capacitor 1 having dimensions in the length direction (X-axis direction) and the width direction (Y-axis direction) of 2 mm or less, the warp of the laminate 2 is substantially less than 10 μm and may be less than 5 μm. Therefore, the first portion 31 can satisfy both the formula (1) and H < 10 μm. By setting the height H of the first portion 31 to less than 10 μm, in the manufacture of the capacitor 1, an increase in the manufacturing cost associated with the formation of the first portion 31 can be suppressed. As a result, the manufacturing cost of the capacitor 1 can be reduced.

[0035] Note that, as shown in FIG. 7, even if the laminate 2 has no warp, the substrate 10 may warp when the capacitor 1 is pressed against the substrate 10. If the main surface electrode portion 30 does not have the first portion 31, both ends of the capacitor 1 in the length direction (X-axis direction) come into contact with the substrate 10, and as a result, stress may concentrate in a specific region of the laminate 2 (for example, a region near the center portion C), and cracks may occur from the specific region. Even if the substrate 10 warps when the capacitor 1 is pressed against the substrate 10, the capacitor 1 has the first portion 31 in contact with the substrate 10, making it difficult for both ends of the capacitor 1 in the length direction to come into contact with the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced.

[0036] As shown in FIG. 7, when the point that overlaps the center portion C in plan view on the mounting surface 10a is 10b, and the points that overlap both ends of the laminate 2 in the length direction (X-axis direction) in plan view are 10c and 10d, the warp of the substrate 10 may be the length L1 between the point 10b and the point 10c in the lamination direction (Z-axis direction), or the length L2 between the point 10b and the point 10d in the lamination direction. The warp of the substrate 10 may be the longer one of the length L1 and the length L2. The warp of the substrate 10 can be known in advance in consideration of the dimensions of the capacitor 1, the force for pressing the capacitor 1 against the mounting surface 10a, and the like. By making the height H of the first portion larger than the warp of the substrate 10, even if the substrate 10 warps, it becomes difficult for both ends of the capacitor 1 in the length direction to come into contact with the substrate 10, so that the occurrence of cracks in the laminate 2 can be reduced.

[0037] Next, the configuration and formation method of the first part 31 and the second part 32 of the main surface electrode part 30 will be described.

[0038] The main surface electrode part 30 may be composed of at least one conductor layer. As shown in FIG. 8, the main surface electrode part 30 may be composed of a plurality of conductor layers 30a, 30b, 30c. The first part 31 may be composed of the conductor layers 30a, 30b, 30c. The conductor layer 30a, the conductor layer 30b, and the conductor layer 30c constituting the first part 31 may be laminated in this order on the main surfaces 8a, 8b. The second part 32 may be composed of the conductor layers 30a, 30c. The conductor layer 30a and the conductor layer 30c constituting the second part 32 may be laminated in this order on the main surfaces 8a, 8b.

[0039] The conductor layer 30a may be formed by the above-described thick film forming technique. The conductor layer 30a may be the dummy electrode 5a that constitutes a part of the main surfaces 8a and 8b. The conductor layer 30b covers a part of the conductor layer 30a. The conductor layer 30b may be formed by the above-described thick film forming technique. The conductor layer 30b may be formed by an inkjet method or a screen printing method. The conductor layer 30c covers the conductor layer 30a and the conductor layer 30b. The conductor layer 30c may be formed by the above-described thin film forming technique. The conductor layer 30c may be formed by an electroless plating method or an electrolytic plating method. The conductor layer 30c may extend from above the conductor layers 30a and 30b over the side surfaces 9a to 9d of the laminate 2. The conductor layer 30c may be connected to the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By configuring the main surface electrode portion 30 with the plurality of conductor layers 30a, 30b, and 30c and making the number of layers of the conductor layers 30a, 30b, and 30c that constitute the first site 31 different from the number of layers of the conductor layers 30a and 30c that constitute the second site 32, it becomes possible to easily form the main surface electrode portion 30 having the first site 31 and the second site 32. Note that the laminate 2 may or may not have the dummy electrode 5a. However, when the laminate 2 has the dummy electrode 5a, the dummy electrode 5a is exposed on the first side surface 9a and the second side surface 9b where the external electrode 3 is located. Therefore, in the manufacturing process of the multilayer ceramic capacitor 1, the plating layer (conductor layer 30c) that constitutes a part of the external electrode 3 can be directly formed on the fired laminate 2, and the step of applying the conductive paste for the base of the plating layer can be omitted. In addition, the adhesion between the laminate 2 and the conductor layer 30c can be enhanced. As a result, a decrease in the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0040] The main surface electrode portion 30 may be composed of at least one dielectric layer and at least one conductor layer. As shown in FIG. 9, the main surface electrode portion 30 may be composed of a dielectric layer 30d and a plurality of conductor layers 30e, 30f. The first portion 31 may be composed of the dielectric layer 30d and the conductor layers 30e, 30f. The dielectric layer 30d, the conductor layer 30e, and the conductor layer 30f constituting the first portion 31 may be laminated in this order on the main surfaces 8a, 8b. The second portion 32 may be composed of the conductor layers 30e, 30f. The conductor layer 30e and the conductor layer 30f constituting the second portion 32 may be laminated in this order on the main surfaces 8a, 8b.

[0041] The dielectric layer 30d may be formed by firing a ceramic green sheet. The ceramic green sheet that becomes the dielectric layer 30d may be formed by disposing the ceramic green sheet on at least one of the upper and lower surfaces of the mother laminate when producing the mother laminate for constituting the laminate 2 (see FIG. 22). As shown in FIG. 9, when the first portion 31 is located at the end portion on the center portion C side in the main surface electrode portion 30, the dielectric layer 30d may further extend toward the center portion C side. The conductor layer 30e is in contact with a part of the main surfaces 8a and 8b and covers a part of the dielectric layer 30d. The conductor layer 30e may be formed by a thick film forming technique. The conductor layer 30f covers the conductor layer 30e. The conductor layer 30f may cover a part of the dielectric layer 30d. The conductor layer 30f may be formed by a thin film forming technique. The conductor layer 30f may be formed by an electroless plating method or an electrolytic plating method. The conductor layer 30f may extend from above the conductor layer 30e over the side surfaces 9a to 9d of the laminate 2. The conductor layer 30f may be connected to the end portions of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By configuring the first portion 31 with the dielectric layer 30d and the conductor layers 30e and 30f, and the second portion 32 with the conductor layers 30e and 30f, it becomes possible to easily form the main surface electrode portion 30 having the first portion (thick portion) 31 and the second portion (thin portion) 32. Further, by adjusting the thickness of the dielectric layer 30d, the height H of the first portion 31 can be adjusted. Note that the laminate 2 may or may not have the dummy electrode 5a. However, when the laminate 2 has the dummy electrode 5a, the dummy electrode 5a is exposed on the first side surface 9a and the second side surface 9b where the external electrode 3 is located. Therefore, in the manufacturing process of the multilayer ceramic capacitor 1, a plating layer (conductor layer 30f) constituting a part of the external electrode 3 can be directly formed on the fired laminate 2, and the process of applying a conductive paste for the base of the plating layer can be omitted. Further, the adhesion between the laminate 2 and the conductor layer 30f can be enhanced. As a result, a decrease in the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0042] As shown in FIG. 10, the first portion 31 may be formed by alternately laminating a plurality of dielectric layers 30d and a plurality of conductor layers 30e on the main surfaces 8a and 8b, and forming a conductor layer 30f that covers the laminate of the plurality of dielectric layers 30d and the plurality of conductor layers 30e. In this case, it becomes easy to adjust the height H of the first portion 31. Further, as shown in FIG. 10, the second portion 32 may be formed by laminating a plurality of conductor layers 30e and forming a conductor layer 30f that covers the laminate of the plurality of conductor layers 30e.

[0043] As shown in FIG. 11, the main surface electrode portion 30 may be composed of a dielectric layer 30g and a plurality of conductor layers 30h, 30i, and 30j. The first portion 31 may be composed of the dielectric layer 30g and the conductor layers 30h, 30i, and 30j. The conductor layer 30h, the dielectric layer 30g, the conductor layer 30i, and the conductor layer 30j that constitute the first portion 31 may be laminated in this order on the main surfaces 8a and 8b. The second portion 32 may be composed of the conductor layers 30h, 30i, and 30j. The conductor layer 30h, the conductor layer 30i, and the conductor layer 30j that constitute the second portion 32 may be laminated in this order on the main surfaces 8a and 8b.

[0044] The conductor layer 30h may be formed by the above-described thick film forming technique. The conductor layer 30h may be the dummy electrode 5a that constitutes a part of the main surfaces 8a and 8b. The dielectric layer 30g covers a part of the conductor layer 30h. The dielectric layer 30g may be formed by firing a ceramic green sheet. The ceramic green sheet that becomes the dielectric layer 30g may be formed by applying a ceramic slurry on the main surfaces 8a and 8b and on the conductor layer 30h and drying it. The conductor layer 30i covers a part of the conductor layer 30h and a part of the dielectric layer 30g. The conductor layer 30h may be formed by the above-described thick film forming technique. The conductor layer 30j covers the conductor layer 30i. The conductor layer 30j may cover a part of the dielectric layer 30g. The conductor layer 30j may be formed by the above-described thin film forming technique. The conductor layer 30j may be formed by electroless plating or electroplating. The conductor layer 30j may extend from above the conductor layer 30i over the side surfaces 9a to 9d of the laminate 2. The conductor layer 30j may be connected to the ends of the internal electrodes 6 exposed on the side surfaces 9a to 9d. By configuring the first part 31 with the dielectric layer 30g and the conductor layers 30h, 30i, and 30j, and the second part 32 with the conductor layers 30h, 30i, and 30j, it becomes possible to easily form the main surface electrode part 30 having the first part (thick part) 31 and the second part (thin part) 32. Further, by adjusting the thickness of the dielectric layer 30g, the height H of the first part 31 can be adjusted. Note that the laminate 2 may or may not have the dummy electrode 5a. However, when the laminate 2 has the dummy electrode, the dummy electrode 5a is exposed on the first side surface 9a and the second side surface 9b where the external electrode 3 is located. Therefore, in the manufacturing process of the multilayer ceramic capacitor 1, a plating layer (conductor layer 30j) that constitutes a part of the external electrode 3 can be directly formed on the fired laminate 2, and the process of applying a conductive paste for the base of the plating layer can be omitted. Also, the adhesion between the laminate 2 and the conductor layer 30f can be enhanced. As a result, a decrease in the electrical characteristics and reliability of the capacitor 1 can be reduced.

[0045] Next, a multilayer ceramic capacitor according to the second embodiment of the present disclosure will be described. The multilayer ceramic capacitor 1A of this embodiment has a different structure of the internal electrode 6 and the external electrode 3 from the above-described multilayer ceramic capacitor 1, and the others (for example, the outer shape of the laminate 2, the materials of the respective components, etc.) are the same as those of the multilayer ceramic capacitor 1. Therefore, detailed descriptions of the same configurations will be omitted.

[0046] As shown in FIG. 12, the multilayer ceramic capacitor 1A includes a laminate 2 and a plurality of external electrodes 3.

[0047] As shown in FIG. 14, the plurality of internal electrodes 6 include a plurality of first internal electrodes 6a and a plurality of second internal electrodes 6b. The first internal electrode 6a and the second internal electrode 6b have different polarities. The first internal electrode 6a and the second internal electrode 6b are alternately arranged with the dielectric layer 7 interposed therebetween in the stacking direction.

[0048] As shown in FIG. 15, the plurality of first internal electrodes 6a are exposed at the corner 2a extending from the first side surface 9a to the third side surface 9c and the corner 2b extending from the second side surface 9b to the fourth side surface 9d. As shown in FIG. 15, the plurality of second internal electrodes 6b are exposed at the corner 2c extending from the first side surface 9a to the fourth side surface 9d and the corner 2d extending from the second side surface 9b to the third side surface 9c.

[0049] As shown in FIGS. 12 and 13, the plurality of external electrodes 3 include a first external electrode 3a, a second external electrode 3b, a third external electrode 3c, and a fourth external electrode 3d.

[0050] The first external electrode 3a is located at least over the first surface 8a from the corner 2a extending from the first side surface 9a to the third side surface 9c. The first external electrode 3a may be located over the first surface 8a and the second surface 8b from the corner 2a extending from the first side surface 9a to the third side surface 9c. The first external electrode 3a is connected to the end of the first internal electrode 6a exposed at the corner 2a. The second external electrode 3b is located at least over the first surface 8a from the corner 2b extending from the second side surface 9b to the fourth side surface 9d. The second external electrode 3b may be located over the first surface 8a and the second surface 8b from the corner 2b extending from the second side surface 9b to the fourth side surface 9d. The second external electrode 3b is connected to the end of the first internal electrode 6a exposed at the corner 2b.

[0051] The third external electrode 3c is located at least over the first surface 8a from the corner 2c extending from the first side surface 9a to the fourth side surface 9d. The third external electrode 3c may be located over the first surface 8a and the second surface 8b from the corner 2c extending from the first side surface 9a to the fourth side surface 9d. The third external electrode 3c is connected to the end of the second internal electrode 6b exposed at the corner 2c. The fourth external electrode 3d is located at least over the first surface 8a from the corner 2d extending from the second side surface 9b to the third side surface 9c. The fourth external electrode 3d may be located over the first surface 8a and the second surface 8b from the corner 2d extending from the second side surface 9b to the third side surface 9c. The fourth external electrode 3d is connected to the end of the second internal electrode 6b exposed at the corner 2d.

[0052] As shown in FIGS. 12 to 14, the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d include a main surface electrode portion 30 located at least on the first surface 8a. When the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are located on the first surface 8a and the second surface 8b, the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d may include the main surface electrode portion 30 located on the first surface 8a and the second surface 8b. The main surface electrode portion 30 includes a first portion (also referred to as a thick portion) 31 and a second portion (also referred to as a thin portion) 32. The first portion 31 is thicker than the second portion 32 in the stacking direction (Z-axis direction). Also, as shown in FIG. 13, in plan view, the first portion 31 is located closer to the center C of the laminate 2 in the main surface electrode portion 30. The center C may be the center (centroid) of the first surface 8a or the second surface 8b in plan view.

[0053] As shown in FIGS. 13 and 14, for the first portion 31, it is sufficient that the location 31H where the height H from the second portion 32 is the highest is located closer to the center C side than the center line M of the main surface electrode portion 30 in the direction in which the diagonal line of the first surface 8a or the second surface 8b extends. The first portion 31 may be located at the end on the center C side of the main surface electrode portion 30. FIG. 13 shows an example in which the shape of the first portion 31 in plan view is a sector (quarter circle), but it is not limited thereto. The shape of the first portion 31 in plan view may be, for example, a rectangle, a right triangle, or the like.

[0054] As shown in FIG. 16, the capacitor 1A may be mounted on a substrate (also referred to as a circuit board) 10. An electronic component formed by mounting the capacitor 1A on the substrate 10 is referred to as a mounting structure 20A. The substrate 10 has a mounting surface 10a on which a first mounting electrode 11, a second mounting electrode 12, a third mounting electrode 13, and a fourth mounting electrode 14 are disposed. The capacitor 1A is mounted on the substrate 10 via a conductive bonding material CA such that the main surface electrode portions 30 of the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d are electrically connected to the first mounting electrode 11, the second mounting electrode 12, the third mounting electrode 13, and the fourth mounting electrode 14, respectively. When the main surface electrode portion 30 is located only on one of the first surface 8a and the second surface 8b of the laminate 2, the capacitor 1A is mounted on the substrate 10 such that the surface of the laminate 2 on which the main surface electrode portion 30 is located faces the mounting surface 10a. When the main surface electrode portion 30 is located on both the first surface 8a and the second surface 8b, the capacitor 1A is mounted on the substrate 10 such that either the first surface 8a or the second surface 8b faces the mounting surface 10a.

[0055] The capacitor 1A is mounted on the substrate 10 by pressing the capacitor 1A adsorbed by the suction nozzle 15 of the mounting device against the substrate 10 on which the conductive bonding material CA is applied to the first mounting electrode 11, the second mounting electrode 12, the third mounting electrode 13, and the fourth mounting electrode 14 (see FIGS. 5 to 7). Since the main surface electrode portion 30 of the capacitor 1A has a first portion 31, even if the laminate 2 is warped, when the capacitor 1A is pressed against the substrate 10, the first portion 31 abuts against the substrate 10, making it difficult for the ends of the laminate 2 (the ends in the length direction and the ends in the width direction) to abut against the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced.

[0056] When the first portion 31 is located at an end portion on the center portion C side in the main surface electrode portion 30, regardless of the direction of warping of the laminate 2, when the capacitor 1A is pressed against the substrate 10, stress concentration in a specific region of the laminate 2 (for example, a region near the center portion C) can be reduced. As a result, the occurrence of cracks from a specific region of the laminate 2 can be effectively reduced.

[0057] The main surface electrode portion 30 (first portion 31) may be located on both the first surface 8a and the second surface 8b. In this case, when mounting the capacitor 1A on the substrate 10, either the first surface 8a or the second surface 8b may face the mounting surface 10a. Thus, the labor of checking the surface on which the main surface electrode portion 30 (first portion 31) in the laminate 2 is located can be simplified. As a result, the manufacturing cost of the mounting structure 20 in which the capacitor 1A is mounted on the substrate 10 can be reduced.

[0058] The capacitor 1A may satisfy the above formula (1). The total thickness Ttot, the thickness Tc of the central portion C, and the height H of the first portion 31 are the same as above. Since the height H of the first portion 31 is greater than the warp of the laminate 2 (the left side in formula (1)), even if the laminate 2 has a warp, when the capacitor 1A is pressed against the substrate 10, the laminate 2 can be prevented from contacting the substrate 10, and the first portion 31 can be made to contact the substrate 10. As a result, the concentration of stress in a specific region of the laminate 2 (for example, a region near the central portion C) can be reduced, and the occurrence of cracks in the laminate 2 can be reduced. Consequently, the degradation of the electrical characteristics and reliability of the capacitor 1A and the mounting structure 20A can be reduced.

[0059] The height H of the first portion 31 may be, for example, less than 10 μm. In a small-sized multilayer ceramic capacitor 1A, for example, a capacitor 1A having dimensions in the length direction (X-axis direction) and the width direction (Y-axis direction) of 2 mm or less, the warp of the laminate 2 is substantially less than 10 μm and may be less than 5 μm. Therefore, the first portion 31 can satisfy both formula (1) and H < 10 μm. By setting the height H of the first portion 31 to less than 10 μm, an increase in the manufacturing cost associated with the formation of the first portion 31 can be suppressed in the manufacture of the capacitor 1A. As a result, the manufacturing cost of the capacitor 1A can be reduced.

[0060] Similar to capacitor 1, when capacitor 1A is pressed against substrate 10, even if the substrate 10 warps, the first part 31 abuts against the substrate 10, making it difficult for both ends of capacitor 1A in the length direction to abut against the substrate 10. As a result, the occurrence of cracks in the laminate 2 can be reduced. Also, by making the height H of the first part larger than the warp of the substrate 10, even if the substrate 10 warps, it becomes difficult for both ends of capacitor 1A in the length direction to abut against the substrate 10, so the occurrence of cracks in the laminate 2 can be reduced.

[0061] Next, a method for manufacturing the multilayer ceramic capacitors 1 and 1A will be described. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 1A will be described. The multilayer ceramic capacitor 1 can be manufactured by the same manufacturing method as the multilayer ceramic capacitor 1A. Note that each constituent member of the multilayer ceramic capacitor 1A has the same structure before and after cutting the mother laminate, and also has the same structure before and after firing. Therefore, in the following description, the above terms and reference numerals may be used.

[0062] FIG. 17 is a perspective view for explaining the manufacturing process of the mother laminate, FIG. 18 is a perspective view showing the mother laminate, FIG. 19 is a perspective view showing the mother laminate on which the main surface electrode part precursor is formed, FIG. 20 is a perspective view showing the laminate precursor obtained by cutting the mother laminate of FIG. 19, and FIG. 21 is a perspective view showing the laminate obtained by firing and polishing the laminate precursor of FIG. 20. FIG. 22 is a perspective view for explaining the manufacturing process of the mother laminate, FIG. 23 is a perspective view showing the mother laminate, FIG. 24 is a perspective view showing the laminate precursor obtained by cutting the mother laminate of FIG. 23, and FIG. 25 is a perspective view showing the laminate obtained by firing and polishing the laminate precursor of FIG. 24. In FIGS. 17 to 25, for ease of illustration, hatching is applied to the internal electrode pattern, dummy electrode pattern, precursor of the conductor layer, etc.

[0063] An example of a method for manufacturing the multilayer ceramic capacitor 1A (hereinafter also referred to as the first manufacturing method) will be described. The first manufacturing method is a method for manufacturing the capacitor 1A having the main surface electrode portion 30 shown in FIG. 8. The first manufacturing method includes a step of producing a mother laminate, a step of producing an unfired laminate, a step of firing the unfired laminate, a step of polishing the laminate, and a step of forming an external electrode.

[0064] First, a raw material powder mainly composed of BaTiO3 is prepared, and an organic vehicle is mixed with the prepared raw material powder to prepare a ceramic slurry. The organic vehicle used for preparing the ceramic slurry may be, for example, a resin such as a butyral resin dissolved in a solvent obtained by mixing ethyl alcohol and toluene.

[0065] Subsequently, using the prepared ceramic slurry, a ceramic green sheet 16 that becomes the dielectric layer 7 is formed on the carrier film by a sheet forming method such as a die coater method, a doctor blade method, or a gravure coater method. The thinner the thickness of the ceramic green sheet 16, the larger the capacitance of the multilayer ceramic capacitor can be.

[0066] Subsequently, an organic vehicle is mixed with a powder mainly composed of a metal such as Ni, Cu, Sn, Pt, Pd, Ag, Au or an alloy thereof to prepare a conductive paste. The organic vehicle used for preparing the conductive paste may be, for example, a resin such as ethyl cellulose dissolved in a solvent obtained by mixing a dihydroterpineol-based solvent and butyl cellosolve. A dispersant such as oleic acid or polyethylene glycol may be added to the conductive paste.

[0067] Subsequently, using the prepared conductive paste, an internal electrode pattern that will become the internal electrode 6 is printed on the main surface of the ceramic green sheet 16 to produce an internal electrode sheet 17. Also, using the prepared conductive paste, a dummy electrode pattern that will become the dummy electrode 5a is printed on the main surface of the ceramic green sheet 16 to produce a dummy electrode sheet 18. The internal electrode pattern and the dummy electrode pattern can be printed by a printing method such as a screen printing method or a gravure printing method, for example.

[0068] Subsequently, as shown in FIG. 17, a predetermined number of dummy electrode sheets 18 are stacked, and on top of that, a predetermined number of internal electrode sheets 17 and a predetermined number of dummy electrode sheets 18 are stacked to produce a provisional laminate. The predetermined number of internal electrode sheets 17 may be stacked while being shifted by a predetermined distance. The predetermined distance may be, for example, half of the period of the internal electrode pattern. In the production of the provisional laminate, as shown in FIG. 17, at least one ceramic green sheet 16 may be disposed between the predetermined number of stacked dummy electrode sheets 18 and the predetermined number of stacked internal electrode sheets 17. Although omitted in FIG. 17, the production of the provisional laminate may be carried out on a support sheet. The support sheet may be an adhesive release sheet such as a weakly adhesive sheet or a foamed release sheet, for example.

[0069] Next, the provisional laminate is pressed in the stacking direction to obtain a mother laminate 19 as shown in FIG. 18. The pressing of the provisional laminate can be carried out using, for example, a hydrostatic pressure pressing device. The dummy electrode patterns exposed on the upper and lower surfaces of the mother laminate 19 are precursors of the conductor layer 30a (see FIG. 8) of the first part 31.

[0070] Next, as shown in FIG. 19, a precursor of the conductor layer 30b (see FIG. 8) of the first part 31 is formed on the dummy electrode patterns exposed on the upper and lower surfaces of the mother laminate 19. The precursor of the conductor layer 30b may be formed by an inkjet method or a screen printing method. The dummy electrode patterns exposed on the upper and lower surfaces of the mother laminate 19 and the precursor of the conductor layer 30b are also referred to as main surface electrode part precursors.

[0071] Next, the mother laminate 19 is cut along the lattice-shaped planned cutting line CL (see FIG. 19), and a plurality of unfired laminates 2 (hereinafter, also simply referred to as unfired laminates 2 or laminate precursors) in which the main surface electrode part precursors are located on the first surface 8a and the second surface 8b as shown in FIG. 20 are produced. The cutting of the mother laminate 19 may be performed with the mother laminate 19 placed on the support sheet. The cutting of the mother laminate 19 can be performed using, for example, a guillotine cutter, a dicing saw device, or the like.

[0072] Next, the unfired laminate 2 is fired. The firing temperature may be appropriately set, but may be, for example, about 1100 to 1250°C. Note that a debinding process may be performed on the unfired laminate 2. The debinding process may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The debinding process may be performed under atmospheric pressure or under reduced pressure. Further, a reoxidation process may be performed on the fired laminate 2 in an oxidizing atmosphere.

[0073] Next, the fired laminate 2 is put into a rotating pot containing an abrasive, and the laminate 2 is barrel-polished. Thereby, burrs on the surface of the laminate 2 are removed, the corners are rounded, and the internal electrodes 6 and the dummy electrodes 5a are sufficiently exposed at the corners 2a, 2b, 2c, 2d. FIG. 21 shows the laminate 2 after polishing. By sufficiently exposing the internal electrodes 6 at the corners 2a, 2b, 2c, 2d, it becomes possible to satisfactorily join the internal electrodes 6 and the external electrodes 3. Further, by sufficiently exposing the dummy electrodes 5a at the corners 2a, 2b, 2c, 2d, it becomes possible to increase the bonding force between the laminate 2 and the external electrodes 3. As a result, it becomes possible to improve the electrical characteristics and reliability of the capacitor 1A.

[0074] Next, a conductor layer 30c is formed on the polished laminate 2 by a plating method such as electroless plating or electrolytic plating so as to cover the conductor layers 30a, 30b, thereby forming the external electrodes 3 (the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d). Thereby, the laminated ceramic capacitor 1A having the main surface electrode part 30 shown in FIG. 8 can be manufactured.

[0075] Next, another example of the manufacturing method of the multilayer ceramic capacitor 1A (hereinafter also referred to as the second manufacturing method) will be described. The second manufacturing method is a method for manufacturing the capacitor 1A having the main surface electrode portion 30 shown in FIG. 9. The second manufacturing method includes a step of producing a mother laminate, a step of producing an unfired laminate, a step of firing the unfired laminate, a step of polishing the laminate, and a step of forming an external electrode. For the steps similar to the first manufacturing method, detailed descriptions will be omitted.

[0076] First, in the same manner as the first manufacturing method, the ceramic green sheet 16, the internal electrode sheet 17, and the dummy electrode sheet 18 are produced.

[0077] Next, as shown in FIG. 22, the conductor layer pattern 24 and the dielectric layer pattern 23 are laminated, and on top of that, a predetermined number of dummy electrode sheets 18, a predetermined number of internal electrode sheets 17, and a predetermined number of dummy electrode sheets 18 are laminated, and on top of that, the dielectric layer pattern 23 and the conductor layer pattern 24 are laminated to produce a temporary laminate. The dielectric layer pattern 23 is a precursor of the dielectric layer 30d of the main surface electrode portion 30 shown in FIG. 9. The conductor layer pattern 24 is a precursor of the conductor layer 30e of the main surface electrode portion 30 shown in FIG. 9. The predetermined number of internal electrode sheets 17 may be laminated while being shifted by a predetermined distance. The predetermined distance may be, for example, half of the period of the internal electrode pattern. In the production of the temporary laminate, as shown in FIG. 22, at least one ceramic green sheet 16 may be disposed between the predetermined number of laminated dummy electrode sheets 18 and the predetermined number of laminated internal electrode sheets 17. Although omitted in FIG. 22, the production of the temporary laminate may be performed on a support sheet. The support sheet may be, for example, an adhesive release sheet such as a weakly adhesive sheet or a foamed release sheet.

[0078] As shown in FIG. 22, the dielectric layer pattern 23 is a lattice pattern and includes a first strip portion 23a extending in a predetermined direction and a second strip portion 23b extending in a direction intersecting the predetermined direction. The center (also referred to as a lattice point) 23c in a plan view of a portion (also referred to as an intersection portion) where the first strip portion 23a and the second strip portion 23b intersect may constitute the central portion C (see FIG. 13) of the laminate 2. The conductor layer pattern 24 fills the openings of the dielectric layer pattern 23 and overlaps the intersection portions of the dielectric layer pattern 23. In the temporary laminate, a portion (also referred to as an overlapping portion) where the dielectric layer pattern 23 and the conductor layer pattern 24 overlap may constitute a part of the first portion 31 of the main surface electrode portion 30. The overlapping portion is a precursor of the dielectric layer 30d and the conductor layer 30e of the main surface electrode portion 30 shown in FIGS. 9 and 10, and is also referred to as a main surface electrode portion precursor. FIG. 22 shows an example in which the planar shape of the overlapping portion is a right triangle, but the present invention is not limited thereto. The planar shape of the overlapping portion may be, for example, a fan shape (quarter circle), a circular shape, a rectangular shape, or the like. By changing the planar shape of the overlapping portion, the planar shape of the first portion 31 can be adjusted. Further, by changing the thickness of the dielectric layer pattern 23, the height H (see FIG. 14) of the first portion 31 can be adjusted.

[0079] Next, the temporary laminate is pressed in the stacking direction to obtain a mother laminate 19 as shown in FIG. 23. The pressing of the temporary laminate can be performed using, for example, a hydrostatic press device.

[0080] Next, the mother laminate 19 is cut along the lattice-shaped planned cutting line CL (see FIG. 23) to produce a plurality of unfired laminates 2 (hereinafter, also simply referred to as unfired laminates 2 or laminate precursors) in which the main surface electrode portion precursors are located on the first surface 8a and the second surface 8b as shown in FIG. 24.

[0081] Next, the unfired laminate 2 is fired. The firing temperature may be set as appropriate, for example, about 1100 to 1250°C. Debinding treatment may be performed on the unfired laminate 2. The debinding treatment may be performed in an air atmosphere, an inert gas atmosphere, or a reducing atmosphere. The debinding treatment may be performed under atmospheric pressure or under reduced pressure. Reoxidation treatment may be performed on the fired laminate 2 in an oxidizing atmosphere.

[0082] Next, the fired laminate 2 is put into a rotating pot containing an abrasive, and the laminate 2 is barrel-polished to remove burrs on the surface of the laminate 2, round the corners, and sufficiently expose the internal electrodes 6 and the dummy electrodes 5a at the corners 2a, 2b, 2c, and 2d. FIG. 25 shows the laminate 2 after polishing. The polished laminate 2 has the dielectric layer 30d and the conductor layer 30e of the main surface electrode portion 30 shown in FIG. 9.

[0083] Next, a conductor layer 30f is formed on the polished laminate 2 by a plating method such as electroless plating or electrolytic plating so as to cover a part of the dielectric layer 30d and the conductor layer 30e, thereby forming the external electrodes 3 (the first external electrode 3a, the second external electrode 3b, the third external electrode 3c, and the fourth external electrode 3d). Thereby, the capacitor 1A having the main surface electrode portion 30 shown in FIG. 9 can be manufactured.

[0084] When producing a temporary laminate (see FIG. 22), by alternately laminating a plurality of dielectric layer patterns 23 and a plurality of conductor layer patterns 24 on the top and bottom of the temporary laminate, it becomes possible to manufacture the multilayer ceramic capacitor 1A having the main surface electrode portion 30 shown in FIG. 10. Further, when producing a temporary laminate (see FIG. 22), by reversing the lamination order of the dielectric layer pattern 23 and the conductor layer pattern 24, it becomes possible to manufacture the multilayer ceramic capacitor 1A having the main surface electrode portion 30 shown in FIG. 11.

[0085] As described above, the embodiments of the present disclosure have been described in detail, but the present disclosure is not limited to the above embodiments, and various changes, improvements, etc. are possible without departing from the gist of the present disclosure.

[0086] This disclosure can be implemented with the following configurations (A) to (F).

[0087] (A) A substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, having a first surface and a second surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the lamination direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the lamination direction and the length direction, and a plurality of external electrodes, including the plurality of internal electrodes having a plurality of first internal electrodes and a plurality of second internal electrodes, the plurality of first internal electrodes being exposed on the first side surface, the plurality of second internal electrodes being exposed on the second side surface, the plurality of external electrodes having a first external electrode and a second external electrode, the first external electrode being located from the first side surface over at least the first surface and being connected to the plurality of first internal electrodes, the second external electrode being located from the second side surface over at least the first surface and being connected to the plurality of second internal electrodes, each of the first external electrode and the second external electrode having a main surface electrode portion located at least on the first surface and having a first portion and a second portion, the first portion being thicker in thickness in the lamination direction than the second portion and being located closer to the center portion of the laminate in the main surface electrode portion when viewed in the lamination direction, a multilayer ceramic capacitor.

[0088] (B) A substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, having a first surface and a second surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the lamination direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the lamination direction and the length direction, and a plurality of external electrodes, including a plurality of external electrodes The plurality of internal electrodes have a plurality of first internal electrodes and a plurality of second internal electrodes. The plurality of first internal electrodes are exposed at corners extending from the first side surface to the third side surface and corners extending from the second side surface to the fourth side surface. The plurality of second internal electrodes are exposed at corners extending from the first side surface to the fourth side surface and corners extending from the second side surface to the third side surface. The plurality of external electrodes include a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode. The first external electrode is located at least over the first surface from the corner extending from the first side surface to the third side surface and is connected to the plurality of first internal electrodes. The second external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface and is connected to the plurality of first internal electrodes. The third external electrode is located at least over the first surface from the corner extending from the first side surface to the fourth side surface and is connected to the plurality of second internal electrodes. The fourth external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface and is connected to the plurality of second internal electrodes. Each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode has a main surface electrode portion located at least on the first surface, and the main surface electrode portion has a first portion and a second portion. The first portion is thicker in the stacking direction than the second portion and is located closer to the center portion of the laminate in the main surface electrode portion when viewed in the stacking direction. A multilayer ceramic capacitor.

[0089] (C) The multilayer ceramic capacitor according to (A) or (B) above, which satisfies the following formula (1) when the total thickness of the laminate in the stacking direction is Ttot, the thickness of the center portion of the laminate is Tc, and the height of the first portion with respect to the second portion is H. Ttot - Tc < H …(1)

[0090] (D) The laminated ceramic capacitor according to (C) above, wherein the H is less than 10 μm.

[0091] (E) The laminated ceramic capacitor according to any one of (A) to (D) above, wherein the first part of the main surface electrode portion is formed by laminating at least one dielectric layer and at least one conductor layer in the lamination direction.

[0092] (F) The laminated ceramic capacitor according to (E) above, wherein the at least one dielectric layer and the at least one conductor layer are alternately laminated in this order on the first surface.

[0093] (G) A laminated ceramic capacitor according to any one of (A) to (F) above, and a substrate having a mounting surface, and the laminated ceramic capacitor is mounted on the substrate such that the first surface of the laminate faces the mounting surface, a mounting structure.

Explanation of reference numerals

[0094] 1, 1A Laminated ceramic capacitor 2 Laminate 2a, 2b, 2c, 2d Corners 3 External electrode 3a First external electrode 3b Second external electrode 3c Third external electrode 3d Fourth external electrode 30 Main surface electrode portion 30a, 30b, 30c, 30e, 30f, 30h, 30i, 30j Conductor layer 30d, 30g Dielectric layer 31 First part 32 Second part 4 Capacitance forming portion 5 Cover portion 5a Dummy electrode 6 Internal electrode 6a First internal electrode 6b Second internal electrode 7 Dielectric layer 8a First surface 8b Second surface 9a First side surface 9b Second side surface 9c Third side surface 9d Fourth side surface 10 Substrate 10a Mounting surface 10b, 10c, 10d Points 11 First mounting electrode 12 Second mounting electrode 13 Third mounting electrode 14 Fourth mounting electrode 15 Suction nozzle 16 Ceramic green sheet 17 Internal electrode sheet 18Dummy electrode sheet 19 Mother laminate 20, 20A Mounting structure 23 Dielectric layer pattern 23a First strip 23b Second strip 23c Center 24 Conductor layer pattern C Central part

Claims

1. A substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, the laminate having a first surface and a second surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the lamination direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the lamination direction and the length direction, and a plurality of external electrodes, wherein the plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes, wherein the plurality of first internal electrodes are exposed on the first side surface, wherein the plurality of second internal electrodes are exposed on the second side surface, wherein the plurality of external electrodes include a first external electrode and a second external electrode, wherein the first external electrode is located from the first side surface at least over the first surface and is connected to the plurality of first internal electrodes, wherein the second external electrode is located from the second side surface at least over the first surface and is connected to the plurality of second internal electrodes, wherein each of the first external electrode and the second external electrode has a main surface electrode portion located at least on the first surface, the main surface electrode portion having a first portion and a second portion, wherein the first portion is thicker in the thickness direction in the lamination direction than the second portion and is located closer to the center portion of the laminate in the main surface electrode portion when viewed in the lamination direction, a multilayer ceramic capacitor.

2. A substantially rectangular parallelepiped laminate in which a plurality of internal electrodes and a plurality of dielectric layers are alternately laminated, the laminate having a first surface and a second surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the length direction orthogonal to the lamination direction, and a third side surface and a fourth side surface facing each other in the width direction orthogonal to the lamination direction and the length direction, and a plurality of external electrodes, wherein the plurality of internal electrodes include a plurality of first internal electrodes and a plurality of second internal electrodes, wherein the plurality of first internal electrodes are exposed at corners extending from the first side surface to the third side surface and at corners extending from the second side surface to the fourth side surface, wherein the plurality of second internal electrodes are exposed at corners extending from the first side surface to the fourth side surface and at corners extending from the second side surface to the third side surface, wherein the plurality of external electrodes include a first external electrode, a second external electrode, a third external electrode, and a fourth external electrode, The first external electrode is located at least over the first surface from the corner extending from the first side surface to the third side surface, and is connected to the plurality of first internal electrodes. The second external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface, and is connected to the plurality of first internal electrodes. The third external electrode is located at least over the first surface from the corner extending from the first side surface to the fourth side surface, and is connected to the plurality of second internal electrodes. The fourth external electrode is located at least over the first surface from the corner extending from the second side surface to the fourth side surface, and is connected to the plurality of second internal electrodes. Each of the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode has a main surface electrode portion located at least on the first surface, and the main surface electrode portion has a first portion and a second portion. The first portion is thicker in the stacking direction than the second portion, and is located closer to the center portion of the stacked body in the main surface electrode portion when viewed in the stacking direction, a multilayer ceramic capacitor.

3. When the total thickness of the stacked body in the stacking direction is Ttot, the thickness of the center portion of the stacked body is Tc, and the height of the first portion with respect to the second portion is H, the multilayer ceramic capacitor according to claim 1 or 2, which satisfies the following formula (1). Ttot - Tc < H …(1)

4. The multilayer ceramic capacitor according to claim 3, wherein the H is less than 10 μm.

5. The first portion of the main surface electrode portion is formed by laminating at least one dielectric layer and at least one conductor layer in the stacking direction, the multilayer ceramic capacitor according to claim 1 or 2.

6. The multilayer ceramic capacitor according to claim 5, wherein the at least one dielectric layer and the at least one conductor layer are alternately laminated in this order on the first surface.

7. A mounting structure including the multilayer ceramic capacitor according to claim 1 or 2, and a substrate having a mounting surface, wherein the multilayer ceramic capacitor is mounted on the substrate such that the first surface of the stacked body faces the mounting surface.

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