Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor in which dielectric breakdown near the side surfaces of a laminate is suppressed ands high-temperature load reliability is improved.　A multilayer ceramic capacitor 10 according to the present invention comprises: a laminate 12 including a plurality of laminated dielectric layers 14 and having a first side surface 12c and a second side surface 12d; a first internal electrode layer 16a; and a second internal electrode layer 16b. The plurality of dielectric layers 14 have a plurality of dielectric particles containing Ba and Ti, and the dielectric particles have a core-shell structure comprising a core portion and a shell portion surrounding the core portion, wherein the cross-sectional area of the core portion of the dielectric particles when viewed in the length direction of the laminate 12 decreases toward each of the first side surface 12c and the second side surface 12d along the width direction of the laminate 12, and the cross-sectional area of the shell portion of the dielectric particles when viewed in the length direction of the laminate 12 increases toward each of the first side surface 12c and the second side surface 12d along the width direction of the dielectric.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known for some time. Generally, multilayer ceramic capacitors include a laminate of sintered ceramic bodies made of dielectric ceramics (dielectric materials) such as barium titanate (BaTiO). The laminate includes an effective layer portion formed by stacking multiple internal electrodes with ceramic layers (dielectric layers) interposed therebetween. External electrodes are formed on both end surfaces of the laminate so as to be electrically connected to the internal electrodes (see, for example, Patent Document 1).

[0003] The multilayer ceramic capacitor described in Patent Document 1 has internal electrodes made of a metal material, and external electrodes made of a glass component and multiple metal components, including the same metal as the internal electrodes or a metal that can be alloyed with the internal electrodes. The external electrodes are bonded to a wiring board via a conductive resin adhesive, and the area content of the metal components relative to the cross-sectional area of ​​the external electrodes is 60 to 95%, thereby providing a multilayer ceramic capacitor that can be mounted on a wiring board inexpensively and with high reliability without using solder.

[0004] Japanese Patent Application Laid-Open No. 2001-237137

[0005] In a typical multilayer ceramic capacitor such as that disclosed in Patent Document 1, the thickness of the dielectric layer at the edge of the effective layer is generally thinner than that at the center of the effective layer due to pressure applied during the lamination press process, etc. This often leads to dielectric breakdown at the widthwise edge where the dielectric layer is thinner, resulting in a problem of reduced high-temperature load reliability.

[0006] The reason why dielectric breakdown occurs at the widthwise ends where the thickness of the dielectric layer is thinner due to the compression bonding in the lamination press process is that the thickness of the dielectric layer has been reduced in response to the recent demand for smaller multilayer ceramic capacitors, which reduces the number of ceramic particles in the lamination direction in the dielectric layer, thereby reducing the voltage resistance.

[0007] Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can suppress dielectric breakdown at the widthwise ends of the laminate and improve high-temperature load reliability.

[0008] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers, the laminate having first and second main surfaces opposing each other in the lamination direction of the plurality of dielectric layers, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; first internal electrode layers arranged on the plurality of dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the plurality of dielectric layers and exposed at the second end surfaces; a first external electrode arranged on the first end surfaces; and a second external electrode arranged on the second end surfaces. and a second external electrode including a first dielectric layer and a second external electrode including a second dielectric layer and a second external electrode, wherein the plurality of dielectric layers have a plurality of dielectric particles containing Ba and Ti, the dielectric particles have a core-shell structure consisting of a core portion and a shell portion surrounding the core portion, and the cross-sectional area of ​​the core portion of the dielectric particle, as viewed in the length direction of the laminate, becomes smaller along the width direction of the laminate toward each of the first side surface and the second side surface of the laminate, and the cross-sectional area of ​​the shell portion of the dielectric particle, as viewed in the length direction of the laminate, becomes larger along the width direction of the laminate toward each of the first side surface and the second side surface of the laminate.

[0009] In the multilayer ceramic capacitor according to the present invention, the dielectric layers each have a plurality of dielectric particles containing Ba and Ti, the dielectric particles each having a core-shell structure consisting of a core portion and a shell portion surrounding the core portion, the cross-sectional area of ​​the core portion of the dielectric particle as viewed in the longitudinal direction of the laminate decreases toward each of the first and second side surfaces of the laminate along the width direction of the laminate, and the cross-sectional area of ​​the shell portion of the dielectric particle as viewed in the longitudinal direction of the laminate increases toward each of the first and second side surfaces of the laminate along the width direction of the laminate, thereby mitigating electric field concentration at grain boundaries between ceramic particles and thereby reducing the risk of dielectric breakdown, thereby enabling improved high-temperature load reliability.

[0010] According to the present invention, in a multilayer ceramic capacitor, it is possible to suppress dielectric breakdown near the side surfaces of the laminate and improve high-temperature load reliability.

[0011] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0012] 1 is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1; FIG. 5 is a schematic cross-sectional view taken along line V-V in FIG. 1; and FIG. 6 is a schematic cross-sectional view taken along line VI-VI in FIG. 4. (a) is a cross-sectional view taken along line IV-IV in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into two; (b) is a cross-sectional view taken along line IV-IV in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into three; and (c) is a cross-sectional view taken along line IV-IV in FIG. 1 showing a structure in which opposing electrode portions of internal electrode layers of a multilayer ceramic capacitor according to an embodiment of the present invention are divided into four. 1A is a diagram showing an example of the concept of the core-shell structure of dielectric particles in the dielectric layers of the multilayer ceramic capacitor according to an embodiment of the present invention, and FIG. 1B is a diagram showing another example of the concept of the core-shell structure of dielectric particles in the dielectric layers of the multilayer ceramic capacitor according to an embodiment of the present invention. It is a diagram showing a schematic view of the vicinity of the boundary between the central region and the end region of the dielectric layer in an inner layer portion of the multilayer ceramic capacitor according to an embodiment of the present invention. It is also a diagram showing a process for manufacturing the multilayer ceramic capacitor according to an embodiment of the present invention, and FIG. 1B is a diagram showing a further process for manufacturing the multilayer ceramic capacitor according to an embodiment of the present invention.

[0013] An example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0014] 1. Multilayer Ceramic Capacitor Fig. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 5 is a cross-sectional view taken along line VV in Fig. 1. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4.

[0015] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 30. The laminate 12 is formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 16, and is composed of an inner layer portion 15a that exhibits capacitance, and first and second outer layer portions 15b1 and 15b2 that are arranged to sandwich the inner layer portion 15a from the upper and lower main surfaces, as will be described later.

[0016] Hereinafter, the configuration of each of the laminate 12, the internal electrode layer 16, and the external electrode 30 will be described in that order.

[0017] (Laminate) The laminate 12 includes a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16. The laminate 12 further includes a first main surface 12a and a second main surface 12b that face in a height direction x, which is the stacking direction of the plurality of dielectric layers 14; a first side surface 12c and a second side surface 12d that face in a width direction y that is perpendicular to the height direction x; and a first end surface 12e and a second end surface 12f that face in a length direction z that is perpendicular to the height direction x and the width direction y. The length direction z is also defined as the L direction, which is the direction connecting the first end surface 12e and the second end surface 12f. The width direction y is also defined as the W direction, which is the direction connecting the first side surface 12c and the second side surface 12d. The height direction x is also defined as the T direction, which is the direction connecting the first main surface 12a and the second main surface 12b.

[0018] The laminate 12 has a rectangular parallelepiped shape. The "rectangular parallelepiped shape" includes a rectangular parallelepiped with rounded corners and ridges. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. In other words, a "rectangular parallelepiped" member refers to any member having a first main surface 12a and a second main surface 12b, a first side surface 12c and a second side surface 12d, and a first end surface 12e and a second end surface 12f.

[0019] The first and second main surfaces 12a and 12b, the first and second side surfaces 12c and 12d, and the first and second end surfaces 12e and 12f may have irregularities or the like formed on some or all of them.

[0020] As shown in Figures 4 and 5, the laminate 12 has, in the height direction x connecting the first main surface 12a and the second main surface 12b, an inner layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 located closest to the first main surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 located closest to the second main surface 12b.

[0021] The first outer layer portion 15b1 is located on the first main surface 12a side of the laminate 12 and is an aggregate of multiple dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0022] The second outer layer portion 15b2 is located on the second main surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0023] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0024] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 10 to 2000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably, for example, about 0.5 μm to 10 μm.

[0025] The dielectric layer 14 is primarily made of a dielectric material having a perovskite structure represented by the general formula ABO3. Here, A always contains Ba and may further contain at least one of Ca and Sr. B always contains Ti and may further contain at least one of Zr and Hf. Depending on the desired properties of the laminate, the dielectric layer 14 may contain additional components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds.

[0026] More specifically, the dielectric layer 14 includes a plurality of dielectric particles containing Ba and Ti as the main components of the dielectric material. The dielectric particles have a core-shell structure consisting of a core and a shell surrounding the core. The core, located in the center of the dielectric particle, contains a low concentration of the secondary component of the dielectric material in solid solution, or the secondary component is not dissolved in solid solution. The shell, located on the surface layer of the dielectric particle and surrounding the core, contains a high concentration of at least a portion of the secondary component of the dielectric material in solid solution.

[0027] 8(a) and 8(b) are cross-sectional views showing the concept of the core-shell structure of the dielectric particles in the dielectric layer 14 of this embodiment. As shown in Fig. 8(a), the dielectric particle 140 has a core-shell structure consisting of a core portion 141 and a shell portion 142 surrounding the core portion 141.

[0028] In the dielectric particle 140 of this embodiment, the WT cross section of the core portion 141, i.e., the cross-sectional area when viewed in the longitudinal direction z of the laminate 12, becomes smaller along the width direction y toward each of the first side surface 12c and the second side surface 12d, and the cross-sectional area of ​​the WT cross section of the shell portion 142 becomes larger along the width direction y toward each of the first side surface 12c and the second side surface 12d.

[0029] 5 will be used as an example. In the inner layer portion 15a, the cross-sectional area in the WT cross section of the core-shell structure of the dielectric particles located near each of the first side surface 12c and the second side surface 12d is smaller than the cross-sectional area of ​​the dielectric particles located in the center in the width direction y, such that the core portion 141 is smaller and the shell portion 142 is larger. Here, in each of the plurality of dielectric layers 14 in the inner layer portion 15a, the region located in the center in the width direction y of the laminate 12 is referred to as the central region, and the regions located at the ends of the laminate 12 in the width direction y, i.e., the regions close to each of the first side surface 12c and the second side surface 12d along the width direction y, are referred to as the end regions.

[0030] 8(a) shows the core-shell structure of the dielectric particle 140 in the central region of the dielectric layer 14, and Fig. 8(b) shows the core-shell structure of the dielectric particle 140 in the edge region of the dielectric layer 14. As shown in each figure, the cross-sectional area of ​​the core portion 141 is smaller in the edge region than in the central region, and the cross-sectional area of ​​the shell portion 142 is larger in the edge region than in the central region.

[0031] The increase in the cross-sectional area of ​​the shell portion 142 of the dielectric particle 140 located in the edge region of the dielectric layer 14 shown in Figure 8(b) is due to the solid solution of the minor component in the dielectric particle 140. That is, the cross-sectional area of ​​the shell portion 142 increases as the solid solution of the minor component in the dielectric particle 140 located in the edge region progresses. This increase in the cross-sectional area of ​​the shell portion 142 alleviates electric field concentration at the grain boundaries between ceramics, thereby reducing the risk of dielectric breakdown. This can improve high-temperature load reliability.

[0032] In this embodiment, the dimension in the height direction x of the inner layer portion 15a in the central region located at the position of the plurality of dielectric layers 14 is preferably greater than the dimension in the height direction x of the end regions.

[0033] This makes it possible to improve the high temperature load reliability even if the thickness of the dielectric layer 14 is formed small in the end region of the inner layer portion 15a by a general manufacturing method for a multilayer ceramic capacitor.

[0034] Furthermore, in this embodiment, the shell portion 142 of the dielectric particle 140 contains a metal, and the metal contained in the shell portion 142 preferably contains at least Dy and also contains a transition metal. The metal contained in the shell portion 142 is added as a minor component to the dielectric material of the dielectric layer 14.

[0035] This can suppress the movement of oxygen vacancies that cause insulation deterioration, and further improve the high temperature load reliability.

[0036] Furthermore, in this embodiment, the concentration of Dy contained in the shell portion 142 is preferably 4 mol % or more and 8 mol % or less.

[0037] By adopting the above-mentioned configuration, the effect of improving the high-temperature load reliability can be more significantly obtained. Note that if the Dy concentration is less than 4 mol%, the effect of Dy in suppressing the migration of oxygen vacancies is weakened. On the other hand, if the Dy concentration is more than 8 mol%, segregation of Dy begins to occur, the resistance value increases, electric field concentration begins to occur, and the high-temperature load reliability decreases.

[0038] 9 is a diagram corresponding to the cross-sectional view of FIG. 5, which schematically illustrates the vicinity of the boundary between the central region 14C and the end region 14E of the dielectric layer 14 in the inner layer portion 15a of the laminate 12. However, FIG. 9 shows an enlarged view of the second side surface 12d of the laminate 12 as an example.

[0039] In the laminate 12, the first internal electrode layer 16a is formed as a plane extending in a direction approximately perpendicular to the height direction x in the central region 14C, while in the end region 14E, it forms a curved portion 21a whose shape changes, including changes in the height direction x, relative to the plane of the central region 14C.

[0040] Similarly, the second internal electrode layer 20b is formed as a plane extending in a direction approximately perpendicular to the height direction x in the central region 14C, while in the end region 14E, it forms a curved portion 21b with a change in shape including a change in the height direction x relative to the plane of the central region 14C.

[0041] Each of the bending portions 21a and 21b preferably has at least one of a bent portion in a bent state, a curved portion in a curved state, and a folded portion in a folded state as a manner of change in shape. In Fig. 9, as an example, the bending portion 21a is schematically shown as having a bent portion and a folded state, and the bending portion 21b is schematically shown as having a curved portion.

[0042] Furthermore, in this embodiment, it is preferable that a plurality of the curved portions 21a and 21b are arranged at the edge portions of each of the first internal electrode layer 16a and the second internal electrode layer 16b, as shown in FIG.

[0043] Here, the cross-sectional areas of the core portion 141 and the shell portion 142 of the dielectric particle 140 are measured as follows. First, the multilayer ceramic capacitor 10 is polished automatically or manually to a position corresponding to L / 2 along the longitudinal direction z, exposing the polished surface (WT cross section). Next, an observation location is removed from the polished surface using a focused ion beam (FIB) to a thickness of approximately 100 nm, forming a sample. Then, elemental mapping of the formed sample is performed using a scanning transmission electron microscope (STEM) / energy dispersive X-ray fluorescence spectroscopy (EDX), and the cross-sectional areas of the core portion 141 and the shell portion 142 are measured.

[0044] The average thickness of each of the multiple dielectric layers 14 in the laminate 12 is measured as follows. That is, first, a WT cross section exposed by polishing using the same method as used to measure the cross-sectional area of ​​each of the core portion 141 and shell portion 142 of the dielectric particle 140 is observed using an STEM. Next, the thickness is measured along a center line along the height direction x that passes through the center of the WT cross section of the laminate 12, and two lines drawn equally spaced on each side of this center line, for a total of five lines. The average value of these five measured values ​​is taken as the average thickness of the dielectric layer 14. Note that, to obtain a more accurate average thickness, the above five measured values ​​are obtained for each of the upper, central, and lower portions along the height direction x, and the average value of these measured values ​​is taken as the average thickness.

[0045] 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and second internal electrode layers 16b are alternately stacked at equal intervals along the height direction x, with the dielectric layers 14 interposed therebetween. The first internal electrode layers 16a and second internal electrode layers 16b are substantially parallel to the first main surface 12a and the second main surface 12b, respectively.

[0046] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a facing the second internal electrode layer 16b, and a first lead electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12. The end of the first lead electrode portion 20a is extended and exposed at the first end face 12e. The other end of the first internal electrode layer 16a is slightly recessed from the second end face 12f. The first lead electrode portion 20a is not exposed at the first principal surface 12a, the second principal surface 12b, or the first side face 12c, the second side face 12d.

[0047] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0048] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0049] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, and a second extraction electrode portion 20b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second end face 12f of the laminate 12. The end of the second extraction electrode portion 20b is extended and exposed at the second end face 12f. The other end of the second internal electrode layer 16b is slightly recessed from the first end face 12e. The second extraction electrode portion 20b is not exposed at the first principal surface 12a, the second principal surface 12b, or the first side face 12c, the second side face 12d.

[0050] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0051] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0052] The laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a of the laminate 12 formed between one ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the first side surface 12c, and between the other ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the width direction y and the second side surface 12d. Furthermore, the laminate 12 includes end portions (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between an end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the second end surface 12f, and between an end of the second internal electrode layer 16b opposite to the second extraction electrode portion 20b and the first end surface 12e.

[0053] The internal electrode layers 16 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. When the base electrode layer of the external electrode 30, which will be described later, is a conductive resin layer, the metal constituting the internal electrode layers 16 forms a compound with the metal constituting the conductive filler contained in the conductive resin layer.

[0054] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 10 to 2000. The thickness of the internal electrode layers 16 is preferably about 0.2 μm to 2.0 μm.

[0055] As shown in FIG. 7, the laminate 12 shown in FIG. 1 may include, in addition to the first internal electrode layer 16a and the second internal electrode layer 16b, a floating internal electrode layer 16c that is not extended to either the first end face 12e or the second end face 12f. The floating internal electrode layer 16c may divide the opposing electrode portion 26c into multiple portions. For example, the opposing electrode portion 26c may have a two-part structure as shown in FIG. 7(a), a three-part structure as shown in FIG. 7(b), a four-part structure as shown in FIG. 7(c), or a structure with more than four parts. By dividing the opposing electrode portion 26c into multiple portions, multiple capacitor components are formed between the opposing first internal electrode layer 16a, the second internal electrode layer 16b, and the floating internal electrode layer 16c, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby increasing the withstand voltage of the multilayer ceramic capacitor 10.

[0056] Furthermore, like the first internal electrode layer 16a and the second internal electrode layer 16b, the floating internal electrode layer 16c can be made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy.

[0057] (External Electrodes) As shown in FIGS. 1 to 3, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0058] The external electrode 30 preferably includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0059] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0060] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed on at least the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is disposed on part of the first main face 12a, part of the second main face 12b, and part of the first side face 12c, part of the second side face 12d. In this case, the first external electrode 30a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0061] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed on at least the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is disposed on part of the first main surface 12a, part of the second main surface 12b, and part of the first side surface 12c, and part of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0062] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0063] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0064] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0065] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is disposed on a part of the first main surface 12a, a part of the second main surface 12b, a part of the first side surface 12c, and a part of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0066] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0067] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0068] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrode layers 16 and dielectric layers 14 and the conductive paste applied to the laminated chip, but may also be baked after baking the laminated chip having internal electrode layers 16 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0069] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the first base electrode layer 32a located on the first end face 12e is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0070] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f at the center in the height direction x of the second base electrode layer 32b located on the second end face 12f is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0071] The thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0072] Furthermore, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first main surface 12a and the second main surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0073] The thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first base electrode layer 32a located on part of the first side surface 12c and the second side surface 12d is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0074] Furthermore, it is preferable that the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z connecting the first end face 12e and the second end face 12f of the second base electrode layer 32b located on part of the first side surface 12c and the second side surface 12d is, for example, approximately 10 μm or more and 100 μm or less.

[0075] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0076] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0077] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the first and second end faces 12e and 12f, and extend to the first and second main faces 12a and 12b and the first and second side faces 12c and 12d, respectively. However, the first and second conductive resin layers may be disposed only on the other layers, such as baked layers, located on the first and second end faces 12e and 12f.

[0078] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0079] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0080] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0081] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0082] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0083] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0084] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0085] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0086] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0087] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0088] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layer.

[0089] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0090] The first conductive resin layer and the second conductive resin layer may each include a resin layer containing conductive particles and a thermosetting resin.

[0091] The conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0092] (In the case of a thin film layer) When the base electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0093] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS.

[0094] The first plating layer 34a and the second plating layer 34b contain, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0095] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0096] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0097] The lower plating layer made of Ni plating is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount.

[0098] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0099] 1 , the length direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as L dimension, the height direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as T dimension, and the width direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as W dimension. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the length direction z L dimension is 0.2 mm to 10.0 mm, the width direction y W dimension is 0.1 mm to 10.0 mm, and the height direction x T dimension is 0.1 mm to 5.0 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0100] In the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 , the dielectric layer 14 includes a plurality of dielectric particles 140 containing Ba and Ti. The dielectric particles 140 have a core-shell structure including a core portion 141 and a shell portion 142 surrounding the core portion 141. The cross-sectional area of ​​the core portion 141 in the WT cross section, i.e., the cross-sectional area as viewed in the longitudinal direction z of the laminate 12, decreases along the width direction y toward the first end face 12 e and the second end face 12 f, respectively, and the cross-sectional area of ​​the shell portion 142 in the WT cross section increases along the width direction y toward the first end face 12 e and the second end face 12 f, respectively. This improves the high-temperature load reliability of the multilayer ceramic capacitor.

[0101] Furthermore, in each of the plurality of dielectric layers 14 of the inner layer portion 15a, the multilayer ceramic capacitor 10 has a central region that is a region at the center of the width direction y of the laminate 12 as a central region, and regions adjacent to the first side surface 12c and the second side surface 12d along the width direction y as edge regions, and the dimension of the central region in the height direction x is larger than the dimension of the edge regions in the height direction x. This allows for improved high-temperature load reliability even if the thickness of the dielectric layers 14 is formed to be small in the edge regions of the inner layer portion 15a using a typical manufacturing method for multilayer ceramic capacitors.

[0102] Furthermore, in the multilayer ceramic capacitor 10, the shell portion 142 of the dielectric particle 140 of the dielectric layer 14 contains a metal. The metal contained in this shell portion 142 preferably contains at least Dy and also contains a transition metal. This can further improve the high-temperature load reliability.

[0103] Furthermore, in the multilayer ceramic capacitor 10, the concentration of Dy contained in the shell portion 142 is preferably 4 mol % or more and 8 mol % or less, which can significantly improve the high temperature load reliability.

[0104] Furthermore, it is preferable that the first internal electrode layers 16a and the second internal electrode layers 16b have curved portions 21a and 21b in the end regions of the multilayer ceramic capacitor 10. This makes it possible to obtain a more significant effect of improving the high-temperature load reliability.

[0105] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor according to the above embodiment will now be described.

[0106] (1) Prepare a dielectric sheet and a conductive paste for the internal electrode layers. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (for example, a known organic binder) and a solvent (for example, a known organic binder).

[0107] (2) Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheets by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode pattern corresponding to the first internal electrode layer 16 a is formed and a dielectric sheet on which a second internal electrode pattern corresponding to the second internal electrode layer 16 b is formed. Note that, with regard to the dielectric sheets, dielectric sheets for outer layers on which no internal electrode pattern is printed are also prepared.

[0108] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked to form a portion that will become a second outer layer portion, and a dielectric sheet on which a first internal electrode pattern is formed and a dielectric sheet on which a second internal electrode pattern is formed are stacked in this order on top of that to form a portion that will become an inner layer portion.

[0109] (4) Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the internal electrode pattern corresponding to the internal electrode layer located on the outermost surface of the inner layer portion to form a portion that will become the first outer layer portion, thereby producing a laminated sheet.

[0110] (5) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0111] (6) The laminated block is cut to a predetermined size to cut out laminated chips (hereinafter referred to as "bases"). At this time, as shown in FIG. 10( a), the base 120 is shaped so that the pattern ends 161 of the internal electrode patterns 160 are exposed on each of the side surfaces 120c located on the first side surface 12c side and the side surface 120d located on the second side surface 12d side of the completed laminate 12. At this time, the corners and ridges of the base 120 may be rounded by barrel polishing or the like.

[0112] (7) Next, a ceramic paste containing crystal particles is applied to the side surfaces 120c and 120d of the base body 120 to form side margin portions 220 that are different from the base body 120 and serve as edge regions. This ceramic paste contains dielectric particles having a different composition from the dielectric sheet prepared in step (1), specifically, a dielectric material with a higher ratio of subcomponent to main component. This allows the cross-sectional areas of the core and shell of the dielectric particles to be different between the side margin portions 220 that are different from the base body 120 and the central portion of the base body 120.

[0113] (8) Next, the base body 120 after the side margin portion 220 is formed is pressure-bonded from a direction along the stacking direction of the laminated sheets. As a result, pressure is applied to the base body 120 itself in a direction perpendicular to the stacking direction, and as shown in Fig. 10(b), the pattern ends 161 of the internal electrode patterns 160 located on the side surfaces 120c and 120d of the base body 120 extend to the inside 221 of the side margin portion 220 formed in step (7), and curves, bends, folds, etc. are generated in the inside 221 of the side margin portion 220, forming curved portions.

[0114] (9) Next, the base electrode layer 32 is formed. The following explanation is for the case where the base electrode layer 32 is a baked layer. To form each of the first base electrode layer 32a and the second base electrode layer 32b, a conductive paste for the base electrode containing a glass component and a metal component is prepared.

[0115] (10) A conductive paste is applied to the first end face 12 e and the second end face 12 f of the laminate 12 by, for example, dipping or screen printing, and then baked to form the first base electrode layer 32 a and the second base electrode layer 32 b. The baking temperature is preferably 700° C. or higher and 900° C. or lower.

[0116] (11) When the base electrode layer is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0117] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the laminate, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in a N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable to keep the oxygen concentration below 100 ppm.

[0118] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0119] (12) If necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surfaces of the first and second base electrode layers. Specifically, a Ni plating layer is formed on the first and second base electrode layers, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0120] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 is manufactured.

[0121] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0122] In other words, various modifications can be made to the above-described embodiments and variants in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0123] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First main surface 12b Second main surface 12c First side surface 12d Second side surface 12e First end surface 12f Second end surface 14 Dielectric layer 14C Central region 14E End region 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 16c Floating internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 21a, 21b Curved portion 22a Side portion 22b End portion 26c Opposing electrode portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 120 Base body 120c, 120d Side surface 140 Dielectric particle 141 Core portion 142 Shell portion 160 Internal electrode pattern 161 Pattern end portion 220 Side margin portion 221 Inside

Claims

1. A laminated body including a plurality of laminated dielectric layers, having a first main surface and a second main surface facing each other in the lamination direction of the plurality of dielectric layers, a first side surface and a second side surface facing each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface facing each other in a length direction orthogonal to the lamination direction and the width direction; a first internal electrode layer disposed on the plurality of dielectric layers and exposed on the first end surface; a second internal electrode layer disposed on the plurality of dielectric layers and exposed on the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface. The plurality of dielectric layers have a plurality of dielectric particles containing Ba and Ti. The dielectric particles have a core-shell structure including a core portion and a shell portion surrounding the core portion. In a view in the length direction of the laminated body, the cross-sectional area of the core portion of the dielectric particles decreases as it goes toward each of the first side surface and the second side surface of the laminated body along the width direction of the laminated body, and in a view in the length direction of the laminated body, the cross-sectional area of the shell portion of the dielectric particles increases as it goes toward each of the first side surface and the second side surface of the laminated body along the width direction of the laminated body. A multilayer ceramic capacitor.

2. The plurality of dielectric layers have a central region disposed in a central region of the width direction of the laminated body and an end region disposed at an end of the width direction of the laminated body. The dimension in the lamination direction of the central region is larger than the dimension in the lamination direction of the end region. The multilayer ceramic capacitor according to claim 1.

3. The shell portion contains a metal. The metal contained in the shell portion contains at least Dy and contains a transition metal. The multilayer ceramic capacitor according to claim 1 or 2.

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