Three-dimensional (3D) memory device

Abstract

To disclose an embodiment and a manufacturing method of a through array contact structure of a 3D memory device.SOLUTION: A 3D NAND memory device includes a substrate including a peripheral circuit, and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack, a second region including an alternating conductor / dielectric stack, and a third region including staircase structures on edges of the alternating conductor / dielectric layer stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region or the third region, a plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with the peripheral circuit.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims priority to Chinese Patent Application No. 201710135654.9, filed on March 8, 2017, and Chinese Patent Application No. 201710135329.2, filed on March 8, 2017, which are hereby incorporated by reference in their entirety.

[0002] Embodiments of the present disclosure relate to three - dimensional (3D) memory devices and methods of manufacturing the same.

Background Art

[0003] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, due to the feature size of the memory cells approaching the lower limit, planar processes and manufacturing technologies have become difficult and costly. As a result, the memory density for planar memory cells is approaching the upper limit.

[0004] 3D memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals between the memory arrays.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of a through - array contact (TAC) structure of a 3D memory device and a method of manufacturing the same are disclosed herein.

[0006] A three-dimensional (3D) NAND memory device is disclosed that includes a substrate having at least one peripheral circuit and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack including a plurality of dielectric layer pairs, a second region including an alternating conductor / dielectric stack having a plurality of conductor / dielectric layer pairs, and a third region including a staircase structure on an edge of the alternating conductor / dielectric layer stack in the word line direction. The memory device further has a barrier structure that extends vertically through the alternating layer stack to laterally separate the first region from the second region or the third region. A plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through array contacts in the first region each extending vertically through the alternating dielectric stack are included. At least one of the plurality of through array contacts is electrically connected to at least one peripheral circuit.

[0007] The barrier structure may be silicon oxide and silicon nitride. Each of the plurality of dielectric layer pairs can include a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs includes a metal layer and a silicon oxide layer. The number of the plurality of dielectric layer pairs is at least 32. The number of the plurality of conductor / dielectric layer pairs is at least 32.

[0008] A plurality of slit structures extend laterally along the word line direction to divide the alternating conductor / dielectric stack into a plurality of memory fins.

[0009] In some embodiments, the barrier structure extends laterally along the word line direction. The first region is separated from the second region by the barrier structure and is sandwiched between two adjacent slit structures.

[0010] In some embodiments, the barrier structure extends laterally along a bit line direction different from the word line direction to laterally separate the first region from the second region. The bit line direction may be perpendicular to the word line direction.

[0011] The width of the first region surrounded by the barrier structure in the bit line direction may be wider than the distance between two adjacent slit structures. The first region surrounded by the barrier structure is sandwiched in the word line direction between two upper selectivity gate staircase regions. At least the upper two layers of the alternating conductor / dielectric stack in each upper selectivity gate staircase region have a staircase structure. At least one conductive layer is on the staircase structure in the upper selectivity gate staircase region and interconnects the upper selection gates on both sides of the first region surrounded by the barrier structure in the word line direction above the alternating conductor / dielectric stack in the second region. In some embodiments, at least two first regions are surrounded by corresponding barrier structures, and each first region extends parallel along the bit line direction.

[0012] In some embodiments, there are a plurality of barrier structures for surrounding a plurality of first regions from a second region, and the plurality of first regions are aligned in the bit line direction. Each of the plurality of first regions is sandwiched in the bit line direction between two adjacent slit structures. In some embodiments, the plurality of first regions are aligned in at least two columns in the bit line direction. At least one slit structure sandwiched between two adjacent barrier structures in the bit line direction includes a gap and is configured to interconnect the word lines of adjacent memory fins.

[0013] In some embodiments, the first region is separated from a third region by a barrier structure. The opening of the barrier structure is at the edge of the alternating layer stack in the word line direction. In some embodiments, the width of the first region in the bit line direction is wider than the distance between two adjacent slit structures. In some other embodiments, the width of the first region in the bit line direction is narrower than the maximum distance between two adjacent slit structures in the third region.

[0014] The memory device further includes a plurality of dummy channel structures adjacent to the barrier structure, and each dummy channel structure extends vertically through the alternating conductor / dielectric stack.

[0015] Disclosed is also a method for forming a three-dimensional (3D) NAND memory device. The method includes forming a substrate including at least one peripheral circuit, forming an alternating dielectric stack including a plurality of dielectric layer pairs on the substrate, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer, forming a staircase structure at an edge of the alternating dielectric stack, and forming a plurality of channel structures and at least one barrier structure each extending vertically through the alternating dielectric stack. At least one barrier structure separates the alternating dielectric stack into at least one first region and a second region laterally surrounded at least by the barrier structure. The method further includes forming a plurality of slits and replacing, through the slits, the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer to form an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs, depositing a conductive material into the slits to form a plurality of slit structures, and forming a plurality of through-array contacts in the first region, each through-array contact extending vertically through the alternating dielectric stack and electrically connecting at least one of the plurality of through-array contacts to at least one peripheral circuit.

[0016] The step of forming the substrate includes forming at least one peripheral circuit on a base substrate, forming at least one interconnect structure to electrically connect at least one of the plurality of through-array contacts to at least one peripheral circuit, and forming an epitaxial substrate over the at least one peripheral circuit.

[0017] In some embodiments, the method further includes forming a plurality of doped regions in the epitaxial substrate such that each slit structure contacts a corresponding doped region before the step of forming the slits.

[0018] In some embodiments, the method further includes forming at least one opening in an epitaxial substrate corresponding to at least one first region to expose an interconnect structure for electronically connecting to at least one peripheral circuit, and filling the at least one opening with a dielectric material.

[0019] In some embodiments, the method further includes forming at least one barrier structure using silicon oxide and silicon nitride, forming at least 32 pairs of dielectric layer pairs using a silicon oxide layer and a silicon nitride layer, and forming at least 32 pairs of conductor / dielectric layer pairs using a metal layer and a silicon oxide layer.

[0020] In some embodiments, the method further includes forming a plurality of slit structures extending laterally along the word line direction to divide an alternating conductor / dielectric stack into a plurality of memory fins.

[0021] In some embodiments, the method further includes forming two parallel barrier structures extending laterally along the word line direction such that a first region is separated from a second region by the two parallel barrier structures and is sandwiched between two adjacent slit structures.

[0022] In some embodiments, the method further includes forming a barrier structure extending laterally along a bit line direction different from the word line direction to laterally separate a first region from a second region. In some embodiments, the method further includes forming a barrier structure extending laterally along a bit line direction perpendicular to the word line direction.

[0023] In some embodiments, the method further includes forming the barrier structure such that a width of a first region surrounded by the barrier structure in the bit line direction is wider than a distance between two adjacent slit structures.

[0024] In some embodiments, the method further includes forming a second staircase structure in the alternating dielectric stack adjacent to the barrier structure, and forming at least one conductive layer on the staircase structure adjacent to the barrier structure to interconnect upper select gates on both sides of a first region surrounded by the barrier structure in the word line direction and above the alternating conductor / dielectric stack in the second region.

[0025] In some embodiments, the method further includes forming at least two barrier structures to surround at least two first regions extending parallel along the bit line direction.

[0026] In some embodiments, the method further includes forming a plurality of barrier structures to surround a plurality of first regions from a second region, and aligning the plurality of first regions in the bit line direction such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0027] In some embodiments, the method further includes forming a plurality of barrier structures such that a plurality of first regions surrounded by the plurality of barrier structures are aligned in at least two columns in the bit line direction.

[0028] In some embodiments, the method further includes forming a gap in at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction to interconnect word lines of adjacent memory fins.

[0029] In some embodiments, the method further includes forming a barrier structure to separate a first region in the staircase structure at an edge of the alternating stack, and an opening of the barrier structure is at an edge of the alternating layer stack in the word line direction.

[0030] In some embodiments, the method further includes forming a barrier structure such that the width of a first region in the bit line direction is wider than the distance between two adjacent slit structures. In some embodiments, the method further includes forming a barrier structure such that the width of a first region in the bit line direction is narrower than the maximum distance between two adjacent slit structures in a third region.

[0031] In some embodiments, the method further includes forming a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through an alternating conductor / dielectric stack.

[0032] Other aspects of the present disclosure will be understood by those of ordinary skill in the art in light of the description, claims, and drawings of the present disclosure.

[0033] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable one of ordinary skill in the art to make and use the present disclosure.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 4A

Figure 4B

Figure 5

Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0035] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0036] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be employed in various other applications.

[0037] References in this specification to "one embodiment", "an embodiment", "exemplary embodiments", "some embodiments", etc., should be noted to indicate that while the described embodiments may include certain features, structures, or characteristics, not all embodiments necessarily include the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described with respect to one embodiment, achieving such a feature, structure, or characteristic with respect to other embodiments, whether or not explicitly described, is within the knowledge of those skilled in the art.

[0038] Generally, terms can be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein can be used, at least in part depending on the context, to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a", "an", or "the" can also be understood, at least in part depending on the context, to convey a singular usage or a plural usage.

[0039] It should be readily understood that the meanings of "on", "above", and "over" in this disclosure should be construed in the broadest sense. Thus, "on" not only means "directly on" something, but also includes the meaning of "on" something with intervening features or layers therebetween. And "above" and "over" not only mean "above" or "over" something, but can also include the meaning of "above" or "over" (i.e., directly above) something without intervening features or layers therebetween.

[0040] Furthermore, terms related to space such as "beneath", "below", "lower than", "above", "upper", etc. may be used in this specification to facilitate the description of the relationship of one element or feature to another element or feature when illustrated in the figures. The terms related to space are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or other orientations), and the terms related to space used in this specification may be interpreted accordingly.

[0041] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Further, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0042] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer can extend over the entirety of a structure below or above it, and can have a range smaller than the range of the structure below or above it. Further, it can be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be disposed between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes of the top and bottom surfaces. A layer can extend along a horizontal, vertical, and / or tapered plane. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductors and contact layers (in which contacts, interconnect lines, and / or vias are formed), as well as one or more dielectric layers.

[0043] As used herein, the term "nominal / nominally" refers to a desired, or target, value of a characteristic or parameter for a component or process operation set during the design phase of a product or process, as well as the range of values above and / or below the desired value. The range of values can be due to slight variations or tolerances during the manufacturing process. As used herein, the term "about" indicates a value of a given quantity that can vary depending on the particular technology node associated with the semiconductor device of the subject matter. Based on the particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0044] As used herein, the term "3D memory device" refers to a semiconductor device having a column of vertically oriented memory cell transistors (i.e., a region in this specification as a "memory column" such as a NAND column) on a laterally oriented substrate such that the memory columns extend in a direction perpendicular to the substrate. As used herein, the term "vertical / perpendicular" means nominally perpendicular to the lateral plane of the substrate.

[0045] Various embodiments in accordance with the present disclosure provide a 3D memory device having a through-array contact (TAC) structure for a memory array (also referred to herein as an "array device"). The TAC structure is fabricated in a limited number of steps (e.g., in a single step or two steps), thereby reducing the complexity of the process and the manufacturing cost, and enabling contact between the memory and various peripheral circuits and / or peripheral devices (e.g., page buffers, latches, decoders, etc.). The disclosed TAC is formed through a stack of alternating dielectric layers that can be etched more easily to form through-holes therein as compared to a stack of alternating conductor and dielectric layers.

[0046] The TAC realizes a vertical interconnection between the stacked array device and the peripheral device (e.g., for a power bus and metal wiring), thereby reducing the number of metal levels and shrinking the die size. In some embodiments, the TAC can interconnect with various lines in the upper conductor layer and / or the bottom conductor layer, which is suitable for a 3D memory architecture that forms or couples a peripheral device formed on a different substrate from the array device in turn or face-to-face by hybrid bonding. In some embodiments, the TAC in the through-array contact structure disclosed herein is formed through a stack of alternating dielectric layers that can be etched more easily to form through-holes therein as compared to a stack of alternating conductor and dielectric layers, thereby reducing the complexity of the process and the manufacturing cost.

[0047] FIG. 1 illustrates a schematic diagram of an exemplary 3D memory device 100 in a plan view, according to some embodiments of the present disclosure. The 3D memory device 100 can include a plurality of channel structure regions (e.g., memory planes, memory blocks, memory fingers, etc., which will be described in detail below with respect to various figures), while one or more TAC structures can be formed between two adjacent channel structure regions.

[0048] As shown in FIG. 1, the 3D memory device 100 can include four or more memory planes 110, each of which can include a plurality of memory blocks 115. It should be noted that the arrangement of the memory planes 110 in the 3D memory device 100 and the arrangement of the memory blocks 115 in each memory plane 110, as illustrated in FIG. 1, are used merely as examples and do not limit the scope of the present disclosure.

[0049] The TAC structure is sandwiched by two adjacent memory blocks 115 in the bit line direction (labeled "BL" in the figure) of the 3D memory device, and includes one or more bit line (BL) TAC regions 160 extending along the word line direction (labeled "WL" in the figure) of the 3D memory device; one or more word line (WL) TAC regions 160 sandwiched by two adjacent memory blocks 115 in the word line direction (WL) and extending along the bit line direction (BL); and one or more staircase structure (SS) TAC regions 180 disposed at the edges of each memory plane 110.

[0050] In some embodiments, the 3D memory device 100 can include a plurality of contact pads 120 linearly arranged at the edges of the 3D memory device 100. Interconnection contacts can be used to electrically interconnect the 3D memory device 100 to an interface that performs functions such as providing any suitable device and / or driving power, receiving control signals, and transmitting response signals.

[0051] FIG. 2 depicts an enlarged plan view of region 130 shown in FIG. 1, including an exemplary bit line (BL) TAC region 160 of a 3D memory device. FIGS. 3A-3D depict enlarged plan views of region 140 shown in FIG. 1, including various exemplary word line (WL) TAC regions 170 of a 3D memory device. FIGS. 4A and 4B depict enlarged plan views of region 150 shown in FIG. 1, including various exemplary staircase structure (SS) TAC regions 180 of a 3D memory device.

[0052] Referring to FIG. 2, an enlarged plan view of region 130 shown in FIG. 1, including an exemplary bit line (BL) TAC region of a 3D memory device, according to some embodiments of the present disclosure, is illustrated. A region 200 of a 3D memory device (i.e., region 130 as shown in FIG. 1) can include two channel structure regions 210 (e.g., memory blocks 115 adjacent in the BL direction) and a bit line (BL) TAC region 233 (e.g., BL TAC region 160 as shown in FIG. 1).

[0053] The channel structure regions 210 can include an array of channel structures 212, each of which is a portion of a NAND string including a plurality of stacked memory cells. The channel structures 212 extend through a plurality of pairs of conductor layers and dielectric layers arranged along a direction perpendicular to the surface of the substrate of the 3D memory device (illustrated in cross-section with respect to FIG. 5 described in detail below) and / or a direction perpendicular to the plane of the plan view, also referred to as the "vertical direction."

[0054] The plurality of conductor / dielectric layer pairs are also referred to herein as "alternating conductor / dielectric stacks." The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack (e.g., 32, 64, or 96) can set the number of memory cells in the 3D memory device 100. The conductor layers and dielectric layers in the alternating conductor / dielectric stack alternate in the vertical direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stack, each conductor layer can be in contact with two dielectric layers on both sides, and each dielectric layer can be in contact with two conductor layers on both sides.

[0055] The conductor layer can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicon compounds, or any combination thereof. The dielectric layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer includes a metal layer such as W, and the dielectric layer includes silicon oxide.

[0056] In some embodiments, the BL TAC region 233 may be sandwiched by two adjacent channel structure regions 210 in the BL direction and can extend in the WL direction. The TAC region 233 can be defined by the barrier structure 224 together with the edge of the BL TAC region 233 of the 3D memory device. A plurality of TACs 226 surrounded laterally by the barrier structure 224 and the edge of the BL TAC region 233 can be formed in the BL TAC region 233. In some embodiments, the plurality of TACs 226 in the BL TAC region 233 can penetrate the alternating dielectric stack for switch path designation and for reducing bit line capacitance.

[0057] The alternating dielectric stack can include a plurality of pairs of dielectric layers arranged along a vertical direction perpendicular to the surface of the substrate of the 3D memory device (illustrated in cross-section with respect to FIG. 5 described in detail below). Each pair of dielectric layers includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. In some embodiments, each of the first dielectric layer and the second dielectric layer includes silicon nitride and silicon oxide. The first dielectric layer in the alternating dielectric stack may be the same as the dielectric layer in the alternating conductor / dielectric stack described above. In some embodiments, the number of pairs of dielectric layers in the alternating dielectric stack is the same as the number of conductor / dielectric layers in the alternating conductor / dielectric stack.

[0058] As shown in FIG. 2, each channel structure region 210 can include one or more slit structures 214 each extending in the WL direction. At least some of the slit structures 214 can function as a common source contact for the array of channel structures 212 in the channel structure region 210. The slit structures 214 can also divide the 3D memory device into a plurality of memory fins 242 and / or dummy memory fins 246. An upper select gate cut 255 can be disposed in the middle of each memory fin 242 to divide the upper select gate (TSG) of the memory fin into two parts. The upper select gate cut 255 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0059] In some embodiments, the dummy channel structure 222 is formed in the BL direction in a portion of the channel structure region 210, for example, in the dummy memory fin 246 adjacent to the BL TAC region 233. The dummy channel structure 222 can provide mechanical support for the memory array structure. The dummy memory fin 246 does not have a memory function, and thus, bit lines and related interconnect lines are not formed in the dummy memory fin 246.

[0060] Referring to FIG. 3A, an enlarged plan view of the region 140 shown in FIG. 1, including an exemplary word line (WL) TAC region of a 3D memory device according to some embodiments of the present disclosure, is illustrated. The region 300A of the 3D memory device (i.e., the region 140 shown in FIG. 1) can include a channel structure region 320, a word line (WL) TAC region 372 (e.g., the WL TAC region 170 shown in FIG. 1), and an upper selectivity gate (TSG) staircase region 330.

[0061] As shown in FIG. 3A, the channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. The TSG staircase region 330 can be disposed adjacent to the WL TAC region 372 at the side of the channel structure region 320 in a plan view. That is, the WL TAC region 372 is sandwiched in the WL direction by two TSG staircase regions 330. The WL TAC region 372 can be defined by a barrier structure 324. A plurality of TACs 326 used for specifying a switch path and reducing word line capacitance can be formed in the WL TAC region 372, which is laterally surrounded by the barrier structure 324.

[0062] In some embodiments, a dummy channel structure 322 is formed outside the WL TAC region 372 to provide mechanical support for the memory array structure. It is understood that the dummy channel structure 322 can be formed in any region other than the WL TAC region 372, for example, in the TSG staircase region 330 or along the edge of the channel structure region 320 adjacent to the TSG staircase region 330. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0063] In some embodiments, a plurality of slit structures 314 each extending in the WL direction can divide the 3D memory device into a plurality of memory fins 342, 344. At least some of the slit structures 314 can function as a common source contact for the array of channel structures 312 in the channel structure region 320. The sidewalls of the slit structure 314 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The filling material of the slit structure 314 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicon compounds, or any combination thereof.

[0064] An upper select gate cut 355 is disposed in the middle of each memory finger 342, 344, and the upper select gate (TSG) of the memory finger can be divided into two parts. The upper select gate cut 355 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0065] Note that the width of the WL TAC region 372 in the BL direction may be wider than the width of each memory finger 342 or 344. That is, in the BL direction, the barrier structure 324 can cross at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Thus, the upper select gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 are not interconnected by the upper conductor layer in the alternating conductor / dielectric stack.

[0066] To interconnect the upper select gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372, the TSG staircase region 330 includes one or more conductive lines (not shown in FIG. 3A) formed in a staircase shape (e.g., within the upper two to four steps) for making electrical interconnections with the upper select gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 separated by the WL TAC region 372.

[0067] For example, the slit structure 314 separated by the WL TAC region 372 can extend into the TSG staircase region 330. The top two conductor layers in the alternating conductor / dielectric stack can have a one-sided staircase structure. One or more interconnect layers with contacts are formed on the one-sided staircase structure to realize an electrical interconnect between the top selective gate of the channel structure 312 in the channel structure region 320 and those in the memory fin 344 separated by the WL TAC region 372.

[0068] Therefore, by introducing the TSG staircase region 330 that interconnects the top selective gates on both sides of the WL TAC region 372, the WL TAC region 372 can extend along the BL direction and be sized sufficiently to surround the desired number of TACs 326. Further, each memory plane 110 shown in FIG. 1 can include a plurality of WL TAC regions 372 arranged in the WL direction. That is, a plurality of memory blocks 115 can be arranged in the WL direction within each memory plane 110.

[0069] Referring to FIG. 3B, an enlarged plan view of the region 140 shown in FIG. 1, including another exemplary word line (WL) TAC region of a 3D memory device, according to some alternative embodiments of the present disclosure, is illustrated. The region 300B of the 3D memory device (i.e., the region 140 shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 (e.g., the WL TAC region 170 shown in FIG. 1) surrounding the word line (WL) TAC region 372.

[0070] As shown in FIG. 3B, the channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. The dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. The WL TAC region 372 is surrounded by the dummy channel region 350. The WL TAC region 372 can be defined by the barrier structure 324. A plurality of TACs 326 can be formed in the WL TAC region 372 that is laterally surrounded by the barrier structure 324.

[0071] In some embodiments, a dummy channel structure 322 is formed outside the WL TAC region 372 to provide mechanical support for the memory array structure. It is understood that the dummy channel structure 322 can be formed in any region other than the WL TAC region 372, for example, in the dummy channel region 350 or along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0072] In some embodiments, a plurality of slit structures 314 each extending in the WL direction can divide the 3D memory device into a plurality of memory fins 342, 344. An upper select gate cut 355 can be disposed in the middle of each memory fin 342, 344 to divide the upper select gate (TSG) of the memory fin into two parts.

[0073] Note that the width of the WL TAC region 372 in the BL direction may be wider than the width of each memory finger 342 or 344. That is, in the BL direction, the barrier structure 324 can cross at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Thus, the upper selective gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 are not interconnected by the upper conductor layer in the alternating conductor / dielectric stack.

[0074] Therefore, in some embodiments related to such a design of the WL TAC region 372, one memory plane 110 can include only two memory blocks 115 in the WL direction. The WL TAC region 372 is sandwiched between two memory blocks (i.e., the channel structure regions 320 shown in FIG. 3B), while the outside of the channel structure regions 320 in the WL direction can have a stepped structure (not shown in FIG. 3B). Thus, the upper selective gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 can be interconnected by using the stepped structure on the edge of the memory plane 110 of the 3D NAND device. Such a design may be suitable for routing a zigzag word line decoder (X-DEC).

[0075] Referring to FIG. 3C, an enlarged plan view of the region 140 shown in FIG. 1, including another exemplary word line (WL) TAC region of a 3D memory device, according to some alternative embodiments of the present disclosure, is illustrated. The region 300C of the 3D memory device (i.e., the region 140 shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0076] As shown in FIG. 3C, in some embodiments, a plurality of slit structures 314 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 342. An upper select gate cut 355 can be disposed in the middle of each memory finger 342 to divide the upper select gate (TSG) of the memory finger into two parts.

[0077] The channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. A plurality of WL TAC regions 376 arranged in columns along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 can be defined by a barrier structure 324. A plurality of TACs 326 can be formed in each WL TAC region 376 laterally surrounded by the barrier structure 324.

[0078] In some embodiments, the width of each WL TAC region 376 in the BL direction can be narrower than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be disposed between two adjacent slit structures 314. Since the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on both sides of the WL TAC region 376 can be interconnected by the upper conductor layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0079] In some embodiments, a dummy channel structure 322 is formed outside the WL TAC region 376 to provide mechanical support for the memory array structure. It is understood that the dummy channel structure 322 can be formed in any region other than the WL TAC region 376, for example, in the dummy channel region 350, along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0080] Thus, by disposing one WL TAC region 376 within each memory fin 342, the upper conductor layer in the alternating conductor / dielectric stack may not be blocked by the WL TAC region 376. Thus, no additional structure is required to further interconnect the upper select gates of the channel structure 312 between the two channel structure regions 320 in each memory fin 342 on both sides of the WL TAC region 376. Thus, the plurality of WL TAC regions 376 can be arranged within each memory fin 342 along the WL direction. That is, the memory 110 can include a plurality of memory blocks 115 in the WL direction.

[0081] Referring to FIG. 3D, an enlarged plan view of the region 140 shown in FIG. 1, including another exemplary word line (WL) TAC region of a 3D memory device, according to some alternative embodiments of the present disclosure, is illustrated. The region 300D of the 3D memory device (i.e., the region 140 shown in FIG. 1) can include a channel structure region 320 and a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0082] As shown in FIG. 3D, in some embodiments, a plurality of slit structures 314, 316, each extending in the WL direction, can divide the 3D memory device into a plurality of memory fingers 342. In some embodiments, the slit structure 314 can extend in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350. As shown in FIG. 3D, at least one slit structure 316 can include a gap 318 within the dummy channel region 350. An upper select gate cut 355 can be disposed in the middle of each memory finger 342 to divide the upper select gate (TSG) of the memory finger into two parts.

[0083] The channel structure region 320 can include an array of channel structures 312, each including a plurality of stacked memory cells. The dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. A plurality of WL TAC regions 376 arranged in columns along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 can be defined by a barrier structure 324. A plurality of TACs 326 can be formed in each WL TAC region 376 laterally surrounded by the barrier structure 324.

[0084] In some embodiments, the width of each WL TAC region 376 in the BL direction can be narrower than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 can be disposed between two adjacent slit structures 314. Since the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper select gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on both sides of the WL TAC region 376 can be interconnected by the upper conductor layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0085] In some embodiments, a dummy channel structure 322 is formed outside the WL TAC region 376 to provide mechanical support for the memory array structure. It is understood that the dummy channel structure 322 can be formed in any region other than the WL TAC region 376, for example, in the dummy channel region 350, along the edge of the channel structure region 320 adjacent to the dummy channel region 350. Note that the channel structure 312 and the dummy channel structure 322 penetrate the alternating conductor / dielectric stack, while the TAC 326 penetrates the alternating dielectric stack.

[0086] In some embodiments, one or more slit structures 316 can include a gap 318 in the dummy channel region 350. Word lines in adjacent memory fins 342 can be interconnected by using conductive lines passing through the gap 318. For example, as shown in FIG. 3D, the slit structure 314 at the edge of the memory block 115 can extend in the WL direction through two or more channel structure regions 320 and one or more dummy channel regions 350, while the slit structure 316 inside each memory block 115 can each include one or more gaps 318 in the corresponding dummy channel region 350. Thus, all upper select gates and / or word lines in the same memory block 115 can be interconnected without additional structures.

[0087] Therefore, by disposing the WL TAC region 376 in the memory fin 342 and providing the gap 318 in the slit structure 316, the upper conductor layer in the alternating conductor / dielectric stack may not be blocked by the WL TAC region 376 and can interconnect word lines in adjacent memory fins 342. Thus, a plurality of WL TAC regions 376 can be disposed in each memory fin 342 along the WL direction. That is, the memory 110 can include a plurality of memory blocks 115 in the WL direction. Such a structure can have a high integration level and a simple layout that can be easily manufactured.

[0088] Referring to FIG. 4A, an enlarged plan view of region 150 shown in FIG. 1 is illustrated, including an exemplary staircase structure (SS) TAC region of a 3D memory device according to some embodiments of the present disclosure. A region 400A of the 3D memory device (i.e., region 150 shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and a staircase structure (SS) TAC region 482.

[0089] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include a staircase structure and an array of word line contacts 432 formed on the staircase structure. In some embodiments, the SS TAC region 482 is within the staircase region 410. The SS TAC region 482 can be defined by only the barrier structure 424 or along with the edge of the staircase region 410 of the 3D memory device. A plurality of TACs 426 can be formed in the SS TAC region 482 laterally surrounded at least by the barrier structure 424.

[0090] As shown in FIG. 4A, in some embodiments, a plurality of slit structures 414, 416, each extending in the WL direction, can divide the 3D memory device into a plurality of memory fingers 442, 444. In some embodiments, the slit structure 414 can extend in the WL direction into at least a portion of the staircase region 410. At least some of the slit structures 416 can include one or more gaps 418 within the staircase region 410. An upper select gate cut 455 can be disposed in the middle of each memory finger 442, 444 to divide the upper select gate (TSG) of the memory finger into two parts.

[0091] In some embodiments, one or more slit structures 416 can include a gap 418 within the staircase region 410. Word line contacts 432 in adjacent memory fingers 442 can be interconnected by using conductive lines passing through the gap 418. For example, as shown in FIG. 4A, the slit structure 414 at the edge of the memory block 115 can extend in the WL direction all the way through the channel structure region 420 and the staircase region 410, while the slit structure 416 inside each memory block 115 can include one or more gaps 418 within the staircase region 410. Thus, all word line contacts 432 in the same memory block 115 can be interconnected without additional structures.

[0092] Note that the width of the SS TAC region 482 in the BL direction may be wider than the width of each memory finger 442, 444. That is, in the BL direction, the barrier structure 424 can cross at least two adjacent slit structures 414. Since the SS TAC region 482 occupies a partial area of the staircase region 410 corresponding to the memory finger 444 that is completely blocked by the barrier structure 424, the staircase structure in the SS TAC region 482 is used to form the TAC 426 rather than to form the word line contact 432 for the memory finger 444. Thus, the staircase structure (not shown in FIG. 4B) corresponding to the memory finger 444 on the other side of the memory plane 110 can be used to form the word line contact 432 rather than the SS TAC region 482.

[0093] Thus, in some embodiments related to such a design of the SS TAC region 482, the SS TAC regions 482 on both sides of the memory plane 110 do not overlap in the WL direction. That is, one memory fin corresponds to at most one SS TAC region 482. Such a design may be suitable for routing a zigzag word line decoder (X-DEC). Further, in some embodiments related to the design of the SS TAC region 482, for the same reason as the WL TAC region 372 described above with respect to FIG. 3B, the SS TAC region 482 and the WL TAC region 372 do not overlap in the WL direction. That is, one memory fin corresponds to at most either one SS TAC region 482 or one WL TAC region 372.

[0094] Referring to FIG. 4B, an enlarged plan view of the region 150 shown in FIG. 1, including another exemplary staircase structure (SS) TAC region of a 3D memory device, according to some alternative embodiments of the present disclosure, is illustrated. A region 400B of the 3D memory device (i.e., the region 150 shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and a plurality of staircase structure (SS) TAC regions 484.

[0095] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include a staircase structure and an array of word line contacts 432 formed on the staircase structure. In some embodiments, the SS TAC region 484 is within the staircase region 410. Each SS TAC region 484 can be defined by only the barrier structure 424 or together with the edge of the staircase region 410 of the 3D memory device. A plurality of TACs 426 can be formed in the SS TAC region 482 that is laterally surrounded at least by the barrier structure 424.

[0096] As shown in FIG. 4B, in some embodiments, a plurality of slit structures 414 each extending in the WL direction within the channel structure region 420 can divide the 3D memory device into a plurality of memory fingers 442. An upper select gate cut 455 can be disposed in the middle of each memory finger 442 to divide the upper select gate (TSG) of the memory finger into two parts. In some embodiments, the slit structure 414 can extend in the WL direction into at least a portion of the staircase region 410. In some embodiments, the staircase region 410 can further include a plurality of slit structures 416 that are not aligned with the slit structure 414 in the WL direction. That is, the distance between adjacent slit structures in the staircase region 410 may be non-uniform. Some adjacent slit structure pairs can have a first distance that is longer than a second distance between other adjacent slit structure pairs.

[0097] In some embodiments, each SS TAC region 484 can be disposed between adjacent slit structure pairs having the first distance. That is, the width of the SS TAC region 484 in the BL direction may be narrower than the first distance. Thus, outside of the space occupied by the SS TAC region 484, the staircase region 410 between such adjacent slit structure pairs having the first distance can have extra space for forming the word line contact 432.

[0098] Referring to FIG. 5, a schematic cross-sectional view of an exemplary 3D memory device 500 according to some embodiments of the present disclosure is illustrated. The 3D memory device 500 can be a portion of a non-monolithic 3D memory device, and its components (e.g., peripheral devices and array devices) can be formed separately on different substrates. For example, the 3D memory device 500 can be the region 130, region 140, or region 150 described above with respect to FIG. 1.

[0099] As shown in FIG. 5, the 3D memory device 500 can include a substrate 570 and an array device on the substrate 570. Note that for further explaining the spatial relationship of the components in the 3D memory device 500, the X-axis and Y-axis are added to FIG. 5. The substrate 570 includes two lateral surfaces (e.g., the upper surface 572 and the bottom surface 574) that extend laterally in the X direction (lateral direction, e.g., the WL direction or the BL direction).

[0100] As used herein, whether one component (e.g., a layer or a device) is on, above, or below another component (e.g., a layer or a device) of a semiconductor device (e.g., the 3D memory device 500) is determined with respect to the substrate (e.g., the substrate 570) of the semiconductor device in the Y direction (vertical direction) when the substrate is located at the lowest surface of the semiconductor device in the Y direction. The cross-sectional view of the 3D memory device 500 shown in FIG. 5 is along the BL direction and the Y-direction plane. The same concept for describing the spatial relationship is applied throughout this disclosure.

[0101] The substrate 570 can be used to support the array device and can include a circuit board 530 and an epitaxial substrate 540. The circuit board 530 can include a base substrate 510 and one or more peripheral circuits (not shown in FIG. 5) formed above the base substrate 510. The base substrate 510 can include any suitable semiconductor material that can include silicon (e.g., single-crystalline silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. In some embodiments, the base substrate 510 is a thin substrate (e.g., a semiconductor layer) thinned by polishing, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0102] One or more peripheral circuits created on circuit board 530 can include any suitable digital, analog, and / or mixed-signal peripheral circuits, such as page buffers, decoders, and latches, used to facilitate the operation of 3D memory device 500 (not shown in FIG. 5). In some embodiments, circuit board 530 can further include one or more interconnect structures 532 for electrically connecting one or more peripheral circuits to the array devices above substrate 570. The one or more interconnect structures 532 can include any suitable conductive structure, including but not limited to contacts, single-layer / multilayer vias, conductive layers, plugs, and the like.

[0103] Epitaxial substrate 540 can be formed on circuit board 530 by using a deposition process including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Epitaxial substrate 540 can be a single-layer substrate or a multilayer substrate, such as, for example, a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, and the like. Further, one or more openings 542 corresponding to one or more through-array contact (TAC) structures of the array device can be formed in the region of epitaxial substrate 540. The plurality of TACs 526 can pass through the one or more openings 542 for electrical connection to one or more interconnect structures 532 in circuit board 530.

[0104] In some embodiments, 3D memory device 500 is a NAND-type flash memory device in which memory cells are provided in the form of an array of channel structures extending in the Y direction above substrate 570 (not shown in FIG. 5). The array device can include a plurality of channel structures extending through an alternating conductor / dielectric stack 580 including pairs of a plurality of conductor layers 580A and dielectric layers 580B. The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580 (e.g., 32, 64, or 96) can set the number of memory cells in 3D memory device 500.

[0105] In the alternating conductor / dielectric stack 580, the conductor layer 580A and the dielectric layer 580B alternate in the Y direction. In other words, except for those at the top or bottom of the alternating conductor / dielectric stack 580, each conductor layer 580A can have two dielectric layers 580B in contact on both sides, and each dielectric layer 580B can have two conductor layers 580A in contact on both sides. The conductor layers 580A can each have the same thickness or different thicknesses. Similarly, the dielectric layers 580B can have the same thickness or different thicknesses. The conductor layer 580A can include a conductor material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicon compounds, or any combination thereof. The dielectric layer 580B can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer 580A includes a metal layer such as W, and the dielectric layer 580B includes silicon oxide.

[0106] In some embodiments, the array device further includes a slit structure 514. Each slit structure 514 can extend in the Y direction through the alternating conductor / dielectric stack 580. The slit structure 514 can also extend laterally (i.e., parallel to the substrate) to separate the alternating conductor / dielectric stack 580 into a plurality of blocks. The slit structure 514 can include slits filled with a conductor material including, but not limited to, W, Co, Cu, Al, silicon compounds, or any combination thereof. The slit structure 514 can further include a dielectric layer having any suitable dielectric material between the filled conductor material and the alternating conductor / dielectric stack 580 to electrically insulate the filled conductor material from the surrounding conductor layer 580A in the alternating conductor / dielectric stack 580. As a result, the slit structure 514 can separate the 3D memory device 500 into a plurality of memory fins (e.g., as shown in FIGS. 2, 3A-3D, 4A-4B in plan view).

[0107] In some embodiments, the slit structure 514 functions as a source contact for the channel structures in the same memory fin that share a common source of the same array. The slit structure 514 can thus be referred to as the "common source contact" of a plurality of channel structures. In some embodiments, the epitaxial substrate 540 includes a doped region 544 (including a p-type or n-type dopant at a desired doping level), and the lower edge of the slit structure 514 contacts the doped region 544 of the epitaxial substrate 540.

[0108] In some embodiments, the alternating dielectric stack 560 can be disposed in a region laterally surrounded by the barrier structure 516 on the epitaxial substrate 540. The alternating dielectric stack 560 can include a plurality of dielectric layer pairs. For example, the alternating dielectric stack 560 is formed by an alternating stack of a first dielectric layer 560A and a second dielectric layer 560B that is different from the first dielectric layer 560A. In some embodiments, the first dielectric layer 560A includes silicon nitride, and the second dielectric layer 560B includes silicon oxide. The second dielectric layer 560B in the alternating dielectric stack 560 may be the same as the dielectric layer 580B in the alternating conductor / dielectric stack 580. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack 560 is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580.

[0109] In some embodiments, a barrier structure 516 extending in the Y direction laterally separates the alternating conductor / dielectric stack 580 and the alternating dielectric stack 560. That is, the barrier structure 516 may serve as a boundary between the alternating conductor / dielectric stack 580 and the alternating dielectric stack 560. The alternating dielectric stack 560 can be laterally surrounded at least by the barrier structure 516. In some embodiments, the barrier structure 516 is in a closed shape (e.g., rectangular, square, circular, etc.) in a plan view to completely surround the alternating dielectric stack 560. For example, as shown in FIGS. 3A-3D, the barrier structure 324 is in a rectangular shape in a plan view to completely surround the alternating dielectric stack in the WL TAC regions 372, 376. In some embodiments, the barrier structure 516 is not in a closed shape in a plan view, but can surround the alternating dielectric stack 560 along one or more edges of the array device. For example, as shown in FIGS. 4A and 4B, the barrier structure 424 along with the edge of the 3D memory device surrounds the alternating dielectric stack in the SS TAC regions 482, 484.

[0110] As shown in FIG. 5, the 3D memory device 500 further includes a plurality of TACs 526 each extending in the Y direction through the alternating dielectric stack 560. The TACs 526 can be formed only inside at least the region laterally surrounded by the barrier structure 516, which includes a plurality of dielectric layer pairs. That is, the TACs 526 can extend vertically through the dielectric layers (e.g., the first dielectric layer 560S and the second dielectric layer 560B), but not through any conductor layer (e.g., the conductor layer 580A). Each TAC 526 can extend through the entire thickness of the alternating dielectric stack 560 (e.g., all the dielectric layer pairs in the Y direction). In some embodiments, the TACs 526 further penetrate through the epitaxial substrate 540 through the openings 542 and are in electrical contact with the interconnect structure 532.

[0111] TAC526 can carry electrical signals to and from the 3D memory device 500, such as portions of the power bus, with a shortened interconnect path. In some embodiments, TAC526 can effectuate an electrical connection between an array device and a peripheral device (not shown in FIG. 5) through one or more interconnect structures 532. TAC526 can also provide mechanical support for the alternating dielectric stack 560. Each TAC526 can include a vertical aperture through the alternating dielectric stack 560, which is filled with a conductor material including, but not limited to, W, Co, Cu, Al, doped silicon, silicon compounds, or any combination thereof. In some embodiments, since TAC526 is formed within the alternating dielectric stack 560 (surrounded by dielectric layers), an additional dielectric layer between TAC526 and the alternating dielectric stack 560 is not necessary for insulation purposes.

[0112] Referring to FIG. 6, a schematic flowchart of an exemplary method 600 for forming a 3D memory device in accordance with some embodiments of the present disclosure is illustrated. It should be understood that the operations shown in method 600 are not exhaustive, and that additional operations can be implemented similarly before, after, or between any of the operations described.

[0113] Referring to FIG. 6, method 600 begins at operation 602, where a substrate is formed. In some embodiments, the step of forming the substrate can include forming a base substrate, forming at least one peripheral circuit on the substrate, forming at least one interconnect structure in electronic contact with the at least one peripheral circuit, and forming an epitaxial substrate on the at least one peripheral circuit.

[0114] The base substrate can be formed by using any suitable semiconductor material including silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any suitable combination thereof. In some embodiments, the step of forming the base substrate includes a thinning process including polishing, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0115] One or more peripheral circuits can include any suitable digital, analog, and / or mixed signal peripheral circuits including, but not limited to, page buffers, decoders, and latches. In some embodiments, one or more interconnect structures can include any suitable conductive structure including, but not limited to, contacts, single / multilayer vias, conductive layers, plugs, etc.

[0116] The epitaxial substrate can be formed over one or more peripheral circuits by using a deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The epitaxial substrate can be, for example, a single layer substrate or a multilayer substrate such as a single crystal single layer substrate, a polycrystalline silicon (polysilicon) single layer substrate, a polysilicon and metal multilayer substrate, etc.

[0117] In some embodiments, the step of forming the epitaxial substrate further includes the step of forming one or more openings such that at least a portion of one or more interconnect structures is exposed by the one or more openings. The one or more openings can correspond to one or more through-array contact TAC structures (e.g., a word line (WL) TAC structure as shown in FIG. 2, a bit line (BL) TAC structure as shown in FIGS. 3A-3D, a staircase structure (SS) TAC structure as shown in FIGS. 4A-4B) formed in a subsequent process. The one or more openings can be filled with a dielectric material.

[0118] Method 600 proceeds to operation 604, in which an alternating dielectric stack is formed on the substrate. In some embodiments, a plurality of pairs of first dielectric layers and second dielectric layers can be formed on the substrate to form the alternating dielectric stack. In some embodiments, each pair of dielectric layers includes a layer of silicon nitride and a layer of silicon oxide. The alternating dielectric stack can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0119] Method 600 proceeds to operation 606, in which a staircase structure is formed at one or more edges of the alternating dielectric stack. In some embodiments, a trim etch process can be performed (laterally) on at least one side of the alternating dielectric stack to form a staircase structure having a plurality of steps. Each step can include one or more pairs of dielectric layers having alternating first and second dielectric layers.

[0120] Method 600 proceeds to operation 608, in which a plurality of channel structures and one or more barrier structures are formed. Each channel structure and each barrier structure can extend vertically through the alternating dielectric stack.

[0121] In some embodiments, the manufacturing process for forming the channel structure includes, for example, forming channel holes that extend vertically through the alternating dielectric stack by wet etching and / or dry etching. In some embodiments, the manufacturing process for forming the channel structure further includes forming a semiconductor channel and a memory film between the semiconductor channel and the dielectric layer pair in the alternating dielectric stack. The semiconductor channel can include a semiconductor material such as polysilicon. The memory film can be a composite dielectric layer such as a combination of a tunneling layer, a storage layer, and a blocking layer.

[0122] The tunneling layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Electrons or holes from the semiconductor channel can tunnel through the tunneling layer to the storage layer. The storage layer can include a material for storing charge for memory operation. The material of the storage layer includes, but is not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer can include a dielectric material including, but not limited to, silicon oxide or a combination of silicon oxide / silicon nitride / silicon oxide (ONO). The blocking layer can further include a high-k dielectric layer such as an aluminum oxide (Al2O3) layer. The semiconductor channel and the memory film can be formed by one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or a combination thereof.

[0123] In some embodiments, the manufacturing process for forming the barrier structure is carried out simultaneously in the same manner as the manufacturing process for forming the channel structure, thereby reducing the complexity and cost of manufacturing. In some embodiments, the channel structure and the barrier structure are formed in different manufacturing steps so that the barrier structure can be filled with a material different from the material filling the channel structure.

[0124] In some embodiments, the manufacturing process for forming the barrier structure includes, for example, forming trenches that extend vertically through the alternating dielectric stack by wet etching and / or dry etching. After the trenches are formed through the alternating dielectric stack, one or more thin film deposition processes can be performed to fill the trenches with a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide / nitride / silicon oxide (ONO), aluminum oxide (Al2O3), etc. or any combination thereof.

[0125] By forming one or more barrier structures, the alternating dielectric stack can be separated into two types of regions, namely, one or more inner regions each laterally surrounded by at least the barrier structure (in some embodiments, together with the edges of the alternating dielectric stack), and an outer region where a channel structure and / or a word line contact can be formed. Note that each inner region corresponds to an opening in the epitaxial substrate.

[0126] In some embodiments, as described above with respect to FIG. 2, at least one inner region can be used to form a BL TAC structure. Therefore, the barrier structure surrounding such an inner region can include two parallel barrier walls extending along the WL direction.

[0127] In some embodiments, as described above with respect to FIG. 3A or FIG. 3B, at least one inner region can be used to form a BL TAC structure. Therefore, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be wider than the distance between two adjacent slit structures formed in a subsequent process.

[0128] In some embodiments, as described above with respect to FIG. 3C or FIG. 3D, at least one inner region can be used to form a BL TAC structure. Therefore, the barrier structure surrounding such an inner region can have a rectangular shape. The width of the barrier structure in the BL direction can be narrower than the distance between two adjacent slit structures formed in a subsequent process.

[0129] In some embodiments, as described above with respect to FIG. 4A, at least one inner region can be used to form an SS TAC structure. Therefore, the barrier structure for separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be wider than the distance between two adjacent slit structures formed in a subsequent process.

[0130] In some embodiments, as described above with respect to FIG. 4B, at least one inner region can be used to form an SS TAC structure. Therefore, the barrier structure for separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be narrower than the maximum distance between two adjacent slit structures formed in the staircase region in a subsequent process.

[0131] In some embodiments, the dummy channel structure can be formed simultaneously with the channel structure. The dummy channel structure can extend vertically through the alternating layer stack and can be filled with the same material as that in the channel structure. Different from the channel structure, contacts for realizing electrical connection with other components of the 3D memory device are not formed on the dummy channel structure. Therefore, the dummy channel structure cannot be used to form memory cells in the 3D memory device.

[0132] Method 600 proceeds to operation 610, where a plurality of slits are formed, and through the plurality of slits, a first dielectric layer in a portion of the alternating dielectric stack is replaced with a conductor layer. For example, a plurality of parallel slits extending in the WL direction can be first formed through the alternating dielectric stack in the outer region by wet etching and / or dry etching of a dielectric (e.g., silicon oxide and silicon nitride). In some embodiments, then, through the slits, a doped region is formed in the epitaxial substrate below each slit, for example, by ion implantation and / or thermal diffusion. It is understood that according to some embodiments, the doped region can be formed at an earlier manufacturing stage, such as before the formation of the slits.

[0133] In some embodiments, the formed slits are used for a gate replacement process (also known as a "word line replacement" process) in which a first dielectric layer (e.g., silicon nitride) in the outer region of the alternating dielectric stack is replaced with a conductor layer (e.g., W). Note that the gate replacement occurs only in the outer region of the alternating dielectric stack due to the formation of the barrier structure and does not occur in the inner region. The barrier structure can prevent the etching of the first dielectric layer (e.g., silicon nitride) in the inner region of the alternating dielectric stack. This is because the barrier structure is filled with a material that cannot be etched in the etching step of the gate replacement process.

[0134] As a result, after the gate replacement process, the alternating dielectric stack in the outer region becomes an alternating conductor / dielectric stack. The replacement of the first dielectric layer with the conductor layer can be performed by wet etching the first dielectric layer (e.g., silicon nitride) selectively with respect to the second dielectric layer (e.g., silicon oxide) and filling the structure with a conductor layer (e.g., W). The conductor layer can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. The conductor layer can include a conductor material including, but not limited to, W, Co, Cu, Al, polysilicon, silicon compounds, or any combination thereof.

[0135] Method 600 proceeds to operation 612, in which a slit structure is formed by filling (e.g., depositing) the slit with a conductor material by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit structure can include a conductor material including, but not limited to, W, Co, Cu, Al, polysilicon, silicon compounds, or any combination thereof. In some embodiments, a dielectric layer (e.g., a silicon oxide layer) is first formed between the conductor material of the slit structure and the conductor layer surrounding the slit structure in the alternating conductor / dielectric stack for insulation purposes. The lower edge of the slit structure can contact the doped region.

[0136] Method 600 proceeds to operation 614, in which a plurality of TACs are formed through an alternating dielectric stack. The TACs can be formed in one or more inner regions by first etching a vertical opening (e.g., by wet etching and / or dry etching) and then filling the opening with a conductor material using ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductor materials used to fill the local contacts can include, but are not limited to, W, Co, Cu, Al, polysilicon, silicon compounds, or any combination thereof. In some embodiments, other conductor materials are also used to fill the opening so as to function as a barrier layer, an adhesion layer, and / or a seed layer.

[0137] The TACs can be formed by etching through the entire thickness of the alternating dielectric stack and through the dielectric layer formed in the opening in the epitaxial substrate. Since the alternating dielectric stack includes alternating layers of dielectrics such as silicon oxide and silicon nitride, the openings of the TACs can be formed by deep etching of the dielectric material (e.g., by a deep reactive ion etching (DRIE) process or any suitable anisotropic etching process). In some embodiments, the TACs penetrate through the epitaxial substrate through the openings of the epitaxial substrate. The lower edge of the TAC can contact the interconnect structure in the substrate. Thus, the TAC can be electrically connected to the peripheral devices formed in the substrate.

[0138] In some embodiments, the TACs are formed after gate replacement, but by ensuring an area of the alternating dielectric stack that is not affected by the gate replacement process (remains an alternating conductor / dielectric stack), the TACs are still formed through the dielectric layer (without passing through any conductor layer), thereby simplifying the manufacturing process and reducing costs.

[0139] Various embodiments in accordance with the present disclosure provide a 3D memory device having a through-array contact structure for a memory array. The through-array contact structure disclosed herein includes TACs to achieve vertical interconnections between stacked array devices and peripheral devices (e.g., for power buses and metal wiring), thereby reducing the number of metal levels and shrinking the die size. In some embodiments, the TACs in the through-array contact structure disclosed herein are formed through a stack of alternating dielectric layers that can be etched more easily to form through-holes therein compared to a stack of conductor and dielectric layers alternating, thereby reducing process complexity and manufacturing cost.

[0140] Accordingly, one aspect of the present disclosure discloses a three-dimensional (3D) NAND memory device including a substrate including at least one peripheral circuit and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack including a plurality of dielectric layer pairs, a second region including an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs, and a third region including a staircase structure on an edge of the alternating conductor / dielectric layer stack in a word line direction. The memory device further includes a barrier structure extending vertically through an alternating layer stack for laterally separating the first region from the second region or the third region, a plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through-array contacts in the first region each extending vertically through the alternating dielectric stack. At least one of the plurality of through-array contacts is electrically connected to at least one peripheral circuit.

[0141] Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) NAND memory device. The method includes forming a substrate including at least one peripheral circuit, forming an alternating dielectric stack including a plurality of dielectric layer pairs on the substrate, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer, forming a staircase structure at an edge of the alternating dielectric stack, and forming a plurality of channel structures and at least one barrier structure each extending vertically through the alternating dielectric stack. The at least one barrier structure separates the alternating dielectric stack into at least one first region and a second region laterally surrounded by at least the barrier structure. The method further includes forming a plurality of slits and replacing, through the slits, the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer to form an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs, depositing a conductive material into the slits to form a plurality of slit structures, and forming a plurality of through-array contacts in the first region, each through-array contact extending vertically through the alternating dielectric stack and electrically connecting at least one of the plurality of through-array contacts to at least one peripheral circuit.

[0142] The foregoing description of specific embodiments has so fully revealed the general nature of the present disclosure that others can, by applying the knowledge of those skilled in the art, readily modify and / or adapt such specific embodiments for various applications without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based upon the teachings and guidance presented herein. It is to be understood that the terminology or phrasing herein is for the purpose of description and not of limitation, such that the terminology or phrasing of this specification is to be interpreted by those skilled in the art in light of the teachings and guidance.

[0143] Embodiments of the present disclosure have been described above using functional building blocks that describe the implementation of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for ease of description. Alternative boundaries can be defined as long as the specified functions and their relationships are properly implemented.

[0144] The sections of the summary and abstract of the invention can describe one or more but not all exemplary embodiments of the present disclosure contemplated by the inventors, and thus are not intended to limit the present disclosure and the appended claims in any way.

[0145] The scope and extent of the present disclosure should not be limited by any of the above exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0146] [Additional Note 1] An alternating layer stack disposed on a substrate, comprising: a first region including an alternating dielectric stack having a plurality of dielectric layer pairs, and a second region including an alternating conductor / dielectric stack having a plurality of conductor / dielectric layer pairs, the alternating layer stack; a barrier structure extending vertically through the alternating layer stack for laterally separating the first region from the second region; a plurality of through-array contacts in the first region, each through-array contact extending vertically through the alternating dielectric stack; and a three-dimensional (3D) NAND memory device, wherein at least one of the plurality of through-array contacts is electrically connected to at least one peripheral circuit. [Additional Note 2] The memory device according to claim 1, wherein the barrier structure includes silicon oxide and silicon nitride. [Additional Note 3] The memory device according to claim 1 or 2, wherein each of the plurality of dielectric layer pairs includes a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs includes a metal layer and a silicon oxide layer. [Additional Note 4] The number of the plurality of dielectric layer pairs is at least 32, and the number of the plurality of conductor / dielectric layer pairs is at least 32. The memory device according to any one of claims 1 to 3. [Additional Note 5] The memory device according to any one of claims 1 to 4, further comprising a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack and laterally along the word line direction for dividing the alternating conductor / dielectric stack into a plurality of memory fins. [Additional Note 6] The barrier structure extends laterally along the word line direction, and the first region is separated from the second region by the barrier structure and sandwiched between two adjacent slit structures. The memory device according to claim 5. [Additional Note 7] The memory device according to claim 5, wherein the barrier structure extends laterally along a bit line direction different from the word line direction and laterally separates the first region from the second region. [Additional Note 8] The memory device according to claim 7, wherein the bit line direction is perpendicular to the word line direction. [Additional Note 9] The memory device according to appended claim 7 or 8, wherein the width of the first region surrounded by the barrier structure in the bit line direction is wider than the distance between two adjacent slit structures. [Appended claim 10] The memory device according to any one of appended claims 7 to 9, wherein the first region surrounded by the barrier structure is sandwiched in the word line direction between two upper selectivity gate staircase regions. [Appended claim 11] The memory device according to appended claim 10, wherein at least the upper two layers of the alternating conductor / dielectric stack in each upper selectivity gate staircase region have a staircase structure. [Appended claim 12] The memory device according to appended claim 11, further comprising at least one conductive layer configured to interconnect upper selection gates on both sides of the first region surrounded by the barrier structure in the word line direction, above the alternating conductor / dielectric stack in the second region, and on the staircase structure in the upper selectivity gate staircase region. [Appended claim 13] The memory device according to any one of appended claims 10 to 12, further comprising a first region which is at least two first regions surrounded by corresponding barrier structures, and each first region extends parallel along the bit line direction. [Appended claim 14] Further comprising a plurality of barrier structures for surrounding the plurality of first regions from the second region, the plurality of first regions being aligned in the bit line direction, The memory device according to appended claim 7 or 8, wherein each of the plurality of first regions is sandwiched in the bit line direction between two adjacent slit structures. [Appended claim 15] The memory device according to appended claim 14, wherein the plurality of first regions are aligned in at least two columns in the bit line direction. [Appended claim 16] The memory device according to appended claim 14, wherein at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction includes a gap and is configured to interconnect word lines of adjacent memory fins. [Appended claim 17] The first region is separated by the barrier structure from a staircase structure on an edge of the alternating conductor / dielectric layer stack along the bit line direction, The memory device according to appended claim 7 or 8, wherein an opening of the barrier structure is at an edge of the alternating layer stack along the bit line direction. [Appended claim 18] The memory device according to claim 17, wherein the width of the first region in the bit line direction is wider than the distance between two adjacent slit structures. [Claim 19] The memory device according to claim 17, wherein the width of the first region in the bit line direction is narrower than the maximum distance between two adjacent slit structures in the staircase structure on the edge of the alternating layer stack along the bit line direction. [Claim 20] The memory device according to any one of claims 1 to 19, further comprising a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack. [Claim 21] Forming an alternating dielectric stack comprising a plurality of dielectric layer pairs on a substrate, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; Forming at least one barrier structure extending vertically through the alternating dielectric stack, the at least one barrier structure separating the alternating dielectric stack into at least one first region and a second region laterally surrounded by at least the barrier structure; Forming a plurality of slits and replacing, through the slits, a first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer to form an alternating conductor / dielectric stack comprising a plurality of conductor / dielectric layer pairs; Depositing a conductive material into the slits to form a plurality of slit structures; Forming a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack and electrically connecting at least one of the plurality of through array contacts to at least one peripheral circuit; A method of forming a three-dimensional (3D) NAND memory device, including the above steps. [Claim 22] Forming the at least one peripheral circuit on a base substrate; Forming at least one interconnect structure to electrically connect at least one of the plurality of through array contacts to the at least one peripheral circuit; Forming an epitaxial substrate on the at least one peripheral circuit; further including the above steps. The method according to claim 21, wherein the substrate comprises at least a base substrate and the epitaxial substrate. [Claim 23] The method according to claim 22, further comprising, before the step of forming the slit, forming a plurality of doped regions in the epitaxial substrate so that each slit structure is in contact with a corresponding doped region. [Claim 24] Forming at least one opening in the epitaxial substrate corresponding to the at least one first region to expose an interconnect structure for electronically connecting to the at least one peripheral circuit; Filling the at least one opening with a dielectric material The method according to claim 22, further comprising. [Claim 25] The method according to any one of claims 21 to 24, wherein the at least one barrier structure is formed of silicon oxide and silicon nitride. [Claim 26] The method according to any one of claims 21 to 25, wherein each of the plurality of dielectric layer pairs is formed of a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs is formed of a metal layer and a silicon oxide layer. [Claim 27] Forming at least 32 pairs of dielectric layer pairs; Forming at least 32 pairs of conductor / dielectric layer pairs The method according to any one of claims 21 to 26, further comprising. [Claim 28] The method according to any one of claims 21 to 27, further comprising forming the plurality of slit structures extending laterally along the word line direction to divide the alternating conductor / dielectric stack into a plurality of memory fingers. [Claim 29] The method according to claim 28, further comprising forming two parallel barrier structures extending laterally along the word line direction such that the first region is separated from the second region by the two parallel barrier structures and sandwiched between two adjacent slit structures. [Claim 30] The method according to claim 28, further comprising forming a barrier structure extending laterally along a bit line direction different from the word line direction to laterally separate the first region from the second region. [Claim 31] The method according to claim 30, further comprising forming a barrier structure extending laterally along the bit line direction perpendicular to the word line direction. [Claim 32] The method according to claim 30 or 31, further comprising forming the barrier structure such that a width of the first region surrounded by the barrier structure in a bit line direction is wider than a distance between two adjacent slit structures. [Claim 33] The memory device according to any one of claims 30 to 32, further comprising forming a staircase structure in the alternating dielectric stack adjacent to the barrier structure. [Claim 34] The method according to claim 33, further comprising forming at least one conductive layer on the staircase structure adjacent to the barrier structure to interconnect upper select gates on both sides of the first region surrounded by the barrier structure in a word line direction above the alternating conductor / dielectric stack in the second region. [Claim 35] The method according to any one of claims 30 to 34, further comprising forming at least two barrier structures to surround at least two first regions extending parallel along the bit line direction. [Claim 36] The method according to claim 30 or 31, further comprising forming a plurality of barrier structures to surround a plurality of first regions from the second region, wherein the plurality of first regions are aligned in the bit line direction such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. [Claim 37] The method according to claim 36, further comprising forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are aligned in at least two columns in the bit line direction. [Claim 38] The method according to claim 36, further comprising forming a gap in the at least one slit structure sandwiched between two adjacent barrier structures in the bit line direction to interconnect word lines of adjacent memory fins. [Claim 39] The method according to claim 28, further comprising forming the barrier structure for separating the first region in the staircase structure at an edge of the alternating stack, wherein an opening of the barrier structure is at the edge of the alternating layer stack along a bit line direction different from the word line direction. [Claim 40] The method according to claim 39, further comprising forming the barrier structure such that a width of the first region in the bit line direction is wider than a distance between two adjacent slit structures. [Claim 41] The method according to claim 39, further comprising forming the barrier structure such that a width of the first region in the bit line direction is narrower than a maximum distance between two adjacent slit structures in the staircase structure. [Claim 42] The method according to any one of claims 21 to 41, further comprising forming a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

Explanation of Symbols

[0147] 100 3D memory device 110 Memory plane 115 Memory block 120 Contact pad 130 Region 140 Region 150 Region 160 Bit line (BL) TAC region, Word line (BL) TAC region 170 Word line (WL) TAC region 180 Staircase structure (SS) TAC region 200 Region 210 Channel structure region 212 Channel structure 214 Slit structure 222 Dummy channel structure 224 Barrier structure 226 TAC 233 Bit line (BL) TAC region 242 Memory finger 246 Dummy memory finger 255 Upper selection gate cut 300A Region 300B Region 300C Region 300D Region 312 Channel structure 314 Slit structure 316 Slit structure 318 Gap 320 Channel Structure Region 322 Dummy Channel Structure 314 Barrier Structure 326 TAC 330 Top Selective Gate (TSG) Staircase Region 342 Memory Finger 344 Memory Finger 350 Dummy Channel Region 355 Top Selective Gate Cut 372 Word Line (WL) TAC Region 376 Word Line (WL) TAC Region 400A Region 400B Region 410 Staircase Region 414 Slit Structure 416 Slit Structure 418 Gap 420 Channel Structure Region 424 Barrier Structure 426 TAC 432 Word Line Contact 442 Memory Finger 444 Memory Finger 455 Top Selective Gate Cut 482 Staircase Structure (SS) TAC Region 484 Staircase Structure (SS) TAC Region 500 3D Memory Device 510 Base Substrate 514 Slit Structure 516 Barrier Structure 526 TAC 530 Circuit Board 532 Interconnection Structure 540 Epitaxial Substrate 542 Opening 544 Doped Region 560 Alternating Dielectric Stack 560A First Dielectric Layer 560B Second Dielectric Layer 560S First Dielectric Layer 570 Substrate 572 Top surface 574 Bottom surface 580 Alternating conductor / dielectric stack 580A Conductor layer 580B Dielectric layer 600 Method

Claims

1. One or more first stacks and second stacks, each of the one or more first stacks comprises first and second dielectric layers arranged in a vertical alternating fashion; the second stack comprises conductive layers and third dielectric layers arranged alternately in the vertical direction; a first stack and a second stack; a barrier structure extending vertically through one of the one or more first stacks and laterally separating said one of the one or more first stacks from said second stack, said barrier structure comprising two parallel first sub-barrier structures; one or more through array contact structures extending vertically through said one of said one or more first stacks; a slit structure extending through the second stack along a first lateral direction parallel to the vertical direction and comprising a conductive structure; A memory device comprising:

2. 10. The memory device of claim 1, wherein each of the one or more through array contact structures is connected to peripheral circuitry.

3. 10. The memory device of claim 1, wherein the conductive structures comprise at least one of polysilicon and doped polysilicon.

4. the slit structure also comprises a fourth dielectric layer; 2. The memory device of claim 1, wherein the fourth dielectric layer is between the first stack and the conductive structure.

5. 5. The memory device of claim 4, wherein the fourth dielectric layer comprises silicon oxide.

6. the memory device comprises a plurality of the first stacks; 2. The memory device of claim 1, wherein a plurality of said first stacks are arranged along a second lateral direction parallel to said vertical direction and said first lateral direction.

7. the memory device comprising a plurality of the through array contact structures; 2. The memory device of claim 1, wherein the through array contact structure of Fukusu is disposed along the first lateral direction in the one of the one or more first stacks.

8. a channel structure extending vertically through the second stack; a dummy channel structure extending vertically through the second stack; Further equipped with 2. The memory device of claim 1, wherein the dummy channel structure is between the channel structure and one or more of the through array contact structures along the first lateral direction.

9. the barrier structure comprises a second sub-barrier structure; 2. The memory device of claim 1, wherein two parallel ends of the second sub-barrier structure are connected to the second sub-barrier structure.

10. the first dielectric layer and the second dielectric layer comprise different materials; 10. The memory device of claim 1, wherein the second dielectric layer and the third dielectric layer comprise the same material.

11. a first substrate having a peripheral circuit; a second substrate disposed on the first substrate; one or more first stacks disposed on the second substrate, each first stack comprising a first dielectric layer and a second dielectric layer arranged in alternating vertical directions; a second stack disposed on the second substrate, the second stack comprising alternating conductive layers and third dielectric layers in the vertical direction; a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, the barrier structure comprising two parallel first sub-barrier structures; one or more through array contact structures extending vertically through one of the one or more first stacks to the first substrate; a slit structure extending through the second stack along a first lateral direction intersecting the vertical direction, the slit structure comprising a conductive structure; A memory device comprising:

12. The memory device of claim 11 , wherein each of the one or more through array contact structures is connected to the peripheral circuitry disposed on the second substrate.

13. 12. The memory device of claim 11, wherein the conductive structures comprise at least one of polysilicon and doped polysilicon.

14. the slit structure also comprises a fourth dielectric layer; 12. The memory device of claim 11, wherein the fourth dielectric layer is located between the first stack and the conductive structure.

15. 15. The memory device of claim 14, wherein the fourth dielectric layer comprises silicon oxide.

16. the memory device comprises a plurality of the first stacks; 12. The memory device of claim 11, wherein a plurality of said first stacks are arranged along a second lateral direction parallel to said vertical direction and said first lateral direction.

17. the memory device comprising a plurality of the through array contact structures; 12. The memory device of claim 11, wherein a plurality of the through array contact structures are disposed along the first lateral direction in one of the one or more first stacks.

18. a channel structure extending vertically through the second stack; a dummy channel structure extending vertically through the second stack; Further equipped with The memory device of claim 11 , wherein the dummy channel structure is between the channel structure and one or more of the through array contact structures along the first lateral direction.

19. the barrier structure comprises a second sub-barrier structure; The memory device of claim 11 , wherein two parallel ends of the second sub-barrier structure are connected to the second sub-barrier structure.

20. the first dielectric layer and the second dielectric layer comprise different materials; 12. The memory device of claim 11, wherein the second dielectric layer and the third dielectric layer comprise the same material.

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