Array substrate, display device, and method for manufacturing array substrate

Abstract

To suppress the occurrence of a short circuit.SOLUTION: An array substrate 21 includes: a first electrode 27E constituted of a first conductive film 34; a first insulating film 33 disposed on a lower layer side of the first conductive film 34; a first conductivity-induced portion 27Bα formed by making a portion of a semiconductor film 32 disposed on a lower layer side of the first insulating film 33 conductive, the portion not overlapping the first electrode 27E; a second conductivity-induced portion 27Bβ formed by making a portion of the semiconductor film 32 other than the first conductivity-induced portion 27Bα conductive, the portion not overlapping the first electrode 27E; a first semiconductor portion 27Dα constituted of a portion of the semiconductor film 32 overlapping the first electrode 27E; and an intervening portion 38 constituted of a portion of the first conductive film 34 other than the first electrode 27E or a part of the first insulating film 33, the intervening portion being disposed between the first conductivity-induced portion 27Bα and the second conductivity-induced portion 27Bβ.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The technology disclosed in this specification relates to an array substrate, a display device, and a method for manufacturing an array substrate.

Background Art

[0002] Conventionally, as an example of a display device including an array substrate, the one described in Patent Document 1 below is known. In the display device described in Patent Document 1, in a pixel region on a substrate, either a transparent oxide layer or a metal layer is formed as an upper layer, and an insulating film and a conductive layer are sequentially laminated thereon. The conductive layer has a gate electrode of a thin film transistor connected to a gate signal line. The metal layer constitutes a source signal line. In the transparent oxide layer, regions other than at least a channel region portion directly under the gate electrode are made conductive, and a source region portion of a thin film transistor connected to the source signal line at this conductive portion, a pixel electrode, and a drain region portion of the thin film transistor connected to this pixel electrode are constituted.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As described above, in the display device described in Patent Document 1, a source region portion, a pixel electrode, and a drain region portion are constituted by the conductive portion of the transparent oxide layer. For this reason, when the pixel arrangement pitch becomes narrow with the increase in the definition of the display device, for example, there is a risk that two adjacent source region portions constituting adjacent pixels may short-circuit due to film residue that may occur when patterning the transparent oxide layer.

[0005] The technology described in this specification has been completed based on the above circumstances, and aims to suppress the occurrence of short circuits.

Means for Solving the Problems

[0006] (1) The array substrate related to the technology described in this specification includes a first electrode made of a first conductive film, a first insulating film disposed on the lower layer side with respect to the first conductive film, and a first conductor portion formed by making conductive a portion of the semiconductor film disposed on the lower layer side with respect to the first insulating film that does not overlap with the first electrode, a second conductor portion formed by making conductive a portion of the semiconductor film that does not overlap with the first electrode and is different from the first conductor portion, a first semiconductor portion formed by a portion of the semiconductor film that overlaps with the first electrode, and an intervening portion formed by a portion of the first conductive film that is different from the first electrode or a part of the first insulating film and is disposed between the first conductor portion and the second conductor portion.

[0007] (2) Further, in addition to the above (1), the array substrate has a first insulating portion that overlaps with the first electrode and the first semiconductor portion, and the intervening portion may be formed by a portion of the first insulating film that is different from the first insulating portion.

[0008] (3) Further, in addition to the above (2), the semiconductor film is made of an oxide semiconductor material, is disposed on the upper layer side with respect to the first conductive film, and includes a second insulating film containing a reducing agent. The second insulating film is in contact with the first conductor portion and the second conductor portion. The first insulating film has a second insulating portion that does not overlap with the first electrode and the first semiconductor portion and is continuous with the first insulating portion. It may include a first high-resistance portion formed by a portion of the semiconductor film that overlaps with the second insulating portion, is continuous with the first conductor portion, and has a higher resistance than the first conductor portion.

[0009] (4) Further, in addition to the above (3), in the array substrate, the distance from the end on the side of the first conductor-forming portion to the end on the side of the second conductor-forming portion of the intervening portion may be larger than the distance from the end on the side of the first semiconductor portion to the end on the side of the first conductor-forming portion in the first high-resistance portion.

[0010] (5) Further, in addition to any one of the above (2) to (4), the array substrate includes a first wiring formed of the first conductive film, extending along a first direction and including the first electrode, and a first linear insulating portion formed of the first insulating film, extending along the first direction and overlapping the first wiring and including the first insulating portion. The first conductor-forming portion and the second conductor-forming portion intersect the first wiring and the first linear insulating portion, and the intervening portion may be continuous with the first linear insulating portion.

[0011] (6) Further, in addition to the above (5), the array substrate includes a second wiring formed of the first conductive film, arranged at a position spaced apart from the first wiring in a second direction intersecting the first direction and extending along the first direction, and a second linear insulating portion formed of the first insulating film, extending along the first direction and overlapping the second wiring. The intervening portion may be continuous with the second linear insulating portion.

[0012] (7) Further, in addition to the above (1), the first conductive film is made of a metal material, and the intervening portion may be formed of a portion of the first conductive film different from the first electrode.

[0013] (8) Further, in addition to any one of (1) to (7) above, the array substrate includes a second insulating film disposed on the upper layer side with respect to the first conductive film, and a second conductive film disposed on the upper layer side with respect to the second insulating film, and includes a third wiring partially overlapping the first conductor portion, and a fourth wiring formed of a portion of the second conductive film different from the third wiring and partially overlapping the second conductor portion. In the second insulating film, a first contact hole connecting the third wiring and the first conductor portion is provided at a position overlapping both the third wiring and the first conductor portion, and in the second insulating film, a second contact hole connecting the fourth wiring and the second conductor portion may be provided at a position overlapping both the fourth wiring and the second conductor portion.

[0014] (9) Further, in addition to (8) above, the third wiring and the fourth wiring are parallel to each other, the first conductor portion has a first inclined portion inclined with respect to the third wiring and the fourth wiring, the second conductor portion has a second inclined portion parallel to the first inclined portion, and the intervening portion may have a third inclined portion parallel to the first inclined portion and the second inclined portion.

[0015] (10) Further, in addition to (8) or (9) above, the first conductor portion may be partially overlapped with respect to the first contact hole so as not to overlap with a portion of the first contact hole on the second conductor portion side.

[0016] (11) A display device related to the technology described in this specification includes the array substrate according to any one of (1) to (10) above, and a counter substrate disposed to face the array substrate.

[0017] (12) The method for manufacturing an array substrate related to the technology described in this specification forms a semiconductor film made of an oxide semiconductor material, and patterns the semiconductor film to provide a first non-conductivized portion, a second non-conductivized portion arranged at an interval from the first non-conductivized portion, and a first semiconductor portion. A first insulating film is formed on the upper layer side of the semiconductor film, a first conductive film is formed on the upper layer side of the first insulating film, and by patterning the first conductive film, a first electrode is provided that overlaps the first semiconductor portion. By patterning the first insulating film, a first insulating portion that overlaps the first electrode and the first semiconductor portion and an intervening portion arranged between the first non-conductivized portion and the second non-conductivized portion are provided. A second insulating film containing a reducing agent is formed on the upper layer side of the first conductive film, and by bringing the second insulating film into contact with the first non-conductivized portion and the second non-conductivized portion, the first non-conductivized portion and the second non-conductivized portion are conductivized to become a first conductivized portion and a second conductivized portion, respectively.

[0018] (13) Further, in addition to the above (12), the method for manufacturing the array substrate provides a second insulating portion that is non-overlapping with the first electrode and the first semiconductor portion and is continuous with the first insulating portion by patterning the first insulating film. By patterning the semiconductor film, a third non-conductivized portion that overlaps the second insulating portion and is continuous with the first non-conductivized portion is provided. When the second insulating film is formed, the third non-conductivized portion may become a first high-resistance portion that is higher in resistance than the first conductivized portion.

[0019] (14) Further, in addition to the above (13), after patterning the first conductive film, the first insulating film may be patterned.

[0020] (15) The manufacturing method of the array substrate related to the technology described in this specification forms a semiconductor film, patterns the semiconductor film, thereby providing a first non-conductive portion, a second non-conductive portion arranged at an interval from the first non-conductive portion, and a first semiconductor portion. A first insulating film is formed on the upper layer side of the semiconductor film, a first conductive film is formed on the upper layer side of the first insulating film, and by patterning the first conductive film, a first electrode that overlaps the first semiconductor portion and an intervening portion arranged between the first non-conductive portion and the second non-conductive portion are provided. By performing a conductorization process of conductorizing the semiconductor film using the first conductive film as a mask, the first non-conductive portion and the second non-conductive portion that are in a non-overlapping relationship with the first electrode and the intervening portion are conductorized to form a first conductorized portion and a second conductorized portion, respectively.

Advantages of the Invention

[0021] According to the technology described in this specification, the occurrence of short circuits can be suppressed.

Brief Description of the Drawings

[0022]

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Embodiments for Carrying Out the Invention

[0023] <Embodiment 1> Embodiment 1 will be described with reference to FIGS. 1 to 17. In this embodiment, a goggle-type head-mounted display (HMD) 10HMD and a liquid crystal display device (display device) 10 used therefor are exemplified. Note that the X-axis, Y-axis, and Z-axis are shown in part of each drawing, and the directions of the respective axes are drawn so as to be the directions shown in each drawing.

[0024] The appearance of the goggle-type head-mounted display 10HMD will be described with reference to FIG. 1. As shown in FIG. 1, the head-mounted display 10HMD includes a head-mounted device 10HMDa that is worn on the head 10HD of the user. The head-mounted device 10HMDa surrounds both eyes of the user.

[0025] The configuration of the head-mounted device 10HMDa will be described with reference to FIG. 2. As shown in FIG. 2, the head-mounted device 10HMDa incorporates at least a liquid crystal display device 10 for displaying an image and a lens unit 10RE for forming an image of the image displayed on the liquid crystal display device 10 on the user's eyeball 10EY. The liquid crystal display device 10 includes at least a liquid crystal panel (display device) 11 and a backlight device (lighting device) 12 for irradiating light onto the liquid crystal panel 11. The main surface of the liquid crystal panel 11 on the side of the lens unit 10RE serves as a display surface 11DS for displaying an image. The lens unit 10RE is arranged to be interposed between the liquid crystal display device 10 and the user's eyeball 10EY. The lens unit 10RE imparts a refracting action to light. By adjusting the focal length of the lens unit 10RE, the user can recognize that the image formed on the retina 10EYb via the crystalline lens 10EYa of the eyeball 10EY appears to exist at the position of a virtual display 10VD at a distance L2 from the eyeball 10EY. This distance L2 is much larger than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. As a result, the user can visually recognize an enlarged image, which is a virtual image displayed on the virtual display 10VD having a screen size much larger than the screen size of the liquid crystal display device 10 (for example, from about 0. several inches to several inches) (for example, from several tens of inches to several hundreds of inches).

[0026] Note that it is possible to mount one liquid crystal display device 10 on the head-mounted device 10HMDa and display a right-eye image and a left-eye image on the liquid crystal display device 10. Alternatively, it is also possible to mount two liquid crystal display devices 10 on the head-mounted device 10HMDa and display a right-eye image on one liquid crystal display device 10 and a left-eye image on the other liquid crystal display device 10, respectively. Further, the head-mounted device 10HMDa may be provided with earphones or the like that are applied to the user's ears to emit sound.

[0027] The configuration of the liquid crystal panel 11 provided in the liquid crystal display device 10 will be described with reference to FIG. 3 and the like. Note that the configuration of the backlight device 12 is as known, and includes, for example, a light source such as an LED and an optical member that converts light from the light source into planar light by imparting an optical action to the light. As shown in FIG. 3, the liquid crystal panel 11 has a rectangular shape as a whole when viewed in a plane. In the liquid crystal panel 11, the central portion on the screen side is a display area AA where an image is displayed. In the liquid crystal panel 11, the frame-shaped outer peripheral side portion surrounding the display area AA on the screen is a non-display area NAA where an image is not displayed. The range surrounded by the dashed-dotted line in FIG. 3 is the display area AA. Note that since the liquid crystal panel 11 according to the present embodiment is used in the above-described head-mounted display 10HMD, it has extremely high definition, and its pixel density is, for example, about 1000 ppi or more.

[0028] As shown in FIG. 3, the liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. Of the pair of substrates 20 and 21, the one arranged on the front side is the counter substrate (second substrate, CF substrate) 20, and the one arranged on the back side is the array substrate (first substrate, active matrix substrate) 21. The counter substrate 20 and the array substrate 21 are each formed by laminating various films on the inner surface side of glass substrates 20GS and 21GS that are substantially transparent and have excellent light transmittance. The substrates 20GS and 21GS contain, for example, non-alkali glass as a main material. The array substrate 21 is larger than the counter substrate 20, and a part of it protrudes laterally with respect to the counter substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 has a configuration in which a plurality of wiring patterns are formed on a base material having insulating properties and flexibility. One end side of the flexible substrate 13 is connected to the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0029] In the non-display area NAA of the liquid crystal panel 11, as shown in FIG. 3, a circuit section (peripheral circuit section) 14 is provided. The circuit section 14 includes a first circuit section 14A and a second circuit section 14B. A pair of the first circuit sections 14A are arranged so as to sandwich the display area AA from both sides in the X-axis direction. The first circuit section 14A is provided in a strip-shaped range extending along the Y-axis direction. The first circuit section 14A is for supplying a scanning signal to each of the gate wirings 25 and 29 described later, and is monolithically provided on the array substrate 21. The first circuit section 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 14A includes a shift register circuit that outputs a scanning signal at a predetermined timing, a buffer circuit for amplifying the scanning signal, and the like. The second circuit section 14B is arranged at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit section 14B is provided in a strip-shaped range extending along the X-axis direction. The second circuit section 14B is for supplying an image signal (data signal) to the source wiring 26 described later, and is monolithically provided on the array substrate 21. The second circuit section 14B includes an SSD (Source Shared Driving) circuit and the like. The second circuit section 14B has a switch function and the like for distributing the image signal supplied by the flexible substrate 13 to each source wiring 26. Similar to the first circuit section 14A, the second circuit section 14B may be arranged to overlap the counter substrate 20.

[0030] Next, the schematic cross-sectional configuration of the liquid crystal panel 11 will be described with reference to FIG. 4. As shown in FIG. 4, a pair of substrates 20 and 21 are arranged to face each other with a space therebetween in the Z-axis direction, which is the normal direction of the main surfaces of the substrates 20 and 21. Between the pair of substrates 20 and 21, at least a liquid crystal layer 22 and a seal portion 23 for sealing (sealing) the liquid crystal layer 22 are interposed. The liquid crystal layer 22 contains liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. The seal portion 23 has a rectangular frame shape (endless loop shape) as viewed in plan as a whole, and surrounds the liquid crystal layer 22 over the entire circumference in the non-display area NAA. A gap (cell gap) corresponding to the thickness of the liquid crystal layer 22 is maintained by this seal portion 23. Polarizing plates 24 are attached to the outer surface sides of the pair of substrates 20 and 21, respectively.

[0031] The outline of the pixel array in the display area AA of the array substrate 21 will be described with reference to FIG. 5. On the inner surface side of the display area AA of the array substrate 21, as shown in FIG. 5, a plurality of lower-layer gate wirings (lower-layer scanning wirings) 25, upper-layer gate wirings (first wiring, second wiring, upper-layer scanning wirings) 29, and source wirings (third wiring, fourth wiring, image wirings) 26 are arranged respectively. Both the lower-layer gate wiring 25 and the upper-layer gate wiring 29 extend along the X-axis direction (first direction) in a form that crosses the display area AA, and are arranged overlapping each other. The upper-layer gate wiring 29 has a narrower line width than the lower-layer gate wiring 25. The both side edges of the lower-layer gate wiring 25 protrude on both sides in the Y-axis direction with respect to the both side edges of the upper-layer gate wiring 29. Note that the lower-layer gate wiring 25 and the upper-layer gate wiring 29 may be arranged such that their centers in the width direction (Y-axis direction) coincide, or may be arranged with their centers shifted. The lower-layer gate wiring 25 and the upper-layer gate wiring 29 are arranged side by side at intervals in the Y-axis direction. A plurality of the lower-layer gate wirings 25 and the upper-layer gate wirings 29 are supplied with the scanning signals output from the above-described first circuit portion 14A. Note that the lower-layer gate wiring 25 and the upper-layer gate wiring 29 in an overlapping relationship are supplied with the scanning signals from the first circuit portion 14A at the same timing and are always at the same potential. The source wiring 26 extends along the Y-axis direction (second direction intersecting the first direction) in a form that crosses the display area AA, and intersects the lower-layer gate wiring 25 and the upper-layer gate wiring 29. A plurality of the source wirings 26 are arranged at intervals in the X-axis direction. Therefore, the plurality of lower-layer gate wirings 25 and upper-layer gate wirings 29 and the plurality of source wirings 26 form a lattice pattern when viewed in a plane. The image signals output from the above-described second circuit portion 14B are distributed to the source wirings 26.

[0032] In the vicinity of the intersection of the two gate wirings 25 and 29 and the source wiring 26, as shown in FIG. 5, a TFT (switching element) 27 and a pixel electrode 28 are provided. The TFTs 27 and the pixel electrodes 28 are regularly arranged in plural along the X-axis direction and the Y-axis direction. The TFT 27 has at least a lower-layer gate electrode 27A, a source region (first conductor portion, second conductor portion) 27B, a drain region 27C, a semiconductor portion (first semiconductor portion) 27D, and an upper-layer gate electrode (first electrode) 27E. The lower-layer gate electrode 27A is formed of a part of the lower-layer gate wiring 25. The upper-layer gate electrode 27E is formed of a part of the upper-layer gate wiring 29. The source region 27B is connected to the source wiring 26. The drain region 27C is connected to the pixel electrode 28. The source region 27B and the drain region 27C are in a relationship of intersecting with the respective gate wirings 26 and 29. The semiconductor portion 27D is connected to the source region 27B and the drain region 27C, respectively, and is disposed so as to overlap a part of the lower-layer gate electrode 27A and the entire upper-layer gate electrode 27E. Thus, the TFT 27 according to the present embodiment has a double-gate structure in which the semiconductor portion 27D is sandwiched between the two upper and lower gate electrodes 27A and 27E. When such a TFT 27 is driven based on a scanning signal supplied from the lower-layer gate wiring 25 and the upper-layer gate wiring 29 to the lower-layer gate electrode 27A and the upper-layer gate electrode 27E, two channel regions are formed in the semiconductor portion 27D, one on the upper layer side and the other on the lower layer side. The image signal supplied from the source wiring 26 to the source region 27B is supplied to the drain region 27C through the channel region of the semiconductor portion 27D, and the pixel electrode 28 is charged to a potential based on the image signal. Thus, the generation of two channel regions in the semiconductor portion 27D increases the charge mobility. The pixel electrode 28 has a longitudinal shape with the Y-axis direction as the longitudinal direction.

[0033] Next, various films laminated on the glass substrate 21GS of the array substrate 21 will be described in detail with reference to FIG. 6. As shown in FIG. 6, on the glass substrate 21GS of the array substrate 21, in order from the lower layer side (glass substrate 21GS side), a base coat film 30, a first metal film, a lower layer side gate insulating film 31, a semiconductor film 32, an upper layer side gate insulating film (first insulating film) 33, a second metal film (first conductive film) 34, a first interlayer insulating film (second insulating film) 35, a third metal film (second conductive film), a planarization film 36, and a first transparent electrode film are at least laminated and formed (see FIGS. 9 and 15 for the semiconductor film 32 and see FIG. 16 for the second metal film 34). Note that an alignment film for aligning liquid crystal molecules contained in the liquid crystal layer 22 is provided on the innermost surface of the array substrate 21 facing the liquid crystal layer 22.

[0034] The first metal film, the second metal film 34, and the third metal film are all made of a single-layer film of one type of metal material or a laminated film or alloy made of different types of metal materials to have conductivity. As shown in FIG. 6, the first metal film constitutes the lower layer side gate wiring 25, the lower layer side gate electrode 27A, and the like. The second metal film 34 constitutes the upper layer side gate wiring 29, the upper layer side gate electrode 27E, and the like (see FIG. 16). The third metal film constitutes the source wiring 26 and the like. The first transparent electrode film is made of a transparent electrode material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The first transparent electrode film constitutes the pixel electrode 28 and the like.

[0035] The semiconductor film 32 is made of an oxide semiconductor material (see FIGS. 9 and 15). Specifically, the semiconductor film 32 is made of, for example, an oxide thin film containing indium (In), gallium (Ga), and zinc (Zn), which is a kind of oxide semiconductor. The oxide thin film containing indium (In), gallium (Ga), and zinc (Zn) is amorphous or crystalline. The oxide semiconductor material of the semiconductor film 32 has the characteristic that its resistance value is high in a state where no voltage is applied (off state) compared with a silicon semiconductor material. Also, the oxide semiconductor material of the semiconductor film 32 has a high electron mobility compared with an amorphous silicon semiconductor material.

[0036] As shown in FIG. 6, the array substrate 21 according to this embodiment has a semiconductor pattern portion 37 formed by patterning a semiconductor film 32. This semiconductor pattern portion 37 constitutes the source region 27B, drain region 27C, semiconductor portion 27D, etc. of the TFT 27. A part of the semiconductor pattern portion 37 is made conductive (low resistance). Among the semiconductor pattern portion 37, the non-conductive portion (non-conductivized portion, non-low resistance portion) constitutes the semiconductor portion 27D, etc. Among the semiconductor pattern portion 37, the conductive portion (conductivized portion, low resistance portion) constitutes the source region 27B and drain region 27C, etc. In the cross-sectional views such as FIG. 6, the conductive portion in the semiconductor pattern portion 37 is shown hatched. The non-conductive portion in the semiconductor pattern portion 37 allows the movement of charges only under specific conditions (when a scanning signal is supplied to each gate electrode 27A, 27E). That is, the non-conductive portion functions as a channel region under specific conditions. The non-conductive portion in the semiconductor pattern portion 37 has a sheet resistance of, for example, 10 6 Ω / sq to 10 7 Ω / sq or so. On the other hand, the non-conductive portion in the semiconductor pattern portion 37 always allows the movement of charges and functions as a conductor. The conductive portion in the semiconductor pattern portion 37 has a sheet resistance of, for example, 10 3 Ω / sq or so. That is, the conductive portion in the semiconductor pattern portion 37 has a resistivity that is about 1 / 1000 to 1 / 10000 lower than that of the non-conductive portion.

[0037] The base coat film 30, lower layer side gate insulating film 31, upper layer side gate insulating film 33, and first interlayer insulating film 35 are all SiO2 (silicon oxide, silicon dioxide) or SiN xIt is made of an inorganic material (inorganic resin material) such as silicon nitride. The base coat film 30 is directly laminated on the glass substrate 21GS and is located on the lower layer side of the first metal film. The lower layer gate insulating film 31 is located on the upper layer side of the first metal film and on the lower layer side of the semiconductor film 32. The lower layer gate insulating film 31 keeps the lower layer gate electrode 27A and the semiconductor part 27D in an insulated state. The upper layer gate insulating film 33 is located on the upper layer side of the semiconductor film 32 and on the lower layer side of the second metal film 34. The upper layer gate insulating film 33 keeps the semiconductor part 27D and the upper layer gate electrode 27E in an insulated state. The first interlayer insulating film 35 is located on the upper layer side of the second metal film 34 and on the lower layer side of the third metal film. The first interlayer insulating film 35 keeps the upper layer gate electrode 27E and the source wiring 26 in an insulated state. In this embodiment, the first interlayer insulating film 35 is made of a laminated film of SiO2 or SiN x or a laminated film of SiO2 and SiN x and contains, for example, H2 (hydrogen) as a reducing agent. The reason why the first interlayer insulating film 35 contains H2 is that the materials used for film formation include hydride gases such as SiH4 (silane gas), TEOS (Tetraethyl orthosilicate), and NH3. The planarization film 36 is made of an organic material (organic resin material) such as PMMA (acrylic resin). The planarization film 36 made of an organic material has a larger film thickness than any of the base coat film 30, the lower layer gate insulating film 31, the upper layer gate insulating film 33, and the first interlayer insulating film 35 made of an inorganic material. Specifically, the film thicknesses of the base coat film 30, the lower layer gate insulating film 31, the upper layer gate insulating film 33, and the first interlayer insulating film 35 made of an inorganic material are, for example, on the order of several tens of nm to several hundreds of nm, while the film thickness of the planarization film 36 is, for example, on the order of 1 μm to 3 μm. The planarization film 36 keeps the source wiring 26 and the pixel electrode 28 in an insulated state.

[0038] In addition, when the display mode of the liquid crystal panel 11 is, for example, the FFS (Fringe Field Switching) mode or the like, a second interlayer insulating film is formed on the upper layer side of the first transparent electrode film, and a second transparent electrode film is formed on the upper layer side of the second interlayer insulating film on the array substrate 21. In this case, either one of the first transparent electrode film and the second transparent electrode film constitutes the pixel electrode 28, and the other remaining one constitutes a common electrode having a common potential. On the other hand, when the display mode of the liquid crystal panel 11 is, for example, the VA (Vertical Alignment) mode, the TN (Twisted Nematic) mode, or the like, a counter electrode is provided on the counter substrate 20.

[0039] Here, the configuration of the TFT27 will be described in detail. As shown in FIG. 5, the semiconductor pattern portion 37 that constitutes the source region 27B, drain region 27C, semiconductor portion 27D, etc. of the TFT27 has an L shape as a whole, and is composed of a portion extending along the X-axis direction and a portion extending along the Y-axis direction. Most of the portion of the semiconductor pattern portion 37 extending along the X-axis direction overlaps with the pixel electrode 28 adjacent to the upper side in FIG. 5 in the Y-axis direction with respect to the pixel electrode 28 to be connected. One end of the portion of the semiconductor pattern portion 37 extending along the X-axis direction overlaps with the source wiring 26, while the other end is arranged near the substantially central position in the X-axis direction of the pixel electrode 28 with which it overlaps. One end of the portion of the semiconductor pattern portion 37 extending along the Y-axis direction is continuous with the other end of the portion extending along the X-axis direction, and the intermediate portion up to the other end is arranged in a manner crossing both gate wirings 26 and 29. The portion of the semiconductor pattern portion 37 extending along the Y-axis direction on the other end side of both gate wirings 26 and 29 overlaps with the pixel electrode 28 to be connected. The entire region of the portion of the semiconductor pattern portion 37 extending along the X-axis direction and a part of the portion extending along the Y-axis direction (the portion from one end to the upper layer side gate wiring 29) constitute the source region 27B. The portion of the semiconductor pattern portion 37 overlapping with the upper layer side gate wiring 29 constitutes the semiconductor portion 27D. A part of the portion of the semiconductor pattern portion 37 extending along the Y-axis direction (the portion from the other end to the upper layer side gate wiring 29) constitutes the drain region 27C.

[0040] Between the source region 27B included in the semiconductor pattern portion 37 and the source wiring 26 to be connected, as shown in FIG. 6, a source contact hole CH1 for connecting the source region 27B and the source wiring 26 is formed to open in the first interlayer insulating film 35. The source contact hole CH1 is disposed at a position overlapping the source region 27B and the source wiring 26 in the first interlayer insulating film 35. Between the drain region 27C included in the semiconductor pattern portion 37 and the pixel electrode 28 to be connected, as shown in FIG. 6, a drain contact hole CH2 for connecting the drain region 27C and the pixel electrode 28 is formed to open in the first interlayer insulating film 35 and the planarization film 36. The drain contact hole CH2 is disposed at a position overlapping the drain region 27C and the pixel electrode 28 in the first interlayer insulating film 35 and the planarization film 36.

[0041] As shown in FIG. 6, the upper gate electrode 27E of the TFT27 is made narrower than the lower gate electrode 27A. Both side edges of the lower gate electrode 27A protrude on both sides in the Y-axis direction with respect to both side edges of the upper gate electrode 27E. Note that the lower gate electrode 27A and the upper gate electrode 27E may be arranged such that their centers in the width direction (Y-axis direction) coincide with each other, or they may be arranged with their centers shifted from each other. The lower gate insulating film 31 interposed between the first metal film constituting the lower gate electrode 27A and the semiconductor film 32 constituting the semiconductor portion 27D and the like is disposed substantially in a solid state. On the other hand, the upper gate insulating film 33 interposed between the second metal film constituting the upper gate electrode 27E and the semiconductor film 32 constituting the semiconductor portion 27D and the like is selectively provided at a position overlapping the lower gate wiring 25 and the upper gate wiring 29.

[0042] Specifically, as shown in FIGS. 5 and 6, the upper-layer gate insulating film 33 has a linear insulating portion 33A that extends along the X-axis direction and is parallel to the lower-layer gate wiring 25 and the upper-layer gate wiring 29. The linear insulating portion 33A may be arranged in a strip-shaped range that is wider than the upper-layer gate wiring 29 and narrower than the lower-layer gate wiring 25. Among the linear insulating portion 33A, the portion that overlaps with the upper-layer gate electrode 27E is defined as the first insulating portion (overlapping insulating portion) 33B. The first insulating portion 33B is a portion within the range of the same width as the upper-layer gate electrode 27E among the linear insulating portion 33A. Among the linear insulating portion 33A, the portion that does not overlap with the upper-layer gate electrode 27E and is continuous with the first insulating portion 33B is defined as the non-overlapping insulating portion 33C. The non-overlapping insulating portion 33C is a portion of the linear insulating portion 33A that protrudes laterally in both directions with respect to the Y-axis direction with respect to the upper-layer gate electrode 27E. A pair of non-overlapping insulating portions 33C is provided in a form continuous with both side edges of the first insulating portion 33B. The width dimension of the non-overlapping insulating portion 33C, that is, the protruding dimension from the side edge of the first insulating portion 33B, is, for example, about 0.5 μm to 2 μm. Hereinafter, when distinguishing between the pair of non-overlapping insulating portions 33C, the non-overlapping insulating portion 33C on the right side (source region 27B side) of FIG. 6 is referred to as the "first non-overlapping insulating portion (second insulating portion, source-side non-overlapping insulating portion)", and the symbol is appended with the subscript "α", and the non-overlapping insulating portion 33C on the left side (drain region 27C side) of FIG. 6 is referred to as the "second non-overlapping insulating portion (third insulating portion, drain-side non-overlapping insulating portion)", and the symbol is appended with the subscript "β". When collectively referring to them without distinction, no subscript is appended to the symbol.

[0043] Of the semiconductor pattern portion 37, the portion that overlaps the above-described non-overlapping insulating portion 33C is a high-resistance portion 27F that has a higher resistance than the source region 27B and the drain region 27C, as shown in FIG. 6. In FIG. 6, the high-resistance portion 27F is illustrated as a hatched pattern with a lower density than the source region 27B and the drain region 27C. The non-overlapping insulating portion 33C of the upper-layer gate insulating film 33 is in contact with the high-resistance portion 27F, and the first interlayer insulating film 35 does not directly contact it. On the other hand, the source region 27B and the drain region 27C of the semiconductor pattern portion 37 do not overlap with the upper-layer gate insulating film 33 (linear insulating portion 33A) and are in contact with the upper-layer first interlayer insulating film 35. Thus, since the source region 27B and the drain region 27C of the semiconductor film 32 made of an oxide semiconductor material are in contact with the first interlayer insulating film 35 containing a reducing agent, a reduction reaction occurs in which oxygen is extracted by the reducing agent of the first interlayer insulating film 35. As a result, the source region 27B and the drain region 27C are being made conductive. In contrast, although the high-resistance portion 27F does not directly contact the first interlayer insulating film 35, it is in contact with the source region 27B and the drain region 27C that are continuous with the high-resistance portion 27F. Therefore, a reduction reaction also occurs in the high-resistance portion 27F in which oxygen is extracted by the reducing agent via the source region 27B and the drain region 27C. At this time, the degree of reduction of the high-resistance portion 27F is lower than the degree of reduction of the source region 27B and the drain region 27C. As a result, although the high-resistance portion 27F is made conductive to a certain extent, it has a higher resistance than the source region 27B and the drain region 27C. Here, when a channel region is generated in the first semiconductor portion 27Dα as the TFT 27 is driven, the image signal supplied to the source region 27B is transmitted through the channel region of the semiconductor portion 27D via one high-resistance portion 27F. Then, the image signal is transmitted from the channel region of the semiconductor portion 27D to the drain region 27C via the other high-resistance portion 27F. Thus, since the high-resistance portion 27Fα is interposed between the source region 27Bα and the channel region of the semiconductor portion 27Dα and between the drain region 27C and the channel region of the semiconductor portion 27Dα, respectively, the generation of hot carrier injection is preferably suppressed.

[0044] Thus, although the high-resistance portion 27F is part of the conductor-formed portion in the semiconductor pattern portion 37, the conductor formation is suppressed so that the sheet resistance is higher than that of the source region 27B and the drain region 27C. A pair of high-resistance portions 27F are provided so as to protrude laterally in the Y-axis direction from both ends in the Y-axis direction in the semiconductor portion 27D. The width dimension of the high-resistance portion 27F, that is, the protruding dimension from the end in the Y-axis direction in the semiconductor portion 27D, is substantially the same as the width dimension of the non-overlapping insulating portion 33C, and is, for example, about 0.5 μm to 2 μm. One of the pair of high-resistance portions 27F is continuous with the source region 27B, and the other high-resistance portion 27F is continuous with the drain region 27C. Hereinafter, when distinguishing between the pair of high-resistance portions 27F, one high-resistance portion 27F continuous with the source region 27B is designated as the "first high-resistance portion (source-side high-resistance portion)" and the suffix "α" is added to its symbol, and the other high-resistance portion 27F continuous with the drain region 27C is designated as the "second high-resistance portion (drain-side high-resistance portion)" and the suffix "β" is added to its symbol. When they are collectively referred to without distinction, no suffix is added to the symbol. Thus, the semiconductor portion 27D is indirectly connected to the source region 27B and the drain region 27C via the pair of high-resistance portions 27F.

[0045] Hereinafter, the configuration of the array substrate 21 shown in FIG. 5 is distinguished as follows. In FIG. 5, three TFTs 27 and source wirings 26 arranged at intervals in the X-axis direction are illustrated. Among these, the central TFT 27 and source wiring 26 are designated as the "first TFT" and "first source wiring", respectively, and the subscript "α" is attached to their reference numerals. The right-side TFT 27 and source wiring 26 are designated as the "second TFT" and "second source wiring", respectively, and the subscript "β" is attached to their reference numerals. The lower-layer gate electrode 27A, source region 27B, drain region 27C, semiconductor portion 27D, and upper-layer gate electrode 27E constituting the first TFT 27α are respectively designated as the "first lower-layer gate electrode", "first source region (first conductor portion)", "first drain region", "first semiconductor portion", and "first upper-layer gate electrode", and the subscript "α" is attached to their respective reference numerals. The lower-layer gate electrode 27A, source region 27B, drain region 27C, semiconductor portion 27D, and upper-layer gate electrode 27E constituting the second TFT 27β are respectively designated as the "second lower-layer gate electrode", "second source region (second conductor portion)", "second drain region", "second semiconductor portion", and "second upper-layer gate electrode", and the subscript "β" is attached to their respective reference numerals. Also, the source contact hole CH1 and drain contact hole CH2 provided in the first TFT 27α are designated as the "first source contact hole (first contact hole)" and "first drain contact hole", respectively, and the subscript "α" is attached to their reference numerals. The source contact hole CH1 and drain contact hole CH2 provided in the second TFT 27β are designated as the "second source contact hole (second contact hole)" and "second drain contact hole", respectively, and the subscript "β" is attached to their reference numerals. Regarding each of the above-described configurations, when they are generically referred to without distinction, no subscript is attached to the reference numerals of each configuration.

[0046] In addition, FIG. 5 illustrates three lower-layer gate wirings 25, upper-layer gate wirings 29, and linear insulating portions 33A that are arranged at intervals in the Y-axis direction. Among these, the central lower-layer gate wiring 25, upper-layer gate wiring 29, and linear insulating portion 33A are designated as the "first lower-layer gate wiring, first upper-layer gate wiring (first wiring), and first linear insulating portion," and subscript "α" is attached to their reference numerals respectively. The upper lower-layer gate wiring 25, upper-layer gate wiring 29, and linear insulating portion 33A are designated as the "second lower-layer gate wiring, second upper-layer gate wiring (second wiring), and second linear insulating portion," and subscript "β" is attached to their reference numerals respectively. For each of the above-described configurations, when they are generically referred to without distinction, no subscript is attached to their reference numerals.

[0047] Now, as shown in FIGS. 5 and 7, an array substrate 21 according to the present embodiment is provided with a source intervening portion (intervening portion, first intervening portion) 38 disposed between a first source region 27Bα and a second source region 27Bβ. A space is provided between the first source region 27Bα and the second source region 27Bβ in the X-axis direction, and the source intervening portion 38 is disposed in this spaced region. Specifically, a space of about several μm is provided between an end portion (a portion overlapping with the first source contact hole CH1α) connected to the first source wiring 26α in the first source region 27Bα and a bent portion in the second source region 27Bβ. And the source intervening portion 38 is composed of a part of the upper gate insulating film 33 (a part different from the first insulating portion 33B). Here, in the manufacturing process of the array substrate 21, when patterning the semiconductor film 32, as shown in FIGS. 8 and 9, there is a possibility that film residue may occur on the semiconductor film 32. When film residue occurs, the first source region 27Bα and the second source region 27Bβ may be mechanically connected by the film residue portion 32R of the semiconductor film 32. Even in that case, since the source intervening portion 38 composed of a part of the upper gate insulating film 33 is disposed between the first source region 27Bα and the second source region 27Bβ, it overlaps with the film residue portion 32R that is mechanically continuous between the first source region 27Bα and the second source region 27Bβ. Therefore, the film residue portion 32R of the semiconductor film 32 can be prevented from being conductorized by being masked from the first interlayer insulating film 35 by the overlapping source intervening portion 38. In other words, since the source intervening portion 38 intervenes between the film residue portion 32R of the semiconductor film 32 and the first interlayer insulating film 35, the film residue portion 32R is prevented from contacting the first interlayer insulating film 35, so that the film residue portion 32R is prevented from being reduced by the reducing agent of the first interlayer insulating film 35. As a result, even when film residue occurs in the semiconductor film 32, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non-connected state is increased.Therefore, it is difficult for a short - circuit situation to occur between the first source wiring 26α connected to the first source region 27Bα through the first source contact hole CH1α of the first interlayer insulating film 35 and the second source wiring 26β connected to the second source region 27Bβ through the second source contact hole CH1β of the first interlayer insulating film 35. As a result, it is difficult to visually recognize a linear display defect caused by a short - circuit between the first source wiring 26α and the second source wiring 26β.

[0048] As shown in FIG. 8, the source intervening portion 38 has a dimension (width dimension) in the X - axis direction that is smaller than the interval in the X - axis direction provided between the first source region 27Bα and the second source region 27Bβ. The dimension in the X - axis direction of the source intervening portion 38 is the distance D1 from the end on the first source region 27Bα side (left side in FIG. 8) to the end on the second source region 27Bβ side (right side in FIG. 8) in the source intervening portion 38. However, the source intervening portion 38 has a dimension in the X - axis direction that is larger than the dimension (width dimension) in the Y - axis direction of the first high - resistance portion 27Fα. The dimension in the Y - axis direction of the first high - resistance portion 27Fα is the distance D2 from the end on the first semiconductor portion 27Dα side (lower side in FIG. 8) to the end on the first source region 27Bα side (upper side in FIG. 8) in the first high - resistance portion 27Fα. In the semiconductor film 32, when a remaining film portion 32R that is mechanically continuous between the first source region 27Bα and the second source region 27Bβ is generated, there is a possibility that the portion of the remaining film portion 32R that overlaps the end on the first source region 27Bα side of the source intervening portion 38 and the portion that overlaps the end on the second source region 27Bβ side of the source intervening portion 38 are respectively made conductive. Even in that case, since the distance D1 from the end on the first source region 27Bα side to the end on the second source region 27Bβ side in the source intervening portion 38 is larger than the distance D2 from the end on the first semiconductor portion 27Dα side to the end on the first source region 27Bα side in the first high - resistance portion 27Fα, it is difficult for the entire remaining film portion 32R of the semiconductor film 32 that overlaps the source intervening portion 38 to be made conductive. As a result, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non - connected state becomes higher.

[0049] As shown in FIG. 8, the source intervening portion 38 is configured to be continuous with the linear insulating portion 33A. Specifically, the source intervening portion 38 is provided in a form that extends along the Y-axis direction from a portion adjacent to the intersection with the source wiring 26 among the linear insulating portions 33A extending along the X-axis direction. The source intervening portion 38 has a tapered planar shape, and the width dimension (dimension in the X-axis direction) becomes smaller toward the extending end side. And the source intervening portion 38 is configured such that the extending tip end portion reaches a position beyond the first source region 27Bα and the second source region 27Bβ. That is, the dimension in the Y-axis direction of the source intervening portion 38 is larger than each dimension in the Y-axis direction of the first source region 27Bα and the second source region 27Bβ. In this way, the first source region 27Bα and the second source region 27Bβ will be partitioned over the entire length in the Y-axis direction by the source intervening portion 38. Therefore, the first source region 27Bα and the second source region 27Bβ are highly likely to be kept in an electrically non-connected state by the source intervening portion 38 over the entire length including the portion near the linear insulating portion 33A.

[0050] As shown in FIGS. 5 and 7, an array substrate 21 is provided with a drain intervening portion (intervening portion, second intervening portion) 39 disposed between a first drain region 27Cα and a second drain region 27Cβ. A gap of about several micrometers in the X-axis direction is provided between the first drain region 27Cα and the second drain region 27Cβ, and the drain intervening portion 39 is disposed in this gap region. The drain intervening portion 39 is composed of a part of the upper gate insulating film 33 (a portion different from the first insulating portion 33B). Here, in the manufacturing process of the array substrate 21, when patterning the semiconductor film 32, there is a possibility that film residue may occur on the semiconductor film 32 (see FIGS. 8 and 9). When film residue occurs, the first drain region 27Cα and the second drain region 27Cβ may be mechanically connected by the film residue portion 32R of the semiconductor film 32. Even in this case, since the drain intervening portion 39 composed of a part of the upper gate insulating film 33 is disposed between the first drain region 27Cα and the second drain region 27Cβ, it overlaps with the film residue portion 32R that is mechanically connected to the first drain region 27Cα and the second drain region 27Cβ. Therefore, the film residue portion 32R of the semiconductor film 32 can be prevented from being conductorized by being masked from the first interlayer insulating film 35 by the overlapping drain intervening portion 39. In other words, since the drain intervening portion 39 is interposed between the film residue portion 32R of the semiconductor film 32 and the first interlayer insulating film 35, it is possible to avoid the film residue portion 32R from contacting the first interlayer insulating film 35, so that the film residue portion 32R is prevented from being reduced by the reducing agent of the first interlayer insulating film 35. As a result, even when film residue occurs in the semiconductor film 32, the certainty that the first drain region 27Cα and the second drain region 27Cβ are kept in an electrically non-connected state is increased. Therefore, it is difficult for a situation where a pixel electrode 28 connected to the first drain region 27Cα through the first drain contact hole CH2α of the first interlayer insulating film 35 and the planarizing film 36 and a pixel electrode 28 connected to the second drain region 27Cβ through the second drain contact hole CH2β of the first interlayer insulating film 35 and the planarizing film 36 are short-circuited to occur. As a result, it is difficult to visually recognize a dot-like display defect caused by short-circuiting of two adjacent pixel electrodes 28 in the X-axis direction.

[0051] As shown in FIG. 5, the drain intervening portion 39 has a dimension (width dimension) in the X-axis direction that is smaller than the interval in the X-axis direction provided between the first drain region 27Cα and the second drain region 27Cβ. The dimension in the X-axis direction in the drain intervening portion 39 is the distance from the end on the first drain region 27Cα side (left side in FIG. 5) to the end on the second drain region 27Cβ side (right side in FIG. 5) in the drain intervening portion 39. However, the drain intervening portion 39 has a dimension in the X-axis direction that is larger than the dimension (width dimension) in the Y-axis direction in the second high-resistance portion 27Fβ. The dimension in the Y-axis direction in the second high-resistance portion 27Fβ is the distance from the end on the first semiconductor portion 27Dα side (upper side in FIG. 5) to the end on the first drain region 27Cα side (lower side in FIG. 5) in the second high-resistance portion 27Fβ. In the semiconductor film 32, when a remaining film portion 32R that is mechanically continuous with the first drain region 27Cα and the second drain region 27Cβ is generated, among the remaining film portion 32R, the portion that overlaps the end on the first drain region 27Cα side in the drain intervening portion 39 and the portion that overlaps the end on the second drain region 27Cβ side in the drain intervening portion 39 may each be conductivized. Even in that case, since the distance from the end on the first drain region 27Cα side to the end on the second drain region 27Cβ side in the drain intervening portion 39 is made larger than the distance from the end on the first semiconductor portion 27Dα side to the end on the first drain region 27Cα side in the second high-resistance portion 27Fβ, a situation where the entire remaining film portion 32R of the semiconductor film 32 that overlaps the drain intervening portion 39 is conductivized is less likely to occur. Thereby, the certainty that the first drain region 27Cα and the second drain region 27Cβ are kept in an electrically non-connected state becomes higher.

[0052] As shown in Fig. 5, the drain intervening portion 39 is configured to be continuous with the linear insulating portion 33A. Specifically, the drain intervening portion 39 extends from a portion adjacent to the intersection with the source wiring 26 among the linear insulating portions 33A extending along the X-axis direction, in a direction opposite to the source intervening portion 38 side along the Y-axis direction. That is, the drain intervening portion 39 is arranged substantially the same as the source intervening portion 38 in the X-axis direction. The drain intervening portion 39 has a tapered planar shape, with the width dimension (dimension in the X-axis direction) becoming smaller toward the extending end side. And the extending tip of the drain intervening portion 39 is configured to reach a position beyond the first drain region 27Cα and the second drain region 27Cβ. That is, the dimension of the drain intervening portion 39 in the Y-axis direction is larger than each dimension of the first drain region 27Cα and the second drain region 27Cβ in the Y-axis direction. In this way, the first drain region 27Cα and the second drain region 27Cβ will be partitioned over the entire length in the Y-axis direction by the drain intervening portion 39. Therefore, the certainty that the first drain region 27Cα and the second drain region 27Cβ are kept in an electrically non-connected state by the drain intervening portion 39 over the entire length including the portion near the linear insulating portion 33A is increased.

[0053] This embodiment has the above-described structure, and subsequently, a method for manufacturing the array substrate 21 will be described. As shown in FIG. 10, the method for manufacturing the array substrate 21 includes at least a base coat film forming step S1 of forming a base coat film 30, a first metal film patterning step S2 of forming and patterning a first metal film, a lower gate insulating film forming step S3 of forming a lower gate insulating film 31, a semiconductor film patterning step S4 of forming and patterning a semiconductor film 32, an upper gate insulating film forming step S5 of forming an upper gate insulating film 33, a second metal film patterning step S6 of forming and patterning a second metal film 34, an upper gate insulating film patterning step S7 of patterning the upper gate insulating film 33, a first interlayer insulating film patterning step S8 of forming and patterning a first interlayer insulating film 35, a third metal film patterning step S9 of forming and patterning a third metal film, a planarizing film patterning step S10 of forming and patterning a planarizing film 36, and a first transparent electrode film patterning step S11 of forming and patterning a first transparent electrode film. Hereinafter, among the above-described steps, the second metal film patterning step S6, the upper gate insulating film patterning step S7, and the first interlayer insulating film patterning step S8 will be described in detail.

[0054] Note that the above-mentioned term "patterning" means processing of a film based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed by an exposure apparatus through a photomask having a predetermined opening pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, whereby the film to be processed, that is, patterning is performed.

[0055] After the semiconductor film 32 is patterned through the semiconductor film patterning step S4, the upper layer side gate insulating film forming step S5 and the second metal film patterning step S6 are successively performed. Note that, when the semiconductor film patterning step S4 is performed, the entire semiconductor pattern portion 37 of the patterned semiconductor film 32 is not made conductive (see FIG. 11). When the upper layer side gate insulating film forming step S5 and the second metal film patterning step S6 are successively performed, as shown in FIG. 11, the upper layer side gate insulating film 33 and the second metal film 34 are successively and continuously formed on the upper layer side of the semiconductor film 32. In the second metal film patterning step S6, a first photoresist film R1 made of a photosensitive material is formed on the upper layer side of the second metal film 34, and the first photoresist film R1 is exposed through a photomask having a predetermined opening pattern. When the exposed first photoresist film R1 is developed, the first photoresist film R1 has a remaining portion (see FIG. 12) that overlaps with the portion where the upper layer side gate electrode 27E is to be formed. When etching is performed through the remaining first photoresist film R1, the second metal film 34 is patterned, and the portion that overlaps with the first photoresist film R1 selectively remains to form the upper layer side gate electrode 27E.

[0056] Thereafter, when the upper layer side gate insulating film patterning step S7 is performed, a second photoresist film R2 made of a photosensitive material is formed on the upper layer side of the upper layer side gate insulating film 33, and the second photoresist film R2 is exposed through a photomask having a predetermined opening pattern. When the exposed second photoresist film R2 is developed, the second photoresist film R2 has remaining portions (see FIG. 13) that overlap with the portions where the linear insulating portion 33A is to be formed, (see FIG. 14) that overlap with the portions where the source intervening portion 38 is to be formed, and (see FIG. 5) that overlap with the portions where the drain intervening portion 39 is to be formed. When etching is performed through the remaining second photoresist film R2, the upper layer side gate insulating film 33 is patterned, and as shown in FIGS. 13 and 14, the portions that overlap with the second photoresist film R2 selectively remain to form the linear insulating portion 33A, the source intervening portion 38, and the drain intervening portion 39 (see FIG. 5).

[0057] Here, as shown in FIGS. 13 and 14, the semiconductor pattern portion 37 of the semiconductor film 32 in a state where the entire area is not conductive has a semiconductor portion 27D (including a first semiconductor portion 27Dα that overlaps with the upper-layer gate electrode 27E and the first insulating portion 33B), a source non-conductive portion 40 and a drain non-conductive portion 41 that do not overlap with the linear insulating portion 33A (the first insulating portion 33B and the non-overlapping insulating portion 33C), and an intermediate non-conductive portion 42 that overlaps with the non-overlapping insulating portion 33C and is located between the semiconductor portion 27D and the source non-conductive portion 40. The source non-conductive portion 40 is a portion that becomes the source region 27B when it is made conductive. The drain non-conductive portion 41 is a portion that becomes the drain region 27C when it is made conductive. The intermediate non-conductive portion 42 is a portion that becomes the high-resistance portion 27F when it is made conductive.

[0058] In the following, when distinguishing the source non-conductive portion 40, the source non-conductive portion 40 that becomes the first source region 27Bα is referred to as the "first source non-conductive portion (first non-conductive portion)" and the suffix "α" is added to its symbol, and the source non-conductive portion 40 that becomes the second source region 27Bβ is referred to as the "second source non-conductive portion (second non-conductive portion)" and the suffix "β" is added to its symbol. When collectively referring to them without distinction, no suffix is added to the symbol. As shown in FIG. 14, the first source non-conductive portion 40α and the second source non-conductive portion 40β are arranged at intervals in the X-axis direction. Also, when distinguishing the intermediate non-conductive portion 42, the intermediate non-conductive portion 42 connected to the source non-conductive portion 40 is referred to as the "first intermediate non-conductive portion (third non-conductive portion)" and the suffix "α" is added to its symbol, and the intermediate non-conductive portion 42 connected to the drain non-conductive portion 41 is referred to as the "second intermediate non-conductive portion" and the suffix "β" is added to its symbol. When collectively referring to them without distinction, no suffix is added to the symbol.

[0059] After the upper-layer side gate insulating film patterning step S7 is performed and then the first interlayer insulating film patterning step S8 is performed, as shown by the two-dot chain lines in FIGS. 13 and 14, the first interlayer insulating film 35 is formed. The formed first interlayer insulating film 35 contacts the source non-conductivized portion 40 and the drain non-conductivized portion 41 of the semiconductor pattern portion 37, but does not contact the intermediate non-conductivized portion 42. Since the first interlayer insulating film 35 contains a reducing agent, in the source non-conductivized portion 40 and the drain non-conductivized portion 41 in contact with the first interlayer insulating film 35, a reduction reaction occurs in which oxygen is extracted by the reducing agent of the first interlayer insulating film 35. In this way, the source non-conductivized portion 40 and the drain non-conductivized portion 41 are conductivized to become the source region 27B and the drain region 27C (see FIG. 6). On the other hand, since the first intermediate non-conductivized portion 42α does not directly contact the first interlayer insulating film 35 and is adjacent to the source non-conductivized portion 40, a reduction reaction also occurs in the first intermediate non-conductivized portion 42α in which oxygen is extracted by the reducing agent via the source non-conductivized portion 40. Similarly, since the second intermediate non-conductivized portion 42β is adjacent to the drain non-conductivized portion 41, a reduction reaction also occurs in the second intermediate non-conductivized portion 42β in which oxygen is extracted by the reducing agent via the drain non-conductivized portion 41. At this time, the degree of reduction of the intermediate non-conductivized portion 42 is lower than the degree of reduction of the source non-conductivized portion 40 and the drain non-conductivized portion 41. In this way, the intermediate non-conductivized portion 42 is conductivized to become a high-resistance portion 27F having a higher resistance than the source region 27B and the drain region 27C (see FIG. 6).

[0060] Incidentally, in the semiconductor pattern portion 37 of the semiconductor film 32 patterned through the semiconductor film patterning step S4, if film residue occurs, as shown in FIG. 15, the first source non-conductivized portion 40α and the second source non-conductivized portion 40β may be mechanically connected by the film residue portion 32R. Even in such a case, among the upper gate insulating films 33 patterned through the upper gate insulating film patterning step S7, the source intervening portion 38 is disposed between the first source non-conductivized portion 40α and the second source non-conductivized portion 40β. Therefore, the source intervening portion 38 is in a relationship of being laminated (superposed) on the upper layer side of the film residue portion 32R. Accordingly, even when the first interlayer insulating film 35 containing a reducing agent is formed in the first interlayer insulating film patterning step S8, since the source intervening portion 38 intervenes between the first interlayer insulating film 35 and the film residue portion 32R of the semiconductor film 32, it is possible to avoid the first interlayer insulating film 35 from contacting the film residue portion 32R. Thereby, the film residue portion 32R of the semiconductor film 32 can be prevented from being reduced and made conductive. As described above, even when film residue occurs in the semiconductor film 32, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non-connected state is increased.

[0061] Here, if film residue occurs in the second metal film 34 patterned through the second metal film patterning step S6, as shown in FIG. 16, for example, the film residue portion 34R may remain over a range that is continuous with the upper gate electrode 27E and overlaps the drain non-conductivized portion 41. Even in such a case, in the present embodiment, since the procedure of performing the upper gate insulating film patterning step S7 after the second metal film patterning step S6 is adopted, the following operations and effects can be obtained. That is, when the upper gate insulating film patterning step S7 is performed after the second metal film patterning step S6 and the second photoresist film R2 is developed, as shown in FIG. 17, the film residue portion 34R of the second metal film 34 is not covered by the remaining second photoresist film R2. Therefore, when the upper gate insulating film 33 is etched through the second photoresist film R2, the film residue portion 34R of the second metal film 34 is also etched. Thus, as shown in FIG. 17, the film residue portion 34R of the second metal film 34 can be removed, so that a situation where the upper gate electrode 27E is short-circuited to the pixel electrode 28 through the film residue portion 34R can be avoided. In addition, even when the film residue portion 34R of the second metal film 34 remains over a range that is continuous with the upper gate electrode 27E and overlaps the source non-conductivized portion 40, the film residue portion 34R can be removed in the same manner as above, so that a situation where the upper gate electrode 27E is short-circuited to the source wiring 26 through the film residue portion 34R can be avoided.

[0062] As described above, the array substrate 21 of the present embodiment includes an upper gate electrode (first electrode) 27E made of a second metal film (first conductive film) 34, an upper gate insulating film (first insulating film) 33 disposed on the lower layer side with respect to the second metal film 34, and a semiconductor film 32 disposed on the lower layer side with respect to the upper gate insulating film 33. A first source region (first conductor portion) 27Bα is formed by making conductive a portion that does not overlap with the upper gate electrode 27E, a second source region (second conductor portion) 27Bβ is formed by making conductive a portion that does not overlap with the upper gate electrode 27E and is different from the first source region 27Bα, a first semiconductor portion 27Dα is formed by a portion that overlaps with the upper gate electrode 27E, and a source intervening portion (intervening portion) 38 is formed by a part of the upper gate insulating film 33 and is disposed between the first source region 27Bα and the second source region 27Bβ.

[0063] A portion of the semiconductor film 32 that does not overlap with the upper gate electrode 27E is the first source region 27Bα and the second source region 27Bβ, while a portion that overlaps with the upper gate electrode 27E is the first semiconductor portion 27Dα. Here, when film residue occurs in the semiconductor film 32 during patterning of the semiconductor film 32, the first source region 27Bα and the second source region 27Bβ may be mechanically connected by the film residue portion 32R. Even in that case, since the source intervening portion 38 formed by a part of the upper gate insulating film 33 is disposed between the first source region 27Bα and the second source region 27Bβ, it overlaps with the film residue portion 32R that is mechanically connected to the first source region 27Bα and the second source region 27Bβ. Therefore, the film residue portion 32R of the semiconductor film 32 can be prevented from being made conductive by being masked by the overlapping source intervening portion 38. As a result, even when film residue occurs in the semiconductor film 32, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non-connected state is increased.

[0064] Further, the upper-layer gate insulating film 33 has a first insulating portion 33B that is disposed to overlap the upper-layer gate electrode 27E and the first semiconductor portion 27Dα. The source intervening portion 38 is formed of a portion of the upper-layer gate insulating film 33 that is different from the first insulating portion 33B. The upper-layer gate electrode 27E and the first semiconductor portion 27Dα are kept in an insulated state by the first insulating portion 33B of the upper-layer gate insulating film 33. By disposing the source intervening portion 38, which is formed of a portion of the upper-layer gate insulating film 33 that is different from the first insulating portion 33B, between the first source region 27Bα and the second source region 27Bβ, it is possible to avoid the film remaining portion 32R, which is continuous with the first source region 27Bα and the second source region 27Bβ in the semiconductor film 32, from being made conductive.

[0065] Further, the semiconductor film 32 is made of an oxide semiconductor material, is disposed on the upper layer side with respect to the second metal film 34, and includes a first interlayer insulating film (second insulating film) 35 containing a reducing agent. The first interlayer insulating film 35 is in contact with the first source region 27Bα and the second source region 27Bβ. The upper layer side gate insulating film 33 has a first non-overlapping insulating portion (second insulating portion) 33Cα that does not overlap with the upper layer side gate electrode 27E and the first semiconductor portion 27Dα and is continuous with the first insulating portion 33B. The first non-overlapping insulating portion 33Cα of the semiconductor film 32 is formed by a portion that overlaps with the first non-overlapping insulating portion 33Cα, is continuous with the first source region 27Bα, and includes a first high-resistance portion 27Fα that has a higher resistance than the first source region 27Bα. The first source region 27Bα and the second source region 27Bβ of the semiconductor film 32 made of an oxide semiconductor material are reduced and made conductive by being in contact with the first interlayer insulating film 35 containing a reducing agent (e.g., hydrogen, etc.). The first non-overlapping insulating portion 33Cα of the upper layer side gate insulating film 33 does not overlap with the upper layer side gate electrode 27E and the first semiconductor portion 27Dα and is continuous with the first insulating portion 33B. Therefore, the first high-resistance portion 27Fα, which is a portion of the semiconductor film 32 that overlaps with the first non-overlapping insulating portion 33Cα, does not directly contact the first interlayer insulating film 35. However, since the first interlayer insulating film 35 is in contact with the first source region 27Bα that is continuous with the first high-resistance portion 27Fα, reduction also occurs in the first high-resistance portion 27Fα. As a result, the first high-resistance portion 27Fα is made conductive to some extent and has a higher resistance than the first source region 27Bα. Here, when a signal is supplied to the upper layer side gate electrode 27E, a channel region is generated in the first semiconductor portion 27Dα. Therefore, the signal supplied to the first source region 27Bα is transmitted through the first high-resistance portion 27Fα and the channel region of the first semiconductor portion 27Dα. Since the first high-resistance portion 27Fα is interposed between the first source region 27Bα and the channel region of the first semiconductor portion 27Dα, the generation of hot carrier injection is preferably suppressed.

[0066] Further, in the source intervening portion 38, the distance D1 from the end on the first source region 27Bα side to the end on the second source region 27Bβ side is greater than the distance D2 from the end on the first semiconductor portion 27Dα side in the first high-resistance portion 27Fα to the end on the first source region 27Bα side. In the semiconductor film 32, when a remaining film portion 32R that is mechanically continuous with the first source region 27Bα and the second source region 27Bβ is generated, among the remaining film portion 32R, the portion overlapping the end on the first source region 27Bα side in the source intervening portion 38 and the portion overlapping the end on the second source region 27Bβ side in the source intervening portion 38 may each be made conductive. Even in that case, since the distance D1 from the end on the first source region 27Bα side to the end on the second source region 27Bβ side in the source intervening portion 38 is made greater than the distance D2 from the end on the first semiconductor portion 27Dα side in the first high-resistance portion 27Fα to the end on the first source region 27Bα side, it is less likely that the entire remaining film portion 32R of the semiconductor film 32 overlapping the source intervening portion 38 will be made conductive. Thereby, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non-connected state becomes higher.

[0067] Also, it includes an upper-layer side gate wiring (first wiring) 29α made of the second metal film 34 and extending along the first direction and including the upper-layer side gate electrode 27E, and a first linear insulating portion 33Aα made of the upper-layer side gate insulating film 33 and extending along the first direction and overlapping the first upper-layer side gate wiring 29α and including the first insulating portion 33B. The first source region 27Bα and the second source region 27Bβ intersect the first upper-layer side gate wiring 29α and the first linear insulating portion 33Aα, and the source intervening portion 38 is continuous with the first linear insulating portion 33Aα. The source intervening portion 38 continuous with the first linear insulating portion 33Aα is arranged between the first source region 27Bα and the second source region 27Bβ that intersect the first upper-layer side gate wiring 29α and the first linear insulating portion 33Aα. Thereby, also for the portions of the first source region 27Bα and the second source region 27Bβ near the first upper-layer side gate wiring 29α and the first linear insulating portion 33Aα, the certainty that they are kept in an electrically non-connected state by the source intervening portion 38 becomes higher.

[0068] Also, it includes a first interlayer insulating film 35 disposed on the upper layer side with respect to the second metal film 34 and a third metal film (second conductive film) disposed on the upper layer side with respect to the first interlayer insulating film 35. A first source wiring (third wiring) 26α, a part of which overlaps with the first source region 27Bα, and a second source wiring (fourth wiring) 26β, which is formed of a part of the third metal film different from the first source wiring 26α and a part of which overlaps with the second source region 27Bβ. In the first interlayer insulating film 35, at a position overlapping both the first source wiring 26α and the first source region 27Bα, a first source contact hole (first contact hole) CH1α for connecting the first source wiring 26α and the first source region 27Bα is provided. In the first interlayer insulating film 35, at a position overlapping both the second source wiring 26β and the second source region 27Bβ, a second source contact hole (second contact hole) CH1β for connecting the second source wiring 26β and the second source region 27Bβ is provided. Even when film residue occurs in the semiconductor film 32, the source intervening portion 38 ensures that the first source region 27Bα and the second source region 27Bβ are kept electrically non-connected. Therefore, a situation where the first source wiring 26α connected to the first source region 27Bα through the first source contact hole CH1α of the first interlayer insulating film 35 and the second source wiring 26β connected to the second source region 27Bβ through the second source contact hole CH1β of the first interlayer insulating film 35 are short-circuited is less likely to occur.

[0069] Also, the liquid crystal panel (display device) 11 of the present embodiment includes the array substrate 21 described above and a counter substrate 20 disposed so as to face the array substrate 21. According to such a liquid crystal panel 11, since the occurrence of a short circuit between the first source region 27Bα and the second source region 27Bβ provided on the array substrate 21 is suppressed, the display quality can be kept good.

[0070] In addition, the manufacturing method of the array substrate 21 of the present embodiment includes forming a semiconductor film 32 made of an oxide semiconductor material and patterning the semiconductor film 32 to provide a first source non-conductivized portion (first non-conductivized portion) 40α, a second source non-conductivized portion (second non-conductivized portion) 40β arranged at an interval from the first source non-conductivized portion 40α, and a first semiconductor portion 27Dα. An upper-layer gate insulating film 33 is formed on the upper layer side of the semiconductor film 32, a second metal film 34 is formed on the upper layer side of the upper-layer gate insulating film 33, and by patterning the second metal film 34, an upper-layer gate electrode 27E that overlaps the first semiconductor portion 27Dα is provided. By patterning the upper-layer gate insulating film 33, a first insulating portion 33B that overlaps and is arranged with respect to the upper-layer gate electrode 27E and the first semiconductor portion 27Dα, and a source intervening portion 38 arranged between the first source non-conductivized portion 40α and the second source non-conductivized portion 40β are provided. A first interlayer insulating film 35 containing a reducing agent is formed on the upper layer side of the second metal film 34, and by bringing the first interlayer insulating film 35 into contact with the first source non-conductivized portion 40α and the second source non-conductivized portion 40β, the first source non-conductivized portion 40α and the second source non-conductivized portion 40β are conductivized to become a first source region 27Bα and a second source region 27Bβ, respectively.

[0071] When film residue occurs in the semiconductor film 32 during patterning of the semiconductor film 32, the first source non-conducting portion 40α and the second source non-conducting portion 40β may be mechanically connected by the film residue portion 32R. Even in such a case, when the upper-layer gate insulating film 33 is patterned, a first insulating portion 33B that is disposed to overlap the upper-layer gate electrode 27E and the first semiconductor portion 27Dα, and a source intervening portion 38 that is disposed between the first source non-conducting portion 40α and the second source non-conducting portion 40β are provided, and the source intervening portion 38 among them is in a relationship of overlapping the film residue portion 32R of the semiconductor film 32. Therefore, when the first interlayer insulating film 35 containing a reducing agent is formed on the second metal film 34 on the upper layer side, even if the first interlayer insulating film 35 contacts the first source non-conducting portion 40α and the second source non-conducting portion 40β, it is possible to avoid the first interlayer insulating film 35 from contacting the film residue portion 32R of the semiconductor film 32. As a result, the first source non-conducting portion 40α and the second source non-conducting portion 40β in contact with the first interlayer insulating film 35 are reduced and made conductive to become the first source region 27Bα and the second source region 27Bβ, while the film residue portion 32R of the semiconductor film 32 can be avoided from being reduced and made conductive. As described above, even when film residue occurs in the semiconductor film 32, the certainty that the first source region 27Bα and the second source region 27Bβ are kept in an electrically non-connected state is increased.

[0072] Further, by patterning the upper gate insulating film 33, a first non-overlapping insulating portion 33Cα that does not overlap with the upper gate electrode 27E and the first semiconductor portion 27Dα and is continuous with the first insulating portion 33B is provided. By patterning the semiconductor film 32, a first intermediate non-conducting portion (third non-conducting portion) 42α that overlaps with the first non-overlapping insulating portion 33Cα and is continuous with the first source non-conducting portion 40α is provided. When the first interlayer insulating film 35 is formed, the first intermediate non-conducting portion 42α becomes a first high-resistance portion 27Fα that has a higher resistance than the first source region 27Bα. The first non-overlapping insulating portion 33Cα provided by patterning the upper gate insulating film 33 does not overlap with the upper gate electrode 27E and the first semiconductor portion 27Dα and is continuous with the first insulating portion 33B. The first intermediate non-conducting portion 42α provided by patterning the semiconductor film 32 overlaps with the first non-overlapping insulating portion 33Cα and is continuous with the first source non-conducting portion 40α. Therefore, even when the first interlayer insulating film 35 is formed, the first intermediate non-conducting portion 42α, which is a portion of the semiconductor film 32 that overlaps with the first non-overlapping insulating portion 33Cα, does not directly contact the first interlayer insulating film 35. However, since the first interlayer insulating film 35 contacts the first source non-conducting portion 40α that is continuous with the first intermediate non-conducting portion 42α, reduction also occurs in the first intermediate non-conducting portion 42α. As a result, the first intermediate non-conducting portion 42α is conductorized to some extent and becomes a first high-resistance portion 27Fα that has a higher resistance than the first source region 27Bα. Here, when a signal is supplied to the upper gate electrode 27E, a channel region is generated in the first semiconductor portion 27Dα. Therefore, the signal supplied to the first source region 27Bα is transmitted through the channel region of the first semiconductor portion 27Dα via the first high-resistance portion 27Fα. Since the first high-resistance portion 27Fα is interposed between the first source region 27Bα and the channel region of the first semiconductor portion 27Dα, the generation of hot carrier injection is preferably suppressed.

[0073] Further, after patterning the second metal film 34, the upper gate insulating film 33 is patterned. Even when film residue occurs during patterning of the second metal film 34, the film residue portion 34R of the second metal film 34 can be removed by subsequently patterning the upper gate insulating film 33.

[0074] <Embodiment 2> Embodiment 2 will be described with reference to FIGS. 18 to 20. In this Embodiment 2, a case where the configurations of the source intervening portion 138 and the drain intervening portion 139 are changed is shown. Note that redundant descriptions of the same structures, operations, and effects as those in Embodiment 1 described above are omitted.

[0075] As shown in FIG. 18, the first source region 127Bα according to the present embodiment has a first inclined portion 43 inclined with respect to the first source wiring 126α and the second source wiring 126β. The first inclined portion 43 extends from the first high-resistance portion 127Fα obliquely upward to the upper right as shown in FIG. 18 and overlaps the first source wiring 126α. In the first source region 127Bα, a portion continuous with the extending tip of the first inclined portion 43 extends in parallel with the first source wiring 126α and is connected to the first source wiring 126α through the first source contact hole CH101α.

[0076] Similar to the first source region 127Bα, the second source region 127Bβ has a second inclined portion 44 parallel to the first inclined portion 43 as shown in FIG. 18. The second inclined portion 44 extends from the first high-resistance portion 127Fα obliquely upward to the upper right as shown in FIG. 18 and overlaps the second source wiring 126β. In the second source region 127Bβ, a portion continuous with the extending tip of the second inclined portion 44 extends in parallel with the second source wiring 126β and is connected to the second source wiring 126β through the second source contact hole CH101β.

[0077] Then, as shown in FIG. 18, the source intervening portion 138 has a third inclined portion 45 that is parallel to the first inclined portion 43 and the second inclined portion 44. The third inclined portion 45 extends obliquely upward to the right as shown in FIG. 18 from the linear insulating portion 133A, and is arranged to be interposed between the first inclined portion 43 and the second inclined portion 44. In the source intervening portion 138, the portion continuous with the extending tip of the third inclined portion 45 extends along the Y-axis direction and is interposed between the portion connected to the first source wiring 126α in the first source region 127Bα and the portion connected to the second source wiring 126β in the second source region 127Bβ. According to the present embodiment, compared with the case where the first source region 27Bα is bent in an L shape from the first source contact hole CH1α to the first semiconductor portion 27Dα as in the above-described Embodiment 1 (see FIG. 5), the distance from the first source contact hole CH101α to the first semiconductor portion 127Dα of the first source region 127Bα becomes shorter. Thereby, while increasing the pattern density of the structure made of the semiconductor film 132, the certainty that the first source region 127Bα and the second source region 127Bβ are kept in an electrically non-connected state by the source intervening portion 138 can be highly maintained.

[0078] Specifically, when film residue occurs in the semiconductor film 132, as shown in FIGS. 19 and 20, the first source region 127Bα and the second source region 127Bβ may be mechanically connected by the film residue portion 132R. Even in that case, since the source intervening portion 138 is arranged between the first source region 127Bα and the second source region 127Bβ, the source intervening portion 138 is in a relationship of being laminated (superposed) on the upper layer side of the film residue portion 132R. Therefore, it is possible to avoid the first interlayer insulating film 135 containing a reducing agent from contacting the film residue portion 132R, whereby the film residue portion 132R is not reduced and the formation of a conductor is avoided.

[0079] As shown in FIG. 18, the first drain region 127Cα according to the present embodiment has a fourth inclined portion 46 inclined with respect to the first source wiring 126α and the second source wiring 126β. The fourth inclined portion 46 extends obliquely downward to the left as shown in FIG. 18 from the second high-resistance portion 127Fβ. In the first drain region 127Cα, the portion continuous with the extending tip of the fourth inclined portion 46 extends in parallel with the first source wiring 126α and is connected to the pixel electrode 128 through the first drain contact hole CH102α.

[0080] Similar to the first drain region 127Cα, as shown in FIG. 18, the second drain region 127Cβ has a fifth inclined portion 47 parallel to the fourth inclined portion 46. The fifth inclined portion 47 extends obliquely downward to the left as shown in FIG. 18 from the first high-resistance portion 127Fα. In the second drain region 127Cβ, the portion continuous with the extending tip of the fifth inclined portion 47 extends in parallel with the second source wiring 126β and is connected to the pixel electrode 128 through the second drain contact hole CH102β.

[0081] As shown in FIG. 18, the drain intervening portion 139 has a sixth inclined portion 48 parallel to the fourth inclined portion 46 and the fifth inclined portion 47. The sixth inclined portion 48 extends obliquely downward to the left as shown in FIG. 18 from the linear insulating portion 133A, intervenes between the fourth inclined portion 46 and the fifth inclined portion 47, and is arranged to overlap the source wiring 126. In the drain intervening portion 139, the portion continuous with the extending tip of the sixth inclined portion 48 extends along the Y-axis direction and intervenes between the portion of the first drain region 127Cα connected to the pixel electrode 128 and the portion of the second drain region 127Cβ connected to the pixel electrode 128. By providing the drain intervening portion 139 having such a configuration, even when a remaining film portion that mechanically connects the first drain region 127Cα and the second drain region 127Cβ is generated in the semiconductor film 132, a situation where the remaining film portion is made conductive can be avoided.

[0082] As described above, according to this embodiment, the first source wiring 126α and the second source wiring 126β are parallel to each other. The first source region 127Bα has a first inclined portion 43 inclined with respect to the first source wiring 126α and the second source wiring 126β. The second source region 127Bβ has a second inclined portion 44 parallel to the first inclined portion 43. The source intervening portion 138 has a third inclined portion 45 parallel to the first inclined portion 43 and the second inclined portion 44. In this way, if the first source region is bent in an L shape from the first source contact hole CH101α to the first semiconductor portion 127Dα, the distance of the first source region 127Bα from the first source contact hole CH101α to the first semiconductor portion 127Dα is shorter than that case. As a result, while increasing the pattern density of the structure formed of the semiconductor film 132, the certainty that the first source region 127Bα and the second source region 127Bβ are kept electrically non-connected by the source intervening portion 138 can be highly maintained.

[0083] <Embodiment 3> Embodiment 3 will be described with reference to FIGS. 21 to 23. This Embodiment 3 shows a case where the source intervening portion 138 is removed from the above-described Embodiment 2 and the configuration of the source region 227B is changed. Note that redundant descriptions of the same structures, operations, and effects as those of the above-described Embodiment 1 are omitted.

[0084] As shown in FIG. 21, the upper-layer gate insulating film 233 according to the present embodiment is configured not to include the source intervening portions 38 and 138 (see FIGS. 5 and 18) described in Embodiments 1 and 2. On top of that, the source region 227B according to the present embodiment is formed to be narrower in width than the drain region 227C and is arranged to partially overlap the source contact hole CH201. Specifically, the first source region 227Bα is arranged to partially overlap the first source contact hole CH201α so as not to overlap with the portion on the second source region 227Bβ side (the right side in FIG. 21) of the first source contact hole CH201α. Similarly, the second source region 227Bβ is arranged to partially overlap the second source contact hole CH201β so as not to overlap with the portion on the side opposite to the first source region 227Bα side (the right side in FIG. 21) of the second source contact hole CH201β. Also, the source region 227B is arranged to overlap with more than half of the range of the source contact hole CH201 when viewed in plan. According to the present embodiment, as in the above-described Embodiments 1 and 2, compared with the case where the first source regions 27Bα and 127Bα are arranged to overlap the entire areas of the first source contact holes CH1α and CH101α (see FIGS. 5 and 18), the distance between the first source region 227Bα and the second source region 227Bβ becomes wider. Therefore, even in a configuration without the source intervening portions 38 and 138 as in the present embodiment, as shown in FIG. 22, when film residue occurs in the semiconductor film 232, the situation where the film residue portion 232R mechanically continues to the first source region 227Bα and the second source region 227Bβ is less likely to occur.

[0085] On the other hand, as shown in FIGS. 22 and 23, since the drain region 227C is formed wider than the source region 227B, when film residue occurs in the semiconductor film 232, the film residue portion 232R is relatively likely to connect to the first drain region 227Cα and the second drain region 227Cβ. In this regard, since the drain intervening portion 239 is interposed between the first drain region 227Cα and the second drain region 227Cβ, even when a film residue portion 232R that mechanically connects the first drain region 227Cα and the second drain region 227Cβ occurs in the semiconductor film 232, a situation where the film residue portion 232R becomes conductive can be avoided.

[0086] As described above, according to the present embodiment, the first source region 227Bα is partially overlapped with the first source contact hole CH201α so as not to overlap with the portion on the second source region 227Bβ side of the first source contact hole CH201α. If the first source region is arranged to overlap the entire area of the first source contact hole CH201α, the distance between the first source region 227Bα and the second source region 227Bβ becomes wider. Thereby, even when film residue occurs in the semiconductor film 232, a situation where the film residue portion 232R mechanically connects to the first source region 227Bα and the second source region 227Bβ is less likely to occur.

[0087] <Embodiment 4> Embodiment 4 will be described with reference to FIG. 24. This Embodiment 4 shows a case where the configuration of the upper gate insulating film 33 is changed from Embodiment 2 described above. Note that redundant descriptions of the same structures, operations, and effects as those in Embodiment 2 described above are omitted.

[0088] As shown in FIG. 24, the upper-layer gate insulating film 33 according to this embodiment has a pixel-crossing insulating portion 33D that extends along the X-axis direction so as to cross the pixel electrode 328. Specifically, the pixel-crossing insulating portion 33D crosses the central portion of the pixel electrode 328 in the longitudinal direction (Y-axis direction) and is parallel to the linear insulating portion 333A. The pixel-crossing insulating portion 33D includes a first pixel-crossing insulating portion 33Dα sandwiched between the first linear insulating portion 333Aα and the second linear insulating portion 333Aβ. The source intervening portion 338 and the drain intervening portion 339 are each configured to be continuous with the pixel-crossing insulating portion 33D. Specifically, in the source intervening portion 338, the extending tip of the third inclined portion 345 extending from the first linear insulating portion 333Aα further extends along the Y-axis direction and is aligned with the first pixel-crossing insulating portion 33Dα. In the drain intervening portion 339, the extending tip of the sixth inclined portion 348 extending from the second linear insulating portion 333Aβ further extends along the Y-axis direction and is aligned with the first pixel-crossing insulating portion 33Dα.

[0089] In this way, the source intervening portion 338 is connected from the first linear insulating portion 333Aα to the second linear insulating portion 333Aβ via the first pixel-crossing insulating portion 33Dα and the drain electrode intervening portion 339. As a result, the region on the first source region 327Bα side and the region on the second source region 327Bβ side are partitioned by the source intervening portion 338, so the certainty that the first source region 327Bα and the second source region 327Bβ are kept electrically non-connected becomes higher. Also, the drain electrode intervening portion 339 is connected from the second linear insulating portion 333Aβ to the first linear insulating portion 333Aα via the first pixel-crossing insulating portion 33Dα and the source intervening portion 338. As a result, the region on the first drain region 327Cα side and the region on the second drain region 327Cβ side are partitioned by the drain intervening portion 339, so the certainty that the first drain region 327Cα and the second drain region 327Cβ are kept electrically non-connected becomes higher.

[0090] As described above, according to the present embodiment, it is composed of the second metal film 34, is arranged at a position spaced apart from the first upper-layer side gate wiring 329α in the second direction intersecting the first direction, and is a second upper-layer side gate wiring (second wiring) 329β extending along the first direction, and is composed of the upper-layer side gate insulating film 333, extends along the first direction, and has a second linear insulating portion 333Aβ overlapping the second upper-layer side gate wiring 329β. The source intervening portion 338 is continuous with the second linear insulating portion 333Aβ. In this way, the region on the first source region 327Bα side and the region on the second source region 327Bβ side are partitioned by the source intervening portion 338, so the certainty that the first source region 327Bα and the second source region 327Bβ are kept in an electrically non-connected state is higher.

[0091] <Embodiment 5> Embodiment 5 will be described with reference to FIG. 25. In this Embodiment 5, a case where the configurations of the source intervening portion 438 and the drain intervening portion 439 are changed in the same manner as in Embodiment 4 from the above-described Embodiment 1 is shown. Note that redundant descriptions of the same structures, operations, and effects as in the above-described Embodiments 1 and 4 are omitted.

[0092] As shown in FIG. 25, the source intervening portion 438 according to the present embodiment has an extending tip portion extending along the Y-axis direction from the first linear insulating portion 433Aα connected to the drain intervening portion 439 continuous with the second linear insulating portion 433Aβ. Similarly, the drain intervening portion 439 has an extending tip portion extending along the Y-axis direction from the first linear insulating portion 433Aα connected to the source intervening portion 438 continuous with the linear insulating portion 433A located on the side opposite to the second linear insulating portion 433Aβ with respect to the first linear insulating portion 433Aα. With the above configuration, the same operations and effects as in Embodiment 4 described above can be obtained.

[0093] <Embodiment 6> Embodiment 6 will be described with reference to FIG. 26. In this Embodiment 6, a case where the source intervening portion 538 is added from the above-described Embodiment 3 is shown. Note that redundant descriptions of the same structures, operations, and effects as in the above-described Embodiment 3 are omitted.

[0094] Between the first source region 527Bα and the second source region 527Bβ according to this embodiment, as shown in FIG. 26, a source intervening portion 538 is interposed and arranged. Here, as described in the above-described Embodiment 3, although the first source region 527Bα and the second source region 527Bβ are narrow in width, a situation may occur in which the remaining film portion 532R generated in the semiconductor film 532 is mechanically continuous between the first source region 527Bα and the second source region 527Bβ. Even in that case, since the source intervening portion 538 is interposed and arranged between the first source region 527Bα and the second source region 527Bβ, it is possible to avoid a situation in which the remaining film portion 532R continuous between the first source region 527Bα and the second source region 527Bβ is made conductive.

[0095] <Embodiment 7> Embodiment 7 will be described with reference to FIG. 27. This Embodiment 7 shows a case where the configuration of the drain region 627C is changed from that of the above-described Embodiment 3. Note that redundant descriptions of the same structure, operation, and effects as those in the above-described Embodiment 3 are omitted.

[0096] As shown in FIG. 26, the drain region 627C is configured to have the same width as the source region 627B. The drain region 627C is arranged to partially overlap with the drain contact hole CH602. Specifically, the first drain region 627Cα is arranged to partially overlap with the first drain contact hole CH602α so as not to overlap with the portion on the side opposite to the second drain region 627Cβ (the left side in FIG. 26) of the first drain contact hole CH602α. Similarly, the second drain region 627Cβ is arranged to partially overlap with the second drain contact hole CH602β so as not to overlap with the portion on the side of the first drain region 627Cα (the left side in FIG. 26) of the second drain contact hole CH602β. Further, the drain region 627C is arranged to overlap with more than half of the range of the drain contact hole CH602 when viewed in the plane. According to the present embodiment, compared with the case where the first drain regions 27Cα and 127Cα are arranged to overlap with the entire areas of the first drain contact holes CH2α and CH102α as in the above-described Embodiments 1 and 2 (see FIGS. 5 and 18), the interval between the first drain region 627Cα and the second drain region 627Cβ becomes wider. Therefore, when film residue occurs in the semiconductor film 632, it is less likely that the film residue portion 632R is mechanically continuous between the first drain region 627Cα and the second drain region 627Cβ. Moreover, since the drain intervening portion 639 is interposed between the first drain region 627Cα and the second drain region 627Cβ, it is possible to avoid the situation where the film residue portion 632R continuous between the first drain region 627Cα and the second drain region 627Cβ is made conductive.

[0097] <Embodiment 8> Embodiment 8 will be described with reference to FIG. 28. This Embodiment 8 shows the case where the configuration described in the above-described Embodiment 3 is applied to Embodiment 1. Note that redundant descriptions of the same structure, operation, and effect as those in the above-described Embodiment 3 are omitted.

[0098] As shown in FIG. 28, the upper-layer gate insulating film 733 according to this embodiment is configured not to include the source intervening portions 38 and 138 (see FIGS. 5 and 18) described in Embodiments 1 and 2. On top of that, the source region 727B according to this embodiment is formed such that the portion extending along the X-axis direction is shorter than the source regions 27B and 127B (see FIGS. 5 and 18) described in Embodiments 1 and 2, and as a result, it is arranged to partially overlap the source contact hole CH701. Even in such a configuration, the same operations and effects as those of Embodiment 3 described above can be obtained.

[0099] <Embodiment 9> Embodiment 9 will be described with reference to FIGS. 29 to 35. This Embodiment 9 shows a case where the configurations of the upper-layer gate insulating film 833 and the source intervening portion 838, and the manufacturing method of the array substrate 821 are changed from those of Embodiment 1 described above. Note that redundant descriptions of the same structures, operations, and effects as those of Embodiment 1 described above are omitted.

[0100] As shown in FIG. 29, the upper-layer gate insulating film 833 according to the present embodiment is formed in a substantially solid state within the main surface of the array substrate 821. The upper-layer gate insulating film 833 formed in a solid state covers substantially the entire semiconductor pattern portion 837. Accordingly, the first interlayer insulating film 835 is not directly in contact with the semiconductor pattern portion 837. Along with this, even if the first interlayer insulating film 835 contains a reducing agent, the semiconductor pattern portion 837 is prevented from being reduced and made conductive by the reducing agent. Accordingly, the semiconductor pattern portion 837 according to the present embodiment does not have the high-resistance portion 27F (see FIG. 6) described in Embodiment 1. Among the semiconductor pattern portion 837, portions that do not overlap with the upper-layer gate electrode 827E are the source region 827B and the drain region 827C. And the upper-layer gate insulating film 833 does not constitute the source intervening portion 838. Further, a source contact hole CH801 formed in the first interlayer insulating film 835 communicates with and is formed as an opening in the upper-layer gate insulating film 833, and a drain contact hole CH802 formed in the first interlayer insulating film 835 and the planarization film 836 communicates with and is formed as an opening in the upper-layer gate insulating film 833.

[0101] As shown in FIGS. 30 and 31, the source intervening portion 838 is formed of a portion of the second metal film 834 that is different from the upper layer side gate wiring 829 (including the upper layer side gate electrode 827E). The source intervening portion 838 is formed in an island shape physically separated from the upper layer side gate wiring 829. Thereby, the source intervening portion 838 is electrically isolated from the upper layer side gate wiring 829. Thus, the source intervening portion 838 made of the second metal film 834 is disposed between the first source region 827Bα and the second source region 827Bβ. Therefore, even when a film residue occurs in the semiconductor film 832 and there is a film residue portion 832R continuous with the first source region 827Bα and the second source region 827Bβ, the source intervening portion 838 is superimposed on the film residue portion 832R, so that the film residue portion 832R of the semiconductor film 832 can be prevented from being conducted. In particular, since the source intervening portion 838 according to the present embodiment is made of a metal material, there is a high certainty that the film residue portion 832R of the semiconductor film 832 is prevented from being conducted. Although not shown, the drain intervening portion 39 is also made of the second metal film 834.

[0102] The present embodiment has the above-described structure. Next, a method for manufacturing the array substrate 821 will be described. As shown in FIG. 32, the method for manufacturing the array substrate 821 includes a base coat film forming step S801 of forming a base coat film 830, a first metal film patterning step S802 of forming and patterning a first metal film, a lower gate insulating film forming step S803 of forming a lower gate insulating film 831, a semiconductor film patterning step S804 of forming and patterning a semiconductor film 832, an upper gate insulating film forming step S805 of forming an upper gate insulating film 833, a second metal film patterning step S806 of forming and patterning a second metal film 834, a conductor conversion treatment step S12 of selectively converting the semiconductor film 832 into a conductor, a first interlayer insulating film patterning step S808 of forming and patterning a first interlayer insulating film 835, a third metal film patterning step S809 of forming and patterning a third metal film, a planarization film patterning step S810 of forming and patterning a planarization film 836, and a first transparent electrode film patterning step S811 of forming and patterning a first transparent electrode film. Hereinafter, among the above-described steps, the conductor conversion treatment step S12 will be described in detail.

[0103] After performing the second metal film patterning step S806 to form the upper gate electrode 827E and the like made of the second metal film 834, a conductor formation process S12 is performed. Specifically, in the conductor formation process S12, as shown in FIG. 33, as the conductor formation process, a process of doping (injecting) accelerated impurity ions into the semiconductor pattern portion 837 of the semiconductor film 832 is performed. In FIG. 33, the direction in which the impurity ions are doped is illustrated by a dashed arrow. Among the semiconductor pattern portions 837 of the semiconductor film 832 before being made conductive, the source non-conductive portion 840 and the drain non-conductive portion 841, which are the portions not covered by the upper gate electrode 827E having a configuration made of the second metal film 834, are selectively doped with impurity ions. On the other hand, among the semiconductor pattern portions 837 of the semiconductor film 832 before being made conductive, the semiconductor portion 827D, which is the portion covered by the upper gate electrode 827E, is not doped with impurity ions. Among the semiconductor pattern portions 837 of the semiconductor film 832, the source non-conductive portion 840 and the drain non-conductive portion 841 are made conductive by being doped with impurity ions and become the source region 827B and the drain region 827C, as shown in FIG. 34.

[0104] On one hand, if film residue occurs in the semiconductor pattern portion 837 of the semiconductor film 832 patterned through the semiconductor film patterning step S804, as shown in FIG. 35, the first source non-conductivized portion 840α and the second source non-conductivized portion 840β may be mechanically connected by the film residue portion 832R. Even in such a case, since the source intervening portion 838 of the second metal film 834 patterned through the second metal film patterning step S806 is disposed between the first source non-conductivized portion 840α and the second source non-conductivized portion 840β, the source intervening portion 838 is laminated (superposed) on the upper layer side of the film residue portion 832R via the upper layer side gate insulating film 833. Therefore, even when a process of doping accelerated impurity ions is performed in the conductivization process step S12, the film residue portion 832R of the semiconductor film 832 is masked by the source intervening portion 838, so that it is difficult for impurity ions to be implanted into the film residue portion 832R. As a result, the film residue portion 832R of the semiconductor film 832 can be avoided from being conductivized. As described above, even when film residue occurs in the semiconductor film 832, the certainty that the first source region 827Bα and the second source region 827Bβ are kept in an electrically non-connected state is increased.

[0105] As described above, the array substrate 821 of the present embodiment includes an upper layer side gate electrode (first electrode) 827E made of a second metal film (first conductive film) 834, an upper layer side gate insulating film (first insulating film) 833 disposed on the lower layer side with respect to the second metal film 834, a first source region (first conductivized portion) 827Bα formed by conductivizing a portion of the semiconductor film 832 that does not overlap with the upper layer side gate electrode 827E and is disposed on the lower layer side with respect to the upper layer side gate insulating film 833, a second source region (second conductivized portion) 827Bβ formed by conductivizing a portion of the semiconductor film 832 that does not overlap with the upper layer side gate electrode 827E and is different from the first source region 827Bα, a first semiconductor portion 827Dα formed by a portion of the semiconductor film 832 that overlaps with the upper layer side gate electrode 27E, and a source intervening portion (intervening portion) 838 formed by a portion of the second metal film 834 that is different from the upper layer side gate electrode 827E and is disposed between the first source region 827Bα and the second source region 827Bβ.

[0106] A portion of the upper-layer gate electrode 827E that does not overlap with the semiconductor film 832 is defined as the first source region 827Bα and the second source region 827Bβ, while a portion that overlaps with the upper-layer gate electrode 827E is defined as the first semiconductor portion 827Dα. Here, when film residue occurs on the semiconductor film 832 during patterning of the semiconductor film 832, the first source region 827Bα and the second source region 827Bβ may be mechanically connected by the film residue portion 832R. Even in such a case, since the source intervening portion 838, which is a portion of the second metal film 834 different from the upper-layer gate electrode 827E, is disposed between the first source region 827Bα and the second source region 827Bβ, it overlaps with the film residue portion 832R that is mechanically connected to the first source region 827Bα and the second source region 827Bβ. Therefore, the film residue portion 832R of the semiconductor film 832 can be prevented from being made conductive by being masked by the overlapping source intervening portion 838. As a result, even when film residue occurs on the semiconductor film 832, the certainty that the first source region 827Bα and the second source region 827Bβ are kept electrically non-connected is increased.

[0107] Also, the second metal film 834 is made of a metal material, and the source intervening portion 838 is a portion of the second metal film 834 different from the upper-layer gate electrode 827E. By disposing the source intervening portion 838, which is a portion of the second metal film 834 different from the upper-layer gate electrode 827E, between the first source region 827Bα and the second source region 827Bβ, it is possible to prevent the film residue portion 832R that is continuous with the first source region 827Bα and the second source region 827Bβ in the semiconductor film 832 from being made conductive. Since the source intervening portion 838 is made of a metal material, the certainty of preventing the film residue portion 832R of the semiconductor film 832 from being made conductive is high.

[0108] In addition, the method for manufacturing the array substrate 821 of the present embodiment includes forming a semiconductor film 832 and patterning the semiconductor film 832 to provide a first source non-conductive portion 840α, a second source non-conductive portion 840β arranged at an interval from the first source non-conductive portion 840α, and a first semiconductor portion 827Dα. An upper gate insulating film 833 is formed on the upper layer side of the semiconductor film 832, a second metal film 834 is formed on the upper layer side of the upper gate insulating film 833, and by patterning the second metal film 834, an upper gate electrode 827E that overlaps the first semiconductor portion 827Dα and a source intervening portion 838 arranged between the first source non-conductive portion 840α and the second source non-conductive portion 840β are provided. By performing a conductivity treatment for conducting the semiconductor film 832 using the second metal film 834 as a mask, the first source non-conductive portion 840α and the second source non-conductive portion 840β, which are in a non-overlapping relationship with the upper gate electrode 827E and the source intervening portion 838, are made conductive to form a first source region 827Bα and a second source region 827Bβ, respectively.

[0109] When a film residue occurs in the semiconductor film 832 during patterning of the semiconductor film 832, the first source non-conducting portion 840α and the second source non-conducting portion 840β may be mechanically connected by the film residue portion 832R. Even in such a case, when the second metal film 834 is patterned, an upper gate electrode 827E disposed to overlap the first semiconductor portion 827Dα and a source intervening portion 838 disposed between the first source non-conducting portion 840α and the second source non-conducting portion 840β are provided, and the source intervening portion 838 of these is in an overlapping relationship with the film residue portion 832R of the semiconductor film 832. Therefore, when a conductivity treatment for making the semiconductor film 832 conductive is performed using the second metal film 834 as a mask, the first source non-conducting portion 840α and the second source non-conducting portion 840β, which are in a non-overlapping relationship with the upper gate electrode 827E and the source intervening portion 838, are made conductive, while it is possible to avoid the film residue portion 832R of the semiconductor film 832, which is in an overlapping relationship with the source intervening portion 838, from being made conductive. As a result, even when a film residue occurs in the semiconductor film 832, the certainty that the first source region 827Bα and the second source region 827Bβ are kept in an electrically non-connected state is increased.

[0110] <Other Embodiments> The technology disclosed in this specification is not limited to the embodiments described by the above description and drawings. For example, the following embodiments are also included in the technical scope.

[0111] (1) In the configurations described in Embodiments 1 to 8, the source intervening portions 38, 138, 338, 438, 538 may be formed in an island shape physically separated from the linear insulating portions 33A, 133A, 333A, 433A. Similarly, the drain intervening portions 39, 139, 239, 339, 439, 639 may be formed in an island shape physically separated from the linear insulating portions 33A, 133A, 333A, 433A.

[0112] (2) In the configurations described in Embodiments 1, 5, and 8, the source intervening portions 38, 438 may be configured to have a constant width. Similarly, the drain intervening portions 39, 439 may be configured to have a constant width.

[0113] (3) In the configurations described in Embodiments 2 to 4, 6, 7, and 9, the source intervening portions 138, 338, 538, and 838 may be configured such that the width dimension varies according to the position in the Y-axis direction. Similarly, the drain intervening portions 139, 239, 339, and 639 may be configured such that the width dimension varies according to the position in the Y-axis direction.

[0114] (4) In addition to the above (2) and (3), the specific planar shape of the source intervening portions 38, 138, 338, 438, 538, and 838 can be appropriately changed. Similarly, the specific planar shape of the drain intervening portions 39, 139, 239, 339, 439, and 639 can be appropriately changed.

[0115] (5) The array substrates 21 and 821 may be configured not to have the upper-layer gate wiring 29, 329, and 829. Even in that case, by connecting the upper-layer gate electrodes 27E, 627E, and 827E to the lower-layer gate electrode 27A or to the lower-layer gate wiring 25, it is possible to supply a scanning signal to the upper-layer gate electrodes 27E, 627E, and 827E at the same timing as the lower-layer gate electrode 27A.

[0116] (6) The array substrates 21 and 821 may be configured not to have the lower-layer gate wiring 25. Even in that case, by connecting the lower-layer gate electrode 27A to the upper-layer gate electrodes 27E, 627E, and 827E or to the upper-layer gate wiring 29, 329, and 829, it is possible to supply a scanning signal to the lower-layer gate electrode 27A at the same timing as the upper-layer gate electrodes 27E, 627E, and 827E.

[0117] (7) The TFT 27 may be configured not to have the lower-layer gate electrode 27A. That is, the TFT 27 may be a top-gate type in addition to the double-gate type. As the lower-layer gate electrode 27A is omitted from the array substrates 21 and 821, the array substrates 21 and 821 can be configured not to have the lower-layer gate wiring 25. Also, it is possible to omit the first metal film from the array substrates 21 and 821.

[0118] (8) In the configurations described in Embodiments 1 to 8, the upper-layer gate insulating films 33, 233, 333, 733 may have a configuration that has the first insulating portion 33B and the non-overlapping insulating portion 33C but does not have the linear insulating portions 33A, 133A, 333A, 433A. That is, the upper-layer gate insulating films 33, 233, 333, 733 may be constituted by the first insulating portions 33B and the non-overlapping insulating portions 33C that are scattered in an island shape for each TFT 27.

[0119] (9) When the pixel electrode 28 and the source wirings 26, 126 are constituted by parts of the conductive portions in the semiconductor films 32, 132, 232, 532, 632, 832, it is also possible to provide an intervening portion so as to intervene between the pixel electrode 28 which is the "first conductive portion" and the source wirings 26, 126 which are the "second conductive portions".

[0120] (10) Specific methods for making the semiconductor films 32, 132, 232, 532, 632, 832 conductive can be appropriately changed in addition to the above.

[0121] (11) Instead of the second circuit portion 14B, a source driver may be attached to the array substrates 21, 821.

[0122] (12) Instead of the second circuit portion 14B, a source driver may be attached to the flexible substrate 13.

[0123] (13) Instead of the first circuit portion 14A, a gate driver may be attached to the array substrates 21, 821.

[0124] (14) The semiconductor films 32, 132, 232, 532, 632, 832 may be amorphous silicon thin films or polycrystalline silicon thin films.

[0125] (15) The liquid crystal panel 11 may be a reflective type or a transflective type in addition to the transmissive type. When the liquid crystal panel 11 is a reflective type, the backlight device 12 can be omitted.

[0126] (16) In addition to the head-mounted display 10HMD, the present invention is applicable to, for example, a head-up display or a projector as a device that magnifies and displays an image displayed on the liquid crystal panel 11 using a lens or the like. Further, the present invention is also applicable to a display device (such as a television receiver, a tablet terminal, or a smartphone) that does not have a magnification display function.

[0127] (17) The linear insulating portions 33A, 133A, 333A, and 433A are arranged in a strip-shaped range having the same width as the lower-layer gate wiring 25 and may overlap the entire area of the lower-layer gate wiring 25.

[0128] (18) In Embodiment 9, after forming the upper-layer gate electrode 827E through the second metal film patterning step, a photoresist film is formed and patterned to provide a source intervening portion 838 made of the photoresist film, and a conductor formation process may be performed using the source intervening portion 838 as a mask. That is, the source intervening portion 838 can also be formed of a photoresist film in addition to the second metal film 834. According to such a method, even if a film remaining portion 832R is generated in the semiconductor film 832, the film remaining portion 832R can be prevented from being made conductive by the source intervening portion 838 that overlaps the film remaining portion 832R, so that the certainty that the first source region 827Bα and the second source region 827Bβ are kept in an electrically non-connected state is increased. Note that the drain intervening portion 839 may also be formed of a photoresist film in the same manner as described above.

Description of Reference Numerals

[0129] 11… Liquid crystal panel (display device), 20… Opposite substrate, 21, 821… Array substrate, 26α, 126α… First source wiring (third wiring), 26β, 126β… Second source wiring (fourth wiring), 27Bα, 127Bα, 227Bα, 327Bα, 527Bα, 827Bα… First source region (first conductor portion), 27Bβ, 127Bβ, 227Bβ, 327Bβ, 527Bβ, 827Bβ… Second source region (second conductor portion), 27Dα, 127Dα, 827Dα… First semiconductor portion, 27E, 627E, 827E… Upper gate electrode (first electrode), 27Fα, 127Fα… First high-resistance portion, 29α, 329α… First upper gate wiring (first wiring), 29β, 329β… Second upper gate wiring (second wiring), 32, 132, 232, 532, 632, 832… Semiconductor film, 33, 233, 333, 733, 833… Upper gate insulating film (first insulating film), 33Aα, 333Aα, 433Aα… First linear insulating portion, 33Aβ, 333Aβ, 433Aβ… Second linear insulating portion, 33B… First insulating portion, 33Cα… First non-overlapping insulating portion (second insulating portion), 34, 834… Second metal film (first conductive film), 35, 135, 835… First interlayer insulating film (second insulating film), 38, 138, 338, 438, 538, 838… Source intervening portion (intervening portion), 40α, 840α… First source non-conductor portion (first non-conductor portion), 40β, 840β… Second source non-conductor portion (second non-conductor portion), 42α… First intermediate non-conductor portion (third non-conductor portion), 43… First inclined portion, 44… Second inclined portion, 45, 345… Third inclined portion, CH1α, CH101α, CH201α… First source contact hole (first contact hole), CH1β, CH101β, CH201β… Second source contact hole (second contact hole), D1, D2… Distance

Claims

1. A first electrode made of a first conductive film, a first insulating film disposed on the lower layer side with respect to the first conductive film, a first conductive portion formed by making conductive a portion of a semiconductor film disposed on the lower layer side with respect to the first insulating film and non-overlapping with the first electrode, a second conductive portion formed by making conductive a portion of the semiconductor film that does not overlap with the first electrode and is different from the first conductive portion, a first semiconductor portion formed of a portion of the semiconductor film that overlaps with the first electrode, an array substrate comprising: a portion of the first conductive film other than the first electrode or a part of the first insulating film, and an intervening portion disposed between the first conductive portion and the second conductive portion.

2. The first insulating film has a first insulating portion disposed to overlap the first electrode and the first semiconductor portion, The array substrate according to claim 1, wherein the intervening portion is formed of a portion of the first insulating film other than the first insulating portion.

3. The semiconductor film is made of an oxide semiconductor material, a second insulating film disposed on the upper layer side with respect to the first conductive film and containing a reducing agent is provided, The second insulating film is in contact with the first conductive portion and the second conductive portion, The first insulating film has a second insulating portion that does not overlap with the first electrode and the first semiconductor portion and is continuous with the first insulating portion, The array substrate according to claim 2, comprising: a first high-resistance portion formed of a portion of the semiconductor film that overlaps with the second insulating portion, continuous with the first conductive portion, and having a higher resistance than the first conductive portion.

4. The array substrate according to claim 3, wherein a distance from an end on the first conductive portion side to an end on the second conductive portion side of the intervening portion is greater than a distance from an end on the first semiconductor portion side to an end on the first conductive portion side in the first high-resistance portion.

5. a first wiring formed of the first conductive film and extending along a first direction and including the first electrode, a first linear insulating portion formed of the first insulating film, extending along the first direction, overlapping the first wiring, and including the first insulating portion, The first conductive portion and the second conductive portion intersect the first wiring and the first linear insulating portion, The array substrate according to any one of claims 2 to 4, wherein the intervening portion is continuous with the first linear insulating portion.

6. It is composed of the first conductive film and is arranged at a position spaced from the first wiring in a second direction intersecting the first direction, and is a second wiring extending along the first direction, It is composed of the first insulating film and includes a second linear insulating portion that extends along the first direction and overlaps the second wiring, The intervening portion is an array substrate according to claim 5 that is continuous with the second linear insulating portion.

7. The first conductive film is made of a metal material, The intervening portion is an array substrate according to claim 1 that is composed of a portion of the first conductive film different from the first electrode.

8. A second insulating film arranged on the upper layer side with respect to the first conductive film, It is composed of a second conductive film arranged on the upper layer side with respect to the second insulating film, and a third wiring, a part of which overlaps the first conductor portion, It is composed of a portion of the second conductive film different from the third wiring, and a fourth wiring, a part of which overlaps the second conductor portion, In the second insulating film, at a position overlapping both the third wiring and the first conductor portion, a first contact hole connecting the third wiring and the first conductor portion is provided, An array substrate according to any one of claims 1 to 4 and claim 7, wherein in the second insulating film, at a position overlapping both the fourth wiring and the second conductor portion, a second contact hole connecting the fourth wiring and the second conductor portion is provided.

9. The third wiring and the fourth wiring are parallel to each other, The first conductor portion has a first inclined portion inclined with respect to the third wiring and the fourth wiring, The second conductor portion has a second inclined portion parallel to the first inclined portion, The intervening portion is an array substrate according to claim 8 that has a third inclined portion parallel to the first inclined portion and the second inclined portion.

10. The first conductor portion is arranged to partially overlap the first contact hole so as not to overlap the portion of the first contact hole on the second conductor portion side according to claim 8.

11. An array substrate according to any one of claims 1 to 4 and claim 7, A display device comprising an opposing substrate arranged to face the array substrate.

12. A semiconductor film made of an oxide semiconductor material is formed, and by patterning the semiconductor film, a first non-conductive portion, a second non-conductive portion arranged at a distance from the first non-conductive portion, and a first semiconductor portion are provided, A first insulating film is formed on the upper layer side of the semiconductor film, A first conductive film is formed on the upper layer side of the first insulating film, By patterning the first conductive film, a first electrode is provided that overlaps the first semiconductor portion, By patterning the first insulating film, a first insulating portion that overlaps the first electrode and the first semiconductor portion and an intervening portion disposed between the first non-conductivized portion and the second non-conductivized portion are provided, A second insulating film containing a reducing agent is formed on the upper layer side of the first conductive film, and by bringing the second insulating film into contact with the first non-conductivized portion and the second non-conductivized portion, the first non-conductivized portion and the second non-conductivized portion are conductivized to become a first conductivized portion and a second conductivized portion, respectively, a method for manufacturing an array substrate.

13. By patterning the first insulating film, a second insulating portion that is non-overlapping with the first electrode and the first semiconductor portion and is continuous with the first insulating portion is provided, By patterning the semiconductor film, a third non-conductivized portion that overlaps the second insulating portion and is continuous with the first non-conductivized portion is provided, When the second insulating film is formed, the third non-conductivized portion becomes a first high-resistance portion having a higher resistance than the first conductivized portion, the method for manufacturing an array substrate according to claim 12.

14. The method for manufacturing an array substrate according to claim 12 or claim 13, wherein the first insulating film is patterned after the first conductive film is patterned.

15. A semiconductor film is formed, and by patterning the semiconductor film, a first non-conductivized portion, a second non-conductivized portion disposed at an interval from the first non-conductivized portion, and a first semiconductor portion are provided, A first insulating film is formed on the upper layer side of the semiconductor film, A first conductive film is formed on the upper layer side of the first insulating film, and by patterning the first conductive film, a first electrode that overlaps the first semiconductor portion and an intervening portion disposed between the first non-conductivized portion and the second non-conductivized portion are provided, By performing a conductivization process of conductivizing the semiconductor film using the first conductive film as a mask, the first non-conductivized portion and the second non-conductivized portion that are non-overlapping with the first electrode and the intervening portion are conductivized to become a first conductivized portion and a second conductivized portion, respectively, a method for manufacturing an array substrate.

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