Semiconductor device and method of manufacturing the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor chip CP is mounted on a die pad DP via a solder material DB. The semiconductor chip CP includes a plurality of corners including a corner CPC1. A recess portion CCV 1 is formed in the die pad DP at the upper surface DPt of the die pad DP. The semiconductor chip CP is mounted on the die pad DP such that the corner CPC1 is located at an inside of the recess portion CCV1. The corner CPC1 is a corner located farthest from a center of a sealing body, among the plurality of corners. The solder material DB has a portion DBP1 that is located between the semiconductor chip and the bottom surface BS1 of the recess portion CCV1, and a portion DBP2 that is located between the semiconductor chip CP and the upper surface DPt of the die pad DP. The thickness TH1 of the solder material DB in the portion DBP1 is greater than the thickness TH2 of the solder material DB in the portion DBP2.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] There is a technique of forming grooves in order to improve the adhesion to a sealing body on the upper surface of a die pad (see, for example, Patent Document 1). Further, in a semiconductor device in which a semiconductor chip is mounted on a die pad via a soldering material, there is a semiconductor device in which a recessed portion is formed on the outer periphery of the back surface of the semiconductor chip (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device in which a semiconductor chip is mounted on a die pad via a soldering material, it has been found that cracks may occur in the soldering material. The inventor of the present application has studied a technique for preventing or suppressing the occurrence of cracks by devising the structure of the die pad.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an embodiment includes a semiconductor chip having a first upper surface and a first lower surface located on the opposite side of the first upper surface, a die pad having a second upper surface facing the first lower surface and a second lower surface located on the opposite side of the second upper surface, on which the semiconductor chip is mounted, a plurality of leads electrically connected to the semiconductor chip, a metal plate electrically connected to each of the plurality of leads and the semiconductor chip, and a sealing body that seals the semiconductor chip and the metal plate. The semiconductor chip is mounted on the second upper surface of the die pad via a soldering material. In plan view, the semiconductor chip includes a plurality of corners including a first corner. A recess is formed in the second upper surface of the die pad. In a transparent plan view, the semiconductor chip is mounted on the second upper surface of the die pad such that the first corner is located within the recess. In a transparent plan view, the first corner is the corner that is located farthest from the center of the sealing body and away from the metal plate among the plurality of corners. The soldering material has a first portion located between the first lower surface of the semiconductor chip and the bottom surface of the recess, and a second portion located between the first lower surface of the semiconductor chip and the second upper surface of the die pad and at a position different from the first portion. The thickness of the soldering material in the first portion is greater than the thickness of the soldering material in the second portion.

[0007] A method for manufacturing a semiconductor device according to another embodiment includes: (a) a step of preparing a semiconductor chip having a first upper surface and a first lower surface located on the opposite side of the first upper surface; (b) a step of preparing a die pad having a second upper surface and a second lower surface located on the opposite side of the second upper surface, and a lead frame having a plurality of leads disposed apart from the die pad; (c) a step of mounting the semiconductor chip on the die pad via a solder material such that the first lower surface of the semiconductor chip faces the second upper surface of the die pad; (d) a step of electrically connecting the plurality of leads and the semiconductor chip via a metal plate; and (e) a step of sealing the semiconductor chip and the metal plate. The semiconductor chip prepared in the step (a) includes a plurality of corners including a first corner in a plan view. A recess is formed on the second upper surface of the die pad of the lead frame prepared in the step (b). In the step (c), the semiconductor chip is mounted on the second upper surface of the die pad such that the first corner overlaps the recess, and the solder material adheres to the entire first lower surface of the semiconductor chip. After the step (c), the solder material has a first portion located between the first lower surface of the semiconductor chip and the bottom surface of the recess, and a second portion located between the first lower surface of the semiconductor chip and the second upper surface of the die pad and at a position different from the first portion. After the step (c), the thickness of the solder material in the first portion is greater than the thickness of the solder material in the second portion. After the step (e), the first corner of the semiconductor chip is located at a position farthest from the center of the sealing body among the plurality of corners and at a position away from the metal plate.

Effect of the Invention

[0008] According to the above embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] (Explanation of the description format, basic terms, and usage in this application) In this application, the description of the embodiments is divided into a plurality of sections, etc. for convenience as necessary. However, unless otherwise explicitly stated, these are not mutually independent and separate. Regardless of the order of description, each part of a single example, one is a detailed part, a partial or total modification example, etc. of the other. Also, in principle, the description of the same part is omitted repeatedly. Further, each component in the embodiments is not essential unless otherwise explicitly stated, limited in number theoretically, and clearly not so from the context.

[0011] Similarly, in the description of embodiments and the like, with respect to materials, compositions, etc., even when it is stated as "X consisting of A" or the like, unless otherwise explicitly stated or clearly not the case from the context, it does not exclude those containing elements other than A. For example, in terms of components, it means "X containing A as the main component" or the like. For example, even when referring to a "silicon member", it is not limited to pure silicon, but also includes members containing alloys with silicon as the main component such as SiGe (silicon-germanium) alloys, alloys without silicon as the main component such as GaN (gallium nitride) alloys, and other additives. Also, for gold plating, Cu layer, nickel plating, etc., unless otherwise explicitly stated, it includes not only pure ones but also members with gold, Cu, nickel, etc. as the main components.

[0012] Furthermore, when referring to specific numerical values or quantities, unless otherwise explicitly stated, not limited to that number theoretically, or clearly not the case from the context, a numerical value exceeding that specific numerical value or a numerical value less than that specific numerical value may also be acceptable.

[0013] Also, in each figure of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and the description is not repeated in principle.

[0014] Also, in the accompanying drawings, conversely, when it becomes complicated or the distinction from voids is clear, hatching etc. may be omitted even for cross-sections. In connection with this, in cases where it is clear from the description etc., even for a planar closed hole, the background contour line may be omitted. Furthermore, even if it is not a cross-section, hatching or dot patterns may be added to clarify that it is not a void or to clarify the boundary of the region.

[0015] In the embodiments described below, as an example of a semiconductor device, a semiconductor device called a power device or a power semiconductor device incorporated in a power control circuit such as a power supply circuit will be described. The semiconductor device described below is incorporated in a power conversion circuit and functions as, for example, a switching element.

[0016] <Semiconductor device> First, the package structure of the semiconductor device PKG1 shown in FIG. 1 will be described. FIG. 1 is a top view of the semiconductor device of the present embodiment. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 1. FIG. 3 is a perspective plan view showing the internal structure of the semiconductor device with the sealing body shown in FIG. 2 removed. FIG. 4 is a cross-sectional view taken along the line A-A of FIG. 3.

[0017] One of the X direction, Y direction, and Z direction is described in FIGS. 1 to 4. The Y direction is a direction intersecting the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is the normal direction to the X-Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means a plan view as viewed from the X-Y plane.

[0018] The semiconductor device PKG1 of the present embodiment includes a semiconductor chip CP (see FIGS. 3 and 4), a die pad on which the semiconductor chip CP is mounted, a plurality of leads LD electrically connected to the semiconductor chip CP, a die pad DP electrically connected to each of the plurality of leads LD and the semiconductor chip CP, and a sealing body MR that seals the semiconductor chip CP.

[0019] As shown in FIGS. 1 and 2, the sealing body MR forms a quadrilateral in a plan view. In other words, the sealing body MR has four sides in a plan view. The sealing body MR includes an upper surface MRt (see FIG. 1) and a lower surface MRb (see FIG. 4) located on the opposite side of the upper surface MRt. The sealing body MR is an insulator made of resin. The sealing body MR may contain a pigment and inorganic insulating particles (such as silica) in addition to the thermosetting resin.

[0020] In the case of this embodiment, the die pad DP shown in each of FIGS. 2 to 4 functions as a chip mounting portion on which the semiconductor chip CP is mounted. The die pad DP includes an upper surface (surface, chip mounting surface) DPt and a lower surface (surface, exposed surface) DPb located on the opposite side of the upper surface DPt. The lower surface DPb is exposed from the sealing body MR on the lower surface MRb of the sealing body MR. The die pad DP is made of a metal material such as copper or a copper alloy.

[0021] As shown in FIGS. 3 and 4, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP. As shown in FIG. 4, the semiconductor chip CP includes an upper surface (surface, front surface, main surface) Cpt and a lower surface (surface, back surface, main surface) CPb located on the opposite side of the upper surface Cpt. The semiconductor chip CP is mounted on the upper surface DPt via a solder material DB so that the lower surface CPb faces the upper surface DPt of the die pad DP. The solder material DB is a die bonding material for fixing the semiconductor chip on the die pad DP. In the case of this embodiment, the solder material DB has a function of electrically connecting the semiconductor chip CP and the die pad DP. As will be described later as a modification, the solder material DB may contain solder and a plurality of inorganic particles mixed in the solder.

[0022] As will be described later, the semiconductor chip CP of the present embodiment has a power transistor composed of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Hereinafter, as an example, an example of a semiconductor chip CP having a power MOSFET will be taken and described. In the following description, the term "power MOSFET" can be replaced with "IGBT". In this case, the term "drain" is replaced with "collector", and the term "source" is replaced with "emitter", respectively.

[0023] As shown in FIGS. 3 and 4, the semiconductor chip CP has a plurality of pads PD. As shown in FIG. 3, the semiconductor chip CP has a gate electrode pad PDG and a source electrode pad PDS on the upper surface Cpt. Specifically, a plurality of openings are arranged in the insulating film (passivation film) having the upper surface Cpt of the semiconductor chip CP. Each of the gate electrode pad PDG and the source electrode pad PDS is exposed from the insulating film at the above opening. The area of the source electrode pad PDS is larger than the area of the gate electrode pad PDG. The gate electrode pad PDG is an electrode pad connected to the gate electrode of the power MOSFET. The source electrode pad PDS is an electrode pad connected to the source of the power MOSFET.

[0024] Also, as shown in FIG. 4, the semiconductor chip CP has a drain electrode pad PDD formed on the lower surface CPb. The drain electrode pad PDD is formed, for example, over the entire lower surface CPb of the semiconductor chip CP. The drain electrode pad PDD is an electrode pad connected to the drain of the power MOSFET.

[0025] In the case of this embodiment, the die pad DP is electrically connected to the semiconductor chip CP. Specifically, the die pad DP is electrically connected to the drain electrode pad PDD of the semiconductor chip CP via a solder material DB which is a conductive member. The die pad DP is integrally formed with a lead LDD which is a drain lead among a plurality of leads LD shown in FIG. 3. The die pad DP constitutes a flow path for the drain current.

[0026] As shown in FIGS. 3 and 4, each of the plurality of leads LD includes an inner lead portion LDM sealed in the sealing body MR and an outer lead portion LDX exposed from the sealing body MR. As shown in FIG. 1, in a plan view, the plurality of leads LD are arranged only on two opposite sides among the four sides of the sealing body MR. The outer lead portion LDX (see FIG. 3) of each of the plurality of leads LD protrudes outward from the side surface of the sealing body MR.

[0027] As shown in FIG. 3, among the plurality of leads LD, a plurality of source leads LDS are electrically connected to the source electrode pad PDS via a metal plate (clip) MP1. A plate-like member for electrically connecting the semiconductor chip and the lead is called a clip. In this embodiment, as shown in FIG. 3, a configuration in which a plurality of source leads LDS are connected to each other will be described as an example, but the plurality of source leads LDS do not have to be connected to each other. Among the plurality of leads LD, the gate lead LDG is electrically connected to the gate electrode pad PDG via a metal plate (clip) MP2. Among the plurality of leads LD, the lead LDD which is a drain lead is integrally formed with the die pad DP and is electrically connected to the drain electrode pad PDD via the die pad DP.

[0028] When the source lead LDS and the source electrode pad PDS are electrically connected via the metal plate MP1 as in this embodiment, the cross-sectional area of the path of the source current can be increased. Therefore, the resistance of the supply path of the current (source current) flowing through the source electrode pad PDS can be reduced.

[0029] As shown in FIG. 4, the metal plate MP1 includes an upper surface (plane) MP1t and a lower surface (plane) MP1b that is located on the side opposite to the upper surface MP1t and faces the semiconductor chip CP. In the example shown in FIG. 4, the entire metal plate MP1 including the upper surface MP1t is sealed by the sealing body MR. The metal plate MP1 is made of a metal material containing iron such as copper, a copper alloy, or 42 alloy.

[0030] As a modification, the upper surface MP1t may be exposed from the sealing body MR on the upper surface MRt of the sealing body MR. In this case, for example, by connecting a heat dissipation member (not shown) to the upper surface MP1t, the heat dissipation characteristics of the semiconductor device can be improved. Alternatively, by connecting a terminal for source current (not shown) to the upper surface MP1t, the terminal can be used as a supply path for the source current.

[0031] The metal plate MP1 is electrically connected to the source electrode pad PDS via the conductive member CM1. The conductive member CM1 is joined to the lower surface MP1b of the metal plate MP1 and the upper surface of the source electrode pad PDS. Also, it is electrically connected to the lead LDS via the conductive member CM2. The conductive member CM2 is joined to the lower surface MP1b of the metal plate MP1 and the upper surface of the lead LDS. Each of the conductive member CM1 and the conductive member CM2 is made of, for example, solder or a conductive resin. The conductive resin is a resin in which a plurality of conductive particles are mixed in a resin component containing a thermosetting resin such as an epoxy resin.

[0032] Although the cross-sectional structure of the metal plate MP2 that electrically connects the gate lead LDG and the gate electrode pad PDG shown in FIG. 3 is not shown, it is electrically connected to each of the lead LDG and the gate electrode pad PDG via a conductive member (a member similar to the conductive member CM1 or the conductive member CM2 in FIG. 4) in the same manner as the metal plate MP1 shown in FIG. 4.

[0033] Although illustration is omitted, as a modification example of the present embodiment, a wire may be used instead of the metal plate MP2 shown in FIG. 3 as a conductive member for electrically connecting the lead LDG for the gate and the gate electrode pad PDG. The gate current flowing through the gate electrode pad PDG is a signal current that controls the switching operation of the transistor. Therefore, the cross-sectional area of the path of the gate current may be smaller compared to the cross-sectional area of the source current.

[0034] However, when the lead LDG for the gate and the gate electrode pad PDG are electrically connected via the metal plate MP2 as in the present embodiment, the waveform quality of the gate signal is improved compared to the case where the lead LDG and the gate electrode pad PDG are electrically connected via a wire (not shown). That is, from the viewpoint of improving the waveform quality of the gate signal, it is preferable that the lead LDG and the gate electrode pad PDG are electrically connected via the metal plate MP2 as in the present embodiment.

[0035] Alternatively, when the lead LDG for the gate and the gate electrode pad PDG are electrically connected via the metal plate MP2, the metal plate MP1 and the metal plate MP2 can be fixed together at the same timing. Therefore, when the lead LDS for the source and the source electrode pad PDS are electrically connected via the metal plate MP1 as in the present embodiment, it is preferable that the lead LDG and the gate electrode pad PDG are electrically connected via the metal plate MP2 in terms of improving the manufacturing efficiency of the semiconductor device. <Circuit configuration example> Next, a configuration example of the circuit included in the semiconductor device PKG1 shown in FIG. 3 and an example of the element structure of the transistor will be described. FIG. 5 is an explanatory diagram schematically showing an example of the circuit included in the semiconductor device shown in FIG. 1. FIG. 6 is a cross-sectional view of a main part showing an example of the element structure of the field effect transistor shown in FIG. 5.

[0036] Semiconductor devices for power control called power semiconductor devices include those having semiconductor elements such as diodes, thyristors, or transistors. Transistors are used in various fields. However, like in this embodiment, a transistor incorporated in a power control circuit where a large current of, for example, 1 A (ampere) or more flows and operates as a switching element is called a power transistor. As shown in FIG. 5, the semiconductor device PKG1 of this embodiment has a semiconductor chip CP including a transistor Q1 that is a power transistor. In the examples shown in FIGS. 5 and 6, the transistor Q1 included in the semiconductor chip CP is a field-effect transistor, specifically, a MOSFET. In a power semiconductor device, a transistor is used as, for example, a switching element. A MOSFET used in a power semiconductor device is called a power MOSFET.

[0037] The above-described MOSFET is described as a general term widely representing a field-effect transistor having a gate electrode made of a conductive material disposed on a gate insulating film. Therefore, even when described as a MOSFET, it does not exclude a gate insulating film other than an oxide film. Also, even when described as a MOSFET, it does not exclude a gate electrode material other than metal, such as polysilicon.

[0038] Also, the transistor Q1 shown in FIG. 5 is formed of, for example, an n-channel type field-effect transistor as shown in FIG. 6. FIG. 6 is a cross-sectional view of a main part showing an example of the element structure of the field-effect transistor shown in FIG. 5.

[0039] In the example shown in FIG. 6, an n-type epitaxial layer EP is formed on the main surface WHt of a semiconductor substrate WH made of, for example, n-type single-crystalline silicon. The semiconductor substrate WH and the epitaxial layer EP constitute the drain region of the MOSFET (the region corresponding to the drain D shown in FIG. 5). This drain region is electrically connected to a drain electrode pad PDD formed on the back surface of the semiconductor chip CP.

[0040] On the epitaxial layer EP, a channel formation region CH, which is a p+-type semiconductor region, is formed. On this channel formation region CH, a source region SR (a region corresponding to the source S shown in FIG. 5), which is an n+-type semiconductor region, is formed. The source region SR is electrically connected to the source electrode pad PDS of the semiconductor chip CP via a lead wiring. Further, in the semiconductor region laminated on the semiconductor substrate WH, a trench (opening, groove) TR1 is formed which penetrates the channel formation region CH from the upper surface of the source region SR and reaches the inside of the epitaxial layer EP.

[0041] Further, a gate insulating film GI is disposed on the inner wall of the trench TR1. Further, on the gate insulating film GI, a gate G laminated so as to fill the trench TR1 is disposed. The gate G is electrically connected to the gate electrode pad PDG of the semiconductor chip CP via a lead wiring.

[0042] Further, in the case of the transistor Q1, since the drain region and the source region SR are disposed in the thickness direction with the channel formation region CH interposed therebetween, a channel is formed in the thickness direction (hereinafter referred to as a vertical channel structure). In this case, compared with a field effect transistor in which a channel is formed along the main surface WHt, the occupied area of the element in a plan view can be reduced. For this reason, the planar size of the semiconductor chip CP can be reduced.

[0043] Further, in the case of the above-described vertical channel structure, in a plan view, the channel width per unit area can be increased, so that the on-resistance can be reduced. Note that FIG. 6 is a diagram showing the element structure of a field effect transistor. In the semiconductor chip CP shown in FIG. 5, a plurality (a large number) of transistors Q1 having an element structure as shown in FIG. 6, for example, are connected in parallel. Thereby, for example, a power MOSFET through which a large current exceeding 1 ampere flows can be configured.

[0044] As described above, when a MOSFET is configured by connecting a plurality of transistors Q1 having a vertical channel structure in parallel, the electrical characteristics of the MOSFET (mainly breakdown voltage characteristics, on-resistance characteristics, and capacitance characteristics) vary according to the planar size of the semiconductor chip CP. For example, if the planar area of the semiconductor chip CP is increased, the number of cells (i.e., the number of elements) of the transistors Q1 connected in parallel increases, so the on-resistance decreases and the capacitance increases.

[0045] In FIGS. 5 and 6, a MOSFET is illustrated as an example of the power transistor included in the power semiconductor device, but various modifications can be applied. For example, instead of a MOSFET, an insulated gate bipolar transistor (IGBT) may be provided.

[0046] Also, in the example shown in FIG. 6, the transistor having a vertical channel structure is illustrated as an example, but it can be replaced with a transistor having a horizontal channel structure. In this case, the drain electrode pad PDD is disposed on the upper surface CPT of the semiconductor chip CP (see FIG. 3). Therefore, the drain lead LDD shown in FIG. 3 and the drain electrode pad PDD (see FIG. 6) connected to the drain of the transistor having a horizontal channel structure are electrically connected via a wire (drain wire) not shown.

[0047] <Regarding the crack of the solder material> Next, the causes of cracks occurring in the solder material DB shown in FIGS. 3 and 4 and countermeasures therefor will be described. In the following description, the semiconductor device described as an examination example for the present embodiment is the same as the semiconductor device PKG1 shown in FIGS. 3 and 4, except that the entire upper surface DPT of the die pad DP is a flat surface. For this reason, the illustration of the semiconductor device of the examination example is omitted, and the components of the semiconductor device PKG1 shown in FIGS. 1 to 4 are used for explanation as necessary.

[0048] When the inventors of the present application examined the semiconductor device which is an example for examination, it was found that cracks may occur in a part of the solder material DB shown in FIG. 3 due to a temperature cycle load applied after the semiconductor device is completed. Further, it was found that when a temperature cycle load is further applied after cracks occur in a part of the solder material DB, the range of the cracks spreads starting from the location where the cracks first occurred.

[0049] As described above, since the solder material DB has a function as a conductive member that electrically connects the semiconductor chip CP and the die pad DP, when cracks progress over a wide range of the solder material DB, it causes a decrease in the electrical characteristics of the semiconductor device.

[0050] Alternatively, since the solder material DB has a function as a fixing member that fixes the semiconductor chip CP on the die pad DP, when cracks progress over a wide range of the solder material DB, the performance of the semiconductor device may decrease due to a decrease in the fixing strength of the semiconductor chip CP.

[0051] Therefore, the inventors of the present application further examined the technology for suppressing the occurrence of cracks. As a result of this examination, it was found that there are several structural features at the location where cracks first occur.

[0052] First, when the semiconductor chip is a polygon having a plurality of corners in a plan view, like the semiconductor chip CP shown in FIG. 3, it was found that cracks occur in the vicinity of any of the plurality of corners. For example, in the case of the example shown in FIG. 3, in a plan view, the semiconductor chip CP forms a quadrilateral having corners CPC1, CPC2, CPC3, and CPC4.

[0053] Cracks generated due to temperature cycle loading are considered to occur as follows. That is, due to the repeated temperature increase and decrease, stress is repeatedly applied around the bonding interface of members with different coefficients of linear expansion (the bonding interface between the semiconductor chip CP and the solder material DB shown in Fig. 4). When an external force exceeding the strength limit of the solder material DB is applied near the location where this stress concentrates, cracks occur in the solder material DB.

[0054] Also, when the semiconductor chip is a polygon with a plurality of corners, stress concentration is likely to occur near each corner. For this reason, when the semiconductor chip is a polygon with a plurality of corners, it is considered that cracks are likely to occur at each corner.

[0055] Second, it was found that cracks are particularly likely to occur near a specific corner among the plurality of corners of the semiconductor chip. Specifically, it was found that cracks are particularly likely to occur near the corner that is at the position farthest from the center of the encapsulant among the plurality of corners of the semiconductor chip. For example, in the case of the example shown in Fig. 3, in the transmission plan view, among the four corners (corner CPC1, corner CPC2, corner CPC3, and corner CPC4) of the semiconductor chip CP, corner CPC1 is the corner at the position farthest from the center MRC of the encapsulant MR. Therefore, when cracks occur in the solder material DB, they are particularly likely to occur near corner CPC1.

[0056] However, according to the study of the inventor of the present application, even for the corner located farthest from the center MRC of the sealing body MR, when that corner is covered by the metal plate MP1 via the conductive member CM1 (see FIG. 4), or when that corner is located in the vicinity of the metal plate MP1, it has also been found that cracks are less likely to occur. For example, in the case of the example shown in FIG. 3, the corner CPC1 is a corner located at a position away from the metal plate MP1. "The corner CPC1 is a corner located at a position away from the metal plate MP1" can be rephrased as "in a transmission plan view, the corner CPC1 does not overlap with the metal plate MP1". If, in a transmission plan view, the corner CPC1 is covered by the metal plate MP1 via the conductive member CM1 (see FIG. 4), cracks are less likely to occur in the vicinity of the corner CPC1, but in the case of the example shown in FIG. 3, cracks are likely to occur.

[0057] In the case of the example shown in FIG. 3, strictly speaking, the distance from the center MRC of the sealing body MR to the corner CPC1 in a transmission plan view is longer than the distance from the center MRC of the sealing body MR to the corner CPC4. However, the difference is within 3 percent with respect to the distance from the center MRC of the sealing body MR to the corner CPC1, and the distance from the center MRC of the sealing body MR to the corner CPC1 and the distance from the center MRC of the sealing body MR to the corner CPC4 in a transmission plan view can be regarded as substantially the same as each other.

[0058] In this case, as a modification example, as in the semiconductor device PKG4 shown in FIG. 13 described later, it is preferable that a recess CCV1 is formed at a position overlapping the corner CPC1 and a recess CCV4 is formed at a position overlapping the corner CPC4.

[0059] On the other hand, in the case of the semiconductor device PKG1 shown in FIG. 3, for the following reasons, the recess is not provided at a position overlapping the corner CPC4, but is provided only at a position overlapping the corner CPC1.

[0060] That is, when there are a plurality of corners where the first element, the "distance from the center MRC of the sealing body MR", is equal (or can be regarded as substantially equal) to each other, cracks are likely to occur in the vicinity of the corner located at a position far from the second element, the "distance from the metal plate MP1". In the case of the example shown in FIG. 3, in the transmission plan view, the corner CPC1 is arranged at the position farthest from the metal plate MP1 among the plurality of corners of the semiconductor chip CP. In the comparison between the corner CPC1 and the corner CPC4, in the transmission plan view, the corner CPC1 is located farther from the metal plate MP1 than the corner CPC4. Moreover, the difference is not a few percent, and the shortest distance from the corner CPC1 to the metal plate MP1 is more than twice the shortest distance from the corner CPC4 to the metal plate MP1. In this case, the corner CPC1 cannot be regarded as being located near the metal plate MP1. And the frequency of crack generation is higher in the vicinity of the corner CPC1 than in the vicinity of the corner CPC4. For this reason, in the comparison between the corner CPC1 and the corner CPC4, a recess CCV1, which is a crack suppression measure, is preferentially provided at the corner CPC1.

[0061] Also, although not shown in the figure, as a modification of FIG. 3, there is a case where the corner CPC1 is covered with the metal plate MP1 via the conductive member CM1 (see FIG. 4). In this case, cracks are likely to occur in the vicinity of the corner CPC4, which is located far from the center MRC of the sealing body MR and away from the metal plate MP1, next to the corner CPC1. Considering the case where a part of the plurality of corners is covered with the metal plate MP1, the following can be said. That is, in the case of the example shown in FIG. 3, the corner CPC1 is the corner arranged at the position farthest from the center MRC of the sealing body MR among the plurality of corners of the semiconductor chip CP located away from the metal plate MP1 in the transmission plan view.

[0062] As described above, through the study of the inventor of the present application, the locations where cracks are likely to occur in the solder material DB have been identified. Therefore, by taking measures at least for the locations where cracks are likely to occur, the risk of crack generation can be reduced.

[0063] Next, measures for suppressing the occurrence of cracks will be described. FIG. 7 is an enlarged plan view showing the peripheral structure of a corner located at the position farthest from the center of the sealing body among the semiconductor chips shown in FIG. 3. FIG. 8 is an enlarged cross-sectional view taken along line B-B of FIG. 7. FIG. 9 is an enlarged cross-sectional view showing the peripheral structure of a corner located at the position closest to the center of the sealing body among the semiconductor chips shown in FIG. 3. FIG. 10 is a plan view of the recess shown in FIG. 8 viewed from above the die pad. Note that FIG. 9 shows a cross-sectional plane passing through corner CPC2 of FIG. 3.

[0064] As shown in FIGS. 7 and 8, a recess CCV1 is formed in the upper surface DPt of the die pad DP. As shown in FIG. 7, in a transmission plan view, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that the corner CPC1 overlaps with the recess CCV1 (i.e., the corner CPC1 is located within the recess CCV1).

[0065] As shown in FIG. 8, the solder material DB has a portion DBP1 located between the lower surface CPb of the semiconductor chip CP and the bottom surface BS1 of the recess CCV1, and a portion DBP2 located between the lower surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP and at a position different from that of the portion DBP1. The thickness TH1 of the solder material DB in the portion DBP1 is greater than the thickness TH2 of the solder material DB in the portion DBP2.

[0066] In other words, in the case of this embodiment, a recess CCV1 is formed in the upper surface DPt of the die pad DP at a position overlapping with the corner CPC1 of the semiconductor chip CP, and the solder material DB is embedded in the recess CCV1. As a result, the thickness of the solder material DB is locally thicker at the position overlapping with the corner CPC1 of the semiconductor chip CP, where the thickness TH1 is greater than the thickness TH2 at other portions (for example, the portion DBP2).

[0067] When the solder material DB has a locally thick portion (for example, the portion DBP1 in FIG. 8), the stress relaxation performance in the thick portion is improved. In the case of this embodiment, due to the stress concentration caused by the temperature cycle load, the portion DBP1 which is a thick portion is set as the portion where cracks are likely to occur. As a result, the occurrence of cracks in the portion DBP1 can be suppressed. Further, when stress concentration occurs in the portion DBP1, the stress around the portion DBP1 is relaxed. Therefore, by taking measures to suppress crack generation in the portion DBP1 where stress concentration is likely to occur, the occurrence of cracks can be suppressed including the peripheral portion of the portion DBP1.

[0068] In the case of this embodiment, the thickness of the portion DBP1 that overlaps with the corner CPC1 of the semiconductor chip CP, which is the location most likely to have cracks, is selectively thickened. No recess is formed in the portion of the upper surface DPt of the die pad DP other than the recess CCV1. For example, among the plurality of corners of the semiconductor chip CP shown in FIG. 3, no recess CCV1 is formed at the position overlapping with the corner CPC2 arranged at the position closest to the center MRC of the sealing body MR. In other words, in the transmission plan view, the corner CPC2 is arranged outside the recess CCV1. Therefore, as shown in FIG. 9, the shortest distance LC2 from the corner CPC2 of the lower surface CPb of the semiconductor chip CP to the upper surface DPt of the die pad DP is smaller than the thickness TH1 of the portion DBP1 shown in FIG. 8. The shortest distance LC2 from the corner CPC2 of the lower surface CPb of the semiconductor chip CP to the upper surface DPt of the die pad DP is the same as the thickness TH2 of the portion DBP2 shown in FIG. 8.

[0069] Also, in the example shown in FIG. 3, no recess CCV1 is formed at the position overlapping with the corner CPC3 of the semiconductor chip CP and at the position overlapping with the corner CPC4 on the upper surface of the die pad DP. Although not shown, the thickness of the solder material DB at the position overlapping with the corner CPC3 of the semiconductor chip CP and at the position overlapping with the corner CPC4 shown in FIG. 3 is the same as the thickness TH2 shown in FIG. 8.

[0070] Note that, as will be described later, as a modification of the present embodiment, there may be a case where recesses are formed at positions overlapping with respective corners of the semiconductor chip CP. Compared with the semiconductor device which is a modification, in the case of the semiconductor device PKG1 shown in FIG. 3, in the die bonding process, among the plurality of corners, it is only necessary to align the corner CPC1 so as to overlap with the recess CCV1. Therefore, it is preferable in that the alignment is easier compared with a modification in which alignment is performed between each of the plurality of corners and the plurality of recesses.

[0071] In the case of the present embodiment, the recess CCV1 shown in FIGS. 7, 8, and 10 is formed by irradiating a laser on the upper surface DPt of the die pad DP. As a modification of the present embodiment, a method of forming the recess CCV1 by press working using a molding die can be exemplified. In the case of the method of forming the recess CCV1 by laser irradiation, it is preferable in that unevenness and distortion are less likely to occur on the upper surface DPt around the recess CCV1 compared with the method of forming the recess CCV1 by press working.

[0072] Also, in the case of the present embodiment, the recess CCV1 is formed by scanning a laser having a spot diameter smaller than the opening diameter (or opening width) of the recess CCV1. In this case, it is preferable in that the opening area and depth of the recess CCV1 can be controlled with high precision.

[0073] As described above, when the recess CCV1 is formed by scanning a laser having a spot diameter smaller than the opening diameter or opening width of the recess CCV1, a recess CCV1 having a shape as shown in FIGS. 8 and 10 can be obtained. That is, as shown in FIG. 8, groove-shaped unevenness is formed on the bottom surface BS1 of the recess CCV1.

[0074] Also, in the example shown in FIG. 10, in a plan view, the outer edge of the concave portion CCV1 forms a circle, and the groove-shaped unevenness forms a spiral shape. The opening diameter ID1 of the concave portion CCV1 is, for example, about 400 μm. The shape shown in FIG. 10 can be obtained when irradiating continuously so as to draw a circle from the center of the concave portion CCV1 toward the outer edge, or when irradiating continuously so as to draw a circle from the outer edge of the concave portion CCV1 toward the center. In this case, the plurality of convex portions CNV are continuously connected. Also, the plurality of groove portions TR are continuously connected.

[0075] Also, as shown in FIG. 8, the thickness TH1 of the portion DBP1 is defined as the shortest distance from the tip of the convex portion CNV to the lower surface CPb of the semiconductor chip CP among the bottom surface BS1. From the viewpoint of exerting the stress relaxation function in the portion DBP1, the height difference HT1 between the convex portion CNV on the bottom surface BS1 of the concave portion CCV1 and the upper surface DPt of the die pad DP is preferably 30 μm or more.

[0076] <Modification example of the layout of the semiconductor chip> Hereinafter, a modification example of the semiconductor device described with reference to FIGS. 1 to 10 will be described. First, a modification example when the planar size of the semiconductor chip is different will be described. FIG. 11 is a perspective plan view showing the internal structure of a semiconductor device which is a modification example of FIG. 3. FIG. 12 is a perspective plan view showing the internal structure of another modification example of the semiconductor device with respect to FIG. 3. Each of the semiconductor device PKG2 shown in FIG. 11 and the semiconductor device PKG3 shown in FIG. 12 is the same as the semiconductor device PKG1 described with reference to FIGS. 1 to 9 except for the differences described below. Therefore, overlapping explanations will be omitted.

[0077] Each of the semiconductor device PKG2 shown in FIG. 11 and the semiconductor device PKG3 shown in FIG. 12 has a different planar size of the semiconductor chip from the semiconductor device PKG1 shown in FIG. 3. Each of the semiconductor chip CPA shown in FIG. 11 and the semiconductor chip CPB shown in FIG. 12 has a smaller planar size (area in a plan view) than the semiconductor chip CPB shown in FIG. 3. On the other hand, the planar size of the die pad DP is the same as in the example shown in FIG. 3.

[0078] In the case of the semiconductor device PKG2 and the semiconductor device PKG3, by shortening the distance between the lead LDS for the source and the source electrode pad PDS, the resistance of the conductive path including the metal plate MP1 can be reduced. Therefore, when the area of the semiconductor chip CPA (or the semiconductor chip CPB shown in FIG. 12) is smaller than the area of the die pad DP, the semiconductor chip CPA is mounted at a position closer to the lead LDS for the source than the center of the die pad DP. For this reason, the magnitude relationship of the distances from the center MRC of the sealing body MR to each of the plurality of corners of the semiconductor chip may be different from the example shown in FIG. 3.

[0079] That is, in the case of the semiconductor device PKG2 shown in FIG. 11, among the four corners (corner CPC1, corner CPC2, corner CPC3, and corner CPC4) of the semiconductor chip CPA, the corner CPC3 is arranged at the position farthest from the center MRC of the sealing body MR. Similarly, in the case of the semiconductor device PKG3 shown in FIG. 12, among the four corners (corner CPC1, corner CPC2, corner CPC3, and corner CPC4) of the semiconductor chip CPB, the corner CPC3 is arranged at the position farthest from the center MRC of the sealing body MR. Also, the corner CPC3 is arranged at a position away from the metal plate MP1.

[0080] In the case of the modified examples shown in FIGS. 11 and 12, cracks are likely to occur in the die pad DP around the position overlapping with the corner CPC3 among the corners CPC1, CPC2, CPC3, and CPC4. Therefore, in the case of the modified examples shown in FIGS. 11 and 12, a recess CCV3 is formed at the position on the upper surface DPt of the die pad DP that overlaps with the corner CPC3 where cracks are likely to occur. In other words, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that the corner CPC3 is located within the recess CCV3 in a plan view through transmission. Note that the shape and dimension examples of the recess CCV3 shown in FIGS. 11 and 12 are the same as the shape and dimension examples of the recess CCV1 described with reference to FIGS. 8 and 10. Since the recess CCV3 is the same as the recess CCV1 except that the position where it is arranged on the upper surface DPt of the die pad DP is different from the recess CCV1 shown in FIGS. 8 and 10, duplicate explanations are omitted.

[0081] In the case of the modification examples shown in FIGS. 11 and 12, in a perspective plan view, if the semiconductor chip CPA (or semiconductor chip CPB) is mounted on the die pad DP such that at least the corner CPC3 where cracks are most likely to occur and the recess CCV3 overlap, the occurrence of cracks can be suppressed. However, as will be described later, there may be cases where a recess is formed at a position overlapping other than the corner CPC3.

[0082] <Modification Example of the Layout of the Recess> Next, a modification example of the layout of the recess shown in FIG. 3 will be described. FIG. 13 is a perspective plan view showing the internal structure of a semiconductor device which is another modification example with respect to FIG. 3. FIG. 14 is an enlarged cross-sectional view showing the peripheral structure of each of a plurality of corners of the semiconductor chip shown in FIG. 13. FIG. 15 is a perspective plan view showing the internal structure of a semiconductor device which is a modification example with respect to FIG. 13. FIG. 16 is a plan view of the die pad showing a state where the solder material, the semiconductor chip, and the metal plate shown in FIG. 15 are removed. Each of the semiconductor device PKG4 shown in FIG. 13 and the semiconductor device PKG5 shown in FIG. 15 is the same as the semiconductor device PKG1 described with reference to FIGS. 1 to 9 except for the differences described below. Therefore, duplicate descriptions will be omitted.

[0083] Each of the semiconductor device PKG4 shown in FIG. 13 and the semiconductor device PKG5 shown in FIG. 15 is different from the semiconductor device PKG1 shown in FIG. 3 in that a plurality of recesses are formed on the upper surface DPt of the die pad DP. As described above, cracks in the solder material DB are likely to occur in the vicinity of a specific corner among a plurality of corners of the semiconductor chip CP. Therefore, by providing the recess CCV1 at a position overlapping the specific corner on the upper surface DPt of the die pad DP, the occurrence of cracks can be suppressed.

[0084] However, it has been found by simulation that stress tends to be high in the vicinity of each of the plurality of corners of the semiconductor chip CP. Therefore, from the viewpoint of suppressing crack generation, it is preferable that recesses are provided at positions overlapping each of the plurality of corners, as in the semiconductor device PKG4 shown in FIGS. 13 and 14. In other words, it is preferable that the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that each of the plurality of corners is located within a recess in a plan view through transmission.

[0085] As shown in FIG. 13, the plurality of corners of the semiconductor chip CP included in the semiconductor device PKG4 include a corner CPC1, a corner CPC2, a corner CPC3, and a corner CPC4. A plurality of recesses including a recess CCV1 are formed on the upper surface DPt of the die pad DP. The plurality of recesses include a recess CCV1, a recess CCV2, a recess CCV3, and a recess CCV4.

[0086] In a plan view through transmission, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that the corner CPC1 is located within the recess CCV1, the corner CPC2 is located within the recess CCV2, the corner CPC3 is located within the recess CCV3, and the corner CPC4 overlaps the recess CCV4.

[0087] As shown in FIG. 14, the solder material DB has a portion DBP1 located between the lower surface CPb of the semiconductor chip CP and the bottom surface BS1 of the recess CCV1, a portion DBP3 located between the lower surface CPb and the bottom surface BS2 of the recess CCV2, a portion DBP4 located between the lower surface CPb and the bottom surface BS3 of the recess CCV3, a portion DBP5 located between the lower surface CPb and the bottom surface BS4 of the recess CCV4, and a portion DBP2 located between the lower surface CPb and the upper surface DPt of the die pad and at a position different from each of the portions DBP1, DBP3, DBP4, and DBP5.

[0088] The thickness of the solder material DB in the partial DBP1, the thickness of the solder material DB in the partial DBP3, the thickness of the solder material DB in the partial DBP4, and the thickness TH1 of the solder material DB in the partial DBP5 are each greater than the thickness TH2 of the solder material DB in the partial DBP2.

[0089] In the case of the semiconductor device PKG4, since recesses are provided at a plurality of positions where stress is likely to increase, the solder material DB has a plurality of thick portions. Thereby, stress can be relaxed at a plurality of positions where stress is likely to increase, so that the certainty of preventing the occurrence of cracks can be improved.

[0090] On the other hand, as described above, from the viewpoint of ease of alignment, as described with reference to FIGS. 3, 11, and 12, it is particularly preferable to arrange the recesses only at specific positions where cracks are likely to occur.

[0091] Although not shown, as a further modification of this modification example, there may be a case where recesses are selectively formed at positions overlapping two or three of the four corners of the semiconductor chip CP shown in FIG. 13. According to the study of the inventor of the present application, among the four corners of the semiconductor chip CP, the corner having a longer distance from the center MRC of the sealing body MR is more likely to cause cracks. Therefore, as a modification example of the example shown in FIG. 13, for example, only the recess CCV1, the recess CCV3, and the recess CCV4 may be provided.

[0092] In the case of the semiconductor device PKG5 shown in FIG. 15, the plurality of recesses include recess FIG. 9 that is disposed at a position that does not overlap any of the plurality of corners of the semiconductor chip CP in a perspective plan view. In the example shown in FIG. 15, a plurality of recesses CCV5 are formed on the upper surface DPt of the die pad DP. For example, when the semiconductor chip CPA shown in FIG. 11 is mounted on the die pad DP, either or both of the corners CPC1 and CPC4 of the semiconductor chip CPA are disposed at a position that overlaps any of the plurality of recesses CCV5. Also, for example, when the semiconductor chip CPB shown in FIG. 12 is mounted on the die pad DP, any or all of the corners CPC1, CPC2, and CPC4 of the semiconductor chip CPB are disposed at a position that overlaps any of the plurality of recesses CCV5.

[0093] Each of the recesses CCV2, recesses CCV3, recesses CCV4, and recesses CCV5 illustrated in any of FIGS. 13, 14, 15, and 16 is the same as the recess CCV1 except that the position where it is disposed on the upper surface DPt of the die pad DP is different from that of the recess CCV1 shown in FIGS. 8 and 10, and thus redundant descriptions are omitted.

[0094] In the case of the semiconductor device PKG5, since a plurality of types of semiconductor chips can be mounted on one type of die pad DP, the versatility of the die pad DP (in other words, the versatility of the lead frame) can be improved.

[0095] <Modification Example of the Shape of the Recess> Next, a modification example of the shape of the recess shown in FIG. 3 will be described. FIG. 17 is a perspective plan view showing the internal structure of a semiconductor device that is another modification example with respect to FIG. 13. FIG. 18 is an enlarged plan view showing an enlarged portion of the groove-shaped recess shown in FIG. 17. FIG. 19 is an enlarged cross-sectional view taken along line C-C of FIG. 18. The semiconductor device PKG6 shown in FIGS. 17 to 19 is the same as the semiconductor device PKG4 shown in FIG. 13 except for the differences described below. Therefore, redundant descriptions are omitted.

[0096] The semiconductor device PKG6 is different from the semiconductor device PKG4 shown in FIG. 13 in that the shape of the recess CCV6 formed on the upper surface DPt of the die pad DP extends in a groove shape.

[0097] The semiconductor chip CP can be expressed as follows. That is, in a plan view, the semiconductor chip CP has four sides. In the example shown in FIG. 17, the semiconductor chip CP includes a side CPS1 extending in the X direction, a side CPS2 extending in the Y direction, a side CPS3 extending in the X direction and located on the opposite side of the side CPS1, and a side CPS4 extending in the Y direction and located on the opposite side of the side CPS2.

[0098] The four corners of the semiconductor chip CP are the intersections of any two of the four sides. In the example shown in FIG. 17, the corner CPC1 is the intersection of the side CPS1 and the side CPS2. The corner CPC2 is the intersection of the side CPS3 and the side CPS4. The corner CPC3 is the intersection of the side CPS2 and the side CPS3. The corner CPC4 is the intersection of the side CPS1 and the side CPS4.

[0099] The recess CCV6 formed on the upper surface DPt of the die pad DP of the semiconductor device PKG6 extends in a groove shape so as to form a rectangular frame shape in a plan view. Further, in a transparent plan view, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that each of the plurality of corners and the four sides overlap with the recess CCV6.

[0100] As already described, cracks in the solder material DB are likely to occur in the vicinity of a specific corner among the plurality of corners of the semiconductor chip CP. Therefore, by providing the recess CCV1 at a position overlapping the specific corner on the upper surface DPt of the die pad DP, the occurrence of cracks can be suppressed.

[0101] However, it has been found by simulation that in the vicinity of the periphery of the semiconductor chip CP (the outer edge of the semiconductor chip CP in plan view), the stress tends to be high next to the vicinity of a plurality of corners. Therefore, from the viewpoint of suppressing crack generation, it is preferable that recesses CCV6 are provided at positions overlapping each of the plurality of corners and the plurality of sides, as in the semiconductor device PKG6 shown in FIGS. 17 to 19.

[0102] The groove-shaped recess CCV6 shown in FIGS. 17 to 19 is formed by laser irradiation in the same manner as the recess CCV1 shown in FIGS. 8 and 10 described above. However, since the opening shape of the recess CCV6 is rectangular instead of circular, for example, the laser is irradiated along the extending direction of the groove of the recess CCV6.

[0103] Also, in the case of this embodiment, the recess CCV6 is formed by scanning a laser having a spot diameter smaller than the opening width W1 (see FIG. 18) of the recess CCV6. The opening width W1 is, for example, about 400 μm. The opening width W1 is defined as the opening length in a direction orthogonal to the extending direction of the recess CCV6.

[0104] As described above, when the recess CCV6 is formed by scanning a laser having a spot diameter smaller than the opening width W1 of the recess CCV6, a recess CCV6 having a shape as shown in FIG. 19 is obtained. That is, as shown in FIG. 19, groove-shaped irregularities are formed on the bottom surface BS6 of the recess CCV6.

[0105] Although illustration is omitted, there are various modifications in the extending direction of the plurality of convex portions CNV shown in FIG. 19. For example, in the example shown in FIG. 19, the plurality of irregularities extend along the extending direction of the recess CCV6 having a frame shape. However, as a modification, there may be a case where the convex portion CNV extends in the width direction of the groove-shaped recess CCV6 (the direction shown as the opening width W1).

[0106] In the example shown in FIG. 17, the recess CCV6 overlaps all the corners and all the sides of the semiconductor chip CP. As a modification, the shape of a part of the recess CCV6 shown in FIG. 17 may be replaced with the shape of the recess CCV1 shown in FIG. 3, or the shapes of the recesses CCV2, CCV3, and CCV4 shown in FIG. 13.

[0107] <Modification Example of Solder Material> Next, a modification example of the solder material shown in FIG. 4 will be described. FIG. 20 is a cross-sectional view of a semiconductor device that is a modification example of FIG. 4. The semiconductor device PKG7 shown in FIG. 20 is the same as the semiconductor device PKG1 described with reference to FIGS. 1 to 9, except for the differences described below. Therefore, redundant descriptions will be omitted.

[0108] The semiconductor device PKG7 differs from the semiconductor device PKG1 shown in FIG. 4 in the material constituting the solder material DB. That is, the solder material DB included in the semiconductor device PKG7 includes a solder SD and a plurality of fillers (inorganic material particles) FL mixed in the solder SD. Examples of the filler FL include silica particles.

[0109] In each of the plurality of embodiments already described, a recess is provided at a position overlapping the outer edge of the semiconductor chip CP in a transmission plan view. When the lower surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP are mounted in parallel, by improving the processing accuracy of the recess, the thickness TH1 of the portion DBP1 shown in FIG. 8 can be made closer to the design value.

[0110] However, if the semiconductor chip CP is mounted in an inclined state with respect to the upper surface DPt of the die pad DP due to the formation of the recess, the value of the thickness TH1 of the portion DBP1 may deviate from the allowable range.

[0111] Therefore, in the case of this modification example, a plurality of fillers FL are mixed in the solder material DB so that the lower surface CPb of the semiconductor chip CP and the upper surface DPt of the die pad DP can be regarded as being substantially parallel.

[0112] The particle diameters of the plurality of fillers FL are, for example, about 20 μm to 40 μm. This value is determined based on the designed value of the separation distance between the lower surface CPb and the upper surface DPt after the semiconductor chip CP is mounted on the die pad DP. When the solder material DB contains the plurality of fillers FL, the fillers FL function as spacer members. As a result, it is possible to suppress the semiconductor chip CP from tilting with respect to the upper surface DPt of the die pad DP.

[0113] <Method of manufacturing a semiconductor device> Next, a method of manufacturing a semiconductor device described with reference to FIGS. 1 to 10 will be described. FIG. 21 is an explanatory diagram showing an example of a manufacturing process of the semiconductor device described with reference to FIGS. 1 to 10. Hereinafter, as a representative example of the method of manufacturing a semiconductor device, a method of manufacturing the semiconductor device PKG1 mainly described with reference to FIGS. 1 to 10 will be described. In addition, regarding the method of manufacturing the semiconductor device PKG2 shown in FIG. 11, the method of manufacturing the semiconductor device PKG3 shown in FIG. 12, the method of manufacturing the semiconductor device PKG4 shown in FIG. 13, the method of manufacturing the semiconductor device PKG5 shown in FIG. 15, the method of manufacturing the semiconductor device PKG6 shown in FIG. 17, and the method of manufacturing the semiconductor device PKG7 shown in FIG. 20, duplicate explanations will be omitted and the differences will be described.

[0114] The method of manufacturing the semiconductor device shown in FIG. 21 includes a semiconductor chip preparation step, a lead frame preparation step, a semiconductor chip mounting step, a lead connection step, a sealing step, and a singulation step.

[0115] In the semiconductor chip preparation step shown in FIG. 21, for example, a semiconductor chip CP (which may be the semiconductor chip CPA shown in FIG. 11 or the semiconductor chip CPB shown in FIG. 12) shown in FIGS. 3 and 4 is prepared. Since the shape and structure of the semiconductor chip CP have already been described in detail, duplicate explanations will be omitted.

[0116] In the lead frame preparation step shown in FIG. 21, a lead frame shown in FIG. 22 is prepared. FIG. 22 is an enlarged plan view of the lead frame prepared in the lead frame preparation step shown in FIG. 21. FIG. 23 is an enlarged cross-sectional view showing an example of a state in which a concave portion is formed by irradiating a laser on the upper surface of the die pad in the lead frame preparation step shown in FIG. 21.

[0117] The lead frame LF prepared in this step includes a device formation portion LFd connected to a frame portion (frame part) LFf. In FIG. 22, one of the plurality of device formation portions LFd included in the lead frame LF is illustrated. The plurality of device formation portions LFd are connected to each other via the frame portion LFf.

[0118] The lead frame LF is made of, for example, copper (Cu) or a copper alloy. Each of the plurality of device formation portions LFd is connected to the frame portion LFf. The frame portion LFf is a support portion that supports each member formed in the device formation portion LFd until the singulation step shown in FIG. 21.

[0119] The device formation portion LFd corresponds to one semiconductor device PKG1 shown in FIG. 1. The device formation portion LFd has a die pad DP and a plurality of leads LD. Among the plurality of leads LD, each of the source lead LDS and the gate lead LDG is separated from the die pad DP. On the other hand, the drain lead LDD is formed integrally with the die pad DP. In the example shown in FIG. 22, the die pad DP is supported by the frame portion LFf via the drain lead LDD. However, as a modification, there may be a case where a suspension lead (support lead) not shown in the die pad DP is connected.

[0120] On the upper surface DPt of the die pad DP, the recess CCV1 already described is pre-formed. The recess CCV1 is formed, for example, by irradiating the upper surface DPt of the die pad DP with a laser LZ as shown in FIG. 23. As described above, as a modification, the recess CCV1 can also be formed by press working using a mold. In the case of the method of forming the recess CCV1 by laser irradiation, it is preferable in that unevenness and distortion are less likely to occur on the upper surface DPt around the recess CCV1 as compared with the method of forming the recess CCV1 by press working.

[0121] Also, in the example shown in FIG. 23, the spot diameter LZD of the laser LZ is smaller than, for example, the opening diameter ID1 of the recess CCV1. Also, when forming the recess CCV6 formed in the die pad DP of the semiconductor device PKG6 described with reference to FIGS. 17 to 19, the spot diameter LZD of the laser LZ is smaller than, for example, the opening width W1 of the recess CCV1. In this case, it is preferable in that the opening area and depth of the recess CCV1 can be controlled with high precision as compared with the case of forming the recess CCV1 by irradiating once with a larger spot diameter LZD of the laser LZ.

[0122] Note that the formation methods of the recesses CCV2, CCV3, CCV4, and CCV5 described in any of FIGS. 11, 12, 13, 15, and 16 are the same as the formation method of the recess CCV1 shown in FIG. 23, for example, and thus redundant descriptions are omitted.

[0123] Next, in the semiconductor chip mounting step shown in FIG. 21, as shown in FIG. 4, the semiconductor chip CP is mounted on the die pad DP via a solder material DB such that the lower surface CPb of the semiconductor chip CP faces the upper surface DPt of the die pad DP.

[0124] Specifically, first, solder paste, which is the raw material of the solder material DB, is applied to the chip mounting area, which is the area on the upper surface DPt of the die pad DP where the semiconductor chip CP is to be mounted (solder material application step). The solder paste is a paste-like material containing a solder component and a flux component. In the case of the method for manufacturing the semiconductor device PKG7 described with reference to FIG. 20, the solder paste contains solder SD and a plurality of fillers FL (inorganic material particles) mixed with the solder SD.

[0125] Next, after spreading the solder material DB as necessary, the semiconductor chip CP is placed on the solder material DB and pressed toward the die pad DP. In the step of placing the semiconductor chip CP on the solder material DB, alignment is performed so that the corner CPC1 of the semiconductor chip CP is positioned on the recess CCV1 of the die pad DP. By this step, the semiconductor chip CP is adhered onto the die pad via the paste-like solder material DB (solder paste). At this time, as shown in FIG. 8, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP such that the corner CPC1 overlaps the recess CCV1. Also, the solder material DB adheres to the entire lower surface CPb of the semiconductor chip CP.

[0126] Next, the solder paste is heated as a reflow process, the temperature is raised to above the melting point of the solder component contained in the solder paste, and then it is cooled. By the reflow process, the solder material DB hardens and the semiconductor chip CP is fixed on the solder material DB. In the reflow process, the flux component contained in the solder paste volatilizes. If the flux component remains as a residue, a cleaning process may be performed to remove the residue of the flux component. As described as a modification example using FIG. 20, when the solder material DB contains solder SD and filler FL, the filler FL remains in the solder material DB even after the reflow process is performed.

[0127] In addition, when solder is used as the conductive members CM1 and CM2 shown in FIG. 4, the reflow process may be performed collectively in the lead connection step shown in FIG. 21.

[0128] Next, in the lead connection process shown in FIG. 21, as shown in FIG. 4, a plurality of leads and the semiconductor chip are electrically connected via the metal plate MP1. In this process, the conductive member CM1 is disposed on the source electrode pad PDS of the semiconductor chip CP. Also, in this process, the conductive member CM2 is applied to the upper surface of the inner lead portion LDM of the lead LD. Each of the conductive member CM1 and the conductive member CM2 used in this process is, for example, solder paste or a conductive resin paste. At this time, a conductive member (not shown) is applied on the gate electrode pad PDG shown in FIG. 3.

[0129] Next, the metal plate MP1 is disposed so as to cover the conductive member CM1 and the conductive member CM2 shown in FIG. 4, and the lower surface MP1b of the metal plate MP1 is adhered to each of the conductive member CM1 and the conductive member CM2. At this time, the metal plate MP2 is disposed on the gate electrode pad PDG shown in FIG. 3 and adhered to a conductive member (not shown).

[0130] Next, each of the conductive member CM1 and the conductive member CM2 is cured to fix the metal plate MP1. Examples of the method for curing each of the conductive member CM1 and the conductive member CM2 include the following methods. When solder paste is used as the conductive member CM1 and the conductive member CM2, the effect is achieved by performing a reflow process. On the other hand, when a conductive resin paste is used as the conductive member CM1 and the conductive member CM2, as a cure bake process, heating is performed up to a temperature at which the thermosetting resin contained in the conductive resin paste cures. As a result, the resin component of the conductive resin paste cures. As a result, each of the conductive member CM1 and the conductive member CM2 made of the conductive resin can be cured.

[0131] The above description is an explanation of the manufacturing process when using a so-called clip as the metal plates MP1 and MP2 (see FIG. 3). When using a strip-shaped metal plate called a ribbon instead of a clip, it can be joined by a method similar to wire bonding. In this case, one end of the metal plate MP1 is directly joined to the source electrode pad PDS without passing through the conductive members CM1 and CM2. On the other hand, the other end of the metal plate MP1 is joined to a metal film (a plating film not shown) formed on the upper surface of the inner lead portion LDM of the lead.

[0132] Next, in the encapsulation process shown in FIG. 21, as shown in FIG. 4, the semiconductor chip CP and the metal plate MP1 are encapsulated with an insulating resin. In this process, the semiconductor chip CP, the metal plate MP1, the inner lead portions LDM of the plurality of leads LD shown in FIG. 3, the metal plate MP2, and the upper surface DPt and side surfaces of the die pad DP are encapsulated by an encapsulant made of an insulating material. Note that the encapsulant MR may contain insulating particles, pigments, etc. made of inorganic materials in addition to the resin.

[0133] The center MRC of the encapsulant MR shown in FIG. 3 does not necessarily coincide with the center of the die pad DP. According to the study by the inventor of the present application, it has been found that among the plurality of corners of the semiconductor chip CP, the corner closest to the crack generation location of the solder material DB can be determined by the length of the distance from the center MRC of the encapsulant MR. That is, the corner CPC1 shown in FIG. 3 is located at the position where the distance from the center MRC of the encapsulant MR is the longest among the four corners of the semiconductor chip CP.

[0134] On the other hand, the corner CPC2 shown in FIG. 3 is located at the position where the distance from the center MRC of the encapsulant MR is the shortest among the four corners of the semiconductor chip CP. For this reason, as described with reference to FIG. 9, the recess CCV1 shown in FIG. 8 is not arranged at the position overlapping with the corner CPC2. In other words, in the transmission plan view, the corner CPC2 is arranged outside the recess CCV1 shown in FIG. 8.

[0135] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Signs

[0136] BS1, BS2, BS3, BS4, BS6 Bottom surface CCV1, CCV2, CCV3, CCV4, CCV5, CCV6 Concave portion CH Channel formation region CM1, CM2 Conductive member CNV Convex portion CP, CPA, CPB Semiconductor chip CPb Bottom surface (surface, back surface, main surface) CPC1, CPC2, CPC3, CPC4 Corner CPS1, CPS2, CPS3, CPS4 Side CPt Top surface (surface, front surface, main surface) D Drain DB Solder material DBP1, DBP2, DBP3, DBP4, DBP5 Portion DP Die pad DPb Bottom surface (surface, exposed surface) DPt Top surface (surface, chip mounting surface) EP Epitaxial layer FL Filler (inorganic material particles) G Gate GI Gate insulating film HT1 Level difference ID1 Opening diameter LC2 Shortest distance LD, LDD, LDG, LDS Lead LDM Inner lead portion LDX Outer lead portion LF Lead frame LFd Device formation portion LFf Frame portion (frame part) LZ Laser LZD Spot diameter MP1 Metal plate (clip) MP1b Bottom (surface) MP1t Top (surface) MP2 Metal plate (clip) MR Sealing body MRb Bottom MRC Center MRt Top PD Pad PDD Drain electrode pad PDG Gate electrode pad PDS Source electrode pad PKG1,PKG2,PKG3,PKG4,PKG5,PKG6,PKG7 Semiconductor device Q1 Transistor S Source SD Solder SR Source region (region corresponding to source S shown in Fig. 5) TR Groove TR1 Trench (opening, groove) W1 Opening width WH Semiconductor substrate WHt Main surface

Claims

1. A semiconductor chip having a first upper surface and a first lower surface located on the opposite side of the first upper surface, A die pad having a second upper surface facing the first lower surface and a second lower surface located on the opposite side of the second upper surface, with the semiconductor chip mounted on the second upper surface, A plurality of leads electrically connected to the semiconductor chip, A metal plate electrically connected to each of the plurality of leads and the semiconductor chip, A sealing body for sealing the semiconductor chip, And having, The semiconductor chip is mounted on the second upper surface of the die pad via a solder material, In plan view, the semiconductor chip has a plurality of corners including a first corner, A recess is formed in the second upper surface of the die pad, In a transparent plan view, the semiconductor chip is mounted on the second upper surface of the die pad such that the first corner is located within the recess, In a transparent plan view, the first corner is the corner that is located farthest from the center of the sealing body and away from the metal plate among the plurality of corners, The solder material is, A first portion located between the first lower surface of the semiconductor chip and the bottom surface of the recess, A second portion located between the first lower surface of the semiconductor chip and the second upper surface of the die pad and at a different position from the first portion, And having, A semiconductor device in which the thickness of the solder material in the first portion is greater than the thickness of the solder material in the second portion.

2. In Claim 1, A semiconductor device in which groove-shaped unevenness is formed on the bottom surface of the recess.

3. In Claim 2, In plan view, the outer edge of the recess is circular, and the groove-shaped unevenness forms a spiral shape, a semiconductor device.

4. In Claim 2, The height difference between the convex portion on the bottom surface of the recess and the second upper surface of the die pad is 30 μm or more, a semiconductor device.

5. In Claim 1, In plan view, the plurality of corners of the semiconductor chip include the first corner and a second corner, In a transparent plan view, the second corner is a corner located closer to the center of the sealing body than the first corner, In a transparent plan view, the second corner of the semiconductor chip is disposed outside the recess, The shortest distance from the second corner of the first lower surface of the semiconductor chip to the second upper surface of the die pad is smaller than the thickness of the first portion, a semiconductor device.

6. In Claim 1, A semiconductor device in which, in a plan view, the first corner is the corner that is located farthest from the center of the sealing body among the plurality of corners and is located farthest from the metal plate.

7. In claim 1, the plurality of corners of the semiconductor chip include the first corner, the second corner, the third corner, and the fourth corner, on the second upper surface of the die pad, in addition to the recess, a second recess, a third recess, and a fourth recess are formed, in a plan view through, the semiconductor chip is mounted on the second upper surface of the die pad such that the first corner is located in the recess, the second corner is located in the second recess, the third corner is located in the third recess, and the fourth corner is located in the fourth recess, the solder material has a first portion located between the first lower surface of the semiconductor chip and the bottom surface of the recess, a third portion located between the first lower surface and the bottom surface of the second recess, a fourth portion located between the first lower surface and the bottom surface of the third recess, a fifth portion located between the first lower surface and the bottom surface of the fourth recess, and a second portion located between the first lower surface and the second upper surface of the die pad and at a position different from each of the first portion, the third portion, the fourth portion, and the fifth portion, A semiconductor device in which the thickness of the solder material in the first portion, the thickness of the solder material in the third portion, the thickness of the solder material in the fourth portion, and the thickness of the solder material in the fifth portion are each greater than the thickness of the solder material in the second portion.

8. In claim 7, on the second upper surface of the die pad, in addition to the recess, the second recess, the third recess, and the fourth recess, a fifth recess is formed at a position that does not overlap any of the plurality of corners of the semiconductor chip in a plan view through.

9. In claim 1, the semiconductor chip has four sides and a plurality of corners that are intersections of any two of the four sides, in a plan view, the recess extends in a groove shape so as to form a quadrangular frame shape, A semiconductor device in which, in a plan view through, the semiconductor chip is mounted on the second upper surface of the die pad such that each of the plurality of corners and the four sides is located in the recess.

10. In claim 1, The semiconductor device, wherein the solder material includes solder and a plurality of inorganic material particles mixed in the solder.

11. In Claim 1, the semiconductor chip includes a first electrode pad disposed on the first upper surface, the metal plate is disposed between the metal plate and the first electrode pad, and is electrically connected to the first electrode pad via a conductive member connected to each of the metal plate and the first electrode pad, the semiconductor device.

12. In Claim 11, the semiconductor chip has a power transistor composed of a power MOSFET or an IGBT, the first electrode pad is electrically connected to the source of the power MOSFET or the emitter of the IGBT, the die pad is electrically connected to the drain of the power MOSFET or the collector of the IGBT via the solder material, the semiconductor device.

13. (a) preparing a semiconductor chip having a first upper surface and a first lower surface located on the opposite side of the first upper surface; (b) preparing a die pad having a second upper surface and a second lower surface located on the opposite side of the second upper surface, and a lead frame having a plurality of leads disposed spaced apart from the die pad; (c) mounting the semiconductor chip on the die pad via a solder material such that the first lower surface of the semiconductor chip faces the second upper surface of the die pad; (d) electrically connecting the plurality of leads and the semiconductor chip via a metal plate; (e) forming a sealing body for sealing the semiconductor chip and the metal plate; including, the semiconductor chip prepared in the step (a) has a plurality of corners including a first corner in a plan view, a recess is formed in the second upper surface of the die pad of the lead frame prepared in the step (b), in the step (c), the semiconductor chip is mounted on the second upper surface of the die pad such that the first corner is located within the recess, the solder material adheres to the entire first lower surface of the semiconductor chip, after the step (c), the solder material has a first portion located between the first lower surface of the semiconductor chip and the bottom surface of the recess, and a second portion located between the first lower surface of the semiconductor chip and the second upper surface of the die pad and at a position different from the first portion. The thickness of the solder material in the first part is greater than the thickness of the solder material in the second part. A method of manufacturing a semiconductor device, after the step (e), the first corner of the semiconductor chip is the position farthest from the center of the encapsulant among the plurality of corners, and is disposed at a position away from the metal plate.

14. In claim 13, The method of manufacturing a semiconductor device, wherein the recess is formed by irradiating a laser on the second upper surface of the die pad.

15. In claim 14, The opening diameter or opening width of the recess is larger than the spot diameter of the laser. The method of manufacturing a semiconductor device, wherein groove-shaped irregularities are formed on the bottom surface of the recess.

16. In claim 13, In a plan view, the plurality of corners of the semiconductor chip include the first corner and the second corner. After the step (e), the second corner is disposed at a position closer to the center of the encapsulant than the first corner. After the step (c), The second corner of the semiconductor chip is disposed outside the recess in a transmission plan view. The method of manufacturing a semiconductor device, wherein the shortest distance from the second corner of the first lower surface of the semiconductor chip to the second upper surface of the die pad is smaller than the thickness of the first part.

17. In claim 13, After the step (e), the first corner of the semiconductor chip is the position farthest from the center of the encapsulant among the plurality of corners, and is disposed at a position farthest from the metal plate.

18. In claim 13, In the step (c), the solder material includes solder and a plurality of inorganic material particles mixed in the solder.

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