Semiconductor storage device

Abstract

To provide a semiconductor storage device that operates suitably.SOLUTION: A semiconductor storage device comprises: a plurality of conductive layers (110) laminated in a lamination direction (Z) and including a plurality of first conductive layers extending in a first direction (X) across a semiconductor pillar region (RMH), a first terrace region (RSGDT0), and a second terrace region (RSGDT1), a second conductive layer including a terrace portion provided in the first terrace region, and a third conductive layer including a terrace part provided in the second terrace region; semiconductor pillars (120) provided in the semiconductor pillar region; a gate insulating film provided between the plurality of conductive layers and the semiconductor pillars and including a charge storage films; and a first insulating member (SHE) including a first insulating part (152) extending in the first direction in the first terrace region and a second insulating part (153) extending in the first direction in the second terrace region. The width (Y153) of the second insulating part in a second direction (Y) is smaller than the width (Y152) of the first insulating part in the second direction.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present embodiment relates to a semiconductor memory device.

Background Art

[0002] A semiconductor memory device including a plurality of conductive layers stacked in a stacking direction, semiconductor pillars extending in the stacking direction and facing the plurality of conductive layers, and a gate insulating film provided between the plurality of conductive layers and the semiconductor pillars is known. The gate insulating layer includes, for example, a charge storage film such as silicon nitride (SiN).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device that can be preferably manufactured.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment includes a plurality of conductive layers stacked in a stacking direction. The plurality of conductive layers include a plurality of first conductive layers extending in a first direction across a semiconductor pillar region, a first terrace region, and a second terrace region arranged in the first direction intersecting the stacking direction, and a second conductive layer extending in the first direction across the semiconductor pillar region and the first terrace region and having a terrace portion provided in the first terrace region. The semiconductor memory device further includes a third conductive layer provided between the plurality of first conductive layers and the second conductive layer, extending in the first direction across the semiconductor pillar region, the first terrace region, and the second terrace region, and having a terrace portion provided in the second terrace region. The semiconductor memory device also includes a semiconductor pillar provided in the semiconductor pillar region and extending in the stacking direction and facing the plurality of conductive layers, a gate insulating film provided between the plurality of conductive layers and the semiconductor pillar and including a charge storage film, and a first insulating member extending in the stacking direction within a range in the stacking direction corresponding to a part including the second conductive layer and the third conductive layer of the plurality of conductive layers. The first insulating member includes a first insulating portion extending in the first direction in the first terrace region and a second insulating portion extending in the first direction in the second terrace region. The width of the second insulating portion in the second direction at a first position in the stacking direction is smaller than the width of the first insulating portion in the second direction at the first position in the stacking direction.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Embodiments for Carrying Out the Invention

[0007] Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Also, the following drawings are schematic, and some configurations or the like may be omitted for the sake of explanation. In addition, the same reference numerals are given to the common parts in a plurality of embodiments, and the description may be omitted.

[0008] Also, in this specification, when referring to a "semiconductor memory device", it may mean a memory die, or may mean a memory system including a controller die such as a memory chip, a memory card, an SSD (Solid State Drive), etc. Furthermore, it may mean a configuration including a host computer such as a smartphone, a tablet terminal, a personal computer, etc.

[0009] Also, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Also, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, for example, this circuit or the like includes a transistor or the like, and this transistor or the like is provided in the current path between the two wirings, which may mean that this transistor or the like is in the ON state.

[0011] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0012] In this specification, the direction intersecting the surface of the substrate may be referred to as the stacking direction. Also, the direction along a predetermined plane intersecting the stacking direction may be referred to as the first direction, and the direction intersecting the first direction along this plane may be referred to as the second direction. The stacking direction may or may not coincide with the Z direction. Also, the first direction and the second direction may or may not correspond to any of the X direction and the Y direction.

[0013] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is referred to as upper, and the direction approaching the substrate along the Z direction is referred to as lower. Also, when referring to the lower surface or lower end of a certain configuration, it means the surface or end on the substrate side of this configuration, and when referring to the upper surface or upper end, it means the surface or end on the side opposite to the substrate of this configuration. Also, a surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[0014] In this specification, when referring to the "width", "length", or "thickness" etc. of a configuration, member, etc. in a predetermined direction, it may mean the width, length, or thickness etc. in a cross-section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0015] [First Embodiment] [Circuit Configuration] FIG. 1 is a schematic block diagram of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a memory die MD. The memory die MD includes a plurality of memory cell arrays MCA and a peripheral circuit PC. Each of the plurality of memory cell arrays MCA includes a plurality of memory blocks BLK. Each of the plurality of memory blocks BLK includes a plurality of string units SU. The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage, a voltage transfer circuit that transfers the generated operating voltage to each wiring in the selected memory block BLK, a sense amplifier module connected to the bit line BL, and a sequencer that controls these components.

[0016] FIG. 2 is a schematic circuit diagram of the memory block BLK. As described above, the memory block BLK includes a plurality of string units SU. Each of these plurality of string units SU includes a plurality of memory strings MS. One end of each of these plurality of memory strings MS is connected to the peripheral circuit PC (FIG. 1) via the bit line BL. Also, the other end of each of these plurality of memory strings MS is connected to the peripheral circuit PC (FIG. 1) via the common source line SL.

[0017] The memory string MS includes drain side selection transistors STDT0, STDT1, STD0, STD1, a plurality of dummy memory cells DMD, a plurality of memory cells MC (memory transistors), a plurality of dummy memory cells DMS, and source side selection transistors STS, STSB. The drain side selection transistors STDT0, STDT1, STD0, STD1, the plurality of dummy memory cells DMD, the plurality of memory cells MC, the plurality of dummy memory cells DMS, and the source side selection transistors STS, STSB are connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistors STDT0, STDT1, STD0, STD1 and the source side selection transistors STS, STSB may be simply referred to as selection transistors STDT0, STDT1, STD0, STD1, STS, STSB.

[0018] The memory cell MC is a field-effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multiple-bit data. Incidentally, word lines WL are connected to the gate electrodes of the multiple memory cells MC corresponding to one memory string MS, respectively. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK, respectively.

[0019] The dummy memory cells DMD, DMS are basically configured in the same manner as the memory cell MC. However, data is not stored in the dummy memory cells DMD, DMS. Incidentally, dummy word lines DWD are connected to the gate electrodes of the multiple dummy memory cells DMD corresponding to one memory string MS, respectively. These dummy word lines DWD are commonly connected to all the memory strings MS in one memory block BLK, respectively. Similarly, dummy word lines DWS are connected to the gate electrodes of the multiple dummy memory cells DMS corresponding to one memory string MS, respectively. These dummy word lines DWS are commonly connected to all the memory strings MS in one memory block BLK, respectively.

[0020] The selection transistors STDT0, STDT1, STD0, STD1, STS, STSB are field effect transistors. The selection transistors STDT0, STDT1, STD0, STD1, STS, STSB include a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines SGDT0, SGDT1, SGD0, SGD1, SGS, SGSB are respectively connected to the gate electrodes of the selection transistors STDT0, STDT1, STD0, STD1, STS, STSB. The drain side selection gate lines SGDT0, SGDT1 are commonly connected to all the memory strings MS in one memory block BLK. The drain side selection gate lines SGD0, SGD1 are commonly connected to all the memory strings MS in one string unit SU. The source side selection gate line SGS is commonly connected to all the memory strings MS in one memory block BLK. The source side selection gate line SGSB is commonly connected to all the memory strings MS in one memory block BLK.

[0021] [Structure] FIG. 3 is a schematic plan view of the memory die MD. The memory die MD includes a semiconductor substrate 100. In the illustrated example, four memory cell array regions R arranged in the X direction and the Y direction are provided on the semiconductor substrate 100 MCA and a peripheral circuit region R PC are provided. In each of the memory cell array regions R MCA the above-described memory cell array MCA (FIG. 1) is provided. In the peripheral circuit region R PC a part of the above-described peripheral circuit PC (FIG. 1) is provided.

[0022] The memory cell array region R MCA includes a plurality of finger structures FS arranged in the Y direction. In the present embodiment, one finger structure FS functions as one memory block BLK (FIGS. 1 and 2). However, a plurality of finger structures FS may function as one memory block BLK.

[0023] In addition, the memory cell array region R MCA comprises two semiconductor pillar regions R arranged in the X direction MH and two hook-up regions R arranged in the X direction between them HUD and a hook-up region R provided between them HUW . Hereinafter, the structures in these regions will be described in order.

[0024] [Structure in the semiconductor pillar region R MH First, with reference to FIGS. 4 to 6, the structure in the semiconductor pillar region R MH will be described. FIG. 4 is a schematic plan view of the semiconductor pillar region R MH , showing an enlarged view of the portion indicated by A in FIG. 3. In a part of the region of FIG. 4, an XY cross section at the height position corresponding to the conductive layer 110 (WL) described later is shown. In the remaining region of FIG. 4, a view from above is shown. Also, in this remaining region, the insulating layer 102 described later and the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0) described later are omitted. Also, in a part of this remaining region, the bit line BL is omitted. FIG. 5 is a schematic cross-sectional view of the semiconductor pillar region R MH , showing a cross section cut along the line B-B' of the structure shown in FIG. 4 and viewed along the direction of the arrow. FIG. 6 is a schematic cross-sectional view of the semiconductor pillar region R MH , showing an enlarged view of the portion indicated by C in FIG. 5. Note that FIG. 6 shows a YZ cross section, but the same structure as FIG. 6 is observed even when observing a cross section other than the YZ cross section along the central axis of the semiconductor pillar 120 described later (for example, an XZ cross section).

[0025] The finger structure FS includes, for example, five string units SU arranged in the Y direction as shown in FIG. 4. A finger-to-finger structure ST is provided between two adjacent finger structures FS in the Y direction. Also, an inter-string insulating member SHE such as silicon oxide (SiO2) is provided between two adjacent string units SU in the Y direction. Note that the finger structure FS may include two to four string units SU or six or more string units SU. ​

[0026] As shown in FIG. 5, the finger structure FS includes a plurality of conductive layers 110 arranged in the Z direction, a conductive layer 112 provided below the plurality of conductive layers 110, and a plurality of semiconductor pillars 120 extending in the Z direction. Further, gate insulating films 130 are provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120, respectively.

[0027] The conductive layer 110 has a substantially plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Further, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction. Further, an insulating layer 102 such as silicon oxide (SiO2) is provided on the upper surface of the uppermost conductive layer 110.

[0028] The plurality of conductive layers 110 function as word lines WL (FIG. 2) and gate electrodes of a plurality of memory cells MC (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (WL). The plurality of conductive layers 110 (WL) are electrically independent for each finger structure FS. The side surfaces of the conductive layer 110 (WL) on the positive side and the negative side in the Y direction are electrically insulated from the components in other finger structures FS via the inter-finger structure ST.

[0029] One or more conductive layers 110 located below the plurality of conductive layers 110 (WL) function as dummy word lines DWS (FIG. 2) and gate electrodes of a plurality of dummy memory cells DMS (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (DWS). The conductive layer 110 (DWS) is configured in the same manner as the conductive layer 110 (WL).

[0030] One or more conductive layers 110 located below the plurality of conductive layers 110 (DWS) function as gate electrodes of a source-side selection gate line SGS (FIG. 2) and a plurality of source-side selection transistors STS (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGS). The conductive layer 110 (SGS) is configured in the same manner as the conductive layer 110 (WL).

[0031] One or more conductive layers 110 located below the plurality of conductive layers 110 (SGS) function as gate electrodes of a source-side selection gate line SGSB (FIG. 2) and a plurality of source-side selection transistors STSB (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGSB). The conductive layer 110 (SGSB) is configured in the same manner as the conductive layer 110 (WL).

[0032] One or more conductive layers 110 located above the plurality of conductive layers 110 (WL) function as gate electrodes of a dummy word line DWD (FIG. 2) and a plurality of dummy memory cells DMD (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (DWD). Some of the conductive layers 110 (DWD) may be configured in the same manner as the conductive layer 110 (WL). Other some of the conductive layers 110 (DWD) provided above these some of the conductive layers 110 (DWD) may be basically configured in the same manner as the conductive layer 110 (SGD1) described later. However, five conductive layers 110 (DWD) arranged in the Y direction at a predetermined height position in one finger structure FS are electrically conductive to each other.

[0033] One conductive layer 110 located above one or more conductive layers 110 (DWD) functions as a gate electrode of a drain-side selection gate line SGD1 (FIG. 2) and a plurality of drain-side selection transistors STD1 (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGD1).

[0034] As shown in FIG. 4, the finger structure FS includes five conductive layers 110 (SGD1) arranged in the Y direction via a string unit inter-insulating member SHE at a predetermined height position. The width Y in the Y direction of the conductive layer 110 (SGD1) SGD is smaller than the width Y in the Y direction of the conductive layer 110 (WL). WL These five conductive layers 110 (SGD1) are each electrically independent for each string unit SU. In each finger structure FS, the conductive layers 110 (SGD1) corresponding to the first and fifth string units SU counted from one side in the Y direction (for example, the negative side in the Y direction) are electrically insulated from the components in other finger structures FS via a finger-to-finger structure ST provided between the finger structures FS. Also, in each finger structure FS, two adjacent conductive layers 110 (SGD1) in the Y direction are electrically insulated via a string unit inter-insulating member SHE.

[0035] One conductive layer 110 located above the conductive layer 110 (SGD1) functions as a drain side select gate line SGD0 (FIG. 2) and gate electrodes of a plurality of drain side select transistors STD0 (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGD0). The conductive layer 110 (SGD0) is configured in the same manner as the conductive layer 110 (SGD1). The five conductive layers 110 (SGD0) arranged in the Y direction at a predetermined height position in one finger structure FS are each electrically independent for each string unit SU.

[0036] One conductive layer 110 located above the conductive layer 110 (SGD0) functions as a drain side select gate line SGDT1 (FIG. 2) and gate electrodes of a plurality of drain side select transistors STDT1 (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as a conductive layer 110 (SGDT1). The conductive layer 110 (SGDT1) is basically configured in the same manner as the conductive layer 110 (SGD1). However, the five conductive layers 110 (SGDT1) arranged in the Y direction at a predetermined height position in one finger structure FS are electrically conductive to each other.

[0037] One conductive layer 110 located above the conductive layer 110 (SGDT1) functions as the gate electrode of the drain-side select gate line SGDT0 (FIG. 2) and a plurality of drain-side select transistors STDT0 (FIG. 2) connected thereto. In the following description, such a conductive layer 110 may be referred to as the conductive layer 110 (SGDT0). The conductive layer 110 (SGDT0) is configured in the same manner as the conductive layer 110 (SGDT1). Five conductive layers 110 (SGDT0) arranged in the Y direction at a predetermined height position in one finger structure FS are electrically conductive with each other.

[0038] The conductive layer 112 (FIG. 5) may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Further, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layer may be provided on the lower surface of the conductive layer 112. An insulating layer 101 such as silicon oxide (SiO2) is provided between the conductive layer 112 and the conductive layer 110.

[0039] The conductive layer 112 functions as a part of the source line SL (FIG. 2). The conductive layer 112 is provided in common for all finger structures FS included in, for example, the memory cell array region R MCA (FIG. 3).

[0040] The semiconductor pillars 120 are arranged in a predetermined pattern in the X direction and the Y direction, for example, as shown in FIG. 4. For example, the finger structure FS includes 20 semiconductor pillar columns SC provided from one side in the Y direction to the other side in the Y direction. Each of these 20 semiconductor pillar columns SC includes a plurality of semiconductor pillars 120 arranged in the X direction.

[0041] Hereinafter, the semiconductor pillars 120 corresponding to the 4nth (n is an integer of 1 or more and 4 or less) and 4n + 1th semiconductor pillar columns SC counted from one side in the Y direction are the semiconductor pillars 120 Omay be referred to as. Also, semiconductor pillars 120 corresponding to the 1st, 2nd, 3rd, (4n + 2)th, (4n + 3)th, and 20th semiconductor pillar columns SC counted from one side in the Y direction are the semiconductor pillars 120 I may be referred to as.

[0042] The semiconductor pillar 120 contains, for example, polycrystalline silicon (Si) or the like. The semiconductor pillar 120 has a substantially cylindrical shape as shown in FIG. 5, for example, and an insulating pillar 127 such as silicon oxide (SiO2) is provided in the central portion.

[0043] The semiconductor pillar 120 includes a region 121 provided below the lower surface of the lowermost conductive layer 110, a region 122 provided above the region 121 and below the lower end of the string unit insulating member SHE, a region 123 provided above the region 122 and below the upper end of the insulating pillar 127, and a region 124 provided above the region 123.

[0044] The region 121 contains an N-type impurity such as phosphorus (P). The region 121 has a substantially cylindrical shape. The region 121 is connected to the conductive layer 112.

[0045] The region 122 faces a plurality of conductive layers 110 (SGSB), 110 (SGS), 110 (DWS), 110 (WL). Also, the region 122 may face at least a part of the plurality of conductive layers 110 (DWD). The region 122 functions as a channel region of the memory cell MC (FIG. 2), the dummy memory cell DMS (FIG. 2), and the selection transistors STS, STSB (FIG. 2). Also, the region 122 may function as a channel region of at least some of the dummy memory cells DMD (FIG. 2). The region 122 may not contain an N-type impurity such as phosphorus (P). The region 122 has a substantially cylindrical shape.

[0046] Region 123 faces the conductive layers 110(SGD1), 110(SGD0), 110(SGDT1), and 110(SGDT0). Also, region 123 may face at least a part of the plurality of conductive layers 110(DWD). Region 123 functions as the channel region of the selection transistors STDT0, STDT1, STD0, and STD1 (Figure 2). Also, region 123 may function as the channel region of at least some of the dummy memory cells DMD. Region 123 may not contain N-type impurities such as phosphorus (P).

[0047] Semiconductor pillar 120 I The region 123 of has a substantially cylindrical shape. On the other hand, the region 123 of the semiconductor pillar 120 O has a shape where a part of the cylinder is missing (an arc shape in the XY cross-section).

[0048] Region 124 contains N-type impurities such as phosphorus (P). Region 124 is electrically connected to the bit line BL extending in the Y direction via the via contact electrode Ch and the via contact electrode Vy (Figure 4) extending in the Z direction. The via contact electrode Ch and the via contact electrode Vy may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The bit line BL may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0049] Semiconductor pillar 120 I The region 124 of has a substantially cylindrical shape. On the other hand, the region 124 of the semiconductor pillar 120 O has a shape where a part of the cylinder is missing.

[0050] The gate insulating film 130 includes, for example, as shown in Figure 6, a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 is a film capable of storing charges such as silicon nitride (SiN), for example.

[0051] Of the gate insulating film 130, the portion provided at the position corresponding to the region 121 of the semiconductor pillar 120 has a substantially cylindrical shape and extends in the Z direction along the outer peripheral surface of the semiconductor pillar 120 excluding the contact portion between the semiconductor pillar 120 and the conductive layer 112.

[0052] Of the gate insulating film 130, the portion provided at the position corresponding to the region 122 of the semiconductor pillar 120 has a substantially cylindrical shape and extends in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0053] Of the gate insulating film 130, the semiconductor pillar 120 I The portions provided at the positions corresponding to the regions 123 and 124 of have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120 I The portions provided at the positions corresponding to the regions 123 and 124 of the semiconductor pillar 120 extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

[0054] Of the gate insulating film 130, the semiconductor pillar 120 O The portions provided at the positions corresponding to the regions 123 and 124 of have a shape in which a part of the cylinder is missing (an arc shape in the XY cross section).

[0055] The finger - to - finger structure ST includes, for example, as shown in FIGS. 4 and 5, an inter - finger electrode 141 extending in the X direction and the Z direction, and an inter - finger insulating member 142 such as silicon oxide (SiO2) provided on the side surface in the Y direction of the inter - finger electrode 141. The lower end of the inter - finger electrode 141 is connected to the conductive layer 112. Also, the upper end of the inter - finger electrode 141 is located above the upper surface of the conductive layer 110 located in the uppermost layer. The inter - finger electrode 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Also, the inter - finger electrode 141 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The inter - finger electrode 141 functions, for example, as a part of the source line SL (FIG. 2).

[0056] The string unit-to-unit insulating member SHE includes, for example, silicon oxide (SiO2) or the like. The string unit-to-unit insulating member SHE is provided between the 4n-th semiconductor pillar row SC and the (4n + 1)-th semiconductor pillar row SC, counted from one side in the Y direction, and extends in the X direction, as shown in FIG. 4, for example. The side surfaces of the string unit-to-unit insulating member SHE in the Y direction are in contact with one of the gate insulating films 130 corresponding to the 4n-th semiconductor pillar row SC and the gate insulating film 130 corresponding to the (4n + 1)-th semiconductor pillar row SC, counted from one side in the Y direction, respectively, and are spaced apart from the other side.

[0057] As shown in FIG. 5, the string unit-to-unit insulating member SHE extends in the Z direction within a height range corresponding to the insulating layer 102, the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), 110 (SGD1) and a part of the conductive layer 110 (DWD), and the insulating layers 101 provided on the upper and lower surfaces of these conductive layers 110, and divides these structures in the Y direction. The lower end of the string unit-to-unit insulating member SHE is located between the lower surface of the conductive layer 110 (SGD1) and the lower surface of the uppermost conductive layer 110 (WL).

[0058] In the illustrated example, the string unit-to-unit insulating member SHE, when viewed from the Z direction, overlaps with a part of the semiconductor pillar 120, O and a part of the tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 that are disposed between the semiconductor pillar 120 O and the conductive layer 110 and constitute the gate insulating film 130.

[0059] [Structure in the hook-up region R HUD Next, with reference to FIGS. 7 to 10, the structure in the hook-up region R HUD will be described. FIGS. 7 and 8 are schematic plan views of the hook-up region R. HUD In FIG. 7, the insulating layer 102 and the bit line BL are omitted. FIG. 8 shows an XY cross section at a height position corresponding to the conductive layer 110 (SGD1). FIGS. 9 and 10 are of the hook-up region R HUD ​is a schematic cross-sectional view, showing a cross-section taken along the line D-D' of the structure shown in FIGS. 7 and 8 and viewed along the direction of the arrow. In FIG. 9, for the sake of illustration, the support insulating column HR described later is shown by a two-dot chain line. In FIG. 10, for the sake of illustration, the support insulating column HR described later is omitted, and the string unit inter-insulating member SHE is shown by a two-dot chain line.

[0060] Hook-up region R HUD In the hook-up region R, as shown in FIG. 7, there are terrace regions R MH arranged in order in the X direction from the semiconductor column region R HUW side to the hook-up region R SGDT0 , R SGDT1 , R SGD0 , R SGD1 provided.

[0061] The terrace region R SGDT0 comprises five terrace portions T of five conductive layers 110 (SGDT0) arranged in the Y direction at a predetermined height position in one finger structure FS. The terrace portion T is, for example, a portion of the upper surface of the conductive layer 110 that does not overlap with other conductive layers 110 when viewed from above. The terrace portion T of the conductive layer 110 (SGDT0) is provided at the end of the conductive layer 110 (SGDT0) on the hook-up region R HUW side in the X direction.

[0062] The terrace region R SGDT1 comprises five terrace portions T of five conductive layers 110 (SGDT1) arranged in the Y direction at a predetermined height position in one finger structure FS. The terrace portion T of the conductive layer 110 (SGDT1) is provided at the end of the conductive layer 110 (SGDT1) on the hook-up region R HUW side in the X direction.

[0063] The terrace region R SGD0 comprises five terrace portions T of five conductive layers 110 (SGD0) arranged in the Y direction at a predetermined height position in one finger structure FS. The terrace portion T of the conductive layer 110 (SGD0) is the hook-up region R of the conductive layer 110 (SGD0) in the X directionHUW is provided at the end portion on the side.

[0064] Terrace region R SGD1 comprises five terrace portions T of five conductive layers 110 (SGD1) arranged in the Y direction at a predetermined height position in one finger structure FS. The terrace portion T of the conductive layer 110 (SGD1) is the hook-up region R of the conductive layer 110 (SGD1) in the X direction HUW is provided at the end portion on the side.

[0065] In addition, as shown in FIG. 9, the terrace region R SGDT0 is provided with conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), and 110 (SGD1).

[0066] Also, in the terrace region R SGDT1 although conductive layers 110 (SGDT1), 110 (SGD0), and 110 (SGD1) are provided, the conductive layer 110 (SGDT0) is not provided. Therefore, the number of conductive layers 110 arranged in the Z direction in the terrace region R SGDT1 is less than the number of conductive layers 110 arranged in the Z direction in the terrace region R SGDT0 .

[0067] Also, in the terrace region R SGD0 although conductive layers 110 (SGD0) and 110 (SGD1) are provided, the conductive layers 110 (SGDT0) and 110 (SGDT1) are not provided. Therefore, the number of conductive layers 110 arranged in the Z direction in the terrace region R SGD0 is less than the number of conductive layers 110 arranged in the Z direction in the terrace region R SGDT1 .

[0068] Also, in the terrace region R SGD1 although the conductive layer 110 (SGD1) is provided, the conductive layers 110 (SGDT0), 110 (SGDT1), and 110 (SGD0) are not provided. Therefore, the number of conductive layers 110 arranged in the Z direction in the terrace region R SGD1 is less than the number of conductive layers 110 arranged in the Z direction in the terrace region R SGD0 .

[0069] Also, in the hookup region R HUD a plurality of support insulating pillars HR are provided. The support insulating pillars HR may, for example, contain silicon oxide (SiO2), or may have a configuration corresponding to the semiconductor pillar 120, the insulating pillar 127, and the gate insulating film 130. As shown in FIG. 9, the support insulating pillars HR penetrate through a part of the insulating layer 102 and a plurality of conductive layers 110 and a plurality of insulating layers 101 and extend in the Z direction. The outer peripheral surfaces of the support insulating pillars HR are respectively surrounded by through holes provided in the conductive layer 110.

[0070] The support insulating pillars HR are arranged in a predetermined pattern in the X direction and the Y direction, for example, as shown in FIG. 7. For example, the finger structure FS includes 13 support insulating pillar columns HC provided from one side in the Y direction to the other side in the Y direction. Each of these 13 support insulating pillar columns HC includes a plurality of support insulating pillars HR arranged in the X direction.

[0071] Also, in the hookup region R HUD a plurality of via contact electrodes CC are provided corresponding to the plurality of terrace portions T. The via contact electrodes CC may, for example, include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). As shown in FIG. 9, the via contact electrodes CC penetrate through the insulating layer 102 and extend in the Z direction, and are connected to the terrace portion T of the conductive layer 110 at the lower end. In the example of FIG. 7, 20 via contact electrodes CC are provided corresponding to the 20 terrace portions T provided in the hookup region R HUD .

[0072] In the example of FIG. 7, the four via contact electrodes CC connected to the terrace portions T of the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), 110 (SGD1) corresponding to the first string unit SU counted from the positive side in the Y direction are respectively provided at positions corresponding to the third support insulating pillar column HC counted from the positive side in the Y direction.

[0073] Also, the four via contact electrodes CC connected to the terrace portions T of the conductive layers 110(SGDT0), 110(SGDT1), 110(SGD0), and 110(SGD1) corresponding to the second string unit SU counted from the positive Y-direction side are respectively provided at positions corresponding to the fifth support insulating pillar row HC counted from the positive Y-direction side.

[0074] Also, the four via contact electrodes CC connected to the terrace portions T of the conductive layers 110(SGDT0), 110(SGDT1), 110(SGD0), and 110(SGD1) corresponding to the third string unit SU counted from the positive Y-direction side are respectively provided at positions corresponding to the seventh support insulating pillar row HC counted from the positive Y-direction side.

[0075] Also, the four via contact electrodes CC connected to the terrace portions T of the conductive layers 110(SGDT0), 110(SGDT1), 110(SGD0), and 110(SGD1) corresponding to the fourth string unit SU counted from the positive Y-direction side are respectively provided at positions corresponding to the ninth support insulating pillar row HC counted from the positive Y-direction side.

[0076] Also, the four via contact electrodes CC connected to the terrace portions T of the conductive layers 110(SGDT0), 110(SGDT1), 110(SGD0), and 110(SGD1) corresponding to the fifth string unit SU counted from the positive Y-direction side are respectively provided at positions corresponding to the eleventh support insulating pillar row HC counted from the positive Y-direction side.

[0077] Also, in the hookup region R HUD a part of the string unit inter-insulating member SHE is provided. The string unit inter-insulating member SHE extends in the X-direction across the semiconductor pillar region R MH and the hookup region R HUD and the X-direction end of the string unit inter-insulating member SHE reaches a part of the hookup region R HUW Also, as shown in FIG. 10, the lower end of the string unit inter-insulating member SHE is in the hookup region R HUDIt is also located between the lower surface of the conductive layer 110 (SGD1) and the lower surface of the uppermost conductive layer 110 (WL). As a result, the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), and 110 (SGD1) are divided in the Y direction.

[0078] In the example of FIG. 7, the string unit insulating member SHE at the first position counted from the positive Y direction side is in the hook-up region R HUD and is provided at a position corresponding to the fourth support insulating pillar row HC counted from the positive Y direction side.

[0079] Also, the string unit insulating member SHE at the second position counted from the positive Y direction side is in the hook-up region R HUD and is provided at a position corresponding to the sixth support insulating pillar row HC counted from the positive Y direction side.

[0080] Also, the string unit insulating member SHE at the third position counted from the positive Y direction side is in the hook-up region R HUD and is provided at a position corresponding to the eighth support insulating pillar row HC counted from the positive Y direction side.

[0081] Also, the string unit insulating member SHE at the fourth position counted from the positive Y direction side is in the hook-up region R HUD and is provided at a position corresponding to the tenth support insulating pillar row HC counted from the positive Y direction side.

[0082] In the following description, the first and fourth string unit insulating members SHE counted from the positive Y direction side may be referred to as the string unit insulating member SHE O and the second and third string unit insulating members SHE counted from the positive Y direction side may be referred to as the string unit insulating member SHE I and may be referred to as such.

[0083] The string unit insulating member SHE according to the present embodiment I is in the semiconductor pillar region R MHThe insulating part 151 provided in and the terrace area R SGDT0 The insulating part 152 provided in and the terrace area R SGDT1 The insulating part 153 provided in and the terrace area R SGD0 The insulating part 154 provided in and the terrace area R SGD1 The insulating part 155 provided in and. The insulating parts 151, 152, 153, 154, and 155 each have a substantially constant width in the Y direction and extend in the X direction. In the illustrated example, the central positions of the insulating parts 152, 153, 154, and 155 in the Y direction are substantially the same. On the other hand, the central position of the insulating part 151 in the Y direction is different from the central positions of the insulating parts 152, 153, 154, and 155 in the Y direction. One end and the other end of the insulating part 152 in the X direction are provided in the terrace area R SGDT0 are provided. One end of the insulating part 153 in the X direction is provided in the terrace area R SGDT0 and the other end in the X direction is provided in the terrace area R SGDT1 are provided. One end of the insulating part 154 in the X direction is provided in the terrace area R SGDT1 and the other end in the X direction is provided in the terrace area R SGD0 are provided. One end of the insulating part 155 in the X direction is provided in the terrace area R SGD0 and the other end in the X direction is provided in the hook-up area R HUW are provided.

[0084] The string unit-to-insulating member SHE according to the present embodiment O includes an insulating part 161 provided in the semiconductor column area R MH and an insulating part 162 provided in the terrace area R SGDT0 and an insulating part 163 provided in the terrace area R SGDT1 and an insulating part 165 provided in the terrace area R SGD0 , R SGD1 The insulating parts 161, 162, 163, and 165 each have a substantially constant width in the Y direction and extend in the X direction. In the illustrated example, the central positions of the insulating parts 162, 163, and 165 in the Y direction are substantially the same. On the other hand, the central position of the insulating part 161 in the Y direction is different from the central positions of the insulating parts 162, 163, and 165 in the Y direction. One end and the other end of the insulating part 162 in the X direction are provided in the terrace area R SGDT0It is provided in. One end of the insulating portion 163 in the X direction is in the terrace region R SGDT0 It is provided in, and the other end in the X direction is in the terrace region R SGDT1 It is provided in. One end of the insulating portion 165 in the X direction is in the terrace region R SGDT1 It is provided in, and the other end in the X direction is in the hook-up region R HUW It is provided in.

[0085] Here, as shown in FIG. 8, the widths Y in the Y direction at the height positions corresponding to the conductive layers 110 (SGD1) of the insulating portions 151 and 161 151 , Y 161 are substantially the same. Also, the widths Y in the Y direction at the above height positions of the insulating portions 152 and 162 152 , Y 162 are substantially the same. The widths Y 152 , Y 162 are the widths Y 151 , Y 161 is larger than. Also, the width Y in the Y direction of the insulating portion 153 at the above height position 153 is larger than the width Y in the Y direction of the insulating portion 163 at the above height position 163 The widths Y 153 , Y 163 are the widths Y 151 , Y 161 is larger than and the width Y 152 , Y 162 is smaller than. Also, the width Y in the Y direction of the insulating portion 154 at the above height position 154 is the width Y 151 , Y 161 is larger than and the width Y 153 , Y 163 is smaller than. Also, the widths Y in the Y direction of the insulating portions 155 and 165 at the above height position 155 , Y 165 are the widths Y 151 , Y 161 and are substantially the same.

[0086] At the above height position, the widths in the Y direction of the string unit insulating members SHE I , SHE O are, respectively, in the hook-up region R HUD in the semiconductor pillar region R MHHook-up region R from the side HUW extends over to the side and decreases monotonically.

[0087] [Structure of hook-up region R HUW Next, with reference to FIG. 11, the structure within hook-up region R HUW will be described. FIG. 11 is a schematic cross-sectional view of hook-up region R HUW . In FIG. 11, for the sake of illustration, support insulating pillar HR is shown by a two-dot chain line.

[0088] Hook-up region R HUW is provided with a plurality of terrace regions R DWD arranged in the X direction and a plurality of terrace regions R WL . The plurality of terrace regions R DWD each include terrace portion T of conductive layer 110 (DWD). The plurality of terrace regions R WL each include terrace portion T of conductive layer 110 (WL).

[0089] Although not shown, hook-up region R HUW is also provided with terrace portions T of conductive layers 110 (DWS), 110 (SGS), 110 (SGSB), and corresponding terrace regions.

[0090] Also, hook-up region R HUW is provided with a plurality of support insulating pillars HR and a plurality of via contact electrodes CC, similar to hook-up region R HUD .

[0091] [Manufacturing method] ​Next, with reference to FIGS. 12 to 26, a method for manufacturing a semiconductor memory device according to the first embodiment will be described. FIGS. 12, 14, 16 to 23, and 26 are schematic cross-sectional views for explaining the manufacturing method, and show cross-sections corresponding to FIG. 5. FIGS. 13, 15, and 25 are schematic cross-sectional views for explaining the manufacturing method, and show cross-sections corresponding to FIG. 10. FIG. 24 is a schematic plan view for explaining the manufacturing method, and shows a cross-section corresponding to FIG. 8.

[0092] In manufacturing the semiconductor memory device according to the present embodiment, for example, as shown in FIG. 12, an insulating layer 101 is formed above a semiconductor substrate (not shown). Next, a semiconductor layer 112A such as silicon, a sacrificial layer 112B such as silicon oxide, a sacrificial layer 112C such as silicon, a sacrificial layer 112D such as silicon oxide, and a semiconductor layer 112E such as silicon are formed on the insulating layer 101. Further, a plurality of insulating layers 101 and a plurality of sacrificial layers 110A are alternately formed. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0093] Next, for example, as shown in FIG. 13, in the hook-up regions R HUD , R HUW , a part of the plurality of insulating layers 101 and the plurality of sacrificial layers 110A is removed to form a plurality of terrace portions TA. The terrace portion TA is, for example, a portion of the upper surface of the sacrificial layer 110A that does not overlap with other sacrificial layers 110A when viewed from above. In this step, for example, a resist is formed above the uppermost sacrificial layer 110A. Further, removal of the sacrificial layer 110A, removal of the insulating layer 101, and partial removal of the resist are repeated. Note that the removal of the resist is performed by isotropic etching such as wet etching.

[0094] Next, for example, as shown in FIGS. 14 and 15, a part of the insulating layer 102 is formed. This step is performed, for example, by a method such as CVD.

[0095] Next, as shown in FIG. 16 for example, a memory hole MH is formed at a position corresponding to the semiconductor pillar 120. The memory hole MH extends in the Z direction, penetrates the insulating layer 102, the insulating layer 101, the sacrificial layer 110A, the semiconductor layer 112E, the sacrificial layer 112D, the sacrificial layer 112C, and the sacrificial layer 112B, and exposes the upper surface of the semiconductor layer 112A. This step is performed by a method such as RIE (Reactive Ion Etching), for example. Although not shown, in this step, via holes may be formed at positions corresponding to the support insulating pillars HR.

[0096] Next, as shown in FIG. 17 for example, a gate insulating film 130, a semiconductor pillar 120, and an insulating pillar 127 are formed inside the memory hole MH. This step is performed by a method such as CVD, for example. Although not shown, in this step, the support insulating pillar HR may be formed.

[0097] Next, as shown in FIG. 18 for example, a part of the insulating layer 102 is formed by a method such as CVD. Also, a groove STA is formed at a position corresponding to the finger - to - finger structure ST. The groove STA extends in the Z direction and the X direction, divides the insulating layer 102, the plurality of insulating layers 101, the plurality of sacrificial layers 110A, the semiconductor layer 112E, and the sacrificial layer 112D in the Y direction, and exposes the sacrificial layer 112C. This step is performed by a method such as RIE, for example.

[0098] Next, as shown in FIG. 19 for example, a part of the sacrificial layer 112B, the sacrificial layer 112C, the sacrificial layer 112D, and the gate insulating film 130 is removed to form a conductive layer 112. The removal of a part of the sacrificial layer 112B, the sacrificial layer 112C, the sacrificial layer 112D, and the gate insulating film 130 is performed by a method such as wet etching, for example. The formation of the conductive layer 112 is performed by a method such as epitaxial growth, for example.

[0099] Next, for example, as shown in FIG. 20, the sacrificial layer 110A is removed through the groove STA to form a plurality of voids 110B. As a result, a hollow structure is formed that includes a plurality of insulating layers 101 and 102 arranged in the Z direction, the structure (semiconductor pillar 120, gate insulating film 130, and insulating pillar 127) within the memory hole MH that supports these, and the support insulating pillar HR. This step is performed by a method such as wet etching, for example.

[0100] Next, for example, as shown in FIG. 21, a conductive layer 110 is formed in the void 110B. This step is performed by a method such as CVD using tungsten hexafluoride (WF6), for example.

[0101] Next, for example, as shown in FIG. 22, a finger - to - finger structure ST is formed in the groove STA. This step is performed by methods such as CVD and RIE, for example.

[0102] Next, for example, as shown in FIGS. 23 to 25, a groove SHEA is formed at a position corresponding to the string unit - to - string unit insulating member SHE. The groove SHEA extends in the Z direction and the X direction and divides the insulating layer 102, the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), 110 (SGD1), and a part of the conductive layer 110 (DWD) in the Y direction, as well as the insulating layer 101 provided on the upper and lower surfaces of these conductive layers 110. This step is performed by a method such as RIE, for example. After this step, wet etching for residue treatment or the like may be performed, for example.

[0103] Note that the groove SHEA has a shape corresponding to the string unit - to - string unit insulating member SHE.

[0104] That is, as shown in FIG. 24, the groove SHEA I corresponding to the string unit - to - string unit insulating member SHE I is composed of a groove portion 151A provided in the semiconductor pillar region R MH a groove portion 152A provided in the terrace region R SGDT0 a groove portion 153A provided in the terrace region R SGDT1 a groove portion 154A provided in the terrace region R SGD0The groove portion 154A provided in and the terrace region R SGD1 include the groove portion 155A provided in. The groove portions 151A, 152A, 153A, 154A, and 155A each have a substantially constant width in the Y direction and extend in the X direction. In the illustrated example, the central positions of the groove portions 152A, 153A, 154A, and 155A in the Y direction are substantially the same. On the other hand, the central position of the groove portion 151A in the Y direction is different from the central positions of the groove portions 152A, 153A, 154A, and 155A in the Y direction. One end portion and the other end portion of the groove portion 152A in the X direction are provided in the terrace region R SGDT0 . One end portion of the groove portion 153A in the X direction is provided in the terrace region R SGDT0 , and the other end portion in the X direction is provided in the terrace region R SGDT1 . One end portion of the groove portion 154A in the X direction is provided in the terrace region R SGDT1 , and the other end portion in the X direction is provided in the terrace region R SGD0 . One end portion of the groove portion 155A in the X direction is provided in the terrace region R SGD0 , and the other end portion in the X direction is provided in the hook-up region R HUW .

[0105] Also, the groove SHEA corresponding to the string unit inter-insulating member SHE O includes the groove portion 161A provided in the semiconductor pillar region R O , the groove portion 162A provided in the terrace region R MH , the groove portion 163A provided in the terrace region R SGDT0 , the groove portion 165A provided in the terrace regions R SGDT1 and R SGD0 . The groove portions 161A, 162A, 163A, and 165A each have a substantially constant width in the Y direction and extend in the X direction. In the illustrated example, the central positions of the groove portions 162A, 163A, and 165A in the Y direction are substantially the same. On the other hand, the central position of the groove portion 161A in the Y direction is different from the central positions of the groove portions 162A, 163A, and 165A in the Y direction. One end portion and the other end portion of the groove portion 162A in the X direction are provided in the terrace region R SGD1 . One end portion of the groove portion 163A in the X direction is provided in the terrace region R SGDT0 , and the other end portion in the X direction is provided in the terrace region R SGDT0 ​SGDT1 is provided in. One end of the groove portion 165A in the X direction is the terrace region R SGDT1 is provided in, and the other end in the X direction is the hook-up region R HUW is provided in.

[0106] Here, the widths Y in the Y direction at the height positions corresponding to the conductive layers 110 (SGD1) of the groove portions 151A and 161A 151A , Y 161A are substantially the same. Also, the widths Y in the Y direction at the above height positions of the groove portions 152A and 162A 152A , Y 162A are substantially the same. The width Y 152A , Y 162A is larger than the width Y 151A , Y 161A . Also, the width Y in the Y direction of the groove portion 153A at the above height position 153A is larger than the width Y in the Y direction of the groove portion 163A at the above height position 163A . The width Y 153A , Y 163A is larger than the width Y 151A , Y 161A and smaller than the width Y 152A , Y 162A . Also, the width Y in the Y direction of the groove portion 154A at the above height position 154A is larger than the width Y 151A , Y 161A and smaller than the width Y 153A , Y 163A . Also, the widths Y in the Y direction of the groove portions 155A and 165A at the above height position 155A , Y 165A are substantially the same as the width Y 151A , Y 161A .

[0107] Next, for example, as shown in FIG. 26, a string unit insulating member SHE is formed in the groove SHEA. This step is performed, for example, by forming an insulating member such as silicon oxide on the inside of the groove SHEA and the upper surface of the insulating layer 102 by a method such as CVD, and removing the insulating member formed on the upper surface of the insulating layer 102 by a method such as RIE. Therefore, the string unit insulating member SHE has a shape along the groove SHEA.

[0108] Thereafter, by forming via contact electrodes CC, Ch, Vy and bit lines BL, etc., a structure as described with reference to FIGS. 3 to 11 is formed.

[0109] [Effect] In the process described with reference to FIGS. 23 to 25, as described above, a groove SHEA corresponding to the string unit insulating member SHE is formed.

[0110] Here, in this process, the conductive layers 110(SGDT0), 110(SGDT1), 110(SGD0), 110(SGD1) are divided in the Y direction. Therefore, the lower end of the groove SHEA is controlled such that the semiconductor pillar region R MH and the hook-up region R HUD are entirely located below the lower surface of the conductive layer 110(SGD1).

[0111] On the other hand, when the lower end of the groove SHEA reaches below the lower surface of the uppermost conductive layer 110(WL), in the wet etching for residue treatment during the formation of the groove SHEA, degassing of fluorine (F) contained in the conductive layer 110(WL) occurs, and due to this influence, the film quality of the insulating layer 101 provided above and below the conductive layer 110(WL) may deteriorate. Here, a relatively large voltage difference occurs between two adjacent conductive layers 110(WL) in the Z direction during a write operation or the like. Therefore, if the film quality of the insulating layer 101 between the conductive layers 110(WL) deteriorates, there is a concern about the occurrence of leakage current and short circuit. Therefore, it is desirable that the lower end of the groove SHEA be controlled to be located above the lower surface of the uppermost conductive layer 110(WL) over the entire semiconductor pillar region R MH and the hook-up region R HUD entirely.

[0112] However, if, for example, the width of the groove SHEA in the Y direction is the hook-up region R HUDIf it is uniform throughout, there is a concern that a part of the lower end of the groove SHEA may be located above the lower surface of the conductive layer 110 (SGD1), making it impossible to divide the conductive layer 110 in the Y direction, or a part of the lower end of the groove SHEA may be located below the lower surface of the topmost conductive layer 110 (WL), resulting in leakage current or short circuit.

[0113] For example, in the process described with reference to FIGS. 23 to 25, RIE is performed under conditions where it is difficult to etch a metal such as tungsten compared to silicon oxide or the like.

[0114] Here, in the example of FIG. 25, the groove SHEA mainly divides six layers of the conductive layer 110 in the semiconductor pillar region R MH and the terrace region R SGDT0 mainly divides five layers of the conductive layer 110 in the terrace region R SGDT1 mainly divides four layers of the conductive layer 110 in the terrace region R SGD0 mainly divides three layers of the conductive layer 110 in the terrace region R SGD1 Also, in the example of FIG. 25, the end of the groove SHEA is located in the hook-up region R HUW and this end cuts two layers of the conductive layer 110. Therefore, if the cutting of the conductive layer 110 that limits the progress of etching here proceeds at a substantially uniform speed throughout the hook-up region R HUD for example, when cutting five layers of the conductive layer 110 in the terrace region R SGDT0 the end of the groove SHEA will also cut five layers of the conductive layer 110 in the hook-up region R HUW and as described above, there is a possibility of causing leakage current or short circuit.

[0115] Therefore, in the present embodiment, in the groove SHEA I the width Y 155A of the groove portion 155A is smaller than the width Y 154A of the groove portion 154A, the width Y 154A of the groove portion 154A is smaller than the width Y 153A of the groove portion 153A, and the width Y 153A of the groove portion 153A is smaller than the width Y of the groove portion 152A152A is made smaller. Also, in the groove SHEA O , the width Y of the groove portion 165A 165A is made smaller than the width Y of the groove portion 163A 163A , and the width Y of the groove portion 163A 163A is made smaller than the width Y of the groove portion 162A 162A .

[0116] Generally, when trying to simultaneously form groove portions with different widths by etching, the larger the width of the groove portion, the larger the etching rate of RIE or the like. Conversely, the smaller the width of the groove portion, the smaller the etching rate of RIE or the like. Therefore, according to the method according to this embodiment, the etching rate of RIE or the like is adjusted to suppress the variation in the height of the lower end of the groove SHEA in the terrace regions R SGDT0 ,R SGDT1 ,R SGD0 ,R SGD1 , and thereby it becomes possible to keep the height position of the lower end of the groove SHEA within a desired range.

[0117] Also, in this embodiment, a plurality of semiconductor pillars 120 etc. are formed in the semiconductor pillar region R MH , and a plurality of support insulating pillars HR are formed in the hookup region R HUD . Here, the density of the semiconductor pillars 120 etc. in the semiconductor pillar region R MH is larger than the density of the support insulating pillars HR in the hookup region R HUD . Conversely, the density of the conductive layer 110 in the semiconductor pillar region R MH is smaller than the density of the conductive layer 110 in the hookup region R HUD . Therefore, if, for example, the width of the groove SHEA in the Y direction is uniform over the entire semiconductor pillar region R MH and the hookup region R HUD , there is a risk that the height of the lower end of the groove SHEA will be located below the lower surface of the uppermost conductive layer 110 (WL) in the semiconductor pillar region R MH .

[0118] Therefore, in this embodiment, the width Y of the groove portion 151A 151Ais made smaller than the width Y of the groove portion 152A. Similarly, the width Y of the groove portion 161A 152A is made smaller than the width Y of the groove portion 162A. Therefore, according to the method of the present embodiment, by adjusting the etching rate such as RIE, the difference between the height of the lower end of the groove SHEA in the semiconductor pillar region R 161A and the height of the lower end of the groove SHEA in the hook-up region R 162A is suppressed, and thereby the height position of the lower end of the groove SHEA can be kept within a desired range. MH Also, when the widths in the Y direction of the grooves SHEA in the terrace regions R HUD are all made the same, in the process described with reference to FIGS. 23 to 25, there is a possibility that a part of the groove SHEA

[0119] will be formed deeper than the groove SHEA SGDT0 ,R SGDT1 ,R SGD0 ,R SGD1 . I Therefore, in the present embodiment, the width Y of the groove portion 163A provided in the terrace region R O is made smaller than the width Y of the groove portion 153A. Also, the width Y of the groove portion 165A provided in the terrace region R O is made smaller than the width Y of the groove portion 154A. Thereby, by adjusting the etching rate such as RIE, the variation in the height of the lower end between the grooves SHEA I is suppressed, and thereby the height position of the lower end of the grooves SHEA

[0120] can be kept within a desired range. SGDT1 ,SHEA 163A can be kept within a desired range. 153A Also, the width Y of the groove portion 165A provided in the terrace region R SGD0 is made smaller than the width Y of the groove portion 154A. Thereby, by adjusting the etching rate such as RIE, the variation in the height of the lower end between the grooves SHEA 165A is suppressed, and thereby the height position of the lower end of the grooves SHEA 154A can be kept within a desired range. I ,SHEA O is suppressed, and thereby the height position of the lower end of the grooves SHEA I ,SHEA O can be kept within a desired range.

[0121] [Second Embodiment] In the first embodiment, according to the number of conductive layers 110 to be cut, the width in the Y direction of the groove SHEA I is, in the hook-up region RHUD is adjusted in four steps. Also, the width of the groove SHEA O in the Y direction is adjusted in three steps in the hook-up region R HUD . However, such a configuration is merely an example, and the number of steps for adjusting the width of the groove SHEA I , SHEA O in the Y direction in the hook-up region R HUD can be adjusted as appropriate.

[0122] That is, even if the width of the groove SHEA in the Y direction is adjusted in two steps in the hook-up region R HUD , it is possible to suppress the variation in the height of the lower end of the groove SHEA compared with the case where the width of the groove SHEA in the Y direction is made uniform. For example, in the process described with reference to FIGS. 23 to 25, if the difference between the etching rate of silicon oxide or the like and the etching rate of a metal such as tungsten is small, such two-step adjustment may be sufficient to suppress the variation in the height of the lower end of the groove SHEA.

[0123] Also, for example, in order to prevent an excessive number of conductive layers 110 from being cut by the end of the groove SHEA in the hook-up region R HUW , the width of the groove SHEA in the Y direction may be further adjusted in one step near the end of the conductive layer 110 (SGD1).

[0124] Hereinafter, as a semiconductor memory device according to the second embodiment, an example in which the width of the groove SHEA I , SHEA O in the Y direction is adjusted in two steps in the hook-up region R HUD is shown.

[0125] FIG. 27 is a schematic plan view of a semiconductor memory device according to the second embodiment. FIG. 27 shows an XY cross section at the height position corresponding to the conductive layer 110 (SGD1).

[0126] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes an insulating member SHE' between string units instead of the insulating member SHE between string units.

[0127] In the following description, the first and fourth insulating members SHE' between string units counted from the positive Y direction may be referred to as the insulating member SHE between string units O '. Also, the second and third insulating members SHE' between string units counted from the positive Y direction may be referred to as the insulating member SHE between string units I '.

[0128] The insulating member SHE' between string units according to the present embodiment is basically configured in the same manner as the insulating member SHE between string units I '. However, the insulating member SHE' between string units has an insulating portion 253 provided in the terrace regions R I , R I , R SGDT1 , R SGD0 , R SGD1 instead of the insulating portions 153, 154, 155. The insulating portion 253 has a substantially constant width in the Y direction and extends in the X direction. In the illustrated example, the central position of the insulating portion 253 in the Y direction substantially coincides with the central position of the insulating portion 152 in the Y direction. One end portion of the insulating portion 253 in the X direction is provided in the terrace region R SGDT0 , and the other end portion in the X direction is provided in the hook-up region R HUW .

[0129] The insulating member SHE' between string units according to the present embodiment is basically configured in the same manner as the insulating member SHE between string units O '. However, the insulating member SHE' between string units has an insulating portion 253 provided in the terrace regions R O , R O , R SGDT1 , R SGD0 , R SGD1It includes an insulating portion 263 provided therein. The insulating portion 263 has a substantially constant width in the Y direction and extends in the X direction. In the illustrated example, the central position of the insulating portion 263 in the Y direction substantially coincides with the central position of the insulating portion 162 in the Y direction. One end portion of the insulating portion 263 in the X direction is in the terrace region R SGDT0 is provided, and the other end portion in the X direction is in the hook-up region R HUW is provided.

[0130] Here, the width Y in the Y direction at the height position of the insulating portion 253 corresponding to the conductive layer 110 (SGD1) 253 is larger than the width Y in the Y direction of the insulating portion 263 at the above height position 263 . The width Y 253 , Y 263 is larger than the width Y 151 , Y 161 and smaller than the width Y 152 , Y 162 .

[0131] [Third Embodiment] In the first embodiment, the width Y in the Y direction of the insulating portion 163 provided in the terrace region R SGDT1 is smaller than the width Y in the Y direction of the insulating portion 153 163 . Also, the width Y in the Y direction of the insulating portion 165 provided in the terrace region R 153 is smaller than the width Y in the Y direction of the insulating portion 154 SGD0 . However, such a configuration is merely an example, and the widths in the terrace regions R 165 of the inter-string unit insulating member SHE 154 in the terrace regions R O of the inter-string unit insulating member SHE SGDT0 , R SGDT1 , R SGD0 , R SGD1 can be made substantially the same as the widths in the terrace regions R I of the inter-string unit insulating member SHE SGDT0 , R SGDT1 , R SGD0 , R SGD1 .

[0132] Hereinafter, as a semiconductor memory device according to the third embodiment, the inter-string unit insulating member SHE I,SHE O An example is shown in which the widths in the Y direction in each region are made substantially equal.

[0133] FIG. 28 is a schematic plan view of a semiconductor memory device according to the third embodiment. FIG. 28 shows an XY cross section at the height position corresponding to the conductive layer 110 (SGD1).

[0134] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the second embodiment. However, the semiconductor memory device according to the third embodiment includes a string unit insulating member SHE'' instead of the string unit insulating member SHE'.

[0135] In the following description, the first and fourth string unit insulating members SHE'' counted from the positive Y direction side may be referred to as the string unit insulating member SHE O ''. Also, the second and third string unit insulating members SHE'' counted from the positive Y direction side may be referred to as the string unit insulating member SHE I ''.

[0136] The string unit insulating member SHE I '' according to the present embodiment is basically configured in the same manner as the string unit insulating member SHE I '. However, the string unit insulating member SHE I '' includes an insulating portion 353 instead of the insulating portion 253. The insulating portion 353 is basically configured in the same manner as the insulating portion 253.

[0137] The string unit insulating member SHE O '' according to the present embodiment is basically configured in the same manner as the string unit insulating member SHE O '. However, the string unit insulating member SHE O '' includes an insulating portion 363 instead of the insulating portion 263. The insulating portion 363 is basically configured in the same manner as the insulating portion 263.

[0138] Here, the width Y in the Y direction at the height position corresponding to the conductive layer 110 (SGD1) of the insulating portion 353 353 is substantially the same as the width Y in the Y direction at the above height position of the insulating portion 363 363 and is substantially the same. The width Y 353 , Y 363 is the width Y 151 , Y 161 is larger than the width Y 152 , Y 162 and smaller than the width Y

[0139] [Other Embodiments] As described above, the semiconductor memory devices according to the first to third embodiments have been described. However, the above description is merely illustrative, and specific configurations and the like can be adjusted as appropriate.

[0140] For example, in the semiconductor memory devices according to the first to third embodiments, the widths in the Y direction of the insulating portions 151, 152, 153, 154, 155, 161, 162, 163, 165, 253, 263, 353, 363 can be adjusted as appropriate. For example, in the first to third embodiments, the widths Y in the Y direction at the height positions corresponding to the conductive layer 110 (SGD1) of the insulating portions 152, 162 152 , Y 162 are substantially the same. However, the width Y 162 may be smaller than the width Y 152

[0141] Also, for example, in the semiconductor memory devices according to the first to third embodiments, the configuration for realizing the memory cell array MCA may be formed upside down. Therefore, the conductive layers 110 (SGDT0), 110 (SGDT1), 110 (SGD0), 110 (SGD1) may be provided below the conductive layer 110 (WL).

[0142] Also, in the semiconductor memory devices according to the first to third embodiments, the memory cell array region R MCA is composed of two semiconductor pillar regions R arranged in the X direction MH and two hook-up regions R arranged in the X direction between these HUD ​and a hook-up region R provided therebetween HUW and. However, such a configuration is merely an example, and the semiconductor pillar region R MH , the hook-up region R HUD , and the hook-up region R HUW can be arranged as appropriate. For example, the hook-up region R HUD ,R HUW may be provided at one or both ends in the X direction of the memory cell array region R MCA . Also, for example, the hook-up region R HUD may be provided between the semiconductor pillar region R MH and the hook-up region R HUW .

[0143] [Others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0144] 101... Insulating layer, 110... Conductive layer, 120... Semiconductor pillar, 127... Insulating pillar, 130... Gate insulating film, 131... Tunnel insulating film, 132... Charge storage film, 133... Block insulating film, 151, 152, 153, 154, 155, 161, 162, 163, 165... Insulating portions, CC... Via contact electrode, SHE... String unit inter-insulating member, R MH ... Semiconductor pillar region, R HUD ,R HUW ... Hook-up region, R SGDT0 ,R SGDT1 ,R SGD0 ,R SGD1 ,R DWD ,R WL ... Terrace region, T... Terrace portion.

Claims

1. A plurality of first conductive layers laminated in a stacking direction and extending in a first direction that is aligned in a first direction intersecting the stacking direction, across a semiconductor pillar region, a first terrace region, and a second terrace region; a second conductive layer extending in the first direction across the semiconductor pillar region and the first terrace region and having a terrace portion provided in the first terrace region; and a third conductive layer provided between the plurality of first conductive layers and the second conductive layer, extending in the first direction across the semiconductor pillar region, the first terrace region, and the second terrace region, and having a terrace portion provided in the second terrace region. A plurality of conductive layers including: A semiconductor pillar provided in the semiconductor pillar region, extending in the stacking direction, and facing the plurality of conductive layers; A gate insulating film provided between the plurality of conductive layers and the semiconductor pillar and including a charge storage film; A first insulating member including a first insulating portion extending in the stacking direction within a range in the stacking direction corresponding to a part including the second conductive layer and the third conductive layer of the plurality of conductive layers and extending the first terrace region in the first direction, and a second insulating portion extending the second terrace region in the first direction; Comprising: The width of the second insulating portion in the second direction at the first position in the stacking direction is smaller than the width of the first insulating portion in the second direction at the first position in the stacking direction. A semiconductor memory device.

2. One end portion of the first insulating member in the stacking direction is provided between a surface of the third conductive layer of the plurality of first conductive layers side in the stacking direction and a surface of the plurality of first conductive layers provided on the most third conductive layer side and opposite to the third conductive layer. The semiconductor memory device according to Claim 1.

3. The width of the first insulating member in the second direction at the first position in the stacking direction monotonically decreases from the semiconductor pillar region side to the opposite side across the first terrace region and a region opposite to the semiconductor pillar region in the first direction with respect to the first terrace region. The semiconductor memory device according to Claim 1.

4. The first insulating member further includes a third insulating portion extending the semiconductor pillar region in the first direction, The width of the third insulating portion in the second direction at the first position in the stacking direction is smaller than the width of the first insulating portion in the second direction at the first position in the stacking direction. The semiconductor memory device according to claim 1.

5. A plurality of first conductive layers laminated in the stacking direction and extending in the first direction across the semiconductor pillar regions and the first terrace regions arranged in the first direction intersecting the stacking direction; and a second conductive layer extending in the first direction across the semiconductor pillar regions and the first terrace regions and having a terrace portion provided in the first terrace region, the plurality of conductive layers including: A semiconductor pillar provided in the semiconductor pillar region, extending in the stacking direction, and facing the plurality of conductive layers; A gate insulating film provided between the plurality of conductive layers and the semiconductor pillar and including a charge storage film; A first insulating member extending in the first direction across the semiconductor pillar region and the first terrace region within a range in the stacking direction corresponding to a part of the plurality of conductive layers including the second conductive layer, overlapping the plurality of first conductive layers in the stacking direction; A second insulating member arranged in the second direction intersecting the stacking direction and the first direction, overlapping the plurality of first conductive layers in the stacking direction, and extending in the first direction across the semiconductor pillar region and the first terrace region within the range in the stacking direction corresponding to the part of the plurality of conductive layers; Comprising: At a position in the first direction corresponding to the first terrace region, the width of the second insulating member in the second direction is smaller than the width of the first insulating member in the second direction A semiconductor memory device.

Images