Monolithic integrated circuit laser multiplexer

Abstract

To provide a device that includes a multiplexer that includes transistors to operate a laser array.SOLUTION: A monolithic integrated circuit laser multiplexer according to an embodiment of the present disclosure may include a monolithic integrated circuit device having an addressable laser array, the addressable laser array includes a plurality of N light emission sources, and also may include a multiplexer including N transistors, and the N transistors are respectively associated with different light emission sources of the plurality of N light emission sources. According to various embodiments, each of the N transistors may be operable to address an associated light emission source.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001]

[0001] This disclosure generally relates to monolithic integrated circuit laser multiplexers.

Background Art

[0002]

[0002] Aspects of this disclosure relate to monolithic integrated circuit laser multiplexers. There may be various problems with conventional solutions for monolithic integrated circuit laser multiplexers. In this regard, conventional systems and methods for monolithic integrated circuit laser multiplexers may be expensive, cumbersome, and / or inefficient.

[0003]

[0003] The limitations and disadvantages of conventional systems and methods will become apparent to those skilled in the art through a comparison of such approaches with some aspects of the methods and systems described in the remainder of this disclosure with reference to the drawings.

Summary of the Invention

[0004]

[0004] What is shown in at least one of the figures and / or described in relation to at least one of the figures, and what is fully described in the claims, is a monolithic integrated circuit laser multiplexer.

[0005]

[0005] These and other advantages, aspects, and novel features of this disclosure, as well as details of the illustrated embodiments, will be more fully understood from the following description and the drawings.

[0006] The various features and advantages of this disclosure can be more readily understood with reference to the following detailed description in conjunction with the accompanying drawings in which like reference numerals designate like structural elements.

Brief Description of the Drawings

[0006]

Figure 1

[0007] A block diagram showing a monolithic integrated circuit laser multiplexer according to some embodiments of the present disclosure.

Figure 2

[0008] An exemplary circuit diagram of a monolithic integrated circuit device 100 according to various embodiments of the present disclosure.

Figure 3

[0009] A further exemplary circuit diagram of a monolithic integrated circuit device 100 according to various embodiments of the present disclosure.

Figure 4

[0010] A diagram showing an exemplary structure of a multiplexer 114 using pHEMT.

Figure 5

[0011] A diagram showing an exemplary structure of a multiplexer 114 using HBT.

Figure 6

[0012] A diagram showing an exemplary monolithic GaAs VCSEL-pHEMT structure.

Figure 7

[0013] A diagram showing an exemplary monolithic GaAs VCSEL-HBT.

Figure 8

[0014] A block diagram further illustrating a monolithic integrated circuit device.

Figure 9

[0015] A block diagram further illustrating a monolithic integrated circuit device.

Figure 10

[0016] A block diagram further illustrating a monolithic integrated circuit device.

DETAILED DESCRIPTION

[0007]

[0017] The following discussion provides various examples of methods and systems for a monolithic integrated circuit laser multiplexer. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "e.g." are non-limiting.

[0008]

[0018] The figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Further, the elements within the figures of the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements within the figures may be exaggerated relative to other elements to assist in understanding the examples discussed in the present disclosure. The same reference numerals in different figures indicate the same element.

[0009]

[0019] The term "and / or" means any one or more of the items in a list joined by "and / or". As an example, "x and / or y" means any element of the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y, and / or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y, and / or z" means "one or more of x, y, and z".

[0010]

[0020] The terms "comprises", "comprising", "includes", and / or "including" are "open-ended" terms that specify the presence of the stated feature but do not preclude the presence or addition of one or more other features.

[0011]

[0021] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure could be termed a second element without departing from the teachings of the present disclosure.

[0012]

[0022] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A can be directly in contact with element B or indirectly connected to element B by an intervening element C. Similarly, the terms "over" or "on" can be used to describe two elements that are in direct contact with each other or two elements that are indirectly connected by one or more other elements.

[0013]

[0023] Embodiments of the present disclosure can include a monolithic integrated circuit device that includes an addressable laser array, and the addressable laser array includes a plurality of N light emitting sources. Embodiments can also include a multiplexer that includes N transistors, and each of the N transistors is associated with a different one of the plurality of N light emitting sources. According to various embodiments, each of the N transistors may be operable to address an associated one of the light emitting sources.

[0014]

[0024] Embodiments may include that each of the plurality of N light emitters may be an LED, EEL, VCSEL, or PCSEL. According to various embodiments, the monolithic integrated circuit can comprise a substrate / wafer made of GaN, GaAs, InP, SiC, or GaSb. Embodiments may include that each of the plurality of N transistors may be a MESFET, pHEMT, HFET, or HBT that may be operable for a three-terminal analog function.

[0015]

[0025] According to various embodiments, the monolithic integrated circuit can comprise a plurality of epitaxial layers operable to form light emitters and transistors. According to various embodiments, the epitaxial layers used to form the light emitters can be insulated from the epitaxial layers used to form the transistors by one or more epitaxial layers of high-resistance GaAs and / or InGaP.

[0016]

[0026] According to various embodiments, InGaP may be operable to stop etching between one or more epitaxial layers associated with the plurality of light emitters and one or more epitaxial layers associated with the plurality of transistors. According to various embodiments, the epitaxial layers used to form the light emitters may be different from the epitaxial layers used to form the transistors. The etch stop layer can similarly be made from AlAs or AlGaAs. According to various embodiments, instead of the etch stop layer, a timed-etch fabrication process can be used. The timed-etch fabrication process can refer to the controlled removal of material from the surface of a semiconductor wafer using a chemical etchant for a specified period of time to etch away the material with a predetermined accuracy. The process can be governed by a predetermined etch rate, i.e., the volume of material removed per unit time.

[0017]

[0027] According to various embodiments, an epitaxial layer associated with a transistor can cover an epitaxial layer associated with a light-emitting source. Embodiments can also include an epitaxial structure of a plurality of N light-emitting sources that can include a smoothing buffer layer, an N-type DBR layer, one or more active layers, and a P-type DBR layer.

[0018]

[0028] According to various embodiments, the smoothing buffer layer, the N-type DBR layer, the one or more active layers, and the P-type DBR layer can each include a plurality of epitaxial layers. Embodiments can also include an epitaxial structure of a plurality of N transistors that can include one or more single-recess pHEMTs.

[0019]

[0029] Embodiments can also include an epitaxial structure of a plurality of N transistors that can include one or more double-recess pHEMTs. Embodiments can also include a lower barrier layer. Embodiments can also include a lower delta-doped layer. Embodiments can also include a lower spacer layer. Embodiments can also include a channel layer. Embodiments can also include an upper spacer layer. Embodiments can also include an upper delta-doped layer. Embodiments can also include an upper barrier layer. Embodiments can also include a Schottky layer. Embodiments can also include a recess layer. Embodiments can also include an etch stop layer. Embodiments can also include a cap layer.

[0020]

[0030] Embodiments can also include an epitaxial structure of a plurality of N transistors that can include an HBT. Embodiments can also include a subcollector layer, a collector layer, a base layer, an emitter layer, and / or an emitter cap layer. According to various embodiments, the transistor can be insulated from the light-emitting source by ion implantation and / or mesa etching.

[0021]

[0031] Traditionally, a laser can often be driven by an external driver circuit. This approach may not allow for optimal switching speeds. If a chip having individually addressable lasers or sub-arrays is desired, such an approach can be expensive and have an inconvenient form factor. The present disclosure monolithically integrates an analog multiplexer function on a laser chip so that the laser chip can be efficiently driven by a circuit. According to various embodiments of the present disclosure, a triode laser function can be monolithically integrated on a chip, which is useful for a laser array.

[0022]

[0032] FIG. 1 is a block diagram illustrating a monolithic integrated circuit device 100 according to some embodiments of the present disclosure. In some embodiments, the monolithic integrated circuit device 100 can include an addressable laser array 110. The addressable laser array 110 can include a plurality of N light emitting sources 112 and a multiplexer 114. The multiplexer 114 can also include N transistors 116, and each of the N transistors 116 is associated with a different one of the plurality of N light emitting sources 112. Each of the N transistors 116 may be operable to address an associated one of the light emitting sources 112.

[0023]

[0033] The monolithic integrated circuit device 100 may operate as an electronic circuit integrated on a single semiconductor substrate or as a component that houses additional elements on the semiconductor. The addressable laser array 110 may be operable to selectively activate a laser source, such as a light emitting source 112. Each light emitting source 112 within the addressable laser array 110 may be individually controlled. The light emitting source 112 may be operable to emit light, for example, using a laser light source. The multiplexer 114 may be operable to manage, address, and control a plurality of light emitting sources 112. Each light emitting source 112 may be associated with a transistor 116 that forms a predetermined portion of the multiplexer 114. The transistor 116 may enable individual control of the light emitting source 112.

[0024]

[0034] FIG. 2 shows an exemplary circuit diagram of the monolithic integrated circuit device 100 according to various embodiments of the present disclosure. In addition to the elements shown in FIG. 1, FIG. 2 further includes a control interface 120 and a driver 130. The control interface 120 may be coupled between the driver 130 and the multiplexer 114. The driver 130 may be operable to supply power to the light emitting sources 112. The control interface 120 may generally be a bandwidth-limited and time-constrained interface. Therefore, it may be desirable to reduce the number of control interfaces 120. According to various embodiments of the present disclosure, instead of individually addressing each light emitting source 112 by the control interface 120, it is preferred to use a single control interface 120 and then use the multiplexer 114 to select the desired light emitting source 112.

[0025]

[0035] FIG. 3 shows a further exemplary circuit diagram of the monolithic integrated circuit device 100 according to various embodiments of the present disclosure.

[0036] In some embodiments, each of the plurality of N light emitting sources 112 may be an LED, EEL, VCSEL, or PCSEL.

[0026]

[0037] The LED may be a light-emitting diode. The LED may be a semiconductor light source that can emit light when current flows through it. This can occur by a process known as electroluminescence in which the movement of electrons within a semiconductor material can release energy in the form of photons. LEDs are very efficient and durable and can provide a long operating life. LEDs can be widely used in various applications, such as displays or indicators. LEDs can have low energy consumption and low heat generation.

[0027]

[0038] The EEL may be an edge-emitting laser. An edge-emitting laser (EEL) may be a type of semiconductor laser in which light can be emitted from the end face of a semiconductor chip rather than from its surface. EELs can often be used in applications that require higher output power and longer coherence length. EELs can often be used in optical communications and high-speed data transmission due to the ability of an EEL to generate a highly collimated or parallel light beam.

[0028]

[0039] The VCSEL (:Vertical-Cavity Surface-Emitting Laser) may be a vertical-cavity surface-emitting laser. The VCSEL may be a type of semiconductor laser diode that emits light perpendicular to the surface of a wafer rather than from the end face of the wafer. A prominent feature of the VCSEL may be its vertical cavity structure that can be formed by Bragg mirrors. VCSELs can offer low manufacturing costs, high efficiency, and the ability to be easily tested and configured into two-dimensional arrays. VCSELs can be commonly used in optical communications, sensing applications, and consumer electronics.

[0029]

[0040] A PCSEL (Photonic Crystal Surface-Emitting Laser) may be a photonic crystal surface-emitting laser. A PCSEL may be a laser that leverages the properties of a photonic crystal to control light emission. A photonic crystal may be an optical material having a periodic structure on the scale of the wavelength of light. This can enable a PCSEL to generate a highly directive and highly coherent light beam. The structure of a PCSEL allows for more detailed control over the optical properties of the laser, which can make the structure of the PCSEL desirable for specific applications such as high-density data storage and advanced optical communication.

[0030]

[0041] In some embodiments, the monolithic integrated circuit can also include a substrate / wafer made of GaN, GaAs, InP, SiC, or GaSb.

[0042] GaN (Gallium Nitride) can refer to gallium nitride. Gallium nitride may be a binary III-V direct bandgap semiconductor material that can possess high electron mobility and thermal stability. As a substrate within a monolithic integrated circuit, GaN can be particularly useful for high-frequency and high-power applications such as radio frequency components and power electronics. Its wide bandgap, high breakdown electric field, and thermal conductivity can make GaN a desirable choice for devices that may be required to operate under extreme conditions such as high-temperature and high-voltage environments.

[0031]

[0043] GaAs can refer to gallium arsenide. Gallium arsenide may be another III-V compound semiconductor having a direct bandgap, known for its higher electron mobility compared to silicon. In the context of a monolithic integrated circuit, GaAs can be used, for example, in applications that require high-frequency operation and low-noise amplification. This can include applications in microwave and millimeter-wave technology. Its high electron mobility can enable high-speed electronic components.

[0032]

[0044] InP (Indium Phosphide) can refer to indium phosphide. Indium phosphide may be a binary semiconductor composed of indium and phosphorus, belonging to the III-V group of semiconductors. InP can have a direct bandgap and possess high electron mobility and high resistivity. InP substrates can be frequently used in optoelectronic devices such as high-speed photodetectors and lasers as well as in high-frequency integrated circuits. InP can offer advantages in terms of low noise and high-frequency capabilities.

[0033]

[0045] SiC (Silicon Carbide) can refer to silicon carbide. Silicon carbide may be a wide-bandgap semiconductor material that is particularly hard, chemically inert, and thermally stable. In the area of monolithic integrated circuits, SiC can be highly evaluated for high-power, high-temperature, and high-frequency applications. Its wide bandgap and high thermal conductivity can make SiC a desirable substrate material for power electronics including high-voltage transistors and diodes, especially in an environment where high temperature or high frequency prevails.

[0034]

[0046] GaSb (Gallium Antimonide) can refer to gallium antimonide. Gallium antimonide may be a III-V compound semiconductor having a bandgap narrower than GaAs or GaN. As a substrate material within a monolithic integrated circuit, GaSb may be desirable for infrared photodetectors and thermophotovoltaic devices. Its bandgap can advantageously make GaSb for specific applications in optoelectronics and also for devices operating within the mid-infrared wavelength range.

[0035]

[0047] In some embodiments, each of the plurality of N transistors may be a MESFET, pHEMT, HFET, or HBT that is operable for a three-terminal analog function.

[0036]

[0048] A MESFET (Metal-Semiconductor Field-Effect Transistor) can refer to a metal-semiconductor field-effect transistor. A MESFET may be a field-effect transistor that uses a metal-semiconductor junction (Schottky barrier) as a gate. This type of transistor can generally be fabricated using compound semiconductors such as GaAs or SiC and may be desirable for use in microwave and radio-frequency (RF) applications. The high electron mobility and low parasitic capacitance of a MESFET make it particularly advantageous for high-frequency, high-power, and low-noise applications such as radar systems and satellite communications.

[0037]

[0049] A pHEMT (Pseudomorphic High Electron Mobility Transistor) can refer to a pseudomorphic high electron mobility transistor. A pHEMT may be a specific type of field-effect transistor characterized by a higher concentration of charge carriers. This can enable an increase in electron mobility and desirable performance. Due to its desirable high-frequency characteristics, a pHEMT can be mainly used in high-frequency and low-noise applications such as RF amplifiers.

[0038]

[0050] A HFET (Heterostructure Field-Effect Transistor) can refer to a heterostructure field-effect transistor. An HFET may also be called a HEMT (High Electron Mobility Transistor), but an HFET can comprise different types of heterostructure transistors. An HFET can use a heterostructure to create a channel with high electron mobility, making the HFET suitable for high-frequency and high-power applications. An HFET can be used, for example, in telecommunications, broadband amplifiers, and other applications that require high-speed operation.

[0039]

[0051] HBT (Heterojunction Bipolar Transistor) can refer to a heterojunction bipolar transistor. An HBT may be a type of bipolar transistor that can use different semiconductor materials for the emitter and base regions to create a heterojunction. This can enable improved performance including high speed and efficiency compared to traditional bipolar transistors. HBTs can generally be used in high-frequency applications such as RF and microwave circuits. HBTs can also be used in optoelectronics where their large current density may be advantageous for laser drivers and photodetectors.

[0040]

[0052] FIG. 4 shows an exemplary structure of a multiplexer 114 using pHEMTs. A plurality of pHEMTs 116 are shown that can switch an “in” signal to one of four output signals labeled “out1”, “out2”, “out3”, “out4”. According to various embodiments of the present disclosure, such a multiplexer 114 can be used in the monolithic integrated circuit 100 shown in FIG. 2. A reference switch 140 is also shown.

[0041]

[0053] The reference switch 140 can be used to provide a consistent voltage or current level to which other inputs can be compared. This may be desirable to ensure that the switching works correctly and that there can be minimal crosstalk or interference between channels. In some cases, the reference switch 140 can be used as a safety or calibration point. For example, when other switches cannot be actuated, the reference switch 140 may engage to ensure that the laser cannot be inadvertently actuated. In other cases, the reference switch 140 can be used to monitor the multiplexer 114.

[0042]

[0054] FIG. 5 shows an exemplary structure of a multiplexer 114 using HBTs. A plurality of HBTs 116 are shown that can switch an “in” signal to one of four output signals labeled “out1”, “out2”, “out3”, and “out4”. According to various embodiments of the present disclosure, such a multiplexer 114 can be used in the monolithic integrated circuit 100 shown in FIG. 3.

[0043]

[0055] In some embodiments, the monolithic integrated circuit can include a plurality of epitaxial layers operable to form a light emitting source 112 and transistors 116.

[0044]

[0056] An epitaxial layer can refer to a layer of crystalline semiconductor material that can be grown on a crystalline semiconductor substrate. The ordered growth of the epitaxial layer aligned with the crystal structure of the substrate can ensure that the epitaxial layer inherits the same crystal structure as the underlying substrate.

[0045]

[0057] FIG. 6 shows an exemplary monolithic GaAs VCSEL-pHEMT structure. A cross-section of a semiconductor layer including a pHEMT 116 and a VCSEL laser light emitting source 112 is shown. For the VCSEL light emitting source 112, the direction 290 of the emitted light, an anode 280, a cathode 201, a smoothing buffer layer 220, an N-type DBR (: Distributed Bragg Reflector) layer 230, an active layer 250, and a P-type DBR layer 240 are further shown. For the pHEMT 116, an epitaxial layer 260, a source connector 272, a gate connector 270, and a drain connector 274 are shown.

[0046]

[0058] The VCSEL light emitting source 112 can act as a mirror and includes an N-type DBR layer 230 and a P-type DBR layer 240 that form the upper and lower parts of the laser cavity. The active layer 250 is a place where light generation and amplification can occur.

[0047]

[0059] pHEMT 116 can be formed by an epitaxial layer 260. The epitaxial layer 260 can comprise a channel made of InGaAs. This layer can be strained, resulting in an increased electron mobility. Further, the epitaxial layer 260 can comprise a barrier layer, such as a layer of AlGaAs or AlGaInAs, that can form a heterojunction with the channel. Further, the epitaxial layer 260 can comprise one or more layers made of, for example, doped GaAs.

[0048]

[0060] In some embodiments, the epitaxial layer used to form the light emitting source 112 can be insulated from the epitaxial layer used to form the transistor 116 by one or more epitaxial layers of high resistivity GaAs (Gallium Arsenide) and / or InGaP (Indium Gallium Phosphide). For example, in FIG. 6, one or more high resistivity epitaxial layers 260 can be located adjacent to the P-type DBR layer 240. In FIG. 7, for example, a high resistivity InGaP layer can be immediately adjacent to the P-type DBR layer 240. According to various embodiments, the etch stop layer of the HBT shown in FIG. 7 can be conductive or resistive. In some embodiments, the high resistivity InGaP layer can also stop the etching between one or more epitaxial layers of the transistor. The etch stop layer can similarly be made of AlAs or AlGaAs. According to various embodiments, instead of the etch stop layer, a timely etching process can be used.

[0049]

[0061] FIG. 7 shows an exemplary monolithic GaAs VCSEL-HBT structure. A cross-section of a semiconductor layer including HBT 116 and VCSEL laser light source 112 is shown. For VCSEL light source 112, the direction 290 of the emitted light, anode 280, cathode 201, smoothing buffer layer 220, N-type DBR (distributed Bragg reflector) layer 230, active layer 250, and P-type DBR layer 240 are further shown. For HBT 116, epitaxial layer 260, collector connector 292, base connector 296, and emitter connector 294 are shown. Further, insulating layer 301, emitter 302 (e.g., InGaP emitter), and base 303 (e.g., GaAs base) are shown.

[0050]

[0062] In some embodiments, the InGaP layer may be operable to stop etching between one or more epitaxial layers associated with the plurality of light sources 112 and one or more epitaxial layers 260 associated with the plurality of transistors. The etch stop layer may similarly be made from AlAs or AlGaAs. According to various embodiments, instead of the etch stop layer, a timely etching process may be used.

[0051]

[0063] In some embodiments, the epitaxial layers used to form the light source 112 may be different from the epitaxial layers used to form the transistor 116, as shown in FIGS. 6 and 7. In some embodiments, the epitaxial layers associated with the transistor 116 may cover the epitaxial layers associated with the light source 112. In some embodiments, the transistor 116 may be insulated from the light source 112 by ion implantation and / or mesa etching. According to various embodiments of the present disclosure, the light source 112 may include a smoothing buffer layer 220, an N-type DBR layer 230, one or more active layers 250, and a P-type DBR layer 240.

[0052]

[0064] FIG. 8 is a block diagram further illustrating the monolithic integrated circuit device 100 from FIGS. 1 and 6, according to some embodiments of the present disclosure. In some embodiments, the epitaxial structure of the plurality of N transistors 116 can comprise one or more single recess pHEMTs 312. The one or more single recess pHEMTs 312 can comprise a lower barrier layer 314, a lower delta-doped layer 316, a lower spacer layer 318, a channel layer 320, an upper spacer layer 322, an upper delta-doped layer 324, an upper barrier layer 326, a Schottky layer 328, an etch stop layer 330, and a cap layer 332.

[0053]

[0065] The delta-doped layers 324 and 316 can be layers that contain a sharp concentration of dopants within a narrow region. The delta-doped layers 324 and 316 can be made of a suitable dopant material, e.g., silicon. According to various embodiments, the pHEMT 312 can be formed without the upper delta-doped layer 324.

[0054]

[0066] The Schottky layer 328 can refer to a region near the interface of a Schottky barrier that can be formed when a metal contacts a semiconductor, e.g., between a metal gate and a underlying semiconductor material within the pHEMT.

[0055]

[0067] The spacer layers 318, 322 can be operable to provide electron separation in the electron gas channel from their donor atoms within the delta-doped layers 316, 324. This can reduce scattering and improve electron mobility. The spacer layers can also contribute to the confinement of electrons within the quantum well, ensuring that electrons remain within the high mobility channel. The spacer layers 318, 322 can be made of, e.g., AlGaAs or InAlAs.

[0056]

[0068] In the context of pHEMT312, a single recess can refer to a fabrication step in which a portion of the semiconductor layer above the two-dimensional electron gas channel can be etched away (``recessed'') to define and optimize the gate region. This recessing process can be performed to reduce the thickness of the barrier layer directly under the metal gate contact (which in turn affects the Schottky barrier height), and can enable better control over the threshold voltage and transconductance of the device.

[0057]

[0069] FIG. 9 is a block diagram further illustrating the monolithic integrated circuit device 100 from FIGS. 1 and 6, according to some embodiments of the present disclosure. In some embodiments, the epitaxial structure of a plurality of N transistors 116 can include one or more double recess pHEMTs 412. One or more double recess pHEMTs 412 can include a lower barrier layer 414, a lower delta-doped layer 416, a lower spacer layer 418, a channel layer 420, an upper spacer layer 422, an upper delta-doped layer 424, an upper barrier layer 426, a Schottky layer 428, a recess layer 430, an etch stop layer 432, and a cap layer 434. These layers may be similar to the layers described with respect to FIG. 8.

[0058]

[0070] In the context of pHEMT412, a double recess can be contrasted with the single recess described with respect to FIG. 8 in that multiple distinct recess etching steps can be performed on different layers or regions of the device to achieve certain device characteristics.

[0059]

[0071] The recess process can enable more precise control over the electron density of the channel, and thus enhance the overall performance of the pHEMT by improving the RF performance, power handling, and linearity of the device. The recess layer 430 can refer to a layer affected by the recessing step, such as a gate recess or a channel recess.

[0060]

[0072] FIG. 10 is a block diagram further illustrating the monolithic integrated circuit device 100 from FIGS. 1 and 7, according to some embodiments of the present disclosure. In some embodiments, the epitaxial structure of the transistor 116 can include an HBT 520. The HBT 520 can include a subcollector layer 521, a collector layer 522, a base layer 523, an emitter layer 524, and an emitter cap layer 525.

[0061]

[0073] The subcollector layer 521 can include, for example, semi-insulating GaAs, or InGaP. The collector layer 522 can include, for example, GaAs. The base layer 523 can include, for example, GaAs. The emitter layer 524 can include, for example, InGaP. The emitter cap layer 525 can include, for example, InGaAs.

[0062]

[0074] In some embodiments, the transistor 116 is insulated from the light emitting source 112 by ion implantation and / or mesa etching.

[0075] The present disclosure includes references to specific examples; however, it will be understood by those skilled in the art that various changes may be made without departing from the scope of the present disclosure and equivalents may be used instead. Further, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Accordingly, it is intended that the present disclosure not be limited to the disclosed examples, but that the disclosure include all examples that fall within the scope of the appended claims.

Claims

1. 1. A monolithic integrated circuit device comprising an addressable laser array, the addressable laser array comprising: A plurality of N light emitting sources; a multiplexer comprising N transistors, each of the N transistors being associated with a different one of the plurality of N light emission sources; wherein each of the N transistors is operable to address one of the light emission sources associated therewith.

2. 10. The device of claim 1, wherein each of the plurality of N light emitting sources is an LED, an EEL, a VCSEL, or a PCSEL.

3. 10. The device of claim 1, wherein the monolithic integrated circuit comprises a substrate / wafer made of GaN, GaAs, InP, SiC, or GaSb.

4. 2. The device of claim 1, wherein each of the plurality of N transistors is a MESFET, a pHEMT, an HFET, or an HBT operable for a three-terminal analog function.

5. 10. The device of claim 1, wherein the monolithic integrated circuit comprises a plurality of epitaxial layers operable to form the light emitting source and the transistor.

6. 6. The device of claim 5, wherein the epitaxial layers used to form the light emitting source are insulated from the epitaxial layers used to form the transistors by one or more epitaxial layers of highly resistive GaAs and / or InGaP.

7. 6. The device of claim 5, wherein the epitaxial layers used to form the light emitting source are different from the epitaxial layers used to form the transistors.

8. 10. The device of claim 1, wherein the epitaxial structures of the plurality of N light emitting sources comprise a smoothing buffer layer, an N-type DBR layer, one or more active layers, and a P-type DBR layer.

9. 9. The epitaxial structure of claim 8, wherein the smoothing buffer layer, the N-type DBR layer, the one or more active layers, and the P-type DBR layer each comprise multiple epitaxial layers.

10. 2. The device of claim 1 , wherein the epitaxial structures of the plurality of N transistors comprise one or more single recess pHEMTs comprising a lower barrier layer, a lower delta doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper delta doped layer, an upper barrier layer, a Schottky layer, an etch stop layer, and a cap layer.

11. 2. The device of claim 1, wherein the epitaxial structures of the plurality of N transistors comprise one or more double recessed pHEMTs comprising a lower barrier layer, a lower delta doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper delta doped layer, an upper barrier layer, a Schottky layer, a recess layer, an etch stop layer, and a cap layer.

12. 2. The device of claim 1, wherein the epitaxial structure of the plurality of N transistors comprises an HBT comprising a subcollector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer.

13. 7. The device of claim 6, wherein the InGaP layer is operable to provide an etch stop between one or more epitaxial layers associated with the plurality of light emitting sources and one or more epitaxial layers associated with the plurality of transistors.

14. 6. The device of claim 5, wherein the epitaxial layer associated with the transistor overlies the epitaxial layer associated with the light emitting source.

15. 10. The device of claim 1, wherein the transistor is isolated from the light emitting source by one or both of ion implantation and mesa etching.

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