Semiconductor device

Abstract

To diminish consumption power.SOLUTION: A semiconductor device comprises a sensor circuit having a sensor element, a power management device and an arithmetic processing circuit, the power management device having a function to control the power feed to the arithmetic processing circuit, the arithmetic processing circuit having a first circuit having a first storage circuit and a second circuit having a second storage circuit, the first circuit having a function to hold first data on the first storage circuit in a duration of power feed to the arithmetic processing circuit, the second circuit having a function to read out the first data held on the first storage circuit and write it to the second storage circuit in the duration of power feed to the arithmetic processing circuit and a function to hold the first data on the second storage circuit in the duration of suspension of power feed to the arithmetic processing circuit, the sensor circuit having a function to determine a detection signal of the sensor element and give second data to the power management device in accordance with a determination result, the power management device having a function to resume or stop the power feed to the arithmetic processing circuit in accordance with the second data.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. Or one aspect of the present invention relates to a control system.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Or one aspect of the present invention relates to a control method for a semiconductor device, a control method for a system including a semiconductor device, and the like.

[0003] Note that in this specification and the like, the semiconductor device refers to all things that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements or semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices.

Background Art

[0004] The spread of portable information terminals typified by smartphones and tablet terminals has been progressing. Along with the spread of information terminals, various communication standards have been established. For example, the operation of the LTE-Advanced standard called the fourth-generation mobile communication system (4G) has started.

[0005] In recent years, due to the development of information technologies such as IoT (Internet of Things), the amount of data handled by information terminals has been increasing. In addition, an improvement in communication speed is required for electronic devices such as information terminals.

[0006] To support various information technologies such as IoT, a new communication standard called the 5th generation mobile communication system (5G) that realizes faster communication speeds, more simultaneous connections, and shorter latency times than 4G is being considered. In 5G, communication frequencies in the 3.7 GHz band, 4.5 GHz band, and 28 GHz band are used.

[0007] Semiconductor devices compatible with 5G are fabricated using semiconductors mainly composed of one type of element such as Si, or compound semiconductors mainly composed of multiple types of elements such as Ga and As. Furthermore, oxide semiconductors, which are a type of metal oxide, have attracted attention.

[0008] In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and nc (nanocrystalline) structures that are neither single crystals nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).

[0009] Non-Patent Document 1 and Non-Patent Document 2 disclose techniques for fabricating transistors using oxide semiconductors having a CAAC structure.

[0010] Also, as techniques for reducing the power consumption of semiconductor devices, for example, power gating (PG), clock gating (CG), voltage scaling, etc. are known. For example, Patent Document 1 describes implementing a technique that is advantageous for power reduction among the DVFS (Dynamic Voltage and Frequency Scaling) technique and the PG technique.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Non-Patent Documents

[0012]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0013] One aspect of the present invention is to provide a novel semiconductor device or a novel method of operating a semiconductor device. Or, one aspect of the present invention is to provide a novel system including a semiconductor device or a novel method of operating a novel system including a semiconductor device. Or, one aspect of the present invention is to reduce power consumption, for example, reduce the power in the standby state. Or, one aspect of the present invention is to shorten the time required for the process of returning from the standby state to the normal state, or to reduce the energy required therefor. Or, one aspect of the present invention is to reduce the power consumption of a circuit that controls a sensor element. Or, one aspect of the present invention is to enhance the safety of an object monitored by a sensor element. Or, one aspect of the present invention is to provide a system for easily monitoring an object. Or, one aspect of the present invention is to provide a semiconductor device with low power consumption. Or, one aspect of the present invention is to provide a control circuit with low power consumption. Or, one aspect of the present invention is to provide a highly safe system.

[0014] Note that the description of multiple problems does not prevent the existence of each other's problems. Note that one aspect of the present invention does not need to solve all of these problems. Also, problems other than those listed will become apparent from the description in the specification, drawings, claims, etc., and these problems can also be the problems of one aspect of the present invention.

Means for Solving the Problems

[0015] One aspect of the present invention includes a sensor circuit, a power management device, and an arithmetic processing circuit. The sensor circuit has a sensor element. The power management device has a function of controlling the power supply to the arithmetic processing circuit. The arithmetic processing circuit includes a first circuit having a first storage circuit and a second circuit having a second storage circuit. The first circuit has a function of holding first data during the period when power is supplied to the arithmetic processing circuit. The second circuit has a function of reading the first data held in the first storage circuit and writing it to the second storage circuit during the period when power is supplied to the arithmetic processing circuit, and a function of holding the first data in the second storage circuit during the period when the power supply to the arithmetic processing circuit is stopped. The sensor circuit has a function of determining the detection signal of the sensor element and giving second data to the power management device according to the determination result. The power management device is a semiconductor device having a function of restarting or stopping the power supply to the arithmetic processing circuit according to the second data. The supply of power to the circuit is, for example, to supply power to the circuit.

[0016] Also, in the above configuration, after the power supply to the arithmetic processing circuit is restarted, it is preferable that the second circuit has a function of reading the first data from the second storage circuit and giving it to the first storage circuit.

[0017] Also, in the above configuration, it is preferable to have an antenna and a secondary battery, and the power management device has a function of supplying power from the secondary battery to the arithmetic processing circuit, and the arithmetic processing circuit has a modulation circuit and a demodulation circuit.

[0018] In addition, in the above configuration, the sensor element preferably has a function of measuring one or more selected from force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared rays.

[0019] Alternatively, one aspect of the present invention includes a sensor circuit, a power management device, and an arithmetic processing circuit. The sensor circuit includes an acceleration sensor. The power management device has a function of controlling the power supply to the arithmetic processing circuit. The arithmetic processing circuit includes a first circuit having a first storage circuit and a second circuit having a second storage circuit. The first circuit has a function of holding first data in the first storage circuit during the period when power is supplied to the arithmetic processing circuit. The second circuit has a function of reading the first data held in the first storage circuit during the period when power is supplied to the arithmetic processing circuit and writing it into the second storage circuit, and a function of holding the first data in the second storage circuit during the period when the power supply to the arithmetic processing circuit is stopped. The sensor circuit has a function of determining the detection signal of the acceleration sensor and giving second data to the power management device according to the determination result. The power management device is a semiconductor device having a function of restarting or stopping the power supply to the arithmetic processing circuit according to the second data.

[0020] Alternatively, one aspect of the present invention includes the semiconductor device described above and a control device. The acceleration sensor has a function of detecting the vibration of an object. The control device has a function of controlling the object. The sensor circuit has a function of determining the detection signal of the acceleration sensor and restarting the power supply to the arithmetic processing circuit when it is determined that the acceleration sensor has detected an abnormality in the vibration of the object. The arithmetic processing circuit has a function of analyzing the detection signal of the acceleration sensor in accordance with the restart of the power supply and giving third data to the control device according to the analysis result. The control device is a control system having a function of controlling the object according to the second data.

[0021] Also, in the above configuration, it is preferable that the semiconductor device has an antenna, the arithmetic processing circuit has a modulation circuit and a demodulation circuit, and the third data is given from the semiconductor device to the control device by wireless communication.

[0022] Also, in the above configuration, it is preferable that the semiconductor device has a secondary battery, and the power management device has a function of supplying power from the secondary battery to the arithmetic processing circuit.

Advantages of the Invention

[0023] One aspect of the present invention makes it possible to provide a novel semiconductor device or a novel operation method of a semiconductor device. Also, one aspect of the present invention makes it possible to provide a novel system including a semiconductor device or a novel operation method of a system including a semiconductor device. Also, one aspect of the present invention makes it possible to reduce power consumption, for example, reduce the power in the standby state. Also, one aspect of the present invention makes it possible to shorten the time required for the process of returning from the standby state to the normal state or reduce the energy required therefor. Also, one aspect of the present invention makes it possible to reduce the power consumption of a circuit that controls a sensor element. Also, one aspect of the present invention makes it possible to enhance the safety of an object monitored by a sensor element. Also, one aspect of the present invention makes it possible to provide a system for easily monitoring an object. Also, one aspect of the present invention makes it possible to provide a semiconductor device with low power consumption. Or, one aspect of the present invention makes it possible to provide a control circuit with low power consumption. Also, one aspect of the present invention makes it possible to provide a highly safe system.

[0024] Note that the description of these effects does not prevent the existence of other effects. Also, one aspect of the present invention does not necessarily have to have all of the exemplified effects. Also, regarding one aspect of the present invention, other problems, effects, and novel features will be apparent from the description and drawings of this specification.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted.

[0027] In addition, the positions, sizes, ranges, etc. of the respective configurations shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. in order to facilitate understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but it may not be reflected in the drawing for the sake of easy understanding.

[0028] In addition, in top views (also referred to as "plan views") and perspective views, etc., for the sake of making the drawings easier to understand, the description of some components may be omitted.

[0029] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0030] Also, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of the wiring or electrode may function as a terminal.

[0031] Note that in this specification and the like, the terms "upper" and "lower" do not limit that the positional relationship of the components is directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary that electrode B is directly formed on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0032] Also, since the functions of the source and drain are interchangeable depending on operating conditions such as when different polarity transistors are employed or when the direction of current changes in circuit operation, it is difficult to limit which is the source or drain. Therefore, in this specification, the terms source and drain can be used interchangeably.

[0033] In addition, in this specification and the like, "electrically connected" includes both the case of direct connection and the case of being connected via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring is extending.

[0034] In addition, in this specification and the like, "parallel" means, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" mean, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0035] Note that in this specification and the like, when referring to count values and measurement values as "identical", "the same", "equal", or "uniform", etc., unless otherwise specified, it shall include an error of plus or minus 20%.

[0036] Also, voltage often indicates the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be interchanged with each other. In this specification and the like, unless otherwise explicitly stated, voltage and potential can be interchanged.

[0037] Note that even when expressed as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "insulator" in place of "semiconductor". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be interchangeable with each other.

[0038] Also, even when denoted as "semiconductor", for example, when the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use it by replacing "semiconductor" with "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be mutually interchangeable.

[0039] Note that ordinal numbers such as "first" and "second" in this specification and the like are attached to avoid confusion of components, and do not indicate any order or rank such as process order or lamination order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0040] Note that in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0041] Also, in this specification and the like, "on-current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0042] In addition, in this specification and the like, the high power supply potential (hereinafter also referred to as "power supply potential VDD", "VDD", "H potential", or "H") refers to a power supply potential with a potential higher than the low power supply potential (hereinafter also referred to as "power supply potential VSS", "VSS", "L potential", or "L"). Also, VSS refers to a power supply potential with a potential lower than VDD. Further, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0043] In addition, in this specification and the like, the gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0044] In addition, in this specification and the like, the source refers to a part or all of the source region, the source electrode, and the source wiring. The source region refers to a region in the semiconductor layer where the resistivity is below a certain value. The source electrode refers to the conductive layer connected to the source region. The source wiring refers to a wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0045] In addition, in this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is below a certain value. The drain electrode refers to the conductive layer connected to the drain region. The drain wiring refers to a wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0046] In addition, in drawings and the like, in order to make the potential of wirings and electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be appended adjacent to the wirings and electrodes, etc. Further, for wirings and electrodes, etc. where a potential change has occurred, "H" or "L" may be appended in enclosed characters. Further, when a transistor is in an off state, an "×" symbol may be appended over the transistor.

[0047] Note that a terminal may refer to an aggregate of a plurality of terminals. For example, independent signals are given to each of the terminals of the aggregate of a plurality of terminals, and one or more wirings are electrically connected to each of the terminals.

[0048] A transistor has three terminals (nodes) called a gate, a source, and a drain. The gate is a terminal that functions as a control terminal for controlling the conduction state of the transistor. A pair of input / output terminals (nodes) that function as a source or a drain become a source and a drain, respectively, depending on the type of the transistor and the levels of the potentials applied to the respective terminals (nodes). Generally, in an n-type transistor, the node to which a low potential is applied is called the source, and the node to which a high potential is applied is called the drain. Conversely, in a p-type transistor, the node to which a low potential is applied is called the drain, and the node to which a high potential is applied is called the source. In this specification, the two terminals (nodes) other than the gate may be referred to as a first terminal (node) and a second terminal (node).

[0049] In this specification, for the purpose of facilitating the understanding of the circuit configuration and its operation, there may be cases where one of the two input / output terminals (nodes) of a transistor is limited to be the source and the other is limited to be the drain for explanation. Of course, depending on the driving method, the magnitude relationship of the potentials applied to the three terminals of the transistor may change, and the source and the drain may be interchanged. Therefore, in one aspect of the present invention, the distinction between the source and the drain of a transistor is not limited to the description in the specification and the drawings.

[0050] In this specification and the like, for all terminals of active elements (such as transistors, diodes, etc.), passive elements (such as capacitor elements, resistor elements, etc.), etc., even if the connection destination is not specified, a person skilled in the art may be able to constitute an aspect of the invention in some cases. That is, even if the connection destination is not specified, it can be said that an aspect of the invention is clear. And when an aspect of the invention in which the connection destination is specified is described in this specification and the like, in some cases, it is possible to determine that an aspect of the invention in which the connection destination is not specified is described in this specification and the like. In particular, when multiple cases of the connection destination of a terminal are considered, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, for some terminals of active elements (such as transistors, diodes, etc.), passive elements (such as capacitor elements, resistor elements, etc.), etc., it may be possible to constitute an aspect of the invention by specifying the connection destination.

[0051] In this specification and the like, for a certain circuit, if at least the connection destination is specified, a person skilled in the art may be able to specify the invention in some cases. Or, for a certain circuit, if at least the function is specified, a person skilled in the art may be able to specify the invention in some cases. That is, if the function can be specified, it can be said that the aspect of the invention is clear. And when an aspect of the invention in which the function is specified is described in this specification and the like, in some cases, it is possible to determine that. Therefore, for a certain circuit, even if the function is not specified, if the connection destination is specified, an aspect of the invention is disclosed and it is possible to constitute an aspect of the invention. Or, for a certain circuit, even if the connection destination is not specified, by specifying the function, an aspect of the invention is disclosed and it is possible to constitute an aspect of the invention.

[0052] (Embodiment 1) In this embodiment, a semiconductor device which is an aspect of the present invention, and an application example of the semiconductor device will be described.

[0053] <Configuration example of semiconductor device> The semiconductor device 700 shown in FIG. 1 has a processing unit (PU), a sensor circuit 301, and a power supply circuit 10.

[0054] The PU 21 has terminals 80, 81, 82, 83, 92, and 94. The PU 21 has a function of executing instructions included in a program or the like. By adopting a configuration using transistors (hereinafter referred to as OS transistors) having an oxide semiconductor in the channel formation region, the PU 21 can extremely reduce the power consumption in the standby state. In addition, the time required to return from the standby state to the normal state can be extremely shortened. Details of the PU 21 will be described later. Instead of the PU 21, a PU 20 described later may be used. As will be described later, the PU 20 and the PU 21 have a processor core, a power management device, a clock control circuit, a power switch, and the like. The processor core is a circuit having a function of processing instructions and can be called an arithmetic processing circuit.

[0055] The sensor circuit 301 has a sensor element 710, a detection unit 711, terminals 90, 91, and 93.

[0056] The sensor circuit 301 has a function of supplying a signal based on the detection result of the sensor element 710 to the PU 21. The PU 21 has a function of processing instructions using the signal supplied from the sensor circuit 301. In addition, the PU 21 has a function of supplying a control signal for controlling each circuit included in the sensor circuit 301.

[0057] The sensor circuit 301 may have either or both of a determination circuit 712 and an analog-to-digital conversion circuit 713.

[0058] The signal detected by the sensor element 710 is provided to the detection unit 711. The detection unit 711 has a function of providing the detection signal given from the sensor element 710 to each circuit such as the terminal 91, the determination circuit 712, and the analog-to-digital conversion circuit 713. The detection signal provided to the terminal 91 is provided from the terminal 91 to the terminal 92 of the PU21. The detection unit 711 may perform processing such as amplification and compression on the detection signal in advance and then provide the processed detection signal to each circuit or terminal.

[0059] The sensor element 710 preferably has a function of measuring one or more selected from force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared rays.

[0060] The sensor element 710 has a function of measuring a parameter representing the state of the object 799.

[0061] The PU21 preferably has a function of providing a control signal to the object 799. The PU21 may be electrically connected to the object 799. Further, the PU21 may have a function of wirelessly providing a control signal to the object 799.

[0062] The sensor element 710 included in the semiconductor device 700 may or may not be electrically connected to the object 799.

[0063] The semiconductor device 700 is preferably arranged to be in contact with the object 799, for example. Alternatively, it is preferably installed in the vicinity of the object 799. The distance between the semiconductor device 700 and the object 799 may be determined according to the detectable range of the signal. For example, when detecting the vibration of the object 799, the semiconductor device 700 is preferably arranged to be in contact with the object 799. Alternatively, it is preferably arranged at a distance of 5 mm or less. For example, when detection data is provided from the object 799 to the semiconductor device 700 by wireless communication, the semiconductor device 700 may be arranged within the range where wireless communication is possible.

[0064] The semiconductor device 700 can monitor the signal detected by the sensor element 710.

[0065] Monitoring the signal, for example, refers to comparing the reference data with the detected signal. Alternatively, monitoring the signal, for example, refers to determining whether the detected signal deviates from the desired range. The determination of whether the detected signal deviates from the desired range can be performed, for example, by comparing the detected signal with the reference data. Alternatively, for example, extracting the feature amount of the detected waveform, more specifically, for example, extracting the frequency component and performing analysis.

[0066] The reference data can be stored in the memory of the semiconductor device 700. For example, it is stored in the cache of the PU21. By providing a backup circuit using an OS transistor in the cache and storing the data, the data can be retained for a long time even when the power is cut off or the clock signal is cut off. Also, after the power supply is resumed, the stored data can be quickly restored. Details of the cache and the backup circuit will be described later.

[0067] Also, the detected signal can be stored in the cache.

[0068] Also, in the process of monitoring, the detection signal is verified, and a control signal corresponding to the verification result is given from the PU21 to the object 799. By the given control signal, the object 799, for example, continues to operate, or restricts the operation, or stops the operation.

[0069] Also, the PU21 may have a neural network. The signal monitoring and verification may be performed by operations using the neural network. Learning of the neural network may be performed in the PU21, or the results of learning performed in advance may be stored in the memory of the PU21.

[0070] For example, abnormal waveforms are learned as learning data, and the detection signal is analyzed using a neural network.

[0071] Details of the configuration example of the neural network will be described later.

[0072] Also, the monitoring of the detection signal does not need to be performed constantly. During the period when monitoring is not performed, power gating of the processor core of PU21 can be performed, putting PU21 in a standby state, and the power consumption can be reduced.

[0073] When PU21 is in the standby state, the sensor circuit 301 may also be in the standby state. Specifically, for example, the supply of power from the power supply circuit 10 is stopped.

[0074] Alternatively, when PU21 is in the standby state, the sensor circuit 301 may be in the normal state. As will be described later, a signal can be given from the sensor circuit 301 to return PU21 from the standby state to the normal state.

[0075] Also, the sensor circuit 301 preferably has a determination circuit 712. The determination circuit 712 determines the signal from the sensor element 710. The determination circuit 712, for example, compares the signal from the sensor element 710 with the desired data. Also, as an example of an abnormality detected by the determination circuit 712, there is a case where the signal detected by the sensor element 710 has a value exceeding the desired range.

[0076] During the period when the sensor element 710 included in the sensor circuit 301 is performing detection, a save sequence can be executed, power gating of the processor core and the like of PU21 can be performed, and PU21 can be put in the standby state.

[0077] Based on the determination result of the determination circuit 712, PU21 determines whether to return from the standby state to the normal state. More specifically, for example, when the signal from the sensor element 710 given to the detection unit 711 is determined to be abnormal in the determination circuit 712, a signal INT, which is a signal requesting an interrupt process, is given to the terminal 82 from the determination circuit 712. By the signal INT, PU21 returns to the normal state and starts monitoring the detection signal from the detection unit 711.

[0078] PU21 according to one aspect of the present invention can shorten the time required to return from the standby state to the normal state. That is, PU21 can be promptly returned from the time when the determination circuit 712 detects an abnormality, and the detection of the signal can be promptly started. Therefore, even when the time during which an abnormality occurs is short, an abnormal signal can be acquired.

[0079] The sensor circuit 301 may include an analog-to-digital conversion circuit 713. The analog-to-digital conversion circuit 713 converts the analog signal from the sensor element 710 given to the detection unit 711 into a digital signal and gives it to the determination circuit 712 and the terminal 91. The signal given to the terminal 91 is given to the terminal 92 of PU21.

[0080] PU21 may include an analog-to-digital conversion circuit. The signal given from the sensor circuit 301 may be processed by the analog-to-digital conversion circuit that PU21 has.

[0081] The detection unit 711 may include a sample-and-hold circuit 714. The sample-and-hold circuit has a function of holding the signal detected by the sensor element 710. An example of the sample-and-hold circuit 714 using an OS transistor will be described later.

[0082] The sensor circuit 301 may include a memory 715. By configuring the memory 715 using an OS transistor, a memory with fast readout speed and long-term holdability can be realized. An example of the memory configured using an OS transistor will be described later.

[0083] PU21 preferably has a function of providing a control signal for controlling circuits such as a sensor element 710, a detection unit 711, a determination circuit 712, an analog-digital conversion circuit 713, a sample-and-hold circuit 714, and a memory 715 included in the sensor circuit 301. The signal is supplied, for example, from a terminal 94 of PU21 to a terminal 93 of the sensor circuit 301, and from the terminal 93 to each circuit.

[0084] Terminal 90 is a terminal to which power is supplied from the power supply circuit 10 to the sensor circuit 301.

[0085] By using a secondary battery as the power supply of the power supply circuit 10, integration with PU21 and the sensor circuit 301 becomes easy. In addition, since the power consumption is reduced when PU21 is in a standby state, the capacity of the secondary battery can be reduced. Since integration is easy and the capacity of the secondary battery can be reduced, miniaturization of the semiconductor device 700 can be realized.

[0086] The semiconductor device according to one aspect of the present invention is small and has a feature of low power consumption. Therefore, it can be easily installed on various objects.

[0087] Further, the semiconductor device according to one aspect of the present invention preferably has a function of performing wireless communication by Bluetooth (registered trademark), Wi-Fi (registered trademark), 4G, 5G, or the like.

[0088] In the semiconductor device 700 illustrated in FIG. 2A, PU21 has a communication circuit 402. The communication circuit 402 has functions such as modulating a signal and demodulating a signal. The communication circuit 402 is electrically connected to an antenna 401.

[0089] FIG. 2B shows an example in which semiconductor devices 700 each having a function of performing wireless communication are installed for a plurality of objects 799. The control device 717 shown in FIG. 2B can wirelessly transmit and receive signals to and from the plurality of installed semiconductor devices 700. Each semiconductor device 700 can perform wireless communication with the control device 717 using the antenna 401 described above. When performing wireless communication, connection of wiring between the control device 717 and the semiconductor device 700 becomes unnecessary, the degree of freedom in installing the semiconductor device 700 is increased, and it becomes convenient to collectively control a plurality of semiconductor devices 700 using one control device 717.

[0090] When the power supply circuit 10 mounted on the semiconductor device 700 has a secondary battery, the secondary battery may be charged by wireless power supply.

[0091] The semiconductor device 700 may have a plurality of sensor circuits 301. FIG. 3 shows an example in which the semiconductor device 700 has two sensor circuits 301 (hereinafter, sensor circuit 301a and sensor circuit 301b). An "a" is attached to the end of the symbol of each circuit, terminal, etc. of the sensor circuit 301a, and a "b" is attached to the end of the symbol of each circuit, terminal, etc. of the sensor circuit 301b.

[0092] Control signals are respectively given from the terminal 94 of the PU21 to each circuit of the sensor circuit 301a via the terminal 93a and to each circuit of the sensor circuit 301b via the terminal 93b. Signals from the detection unit 711a and the analog-to-digital conversion circuit 713a are given to the terminal 94 via the terminal 93a, and signals from the detection unit 711b and the analog-to-digital conversion circuit 713b are given to the terminal 94 via the terminal 93b.

[0093] The signal INT, which is a signal requesting interrupt processing, is given to the terminal 82 from the determination circuit 712a and the determination circuit 712b, respectively.

[0094] Further, the sensor circuit 301 may have a plurality of sensor elements 710. FIG. 4 shows an example in which the sensor circuit 301 has two sensor elements 710 (hereinafter, sensor element 710c and sensor element 710d).

[0095] The detection signals of the sensor element 710c and the sensor element 710d are supplied to the detection unit 711. FIG. 4 shows an example in which the detection unit 711 has two sample-and-hold circuits 714 (hereinafter, sample-and-hold circuit 714c and sample-and-hold circuit 714d), and the detection signal of the sensor element 710c is supplied to the sample-and-hold circuit 714c, and the detection signal of the sensor element 710d is supplied to the sample-and-hold circuit 714d, respectively.

[0096] <Operation example of semiconductor device> Next, an operation example of the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 5.

[0097] Steps S000 to S009 are steps for explaining the operation of PU21, and steps S100 to S106 are steps for explaining the operation of the sensor circuit 301.

[0098] First, steps S000 to S009 and steps S100 to 101 will be described.

[0099] In step S000, the processing of PU21 is started. In step S100, the processing of the sensor circuit 301 is started.

[0100] In step S001, a data request signal is supplied from PU21 to the sensor circuit 301. In step S101, a first signal is supplied from the sensor circuit 301 to PU21. The first signal is a signal obtained by processing the detection signal of the sensor element 710 by the detection unit 711, the analog-to-digital conversion circuit 713, and the like.

[0101] Next, in step S002, the first signal is processed. Signal processing includes, for example, extraction of frequency components, noise removal, Fourier transform, differentiation of waveforms, etc. Note that it is also possible to proceed to step S003 without performing step S002.

[0102] Next, in step S003, the processed signal is analyzed. As signal analysis, for example, comparison with reference data is performed. Or for example, statistical processing of the signal is performed. As statistical processing, for example, the maximum value, minimum value, median, average value, standard deviation, etc. are calculated and compared with the reference data. Or for example, analysis using a neural network is performed.

[0103] Next, in step S004, if an abnormality is detected as a result of the analysis in step S003, the process proceeds to step S009, and if no abnormality is detected, the process proceeds to step S005 respectively.

[0104] In step S009, the operation of the object is controlled. For example, a signal notifying the abnormality is given to the control device 717, and the control device 717 controls the operation of the object. Also, in the semiconductor device 700 and the control device 717, the abnormality may be displayed by an indicator. Examples of the indicator include lighting or flashing of a lamp, input of a message to a display screen, sounding of a warning sound, etc.

[0105] In step S005, PU21 shifts to a standby state.

[0106] Next, in step S006, if PU21 does not receive an interrupt signal, the process proceeds to step S007. If an interrupt signal is received, the process proceeds to step S008, PU21 returns to the normal state, and the process returns to step S001.

[0107] In step S007, if a certain period of time has elapsed since step S005, the process proceeds to step S008, PU21 returns to the normal state, and the process returns to step S001. If the certain period of time has not elapsed, the process returns to step S006. The elapsed time since step S005 can be measured using a timer circuit.

[0108] By executing steps S001 to S008, when no interrupt signal is given from the sensor circuit 301, PU21 returns from the standby state to the normal state at regular intervals and can receive the detection signal from the sensor circuit 301. Also, when an interrupt signal is given from the sensor circuit 301, PU21 immediately returns to the normal state, returns to step S001, and can receive the detection signal from the sensor circuit 301. The semiconductor device according to one aspect of the present invention has a short time required for returning from the standby state to the normal state, and after receiving the interrupt signal from the sensor circuit 301, PU21 immediately returns to the normal state and can process and analyze the signal from the sensor circuit 301.

[0109] Next, steps S102 to S106 will be described.

[0110] In step S102, the sensor circuit 301 starts processing. The sensor element 710 performs detection.

[0111] Next, in step S103, the sensor element 710 gives a detection signal to the detection unit 711.

[0112] Next, in step S104, the detection signal is given to the determination circuit 712, and the determination circuit 712 determines the detection signal. Here, a comparison is made between the threshold value stored in advance in the determination circuit 712 or the memory and the detection signal. Note that the detection signal may be given to the determination circuit 712 after being processed by an analog-digital conversion circuit.

[0113] Next, in step S105, if the detection signal exceeds the threshold value as a result of the determination made in step S104, the process proceeds to step S106. If the threshold value is not exceeded, the process returns to step S103.

[0114] Next, in step S106, the sensor circuit 301 gives an interrupt signal to the PU21.

[0115] FIG. 6A shows an example of a perspective view of a semiconductor device 700 on which the PU21 and the sensor circuit 301 are mounted. In the semiconductor device 700 shown in FIG. 6A, the PU21 and the sensor circuit 301 are provided on one substrate.

[0116] FIG. 6B shows an example of a perspective view of a control device 717 and a plurality of semiconductor devices 700 controlled by the control device 717.

[0117] FIG. 6C is a perspective view showing an example in which a fan is used as an object 799, the semiconductor device 700 is placed on each of a plurality of fans, and each semiconductor device 700 is controlled by the control device 717.

[0118] The semiconductor device 700 has an acceleration sensor as a sensor element 710. It is possible to acquire acceleration time change data as a signal from the sensor element. Fast Fourier transform can be performed as processing on the obtained data.

[0119] The acceleration sensor can detect vibrations associated with the rotation of the fan. When an abnormality occurs in a motor or the like that drives the rotating part of the fan, a change occurs in the signal obtained from the sensor element. The PU21 included in the semiconductor device 700 analyzes the detection signal obtained from the sensor element, and when it is determined that an abnormality has occurred, it sends a signal to the control device 717. Also at this time, in the semiconductor device 700 and the control device 717, an indicator may notify the abnormality. The control device 717 restricts the operation of the object 799 in which the abnormality has occurred. For example, it changes the rotation speed of the fan or stops the rotation of the fan.

[0120] FIG. 7A shows an example of a sample-and-hold circuit 714. The sample-and-hold circuit 714 shown in FIG. 7A includes a buffer circuit 121, a transistor 122, and a capacitive element 123. For the sake of explanation, the node on the other side of the source or drain of the transistor 122 is referred to as node ND.

[0121] A potential Vs, which is a signal from the sensor element 710, is applied to the buffer circuit of the sample-and-hold circuit 714. The buffer circuit 121 has a function of amplifying and outputting a signal such as analog data input to the sample-and-hold circuit 714. Note that the buffer circuit 121 may be provided on the gate side of the transistor 122.

[0122] It is preferable to use an OS transistor as the transistor 122. The OS transistor has an extremely low off-current, and the capacitive element 123 has a function of holding, at node ND, a charge corresponding to the potential Vin, which is an analog potential, by turning off the transistor 122.

[0123] Note that the analog potential obtained by the sensor element may be constant or may always vary. When sampling a varying analog potential, sampling may be performed via a correlated double sampling (CDS) circuit. The correlated double sampling circuit is used for noise removal by obtaining the relative difference between two timings.

[0124] FIG. 7B shows an example of a correlated double sampling circuit. The correlated double sampling circuit includes a plurality of sample-and-hold circuits 714A to 714C. A control signal φ1 is applied to the transistors of the sample-and-hold circuit 714A, and a control signal φ2 is applied to the transistors of the sample-and-hold circuits 714B and 714C.

[0125] By using an OS transistor for the transistor that is turned off by the control signals φ1 and φ2, it is possible to reduce the variation in the sampled potential for taking the difference. Therefore, the accuracy of the correlation double sampling circuit can be improved. Also, after sampling the potential once, the power supply to the buffer circuits included in the sample and hold circuits 714A to 714C can be stopped, and power consumption can be reduced.

[0126] FIG. 7C shows a timing chart which is an example of the operation of the correlation double sampling circuit shown in FIG. 7B. The potential Vs is a fluctuating potential obtained by the sensor element 710, and the potential Vin is an analog potential that has passed through the correlation double sampling circuit. As shown in FIG. 7C, even if the potential Vs fluctuates, by sampling at a constant period and taking the difference, the potential Vin can be obtained as an analog potential having a constant potential with a voltage ΔV.

[0127] <Configuration Example 1 of Processing Device> The processing devices 20 and 21 are shown below as processing devices capable of power gating. The processing devices 20 and 21 can each be used as the processing device included in the semiconductor device 700 shown above. Also, the power management mechanisms and the like of the processing devices 20 and 21 will be described together.

[0128] FIG. 8A shows a power supply circuit 10 and a processing unit (PU). The PU 20 is a circuit having a function of executing instructions. The PU 20 has a plurality of functional circuits integrated on one chip. The PU 20 includes a processor core 30, a power management unit (PMU) 60, a clock control circuit 65, a power switch (PSW) 70, and terminals 80 to 83. FIG. 8A shows an example in which the power supply circuit 10 is provided on a chip different from the PU 20. The terminal 80 is a terminal to which a power supply potential MVDD is input from the power supply circuit 10. The terminal 81 is a terminal to which a reference clock signal CLKM is input from the outside. The terminal 82 is a terminal to which a signal INT is input from the outside. The signal INT is an interrupt signal that requests interrupt processing. The signal INT is input to the processor core 30 and the PMU 60. The terminal 83 is a terminal from which a control signal generated by the PMU 60 is output, and is electrically connected to the power supply circuit 10.

[0129] In the semiconductor device according to one aspect of the present invention, the number of bits that can be handled by the processing device according to one aspect of the present invention, such as an arithmetic circuit, can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

[0130] <Processor core 30, memory circuit 31> The processor core 30 is a circuit having a function of processing instructions and can be called an arithmetic processing circuit. It has a memory circuit 31, a plurality of combinational circuits 32, etc., and various functional circuits are configured by these. For example, the memory circuit 31 is included in a register.

[0131] As shown in FIG. 8B, the memory circuit 31 includes a circuit MemC1 and a circuit BKC1. The circuit MemC1 has a function of holding data generated by the processor core 30, and can be configured by, for example, a flip-flop circuit (FF), a latch circuit, or the like. The circuit BKC1 can function as a backup circuit for the circuit MemC1, and is a circuit capable of holding data for a long time even when the power supply is cut off or the clock signal is cut off. By having such a memory circuit 31, it becomes possible to perform power gating of the processor core 30. This is because, before cutting off the power supply, by saving the data of the circuit MemC1 to the circuit BKC1 in the memory circuit 31, the state of the processor core 30 at the time of power-off can be maintained. When the power supply is resumed, the data held in the circuit BKC1 is written into the circuit MemC1, so that the processor core 30 can be restored to the state at the time of power-off. Therefore, after the power supply is resumed, the PU20 can immediately perform normal processing operations.

[0132] The circuit BKC1 includes at least a holding circuit having one transistor (MW1) and one capacitive element (CB1). The holding circuit shown in FIG. 8B has the same circuit configuration as a 1T1C (one transistor one capacitive element) type memory cell of a standard DRAM (dynamic random access memory), and can perform write and read operations in the same manner. By controlling the conduction state of the transistor MW1, the charging and discharging of the capacitive element CB1 are controlled. By turning off the transistor MW1, the node FN1 becomes electrically floating. By making the drain current (off current) of the transistor MW1 in the off state extremely small, the fluctuation of the potential of the node FN1 can be suppressed, so that the data holding time of the circuit BKC1 can be extended. The data holding time of the circuit BKC1 is determined by the leakage current of the transistor MW1, the capacitance of the capacitive element CB1, and the like. By making the transistor MW1 a transistor with an extremely small off current, it is not necessary to refresh the circuit BKC1 during the period when the PU20 is operating. Therefore, the circuit BKC1 can be used as a non-volatile memory circuit.

[0133] It is preferable to use a transistor (also referred to as an "OS transistor" or "OS-FET") including an oxide semiconductor (Oxide Semiconductor: OS), which is a kind of metal oxide, in a semiconductor layer in which a channel is formed as the transistor MW1. Since the oxide semiconductor has a bandgap of 2 eV or more, the off-current is extremely small. In the OS transistor, in a state where the source-drain voltage is 10 V, the normalized off-current per 1 μm of channel width can be 10×10 -21 A (10 zepto A) or less. By using the transistor MW1 as the OS transistor, during the period when the PU20 is operating, the circuit BKC1 can function as a substantially non-volatile memory circuit. The OS transistor will be described in Embodiment 2.

[0134] The oxide semiconductor film used for the semiconductor layer in which the channel is formed may be formed of a single-layer oxide semiconductor film or a laminated oxide semiconductor film. The oxide semiconductor constituting the semiconductor layer in which the channel is formed is preferably an oxide containing at least one element of In, Ga, Sn, and Zn. As such oxides, In-Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In oxide, Sn oxide, Zn oxide, etc. can be used.

[0135] Since the circuit BKC1 writes data by voltage, it can suppress the writing power more than MRAM (Magnetoresistive RAM) that writes by current. Further, since the data is held by the load capacitance of the node FN1, there is no limit on the number of times of data rewriting like a flash memory.

[0136] In circuit BKC1, the energy required for data writing corresponds to the energy associated with the charging and discharging of the charge in capacitor element CB1. On the other hand, in a memory circuit using a two-terminal memory element such as MRAM, the energy required for data writing corresponds to the energy consumed when a current flows through the memory element. In MRAM, since a current continues to flow during the data writing period, the energy required for data writing becomes high. Compared with such MRAM, circuit BKC1 can reduce the energy consumed in data writing. Therefore, compared with a memory circuit configured with MRAM for the backup circuit, memory circuit 31 has more opportunities to perform voltage scaling and power gating that can reduce the consumed energy, so the power consumption of PU20 can be reduced.

[0137] <Power Management> PMU60 has a function of controlling power gating operation, clock gating operation, voltage scaling operation, etc. More specifically, PMU60 has a function of being able to control power supply circuit 10, a function of being able to control memory circuit 31, a function of being able to control clock control circuit 65, and a function of being able to control PSW70. Therefore, PMU60 has a function of generating control signals for controlling these circuits (power supply circuit 10, memory circuit 31, clock control circuit 65, PSW70). PMU60 has circuit 61. Circuit 61 has a function of being able to measure time. PMU60 has a function of being able to perform power management based on the data regarding time obtained by circuit 61.

[0138] PSW70 has a function of controlling the supply of the power potential MVDD to PU20 according to the control signal of PMU60. Here, the power potential supplied to PU20 via PSW70 is referred to as the power potential VDD. The processor core 30 may have a plurality of power domains. In this case, PSW70 may be used to independently control the power supply to the plurality of power domains. Further, the processor core 30 may have a power domain that does not need to perform power gating. In this case, the power potential may be supplied to this power domain without passing through PSW70.

[0139] The clock control circuit 65 has a function of receiving the reference clock signal CLKM, generating a gated clock signal, and outputting it. The clock control circuit 65 has a function of blocking the clock signal to the processor core 30 according to the control signal of PMU60. The power supply circuit 10 has a function of changing the magnitude of the potential of the power potential VDD according to the control signal of PMU60.

[0140] The signal SLP output from the processor core 30 to PMU60 is a signal that triggers the processor core 30 to enter the sleep state. When the signal SLP is input, PMU60 generates a control signal for entering the sleep state and outputs it to the functional circuit to be controlled. The power supply circuit 10 lowers the power potential MVDD based on the control signal of PMU60 to be lower than that during normal operation. When a certain period of time has elapsed in the sleep state, PMU60 controls PSW70 to cut off the power supply to the processor core 30. When the processor core 30 transitions from the normal state to the sleep state, PMU60 performs a voltage scaling operation to lower the power potential VDD of the processor core 30. When the period of the sleep state exceeds the set time, in order to further reduce the power consumption of the processor core 30, a power gating operation of stopping the supply of the power potential VDD to the processor core 30 is performed. Hereinafter, with reference to FIGS. 9 and 10, the power management of the semiconductor device shown in FIG. 8 will be described.

[0141] FIG. 9 schematically shows the change in the potential of the power line 35. The power line 35 is a wiring to which the power supply potential VDD is supplied via the PSW 70. The horizontal axis of the figure is the elapsed time (time) from the normal state to the standby state, and t0, t1, etc. represent time. FIG. 9A is an example in which only power gating is executed in the standby state, and FIG. 9B is an example in which only voltage scaling is executed in the standby state. FIGS. 9C and 9D are examples in which voltage scaling and power gating are executed. In the normal state, it is assumed that the magnitude of the power supply potential MVDD supplied from the power supply circuit 10 is VH1.

[0142] Also, hereinafter, the power supply mode of the PU 20 is classified into three modes: the power-on mode, the power-off mode, and the low-power mode. The power-on mode is a mode in which the power supply potential VDD at which normal processing is possible is supplied to the PU 20. The power-off mode is a mode in which the supply of the power supply potential VDD is stopped by the PSW 70. The low-power mode is a mode in which a power supply potential VDD lower than that in the power-on mode is supplied.

[0143] The example of FIG. 9A will be described. At time t0, the process of shifting to the standby state is started in the processor core 30. For example, the backup of the memory circuit 31 is performed. The PMU 60 controls the PSW 70 and cuts off the power supply to the processor core 30 at time t1. The power line 35 discharges naturally, and its potential drops to 0V. As a result, the leakage current of the processor core 30 in the standby state can be significantly reduced, so that the power consumption in the standby state (hereinafter sometimes referred to as standby power) can be reduced. When returning to the normal state due to an external interrupt request or the like, the PMU 60 controls the PSW 70 to resume the supply of VDD. Here, at time t4, the supply of VDD is resumed. The potential of the power line 35 rises and becomes VH1 at time t6.

[0144] In the case of the example of FIG. 9B, in order to perform voltage scaling, at time t1, the PMU 60 controls the power supply circuit 10 to lower the power supply potential MVDD to VH2. The potential of the power supply line 35 will eventually become VH2. At time t4, when the power supply potential MVDD returns from VH2 to VH1, the potential of the power supply line 35 rises and becomes VH1 at time t5.

[0145] In the case of the example of FIG. 9A, the time (overhead time) required to return from the standby state to the normal state is the time it takes for the potential of the power supply line 35 to rise from 0V to VH1. Also, the energy overhead required for the return is the energy required to charge the load capacitance of the power supply line 35 from 0V to VH1. If the period (t1 - t4) of the power-off mode is long enough, power gating is effective for reducing the standby power of the PU 20. On the other hand, if the period (t1 - t4) is short, the power required to return to the normal state becomes larger than the power that can be reduced by cutting off the power supply, and the effect of power gating cannot be obtained.

[0146] In the example of voltage scaling shown in FIG. 9B, since the potential of the power supply line 35 is VH2 in the standby state, the reduction amount of standby power is less than that in the example of power gating in FIG. 9A. On the other hand, in the example of FIG. 9B, since the fluctuation of the potential of the power supply line 35 is small, the time required to return to the normal state is shorter and the energy required for the return is less than that in the example of FIG. 9A. Therefore, in the semiconductor device shown in FIG. 8, in order to more efficiently reduce the standby power of the PU 20, power management combining power gating and voltage scaling is enabled. Examples of power management are shown in FIGS. 9C and 9D.

[0147] As shown in FIG. 9C, first, in the standby state, a voltage scaling operation is performed to shift from the power-on mode to the low-power mode. Similar to FIG. 9B, at time t1, the PMU 60 controls the power supply circuit 10 to lower the power supply potential MVDD to VH2, so the potential of the power supply line 35 will eventually become VH2. After a certain period (t1 - t3) has elapsed since shifting to the low-power mode, the PMU 60 controls the PSW 70 to enter the power-off mode. The period (t3 - t4) is a period in which it is possible to reduce power more by cutting off the power supply of the PU 20 by power gating, even including the power consumed to return to the normal state rather than supplying VH2 to the PU 20.

[0148] For example, assume that the potential VH2 is a power supply potential of a magnitude capable of holding data in the circuit MemC1 of the memory circuit 31, and the potential VH3 is a potential at which the data of the circuit MemC1 is lost. In the PU 20 of FIG. 8A, the circuit BKC1 is a circuit capable of holding data even during a period when the power supply is stopped. By saving the data of the memory circuit 31 to the circuit BKC1 during the period (t0 - t1), it is possible to lower VDD to the potential VH3 at which the data of the circuit MemC1 is lost in the low-power mode. Thereby, the standby power of the PU 20 can be further reduced.

[0149] The PMU 60 has a function of being able to return the PU 20 to the normal state based on an interrupt request or the like. The PMU 60 controls the power supply circuit 10 to boost the magnitude of MVDD to VH1, and also controls the PSW 70 to resume the supply of VDD to the PU 20. After time t4, it is the power-on mode. When the potential of the power supply line 35 stabilizes at time t6, the PU 20 can operate normally after time t6.

[0150] FIG. 9D shows an example in which there is an interrupt request to return to the normal operation before time t3. After time t2, it is the power-on mode. At time t2, the PMU 60 controls the power supply circuit 10 to change the magnitude of MVDD to the potential VH1 of the power-on mode. At time t3, the potential of the power supply line 35 rises to VH1.

[0151] As shown in FIGS. 9C and 9D, in the standby state, the time required to return the potential of the power supply line 35 to VH1 is longer when returning from the power-off mode to the power-on mode than when returning from the low-power mode to the power-on mode. Therefore, the PMU 60 has a function of being able to adjust the timing of the operation of returning the processor core 30 from the standby state to the normal state according to the power mode. This makes it possible to return the processor core 30 from the standby state to the normal state in the shortest time.

[0152] Also, in the standby state, the transition from the low-power mode to the power-off mode is made possible by measuring time with a circuit 61 provided in the PMU 60. When the signal SLP is input from the PU 20 to the PMU 60, the PMU 60 starts measuring time with the circuit 61. When a predetermined time has elapsed since entering the low-power mode, the PMU 60 shifts to the power-off mode. The PSW 70 is turned off by the control signal of the PMU 60, and the supply of VDD is cut off. In this way, it is possible to shift from the low-power mode to the power-off mode by an interrupt request based on the measurement data of the circuit 61. Hereinafter, an example of the power management operation of the PMU 60 will be described with reference to FIG. 10.

[0153] PU20 is performing normal operations. The power mode is the power-on mode, and PMU60 is in the idle state (step S10). PMU60 remains in the idle state until the signal SLP is input, and triggers the execution of the save sequence upon the input of the signal SLP (step S11). In the example of the save sequence in FIG. 10, first, PMU60 outputs a control signal to the clock control circuit 65 to stop the output of the clock signal (step S12). Next, a control signal for causing data saving is output to the storage circuit 31 (step S13). In the storage circuit 31, according to the control signal of PMU60, the data held in the circuit MemC1 is saved to the circuit BKC1. Finally, PMU60 controls the power supply circuit 10 to reduce MVDD. By these operations, the power mode shifts to the low-power mode (step S14). When the signal SLP is input, PMU60 controls the built-in circuit 61 to measure the time Ta in the low-power mode (step S15). The timing for operating the circuit 61 can be arbitrary as long as it is during the execution of the save sequence. For example, when the signal SLP is input, when a control signal is output to the clock control circuit 65, when data saving starts, when data saving ends, when a control signal is output to the power supply circuit 10, etc.

[0154] After the execution of the save sequence, PMU60 becomes idle (step S16), monitors the input of the signal INT, and monitors the time Ta which is the measurement time of the clock control circuit 65. When the signal INT is input, it shifts to the return sequence (step S17). It is determined whether the time Ta exceeds the set time T vs (step S18). If PMU60 determines that the time Ta exceeds the time T vs , it performs control to shift the power mode to the power-off mode (step S19), and if it does not exceed, the idle state is maintained (step S16). The time T vs may be set to a time such that the standby power of the processor core 30 can be reduced more in the power-off mode than in the low-power mode.

[0155] In step S19, the PMU 60 outputs a control signal to the PSW 70 to cut off the power supply to the processor core 30. After entering the power-off mode, the PMU 60 again enters the idle state (step S20) and monitors the input of the signal INT (step S21). When the signal INT is input, the PMU 60 executes a return sequence.

[0156] In the return sequence, first, the PMU 60 shifts from the power-off mode to the power-on mode (step S22). The PMU 60 controls the power circuit 10 to output the power potential for normal operation. Also, the PMU 60 controls the PSW 70 to resume the supply of VDD to the processor core 30. Next, a control signal is output to the memory circuit 31 to restore the data in the memory circuit 31 (step S23). The memory circuit 31 writes back the data held in the circuit BKC1 to the circuit MemC1 according to the control signal of the PMU 60. The PMU 60 outputs a control signal for outputting a clock signal to the clock control circuit 65 (step S24). The clock control circuit 65 resumes the output of the clock signal according to the control signal of the PMU 60.

[0157] When executing the return sequence from the determination process in step S17, it will return from the low-power mode to the power-on mode, and the potential of the power line 35 can be stabilized faster than when executing the return sequence from the determination process in step S21. Therefore, in the PMU 60, when shifting to the return sequence from step S17, the timing of executing step S23 is made earlier than when shifting to the return sequence from step S21. Thereby, the time for the processor core 30 to resume from the pause state to the normal state can be shortened.

[0158] As described above, in the power management of the semiconductor device shown in FIG. 8, when PU20 enters the standby state, first, by the voltage scaling operation, the power supply potential supplied to the processor core 30 is lowered to reduce the leakage current, while suppressing the time and energy overhead of the process of returning from the standby state to the normal state. When the standby state continues for a certain period, a power gating operation is performed to suppress the leakage current of the processor core 30 as much as possible. As a result, it becomes possible to reduce the power consumption in the standby state of PU20 without degrading the processing ability of PU20.

[0159] <<Configuration Example 2 of Processing Device>> FIG. 11A shows a modified example of the processing device of FIG. 8A. The processing device (PU) 21 shown in FIG. 11A is obtained by adding a cache 40 and a power switch (PSW) 71 to PU20. The cache 40 can be power gated and voltage scaled in the same manner as PU20, and the power mode of the cache 40 also changes in conjunction with the power mode of PU21. The PSW 71 is a circuit that controls the supply of the power supply potential MVDD to the cache 40 and is controlled by the PMU 60. Here, the power supply potential input to the cache 40 via the PSW 71 is designated as VDD_MEM. The cache 40 receives a control signal from the PMU 60 and a gated clock signal from the clock control circuit 65 in the same manner as the processor core 30.

[0160] <Cache 40> The cache 40 is a storage device having a function of temporarily storing frequently used data. The cache 40 includes a memory array 41, a peripheral circuit 42, and a control circuit 43. The memory array 41 includes a plurality of memory cells 45. The control circuit 43 controls the operation of the cache 40 in accordance with the requests of the processor core 30. For example, it controls the write operation and read operation of the memory array 41. The peripheral circuit 42 has a function of generating a signal for driving the memory array 41 in accordance with a control signal from the control circuit 43. The memory array 41 includes memory cells 45 that hold data.

[0161] As shown in FIG. 11B, the memory cell 45 has a circuit MemC2 and a circuit BKC2. The circuit MemC2 is a memory cell to be accessed in normal operation. For example, a memory cell of SRAM (Static Random Access Memory) may be applied. The circuit BKC2 can function as a backup circuit of the circuit MemC2 and is a circuit capable of holding data for a long period even when the power supply is cut off or the clock signal is cut off. By providing such a memory cell 45, it becomes possible to perform power gating of the cache 40. Before cutting off the power supply, in the memory cell 45, the data of the circuit MemC2 is saved to the BKC2. After restarting the power supply, by writing back the data held in the circuit BKC2 to the circuit MemC2, it is possible to quickly return the PU21 to the state before the power supply was cut off.

[0162] Similar to the circuit BKC1 in FIG. 8B, the circuit BKC2 of the memory cell 45 also has at least a holding circuit having one transistor (MW2) and one capacitive element (CB2). That is, the circuit BKC2 also has a holding circuit with a configuration similar to that of a standard DRAM 1T1C type memory cell. The transistor MW2 has an extremely low off-current. For the transistor MW2, an OS transistor may be applied in the same manner as the transistor MW1. With such a configuration, the circuit BKC2 can also suppress fluctuations in the potential of the node FN2, which is in an electrically floating state, so that the circuit BKC2 can hold data for a long period. The data holding time of the circuit BKC2 is determined by the leakage current of the transistor MW2, the capacitance of the capacitive element CB2, etc. By making the transistor MW2 a transistor with an extremely small off-current, it becomes possible to use the circuit BKC2 as a non-volatile memory circuit that does not require a refresh operation.

[0163] In the PU21 shown in FIG. 11A as well, similar to the PU20, the PMU60 performs power management. (See FIG. 10). In step S13 shown in FIG. 10, the data backup operation of the memory circuit 31 and the cache 40 is performed. In step S19, the PSW70 and PSW71 are controlled to stop the power supply to the processor core 30 and the cache 40. In step S22, the PSW70 and PSW71 are controlled to resume the power supply to the processor core 30 and the cache 40. In step S23, the data restoration operation of the memory circuit 31 and the cache 40 is performed.

[0164] Therefore, similar to the semiconductor device shown in FIG. 8, the semiconductor device shown in FIG. 11 also performs power management by combining voltage scaling and power gating, so that it is possible to reduce the power in the standby state of the PU21 without degrading the processing ability of the PU21.

[0165] <<Configuration Example of Processor Core>> FIG. 12 shows a configuration example of a processor core. The processor core 130 shown in FIG. 12 includes a control device 131, a program counter 132, a pipeline register 133, a pipeline register 134, a register file 135, an arithmetic logic unit (ALU) 136, and a data bus 137. The data exchange between the processor core 130 and peripheral circuits such as the PMU and the cache is performed via the data bus 137.

[0166] The control device 131 has a function of decoding and executing instructions included in an input program such as an application by comprehensively controlling the operations of the program counter 132, the pipeline register 133, the pipeline register 134, the register file 135, the ALU 136, and the data bus 137. The ALU 136 has a function of performing various arithmetic processes such as arithmetic operations and logical operations. The program counter 132 is a register having a function of storing the address of the next instruction to be executed.

[0167] The pipeline register 133 is a register that temporarily stores instruction data. The register file 135 has a plurality of registers including general-purpose registers, and can store data read from the main memory, or data obtained as a result of arithmetic processing by the ALU 136, etc. The pipeline register 134 is a register that has a function of temporarily storing data used for arithmetic processing by the ALU 136, or data obtained by arithmetic processing by the ALU 136, etc.

[0168] The storage circuit 31 in FIG. 8B is used for the registers included in the processor core 130.

[0169] <Configuration example of storage circuit> A more specific configuration example of the storage circuit 31 shown in FIG. 8B will be described. FIG. 13 is a circuit diagram showing an example of the configuration of the storage circuit. The storage circuit 100 shown in FIG. 13 functions as a flip-flop circuit.

[0170] It is possible to apply a standard flip-flop circuit (FF) to the circuit MemC1. For example, a master-slave type FF can be applied. Such a configuration example is shown in FIG. 13. The FF 110 has transmission gates (TG1, TG2, TG3, TG4, TG5), inverter circuits (INV1, INV2), and NAND circuits (NAND1, NAND2). The signal RESET and the signal OSR are control signals output from the PMU 60. The signal OSR and its inverted signal are input to TG5. The clock signal CLK and its inverted signal are input to TG1 - TG4. Instead of TG1 and INV1, one clocked inverter circuit may be provided. Instead of TG2 and NAND2, one clocked NAND circuit may be provided. Instead of TG3 and INV3, a clocked inverter circuit may be provided. TG5 functions as a switch that controls the conduction state between the output node of NAND1 and the node NR1. The node NB1 is electrically connected to the input node of the circuit BKC10, and the node NR1 is electrically connected to the output node of the circuit BKC10.

[0171] The circuit BKC10 shown in FIG. 13 functions as a backup circuit for the FF110. The circuit BKC10 includes a circuit RTC10 and a circuit PCC10. The signals (OSG, OSC, OSR) input to the circuit BKC10 are control signals output from the PMU60. The power supply potential VSS is a low power supply potential, for example, it may be the ground potential (GND) or 0V. The power supply potential VSS and the power supply potential VDD are also input to the FF110 in the same manner as in BKC1. In the memory circuit 100, the supply of VDD is managed by the PMU60.

[0172] The circuit RTC10 includes a transistor MW1, a transistor MA1, a transistor MR1, a node FN1, and a node NK1. The circuit RTC10 has a function of holding data, and here it is composed of a memory circuit with a 3T type gain cell structure. The transistor MW1 is a write transistor and an OS transistor. The transistor MR1 is a read transistor, and the transistor MA1 is an amplification transistor and a read transistor. Data is held at the node FN1. The node NK1 is a data input node. The node NR1 is an output node of the data of the circuit RTC10.

[0173] FIG. 13 shows a configuration example in which the circuit BKC10 reads the data of the slave - side latch circuit of the FF110 during the backup operation and writes back the held data to the master - side latch circuit during the recovery operation. The data to be backed up may be the data of the master - side latch circuit. Also, the data may be restored to the slave - side latch circuit. In this case, TG5 may be provided in the slave - side latch circuit.

[0174] Also, the transistors MR1 and MA1 of the circuit RTC10 can be either n-type or p-type. The potential of the signal OSR and the level of the power supply potential supplied to the transistor MA1 can be changed according to the conductivity types of the transistors MR1 and MA1. Also, the logic circuit of the FF110 can be set as appropriate. For example, when the transistors MR1 and MA1 are p-type transistors, in the master-side latch circuit, NAND1 and INV3 can be interchanged, and in the slave-side latch circuit, INV2 and NAND2 can be interchanged. Also, the input to the transistor MA1 can be changed from VSS to VDD.

[0175] Since the circuit BKC10 writes data by voltage, it can suppress the writing power more than MRAM that writes by current. Also, since the data is held by the load capacitance of the node FN1, there is no limit on the number of times of data rewriting like flash memory.

[0176] In the circuit RTC10, the energy required for data writing corresponds to the energy associated with the charging and discharging of the charge to the capacitive element CB1. On the other hand, in a memory circuit using a two-terminal memory element such as MRAM, the energy required for data writing corresponds to the energy consumed when a current flows through the memory element. Therefore, compared with the case of using MRAM or the like in which a current continues to flow during the data writing period, the circuit BKC10 can reduce the energy consumed by data evacuation. Therefore, by providing the circuit BKC10 in the backup circuit, the BET (Break Even Time) can be shortened compared with the case of providing MRAM. As a result, the opportunity to perform power gating that can reduce the consumed energy increases, and the power consumption of the semiconductor device can be reduced.

[0177] The circuit PCC10 has transistors MC1 and MC2. The circuit PCC10 has a function of precharging node FN1. The circuit PCC10 may not be provided. As will be described later, by providing the circuit PCC10, the data backup time of the circuit BKC10 can be shortened.

[0178] <Operation Example of Memory Circuit> FIG. 14 is a timing chart showing an example of the operation of the memory circuit 100, and shows the waveforms of the control signals (signal SLP, signal RESET, clock signal CLK, signal OSG, signal OSR), and the changes in the power supply potential VDD, the potential of node FN1, and the potential of node NR1.

[0179] [Normal Operation] The period of "Normal Operation" in FIG. 14 will be described. The memory circuit 100 is supplied with the power supply potential VDD and the clock signal CLK. FF110 functions as a sequential circuit. Since the signal RESET is maintained at a high level, NAND1 and NAND2 function as inverter circuits. In the circuit BKC1, since the transistor MC1 is in an off state and the transistors MC2 and MW1 are in an on state, the potential of node FN1 is precharged to a high level.

[0180] [Data Backup] Next, the "Back up" period in FIG. 14 will be described. First, the clock signal CLK is stopped. As a result, the rewriting of the data at node NB1 is stopped. In the example of FIG. 14, the potential level of node NB1 is low level ("0") if the potential of node NR1 is high level ("1"), and high level ("1") if it is low level ("0"). During the period when the signal OSC is at high level, the data at node NB1 is backed up to node FN1. Specifically, since transistors MC1 and MW1 are in the on state, node FN1 and node NB1 are electrically connected. By setting the signal OSG to low level and turning off transistor MW1, node FN1 becomes electrically floating, and circuit BKC10 enters the data holding state. The potential of node FN1 is high level if node NR1 is low level ("0"), and low level if it is high level ("1").

[0181] Since the backup of data is completed by setting the signal OSG to low level, after setting the signal OSG to low level, the voltage scaling operation of PU20 can be immediately performed. Also, since node FN1 is pre-charged to high level during normal operation by transistor MC2, no charge movement occurs at node FN1 during the data backup operation to set node FN1 to high level. Therefore, circuit BKC10 can complete the backup operation in a short time.

[0182] In the data backup operation, it is only necessary for the clock signal CLK to be inactive. In the example of FIG. 14, the potential of the clock signal CLK is set to low level, but it may also be set to high level.

[0183] [Voltage Scaling, Low Power Mode] Next, the "Low power" period in FIG. 14 will be described. In conjunction with the fall of the signal OSC, PMU60 performs a voltage scaling operation. As a result, the memory circuit 100 shifts to the low power mode.

[0184] [Power Gating, Power Off Mode] Next, the period of "Power off" in FIG. 14 will be described. When a certain period has elapsed after shifting to the low power mode, the PMU 60 performs a power gating operation to turn off the memory circuit 100 to the power-off mode.

[0185] [Power-on mode] Next, the period of "Power on" in FIG. 14 will be described. In response to an interrupt request, the PMU 60 returns the memory circuit 100 to the power-on mode. In the example of FIG. 14, when the potential of the power supply line that supplies VDD stabilizes, the clock signal CLK is set to a high level.

[0186] [Data restoration] The data restoration operation is performed during the period when the signal OSR is at a high level. By setting the signal RESET to a high level, the potential of the node NR1 is pre-charged to a high level ("1"). By setting the signal OSR to a high level, TG5 becomes a high impedance state and the transistor MR1 becomes a conducting state. The conducting state of the transistor MA1 is determined by the potential of the node FN1. If the node FN1 is at a high level, since the transistor MA1 is in a conducting state, the potential of the node NR1 decreases and becomes a low level ("0"). If the node FN1 is at a low level, the potential of the node NR1 is maintained at a high level. That is, the state of the FF110 is restored to the state before shifting to the standby state.

[0187] As described above, by the rising edges of the signal RESET and the signal OSR, high-level data can be restored to the node NR1. Therefore, the memory circuit 100 can shorten the restoration operation period.

[0188] FIG. 14 shows an example of returning from the power-off mode to the power-on mode. When returning from the low power mode to the power-on mode, the period T on until the potential of the power supply line that supplies VDD stabilizes becomes shorter. In this case, it is preferable to raise the signal OSR earlier than when returning from the power-off mode.

[0189] [Normal operation] Next, the period of "Normal operation" in FIG. 14 will be described. By resuming the supply of the clock signal CLK, the state where normal operation is possible is restored. By setting the signal OSG to a high level, the node FN1 is precharged by the circuit PCC10 and becomes high level.

[0190] [[CACHE]] An example of configuring the cache 40 with SRAM will be described below.

[0191] [Example of memory cell configuration] FIG. 15 shows an example of the configuration of the memory cell of the cache. The memory cell 120 shown in FIG. 15 has a circuit SMC20 and a circuit BKC20. The circuit SMC20 may have the same circuit configuration as a standard SRAM memory cell. The circuit SMC20 shown in FIG. 15 has an inverter circuit INV11, an inverter circuit INV12, a transistor M11, and a transistor M12.

[0192] The circuit BKC20 functions as a backup circuit for the circuit SMC20. The circuit BKC20 has transistors MW11, MW12, capacitor elements CB11, and capacitor elements CB12. The transistors MW11 and MW12 are OS transistors. The circuit SMC20 has two 1T1C type holding circuits, and data is held at the nodes SN1 and SN2 respectively. The holding circuit composed of the transistor MW11 and the capacitor element CB11 has a function of backing up the data at the node NET1. The holding circuit composed of the transistor MW12 and the capacitor element CB12 has a function of backing up the data at the node NET2.

[0193] The memory cell 120 is supplied with a power supply potential VDDMC and VSS. The memory cell 120 is electrically connected to wirings (WL, BL, BLB, BRL). A signal SLC is input to the wiring WL. At the time of data writing, data signals D and DB are input to the wirings BL and BLB, respectively. Data reading is performed by detecting the potentials of the wirings BL and BLB. A signal OSS is input to the wiring BRL. The signal OSS is a signal input from the PMU60.

[0194] <Operation Example of Memory Cell> An example of the operation of the memory cell 120 will be described. FIG. 16 is an example of a timing chart of the memory cell 120.

[0195] [Normal Operation] An access request is made to the circuit MemC2, and data writing and reading are performed. In the circuit BKC2, since the signal OSS is at a low level, the nodes SN1 and SN2 are in an electrically floating state and are in a data holding state. In the example of FIG. 16, the potential of the node SN1 is at a low level ("0"), and the potential of the other node, the node SN2, is at a high level ("1").

[0196] [Data Backup] By setting the signal OSS to a high level, the transistors MW11 and MW12 become conductive states, and the nodes SN1 and SN2 have the same potential levels as the nodes NET1 and NET2, respectively. In the example of FIG. 16, the potentials of the nodes SN1 and SN2 are at a high level and a low level, respectively. When the signal OSS becomes a low level and the circuit BKC20 enters a data holding state, the data backup operation ends.

[0197] [Voltage Scaling, Low Power Mode] In conjunction with the fall of the signal OSS, the PMU60 performs a voltage scaling operation. As a result, the cache 40 shifts to the low power mode.

[0198] [Power Gating, Power Off Mode] After a certain period of time has elapsed since transitioning to the low power mode, the PMU 60 performs a power gating operation to turn off the cache 40.

[0199] [Data restoration, power-on mode] In response to an interrupt request, the PMU 60 restores the cache 40 to its normal state. By setting the signal OSS to a high level, the data held in the circuit BKC 20 is written back to the circuit SMC 20. During the period when the signal OSS is at a high level, the PMU 60 performs a voltage scaling operation and a power gating operation to restore the memory circuit 100 to the power-on mode. In the example of FIG. 14, when the potential of the power supply line supplying VDD stabilizes, the clock signal CLK is set to a high level. When the potential of the power supply line supplying VDDMC stabilizes, the signal OSS is returned to a low level to end the data restoration operation. The states of the nodes SN1 and SN2 are restored to the states just before entering the standby state.

[0200] [Normal operation] By resuming the supply of VDDMC, the circuit SMC 20 returns to the normal mode in which normal operation is possible.

[0201] As described above, by using an OS transistor, it is possible to configure a backup circuit that can hold data for a long time even when the power is cut off. By providing this backup circuit, it becomes possible to perform power gating on the processor core and the cache. Also, in the standby state, by performing power management that combines voltage scaling and power gating, it is possible to reduce the energy and time overhead required for the process of returning from the standby state to the normal state. Therefore, it is possible to efficiently reduce power without degrading the processing ability of the processing device.

[0202] <An example of a memory> Hereinafter, a memory using the OS transistor according to one aspect of the present invention will be described.

[0203] The power storage device according to one aspect of the present invention preferably has a memory. As the memory, a memory device using an OS transistor can be applied. For example, NOSRAM (registered trademark), DOSRAM (registered trademark), etc. described below can be applied.

[0204] NOSRAM refers to a gain cell type DRAM in which the write transistor of a memory cell is composed of an OS transistor. NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. A configuration example of NOSRAM is shown below.

[0205] FIG. 17A is a block diagram showing a configuration example of NOSRAM. In NOSRAM 240, power domains 242 and 243, and power switches 245 to 247 are provided. In power domain 242, a memory cell array 250 is provided, and in power domain 243, peripheral circuits of NOSRAM 240 are provided. The peripheral circuits include a control circuit 251, a row circuit 252, and a column circuit 253.

[0206] Voltage VDDD, voltage VSSS, voltage VDHW, voltage VDHR, voltage VBG2, clock signal GCLK2, address signal Address, signal CE, signal WE, and signal PSE5 are input to NOSRAM 240 from the outside. Signal CE and signal WE are chip enable signals and write enable signals. Signal PSE5 controls the on / off of power switches 245 to 247. Power switches 245 to 247 respectively control the input of voltage VDDD, voltage VDHW, and voltage VDHR to power domain 243.

[0207] Note that the voltage, signal, etc. input to NOSRAM 240 are appropriately selected according to the circuit configuration and operation method of NOSRAM 240. For example, a power domain that is not power gated may be provided in NOSRAM 240, and a power gating control circuit that generates signal PSE5 may be provided.

[0208] The memory cell array 250 has memory cells 11, write word lines WWL, read word lines RWL, write bit lines WBL, read bit lines RBL, and source lines SL.

[0209] As shown in FIG. 17B, the memory cell 11 is a 2T1C (2 transistor 1 capacitor) type gain cell and has a node SN1, transistors M1, M2, and a capacitor element C1. The transistor M1 is a write transistor and is an OS transistor having a back gate. The back gate of the transistor M1 is electrically connected to a wiring BGL2 that supplies a voltage VBG2. The transistor M2 is a read transistor and is a p-channel type Si transistor. The capacitor element C1 is a holding capacitor that holds the voltage of the node SN1.

[0210] The voltages VDDD and VSSS are voltages representing data "1" and "0". Note that the high-level voltages of the write word line WWL and the read word line RWL are the voltages VDHW and VHDR.

[0211] FIG. 18A shows a configuration example of the memory cell array 250. In the memory cell array 250 shown in FIG. 18, one source line is supplied for every two adjacent rows.

[0212] In principle, the memory cell 11 has no limit on the number of rewrite times, can rewrite data with low energy, and does not consume power for data holding. Since the transistor M1 is an OS transistor with an extremely small off-current, the memory cell 11 can hold data for a long time. Therefore, by configuring a cache memory device with the NOSRAM 240, the cache memory device can be made into a non-volatile low-power memory device.

[0213] The circuit configuration of the memory cell 11 is not limited to the circuit configuration of FIG. 17B. For example, the read transistor M2 may be an OS transistor having a back gate or an n-channel type Si transistor. Alternatively, the memory cell 11 may be a 3T gain cell. Examples of the 3T gain cell are shown in FIGS. 18B and 18C. The memory cell 15 shown in FIG. 18B includes transistors M3 to M5, a capacitor element C3, and a node SN3. The transistors M3 to M5 are a write transistor, a read transistor, and a selection transistor. The transistor M3 is an OS transistor having a back gate, and the transistors M4 and M5 are p-channel type Si transistors. The transistors M4 and M5 may be configured with n-channel type Si transistors or OS transistors having a back gate. In the memory cell 16 shown in FIG. 18C, the three transistors are configured with OS transistors having a back gate.

[0214] The node SN3 is a holding node. The capacitor element C3 is a holding capacitor for holding the voltage of the node SN3. The capacitor element C3 may not be intentionally provided, and the holding capacitor may be configured by the gate capacitance of the transistor M4 or the like. A fixed voltage (for example, VDDD) is input to the wiring PDL. The wiring PDL is a wiring that replaces the source line SL, and for example, the voltage VDDD is input.

[0215] The control circuit 251 has a function of controlling the overall operation of the NOSRAM 240. For example, the control circuit 251 performs a logical operation on the signals CE and WE to determine whether the external access is a write access or a read access.

[0216] The row circuit 252 has a function of selecting the write word line WWL and the read word line of the selected row specified by the address signal. The column circuit 253 has a function of writing data to the write bit line of the column specified by the address signal and a function of reading data from the read bit line of the column.

[0217] DOSRAM is a RAM that has a 1T1C type memory cell and is an abbreviation for Dynamic Oxide Semiconductor RAM. Hereinafter, with reference to FIG. 19, DOSRAM will be described.

[0218] As shown in FIG. 19A, the memory cell 16 of DOSRAM 351 is electrically connected to the bit line BL1 (or BLB1), the word line WL1, the wiring BGL6, and the PL. The bit line BLB1 is an inverted bit line. For example, the voltages VBG6 and VSSS are input to the wirings BGL6 and PL. It has the transistor M6 and the capacitor element C6. The transistor M6 is an OS transistor having a back gate.

[0219] In order to rewrite data by charging and discharging the capacitor element C6, there is in principle no restriction on the number of rewrite times for DOSRAM 351, and data can be written and read with low energy. Also, since the circuit configuration of the memory cell 16 is simple, it is easy to increase the capacity. Since the write transistor of the memory cell 16 is an OS transistor, the retention time of DOSRAM 351 is very long compared to DRAM. Therefore, the frequency of refreshing can be reduced, or the refresh operation can be made unnecessary, so that the power required for the refresh operation can be reduced.

[0220] As shown in FIG. 19B, in DOSRAM 351, the memory cell array 361 can be stacked on the peripheral circuit 365. This is because the transistor M6 of the memory cell 16 is an OS transistor.

[0221] In the memory cell array 361, a plurality of memory cells 16 are arranged in a matrix, and according to the arrangement of the memory cells 16, the bit lines BL1, BLB1, the word line WL1, the wiring BGL6, and the PL are provided. The peripheral circuit 365 is provided with a control circuit, a row circuit, and a column circuit. The row circuit selects the word line WL1 to be accessed, etc. The column circuit writes and reads data, etc., for the bit line pair consisting of BL1 and BLB1.

[0222] Power switches 371 and 373 are provided to perform power gating on the peripheral circuit 365. The power switches 371 and 373 control the inputs of voltages VDDD and VDHW6 to the peripheral circuit 365, respectively. Note that the voltage VDHW6 is the high-level voltage of the word line WL1. The on / off states of the power switches 371 and 373 are controlled by the signal PSE6.

[0223] <An example of an arithmetic circuit> Next, a configuration example of a semiconductor device that can be used for neural network operations will be described.

[0224] As shown in FIG. 20A, the neural network NN can be composed of an input layer ILy, an output layer OLy, and an intermediate layer (hidden layer) HLy. The input layer ILy, the output layer OLy, and the intermediate layer HLy each have one or more neurons (units). Note that the intermediate layer HL may be one layer or two or more layers. A neural network having two or more intermediate layers HLy can also be called a DNN (Deep Neural Network), and learning using a deep neural network can also be called deep learning.

[0225] Input data is input to each neuron of the input layer ILy, the output signal of a neuron in the previous layer or the next layer is input to each neuron of the intermediate layer HLy, and the output signal of a neuron in the previous layer is input to each neuron of the output layer OLy. Note that each neuron may be connected to all neurons in the previous and subsequent layers (fully connected) or may be connected to some neurons.

[0226] FIG. 20B shows an example of calculation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Output x1 of the neuron in the previous layer and output x2 of the neuron in the previous layer are input to neuron N. Then, in neuron N, after calculating the sum x1w1 + x2w2 of the multiplication result (x1w1) of output x1 and weight w1 and the multiplication result (x2w2) of output x2 and weight w2, a bias b is added as necessary, and a value a = x1w1 + x2w2 + b is obtained. Then, the value a is converted by the activation function h, and an output signal y = h(a) is output from neuron N.

[0227] Thus, the calculation by a neuron includes an operation of adding up the products of the outputs of the neurons in the previous layer and the weights, that is, a multiply-accumulate operation (the above x1w1 + x2w2). This multiply-accumulate operation may be performed on software using a program or may be performed by hardware. When performing the multiply-accumulate operation by hardware, a multiply-accumulate circuit can be used. As this multiply-accumulate circuit, a digital circuit or an analog circuit may be used. When using an analog circuit for the multiply-accumulate circuit, it is possible to reduce the circuit scale of the multiply-accumulate circuit or improve the processing speed and reduce the power consumption by reducing the number of accesses to the memory.

[0228] The multiply-accumulate circuit may be configured by transistors (hereinafter also referred to as Si transistors) including silicon (such as single-crystalline silicon) in the channel formation region, or may be configured by transistors (hereinafter also referred to as OS transistors) including an oxide semiconductor in the channel formation region. In particular, since the OS transistor has an extremely small off-current, it is suitable as a transistor constituting the memory of the multiply-accumulate circuit. Note that the multiply-accumulate circuit may be configured using both Si transistors and OS transistors. Hereinafter, a configuration example of a semiconductor device having the function of the multiply-accumulate circuit will be described.

[0229] Fig. 21 shows a configuration example of a semiconductor device MAC having a function of performing neural network operations. The semiconductor device MAC has a function of performing a sum-of-products operation on first data corresponding to the coupling strength (weight) between neurons and second data corresponding to input data. Note that the first data and the second data can each be analog data or multi-valued digital data (discrete data). Further, the semiconductor device MAC has a function of converting the data obtained by the sum-of-products operation by an activation function.

[0230] The semiconductor device MAC includes a cell array CA, a current source circuit CS, a current mirror circuit CM, a circuit WDD, a circuit WLD, a circuit CLD, an offset circuit OFST, and an activation function circuit ACTV.

[0231] The cell array CA includes a plurality of memory cells MC and a plurality of memory cells MCref. Fig. 21 shows a configuration example in which the cell array CA has memory cells MC (MC[1,1] to [m,n]) arranged in m rows and n columns (m and n are integers of 1 or more) and m memory cells MCref (MCref[1] to [m]). The memory cell MC has a function of storing first data. The memory cell MCref has a function of storing reference data used for the sum-of-products operation. Note that the reference data can be analog data or multi-valued digital data.

[0232] The memory cell MC[i,j] (i is an integer from 1 to m, j is an integer from 1 to n) is connected to a wiring WL[i], a wiring RW[i], a wiring WD[j], and a wiring BL[j]. The memory cell MCref[i] is connected to a wiring WL[i], a wiring RW[i], a wiring WDref, and a wiring BLref. Here, the current flowing between the memory cell MC[i,j] and the wiring BL[j] is denoted as I MC[i,j] and the current flowing between the memory cell MCref[i] and the wiring BLref is denoted as I MCref[i] as described above.

[0233] A specific configuration example of the memory cell MC and the memory cell MCref is shown in FIG. 22. FIG. 22 shows, as representative examples, memory cells MC[1,1], [2,1] and memory cells MCref[1], [2], but the same configuration can also be used for other memory cells MC and memory cells MCref. The memory cell MC and the memory cell MCref each have transistors Tr11, Tr12 and a capacitive element C11. Here, the case where the transistor Tr11 and the transistor Tr12 are n-channel type transistors will be described.

[0234] In the memory cell MC, the gate of the transistor Tr11 is connected to the wiring WL, one of the source or drain is connected to the gate of the transistor Tr12 and the first electrode of the capacitive element C11, and the other of the source or drain is connected to the wiring WD. One of the source or drain of the transistor Tr12 is connected to the wiring BL, and the other of the source or drain is connected to the wiring VR. The second electrode of the capacitive element C11 is connected to the wiring RW. The wiring VR is a wiring having a function of supplying a predetermined potential. Here, as an example, the case where a low power supply potential (such as a ground potential) is supplied from the wiring VR will be described.

[0235] A node connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is defined as the node NM. Also, the nodes NM of the memory cells MC[1,1], [2,1] are denoted as nodes NM[1,1], [2,1], respectively.

[0236] The memory cell MCref also has the same configuration as the memory cell MC. However, the memory cell MCref is connected to a wiring WDref instead of the wiring WD, and is connected to a wiring BLref instead of the wiring BL. Also, in the memory cells MCref[1], [2], a node connected to one of the source or drain of the transistor Tr11, the gate of the transistor Tr12, and the first electrode of the capacitive element C11 is denoted as node NMref[1], [2], respectively.

[0237] Node NM and node NMref each function as the holding nodes of memory cell MC and memory cell MCref, respectively. The first data is held in node NM, and reference data is held in node NMref. Also, currents I MC[1,1] , I MC[2,1] flow through the transistors Tr12 of memory cells MC[1,1], [2,1] from wiring BL[1]. Also, currents I MCref[1] , I MCref[2] flow through the transistors Tr12 of memory cells MCref[1], [2] from wiring BLref.

[0238] Since transistor Tr11 has the function of holding the potential of node NM or node NMref, it is preferable that the off-current of transistor Tr11 is small. Therefore, it is preferable to use an OS transistor with an extremely small off-current as transistor Tr11. Thereby, fluctuations in the potential of node NM or node NMref can be suppressed, and the arithmetic accuracy can be improved. Also, the frequency of the operation for refreshing the potential of node NM or node NMref can be kept low, and power consumption can be reduced.

[0239] Transistor Tr12 is not particularly limited, and for example, an Si transistor or an OS transistor can be used. When an OS transistor is used for transistor Tr12, it becomes possible to fabricate transistor Tr12 using the same manufacturing apparatus as for transistor Tr11, and the manufacturing cost can be suppressed. Note that transistor Tr12 may be an n-channel type or a p-channel type.

[0240] Current source circuit CS is connected to wirings BL[1] to [n] and wiring BLref. Current source circuit CS has the function of supplying current to wirings BL[1] to [n] and wiring BLref. Note that the current values supplied to wirings BL[1] to [n] and the current value supplied to wiring BLref may be different. Here, the current supplied from current source circuit CS to wirings BL[1] to [n] is I C、Let the current supplied from the current source circuit CS to the wiring BLref be I. Cref and denote it as such.

[0241] The current mirror circuit CM has wirings IL[1] to [n] and wiring ILref. The wirings IL[1] to [n] are respectively connected to the wirings BL[1] to [n], and the wiring ILref is connected to the wiring BLref. Here, the connection points of the wirings IL[1] to [n] and the wirings BL[1] to [n] are denoted as nodes NP[1] to [n]. Also, the connection point of the wiring ILref and the wiring BLref is denoted as node NPref.

[0242] The current mirror circuit CM has a function of flowing a current I CM corresponding to the potential of the node NPref through the wiring ILref, and a function of also flowing this current I CM through the wirings IL[1] to [n]. In FIG. 21, an example is shown in which the current I CM is discharged from the wiring BLref to the wiring ILref, and the current I CM is discharged from the wirings BL[1] to [n] to the wirings IL[1] to [n]. Also, the currents flowing from the current mirror circuit CM to the cell array CA through the wirings BL[1] to [n] are denoted as I B [1] to [n]. Also, the current flowing from the current mirror circuit CM to the cell array CA through the wiring BLref is denoted as I Bref and denoted as such.

[0243] The circuit WDD is connected to the wirings WD[1] to [n] and the wiring WDref. The circuit WDD has a function of supplying a potential corresponding to the first data stored in the memory cell MC to the wirings WD[1] to [n]. Further, the circuit WDD has a function of supplying a potential corresponding to the reference data stored in the memory cell MCref to the wiring WDref. The circuit WLD is connected to the wirings WL[1] to [m]. The circuit WLD has a function of supplying a signal for selecting the memory cell MC or the memory cell MCref for writing data to the wirings WL[1] to [m]. The circuit CLD is connected to the wirings RW[1] to [m]. The circuit CLD has a function of supplying a potential corresponding to the second data to the wirings RW[1] to [m].

[0244] The offset circuit OFST is connected to the wirings BL[1] to [n] and the wirings OL[1] to [n]. The offset circuit OFST has a function of detecting the amount of current flowing from the wirings BL[1] to [n] to the offset circuit OFST and / or the amount of change in the current flowing from the wirings BL[1] to [n] to the offset circuit OFST. Further, the offset circuit OFST has a function of outputting the detection result to the wirings OL[1] to [n]. Note that the offset circuit OFST may output a current corresponding to the detection result to the wiring OL, or may convert the current corresponding to the detection result into a voltage and output it to the wiring OL. The current flowing between the cell array CA and the offset circuit OFST is denoted as I α [1] to [n].

[0245] A configuration example of the offset circuit OFST is shown in FIG. 23. The offset circuit OFST shown in FIG. 23 has circuits OC[1] to [n]. Each of the circuits OC[1] to [n] has a transistor Tr21, a transistor Tr22, a transistor Tr23, a capacitive element C21, and a resistive element R1. The connection relationship of each element is as shown in FIG. 23. Note that a node connected to the first electrode of the capacitive element C21 and the first terminal of the resistive element R1 is defined as node Na. Also, a node connected to the second electrode of the capacitive element C21, either the source or drain of the transistor Tr21, and the gate of the transistor Tr22 is defined as node Nb.

[0246] The wiring VrefL has a function of supplying the potential Vref, the wiring VaL has a function of supplying the potential Va, and the wiring VbL has a function of supplying the potential Vb. Also, the wiring VDDL has a function of supplying the power supply potential VDD, and the wiring VSSL has a function of supplying the power supply potential VSS. Here, the case where the power supply potential VDD is the high power supply potential and the power supply potential VSS is the low power supply potential will be described. Also, the wiring RST has a function of supplying a potential for controlling the conduction state of the transistor Tr21. A source follower circuit is configured by the transistor Tr22, the transistor Tr23, the wiring VDDL, the wiring VSSL, and the wiring VbL.

[0247] Next, an operation example of the circuits OC[1] to [n] will be described. Here, as a representative example, the operation example of the circuit OC[1] will be described, but the circuits OC[2] to [n] can also be operated in the same manner. First, when a first current flows through the wiring BL[1], the potential of node Na becomes a potential corresponding to the first current and the resistance value of the resistive element R1. At this time, the transistor Tr21 is in the on state, and the potential Va is supplied to node Nb. Thereafter, the transistor Tr21 becomes in the off state.

[0248] Next, when a second current flows through the wiring BL[1], the potential of the node Na changes to a potential corresponding to the second current and the resistance value of the resistance element R1. At this time, the transistor Tr21 is in the off state and the node Nb is in the floating state. Therefore, as the potential of the node Na changes, the potential of the node Nb changes by capacitive coupling. Here, let the change in the potential of the node Na be ΔV Na and assuming the capacitive coupling coefficient is 1, the potential of the node Nb becomes Va + ΔV Na . Then, assuming the threshold voltage of the transistor Tr22 is V th , a potential Va + ΔV Na - V th is output from the wiring OL[1]. Here, by setting Va = V th , a potential ΔV Na can be output from the wiring OL[1].

[0249] The potential ΔV Na is determined according to the change amount from the first current to the second current, the resistance value of the resistance element R1, and the potential Vref. Here, since the resistance value of the resistance element R1 and the potential Vref are known, the change amount of the current flowing through the wiring BL can be obtained from the potential ΔV Na .

[0250] The amount of current detected by the offset circuit OFST as described above and / or the signal corresponding to the change amount of the current is input to the activation function circuit ACTV via the wirings OL[1] to [n].

[0251] The activation function circuit ACTV is connected to the wirings OL[1] to [n] and the wirings NIL[1] to [n]. The activation function circuit ACTV has a function of performing an operation for converting the signal input from the offset circuit OFST according to a predefined activation function. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, etc. can be used. The signal converted by the activation function circuit ACTV is output to the wirings NIL[1] to [n] as output data.

[0252] Using the above semiconductor device MAC, the sum-of-products operation of the first data and the second data can be performed. Hereinafter, an operation example of the semiconductor device MAC when performing the sum-of-products operation will be described.

[0253] Fig. 24 shows a timing chart of an operation example of the semiconductor device MAC. Fig. 24 shows the potential transitions of the wiring WL[1], wiring WL[2], wiring WD[1], wiring WDref, node NM[1,1], node NM[2,1], node NMref[1], node NMref[2], wiring RW[1], and wiring RW[2] in Fig. 22, and the current I B [1] - I α [1], and the value transitions of the current I Bref are shown. The current I B [1] - I α [1] corresponds to the sum of the currents flowing from the wiring BL[1] to the memory cells MC[1,1], [2,1].

[0254] Here, as a representative example, the operation will be described by focusing on the memory cells MC[1,1], [2,1] and the memory cells MCref[1], [2] shown in Fig. 22, but other memory cells MC and memory cells MCref can also be operated in the same manner.

[0255] First, at times T01 - T02, the potential of the wiring WL[1] becomes high level, the potential of the wiring WD[1] becomes higher than the ground potential (GND) by V PR -V W[1,1] higher potential, and the potential of the wiring WDref becomes higher than the ground potential by V PR higher potential. Also, the potentials of the wiring RW[1] and the wiring RW[2] become the reference potential (REFP). Note that the potential V W[1,1] is the potential corresponding to the first data stored in the memory cell MC[1,1]. Also, the potential V PR is the potential corresponding to the reference data. As a result, the transistor Tr11 included in the memory cell MC[1,1] and the memory cell MCref[1] is turned on, and the potential of the node NM[1,1] becomes V PR -V W[1,1] , and the potential of the node NMref[1] becomes V PR .

[0256] At this time, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[1,1] MC[1,1],0 can be expressed by the following equation. Here, k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor Tr12. Also, V th is the threshold voltage of the transistor Tr12.

[0257] I MC[1,1],0 = k(V PR - V W[1,1] - V th ) 2 (E1)

[0258] Also, the current I flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] MCref[1],0 can be expressed by the following equation.

[0259] I MCref[1],0 = k(V PR - V th ) 2 (E2)

[0260] Next, at time T02 - T03, the potential of the wiring WL[1] becomes low level. As a result, the transistor Tr11 included in the memory cell MC[1,1] and the memory cell MCref[1] turns off, and the potentials of the nodes NM[1,1] and NMref[1] are held.

[0261] As described above, it is preferable to use an OS transistor as the transistor Tr11. Thereby, the leakage current of the transistor Tr11 can be suppressed, and the potentials of the nodes NM[2,1] and NMref[2] can be accurately held.

[0262] Next, at time T03 - T04, the potential of the wiring WL[2] becomes high level, and the potential of the wiring WD[1] is higher than the ground potential by V PR - V W[2,1]It becomes a large potential, and the potential of the wiring WDref becomes higher than the ground potential by V PR It becomes a large potential. Note that the potential V W[2,1] corresponds to the first data stored in the memory cell MC[2,1]. As a result, the transistor Tr11 included in the memory cell MC[2,1] and the memory cell MCref[2] is turned on, and the potential of the node NM[2,1] becomes V PR -V W[2,1] , and the potential of the node NMref[2] becomes V PR .

[0263] At this time, the current I flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] MC[2,1],0 can be expressed by the following equation.

[0264] I MC[2,1],0 =k(V PR -V W[2,1] -V th ) 2 (E3)

[0265] Also, the current I flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] MCref[2],0 can be expressed by the following equation.

[0266] I MCref[2],0 =k(V PR -V th ) 2 (E4)

[0267] Next, at time T04 - T05, the potential of the wiring WL[2] becomes a low level. As a result, the transistor Tr11 included in the memory cell MC[2,1] and the memory cell MCref[2] is turned off, and the potentials of the nodes NM[2,1] and NMref[2] are held.

[0268] Through the above operations, the first data is stored in the memory cells MC[1,1], [2,1], and the reference data is stored in the memory cells MCref[1], [2].

[0269] Here, consider the currents flowing through wiring BL[1] and wiring BLref at times T04 - T05. A current is supplied from current source circuit CS to wiring BLref. Also, the current flowing through wiring BLref is discharged to current mirror circuit CM and memory cells MCref[1], [2]. Let the current supplied from current source circuit CS to wiring BLref be I Cref and the current discharged from wiring BLref to current mirror circuit CM be I CM,0 . Then, the following equation holds.

[0270] I Cref - I CM,0 = I MCref[1],0 + I MCref[2],0 (E5)

[0271] A current is supplied from current source circuit CS to wiring BL[1]. Also, the current flowing through wiring BL[1] is discharged to current mirror circuit CM and memory cells MC[1,1], [2,1]. Further, a current flows from wiring BL[1] to offset circuit OFST. Let the current supplied from current source circuit CS to wiring BL[1] be I C,0 and the current flowing from wiring BL[1] to offset circuit OFST be I α,0 . Then, the following equation holds.

[0272] I C - I CM,0 = I MC[1,1],0 + I MC[2,1],0 + I α,0 (E6)

[0273] Next, at times T05 - T06, the potential of wiring RW[1] becomes a potential V X[1] higher than the reference potential. At this time, a potential V X[1] is supplied to each capacitive element C11 of memory cell MC[1,1] and memory cell MCref[1], and the potential of the gate of transistor Tr12 rises due to capacitive coupling. Note that potential V X[1] is the potential corresponding to the second data supplied to memory cell MC[1,1] and memory cell MCref[1].

[0274] The change amount of the potential of the gate of transistor Tr12 is a value obtained by multiplying the change amount of the potential of wiring RW by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of capacitor element C11, the gate capacitance of transistor Tr12, and parasitic capacitance, etc. Hereinafter, for the sake of convenience, it will be described assuming that the change amount of the potential of wiring RW and the change amount of the potential of the gate of transistor Tr12 are the same, that is, the capacitance coupling coefficient is 1. Actually, the potential V X should be determined considering the capacitance coupling coefficient.

[0275] When potential V X[1] is supplied to the capacitor elements C11 of memory cell MC[1,1] and memory cell MCref[1], the potentials of nodes NM[1,1] and NMref[1] rise to V X[1] respectively.

[0276] Here, at time T05 - T06, the current I MC[1,1],1 flowing from wiring BL[1] to transistor Tr12 of memory cell MC[1,1] can be expressed by the following equation.

[0277] I MC[1,1],1 =k(V PR -V W[1,1] +V X[1] -V th ) 2 (E7)

[0278] That is, by supplying potential V X[1] to wiring RW[1], the current flowing from wiring BL[1] to transistor Tr12 of memory cell MC[1,1] increases by ΔI MC[1,1] =I MC[1,1],1 -I MC[1,1],0 .

[0279] Also, at time T05 - T06, the current I MCref[1],1 flowing from wiring BLref to transistor Tr12 of memory cell MCref[1] can be expressed by the following equation.

[0280] I MCref[1],1 =k(V PR +VX[1] -V th ) 2 (E8)

[0281] That is, by supplying the potential V to the wiring RW[1], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[1] is ΔI X[1] = I MCref[1] = I MCref[1],1 - I MCref[1],0 increases.

[0282] Next, consider the currents flowing through the wiring BL[1] and the wiring BLref. A current I Cref is supplied to the wiring BLref from the current source circuit CS. Also, the current flowing through the wiring BLref is discharged to the current mirror circuit CM and the memory cells MCref[1], [2]. Let the current discharged from the wiring BLref to the current mirror circuit CM be I CM,1 . Then, the following equation holds.

[0283] I Cref - I CM,1 = I MCref[1],1 + I MCref[2],1 (E9)

[0284] A current I C is supplied to the wiring BL[1] from the current source circuit CS. Also, the current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1], [2,1]. Further, a current also flows from the wiring BL[1] to the offset circuit OFST. Let the current flowing from the wiring BL[1] to the offset circuit OFST be I α,1 . Then, the following equation holds.

[0285] I C - I CM,1 = I MC[1,1],1 + I MC[2,1],1 + I α,1 (E10)

[0286] And from equations (E1) to (E10), the difference (differential current ΔI α,0 between the current I α,1 and the current I α) can be expressed by the following equation.

[0287] ΔI α =I α,1 -I α,0 =2kV W[1,1] V X[1] (E11)

[0288] Thus, the differential current ΔI α is a value corresponding to the product of the potentials V W[1,1] and V X[1] .

[0289] Thereafter, at time T06 - T07, the potential of the wiring RW[1] becomes the reference potential, and the potentials of the nodes NM[1,1] and NMref[1] become the same as those at time T04 - T05.

[0290] Next, at time T07 - T08, the potential of the wiring RW[1] becomes a potential higher than the reference potential by V X[1] , and the potential of the wiring RW[2] becomes a potential higher than the reference potential by V X[2] . As a result, a potential V X[1] is supplied to each of the capacitive elements C11 of the memory cell MC[1,1] and the memory cell MCref[1], and the potentials of the nodes NM[1,1] and NMref[1] rise by V X[1] respectively due to capacitive coupling. Also, a potential V X[2] is supplied to each of the capacitive elements C11 of the memory cell MC[2,1] and the memory cell MCref[2], and the potentials of the nodes NM[2,1] and NMref[2] rise by V X[2] respectively due to capacitive coupling.

[0291] Here, at time T07 - T08, the current I MC[2,1],1 flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] can be expressed by the following equation.

[0292] I MC[2,1],1 =k(V PR -V W[2,1] +V X[2] -V th )2 (E12)

[0293] That is, by supplying the potential V to the wiring RW[2], the current flowing from the wiring BL[1] to the transistor Tr12 of the memory cell MC[2,1] is ΔI X[2] = I MC[2,1] = I MC[2,1],1 - I MC[2,1],0 increases.

[0294] Also, at times T07 - T08, the current I flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] can be expressed by the following equation. MCref[2],1 is as follows.

[0295] I MCref[2],1 = k(V PR + V X[2] - V th )(E13) 2 (E13)

[0296] That is, by supplying the potential V to the wiring RW[2], the current flowing from the wiring BLref to the transistor Tr12 of the memory cell MCref[2] is ΔI X[2] = I MCref[2] = I MCref[2],1 - I MCref[2],0 increases.

[0297] Also, consider the currents flowing through the wiring BL[1] and the wiring BLref. A current I Cref is supplied to the wiring BLref from the current source circuit CS. Also, the current flowing through the wiring BLref is discharged to the current mirror circuit CM, the memory cells MCref[1], [2]. Let the current discharged from the wiring BLref to the current mirror circuit CM be I CM,2 . Then the following equation holds.

[0298] I Cref - I CM,2 = I MCref[1],1 + I MCref[2],1 (E14)

[0299] A current I Cis supplied. Also, the current flowing through the wiring BL[1] is discharged to the current mirror circuit CM and the memory cells MC[1,1], [2,1]. Further, current also flows from the wiring BL[1] to the offset circuit OFST. Let the current flowing from the wiring BL[1] to the offset circuit OFST be I α,2 Then, the following equation holds.

[0300] I C -I CM,2 =I MC[1,1],1 +I MC[2,1],1 +I α,2 (E15)

[0301] And, from equations (E1) to (E8) and equations (E12) to (E15), the difference (differential current ΔI α,0 ) between the current I α,2 and the current I α can be expressed by the following equation.

[0302] ΔI α =I α,2 -I α,0 =2k(V W[1,1] V X[1] +V W[2,1] V X[2] )(E16)

[0303] Thus, the differential current ΔI α becomes a value corresponding to the result of adding the product of the potential V W[1,1] and the potential V X[1] and the product of the potential V W[2,1] and the potential V X[2] .

[0304] Thereafter, at time T08 - T09, the potentials of the wirings RW[1], [2] become the reference potential, and the potentials of the nodes NM[1,1], [2,1] and the nodes NMref[1], [2] become the same as those at time T04 - T05.

[0305] As shown in equations (E11) and (E16), the differential current ΔI α input to the offset circuit OFST is the potential V Wand the potential V corresponding to the second data (input data) X can be calculated from an expression having a product term. That is, the differential current ΔI α is measured by the offset circuit OFST, whereby the result of the sum-of-products operation of the first data and the second data can be obtained.

[0306] Note that in the above, particular attention was paid to the memory cells MC[1,1], [2,1] and the memory cells MCref[1], [2], but the numbers of the memory cells MC and the memory cells MCref can be arbitrarily set. When the number of rows m of the memory cells MC and the memory cells MCref is an arbitrary number i, the differential current ΔIα can be expressed by the following equation.

[0307] ΔI α =2kΣ i V W[i,1] V X[i] (E17)

[0308] Also, by increasing the number of columns n of the memory cells MC and the memory cells MCref, the number of sum-of-products operations executed in parallel can be increased.

[0309] As described above, by using the semiconductor device MAC, the sum-of-products operation of the first data and the second data can be performed. Note that by using the configuration shown in FIG. 22 as the memory cells MC and the memory cells MCref, a sum-of-products operation circuit can be configured with a small number of transistors. Therefore, the circuit scale of the semiconductor device MAC can be reduced.

[0310] When the semiconductor device MAC is used for operations in a neural network, the number of rows m of the memory cells MC can correspond to the number of input data supplied to one neuron, and the number of columns n of the memory cells MC can correspond to the number of neurons. For example, consider the case of performing a multiply-accumulate operation using the semiconductor device MAC in the hidden layer HL shown in FIG. 20A. At this time, the number of rows m of the memory cells MC can be set to the number of input data (the number of neurons in the input layer IL) supplied from the input layer IL, and the number of columns n of the memory cells MC can be set to the number of neurons in the hidden layer HL.

[0311] Note that the structure of the neural network to which the semiconductor device MAC is applied is not particularly limited. For example, the semiconductor device MAC can also be used in a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a Boltzmann machine (including a restricted Boltzmann machine), etc.

[0312] As described above, by using the semiconductor device MAC, the multiply-accumulate operation of the neural network can be performed. Furthermore, by using the memory cells MC and the memory cells MCref shown in FIG. 22 in the cell array CA, an integrated circuit capable of improving the operation accuracy, reducing the power consumption, or reducing the circuit scale can be provided.

[0313] The configurations, structures, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0314] (Embodiment 2) In the present embodiment, the configuration of the transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By adopting such a configuration, the design freedom of the semiconductor device can be increased. Also, by stacking transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0315] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 25. The semiconductor device shown in FIG. 25 has a transistor 550, a transistor 500, and a capacitor 600. FIG. 27A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 27B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 27C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 is an OS transistor and can be used as the OS transistor described in the above embodiment. The transistor 550 has a configuration applicable to the Si transistor described in the above embodiment. Also, the capacitor 600 has a configuration applicable to the capacitor element described in the above embodiment.

[0316] The transistor 500 is an OS transistor. The transistor 500 has an extremely small off-current. Therefore, it is possible to hold the data voltage or charge written to the storage node via the transistor 500 for a long period of time. That is, since the refresh operation frequency of the storage node can be reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

[0317] In FIG. 25, the transistor 500 is provided above the transistor 550, and the capacitor 600 is provided above the transistor 550 and the transistor 500.

[0318] The transistor 550 is provided on the substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 formed of a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0319] As shown in FIG. 27C, the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 550 are covered with a conductor 316 via an insulator 315. In this way, by making the transistor 550 a Fin type, the effective channel width increases, thereby improving the on characteristics of the transistor 550. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 550 can be improved.

[0320] Note that the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.

[0321] In the region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 550 may be a HEMT.

[0322] The low resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0323] The conductor 316 that functions as the gate electrode can be formed of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material that includes an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0324] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

[0325] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0326] Also, as the SOI substrate, a SIMOX (Separation by Implanted Oxygen) substrate formed by implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature to form an oxide layer at a certain depth from the surface and eliminating defects generated in the surface layer, or a smart cut method of splitting a semiconductor substrate by utilizing the growth of microvoids formed by hydrogen ion implantation through heat treatment, an SOI substrate formed using the ELTRAN method (registered trademark: Epitaxial Layer Transfer), etc. may be used. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0327] Note that the transistor 550 shown in FIG. 25 is an example and is not limited to its configuration, and an appropriate transistor may be used according to the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit consisting only of OS transistors (meaning transistors of the same polarity such as only n-channel type transistors), as shown in FIG. 26, the configuration of the transistor 550 may be the same as that of the transistor 500. Details of the transistor 500 will be described later.

[0328] Over the transistor 550, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially laminated and provided.

[0329] As the insulators 320, 322, 324, and 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0330] In this specification, silicon oxynitride refers to a material having an oxygen content higher than that of nitrogen in its composition, and silicon nitride oxide refers to a material having a nitrogen content higher than that of oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having an oxygen content higher than that of nitrogen in its composition, and aluminum nitride oxide refers to a material having a nitrogen content higher than that of oxygen in its composition.

[0331] The insulator 322 may have a function as a planarization film that planarizes a step formed by a transistor 550 or the like provided below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0332] In addition, for the insulator 324, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 311 or the transistor 550 or the like into the region where the transistor 500 is provided.

[0333] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0334] The amount of hydrogen desorption can be analyzed using, for example, temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of the insulator 324, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0335] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0336] In addition, conductors 328, 330, etc. that are connected to the capacitor 600 or the transistor 500 are embedded in the insulators 320, 322, 324, and 326. Note that the conductors 328 and 330 have the function of plugs or wirings. Also, conductors having the function of plugs or wirings may be given the same reference numeral when summarizing a plurality of configurations. In this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0337] As the material of each plug and wiring (conductors 328, 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used singly or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0338] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 25, the insulators 350, 352, and 354 are laminated and provided in order. Further, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 has a function as a plug connected to the transistor 550 or a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328 and 330.

[0339] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350 in the same manner as the insulator 324. Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0340] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0341] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 25, the insulators 360, 362, and 364 are laminated and provided in order. Further, a conductor 366 is formed in the insulators 360, 362, and 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductors 328 and 330.

[0342] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 360. Further, conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of insulator 360 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0343] A wiring layer may be provided on insulator 364 and conductor 366. For example, in FIG. 25, insulators 370, 372, and 374 are sequentially stacked and provided. Further, conductor 376 is formed in insulators 370, 372, and 374. Conductor 376 has a function as a plug or wiring. Note that conductor 376 can be provided using the same materials as conductor 328 and conductor 330.

[0344] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 370. Further, conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of insulator 370 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0345] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. 25, the insulators 380, 382, and 384 are stacked in order. Also, a conductor 386 is formed on the insulators 380, 382, and 384. The conductor 386 has the function of a plug or wiring. Note that the conductor 386 can be provided using the same material as the conductors 328 and 330.

[0346] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 380, similar to the insulator 324. Also, the conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0347] In the above, the wiring layers including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or may be five or more.

[0348] On the insulator 384, the insulators 510, 512, 514, and 516 are stacked in order. It is preferable to use a material having a barrier property against oxygen or hydrogen for any of the insulators 510, 512, 514, and 516.

[0349] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property against hydrogen and impurities in a region where the transistor 500 is provided, such as a region where the substrate 311 or the transistor 550 is provided. Therefore, the same material as that of the insulator 324 can be used.

[0350] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.

[0351] Also, as a film having a barrier property against hydrogen, for example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 510 and the insulator 514.

[0352] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0353] Also, for example, the same material as that of the insulator 320 can be used for the insulator 512 and the insulator 516. In addition, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 512 and the insulator 516.

[0354] In addition, the insulators 510, 512, 514, and 516 have conductors such as the conductor 518 and the conductors (for example, the conductor 503) that constitute the transistor 500 embedded therein. Note that the conductor 518 functions as a capacitor 600, a plug connected to the transistor 550, or a wiring. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0355] In particular, the conductor 518 in the regions in contact with the insulators 510 and 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0356] A transistor 500 is provided above the insulator 516.

[0357] As shown in FIGS. 27A and 27B, the transistor 500 includes a conductor 503 arranged to be embedded in the insulators 514 and 516, an insulator 520 arranged on the insulators 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged separately from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 arranged on the bottom surface and the side surface of the opening, and a conductor 560 arranged on the formation surface of the insulator 545. The conductors 542a and 542b may be collectively referred to as the conductor 542.

[0358] Also, as shown in FIGS. 27A and 27B, it is preferable that an insulator 544 is disposed between the oxides 530a, 530b, the conductors 542a, 542b, and the insulator 580. Further, as shown in FIGS. 27A and 27B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 27A and 27B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.

[0359] Note that in this specification and the like, the oxides 530a and 530b may be collectively referred to as the oxide 530.

[0360] Note that in the transistor 500, a configuration in which two layers of the oxides 530a and 530b are laminated in a region where a channel is formed and in the vicinity thereof is shown, but the present invention is not limited thereto. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0361] Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated configuration, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer configuration or a laminated configuration of three or more layers. Also, the transistor 500 shown in FIGS. 25, 26, and 27A is an example, and the present invention is not limited to its configuration. An appropriate transistor may be used according to the circuit configuration, driving method, and the like.

[0362] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0363] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0364] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0365] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and can cover the channel formation region formed in the oxide 530.

[0366] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by an electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (S-channel) configuration. Further, the S-channel configuration disclosed in this specification and the like is different from a Fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to enhance the resistance to the short-channel effect, in other words, to make a transistor in which the short-channel effect hardly occurs.

[0367] Also, the conductor 503 has the same configuration as the conductor 518. The conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is further formed inside. Note that, in the transistor 500, a configuration in which the conductor 503a and the conductor 503b are laminated is shown, but the present invention is not limited to this. For example, the conductor 503 may be provided in a single layer or a laminated configuration of three or more layers.

[0368] Here, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Or, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that, in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0369] For example, since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0370] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. In the present embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.

[0371] The insulators 520, 522, and 524 have a function as a second gate insulating film.

[0372] Here, it is preferable to use an insulator that contains more oxygen than stoichiometric composition oxygen for the insulator 524 in contact with the oxide 530. The oxygen is likely to be released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter, may be referred to as V O H) may function as a donor and electrons as carriers may be generated. Also, a part of hydrogen may combine with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, V in the oxide 530 OIt is preferable to reduce H as much as possible to high-purity true or substantially high-purity true. Thus, V O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also referred to as "oxygen addition treatment"). V O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0373] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which some oxygen is desorbed by heating. The oxide from which oxygen is desorbed by heating is an oxide film in which the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0374] Also, any one or more of heat treatment, microwave treatment, or RF treatment may be performed by bringing the insulator having the excess oxygen region into contact with the oxide 530. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is broken, in other words, "V OThe reaction of "H→Vo + H" occurs, enabling dehydrogenation. A part of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from the oxide 530 or the insulator near the oxide 530. Also, a part of the hydrogen may be gettered by the conductor 542.

[0375] Also, the above microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Also, the above microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. As the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0376] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at 100°C or more and 450°C or less, more preferably 350°C or more and 400°C or less. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen is supplied to the oxide 530 to create oxygen vacancies (V OIt is possible to reduce ). Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after heat treatment in an atmosphere of nitrogen gas or an inert gas in order to supplement the desorbed oxygen. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0377] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with the oxygen deficiency to form V O H.

[0378] Further, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0379] It is preferable that the oxygen of the oxide 530 does not diffuse to the insulator 520 side because the insulator 522 has a function of suppressing the diffusion of oxygen and impurities. Further, it is possible to suppress the conductor 503 from reacting with the oxygen of the insulator 524 and the oxide 530.

[0380] The insulator 522 preferably uses, as a single layer or a laminate, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0381] In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the oxygen is less permeable). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0382] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. It is also possible to use a laminate of silicon oxide, silicon oxynitride, or silicon nitride on the above insulators.

[0383] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0384] Note that in the transistors 500 of FIGS. 27A and 27B, the insulators 520, 522, and 524 are illustrated as a second gate insulating film having a three-layer laminated structure, but the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0385] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for an oxide 530 including a channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0386] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0387] In addition, for the metal oxide that functions as a channel formation region in the oxide 530, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a large band gap in this way, the off-current of the transistor can be reduced.

[0388] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the components formed below the oxide 530a to the oxide 530b.

[0389] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0390] Also, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0391] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is advisable to lower the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0392] Specifically, by having a common element (as the main component) other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0393] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0394] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0395] In addition, in FIG. 27A, the conductors 542a and 542b are shown in a single-layer configuration, but they may also be in a laminated configuration of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer configuration in which an aluminum film is laminated on a tungsten film, a two-layer configuration in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer configuration in which a copper film is laminated on a titanium film, or a two-layer configuration in which a copper film is laminated on a tungsten film may be used.

[0396] Also, a three-layer configuration in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and then a titanium film or a titanium nitride film is formed thereon, a three-layer configuration in which a molybdenum film or a molybdenum nitride film is provided, an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and then a molybdenum film or a molybdenum nitride film is formed thereon, etc. are available. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0397] Also, as shown in FIG. 27A, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0398] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0399] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0400] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulator 544, silicon oxynitride or silicon nitride can also be used.

[0401] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium and aluminum (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in a later process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or the conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0402] By having the insulator 544, it is possible to suppress impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b through the insulator 545. Further, oxidation of the conductor 560 can be suppressed by the excess oxygen of the insulator 580.

[0403] The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0404] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they are stable against heat.

[0405] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less.

[0406] Further, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0407] Note that insulator 545 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be achieved.

[0408] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 27A and 27B, but it may be a single-layer structure or a laminated structure of three or more layers.

[0409] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by oxygen contained in the insulator 545 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Further, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0410] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0411] Insulator 580 is provided on conductor 542a and conductor 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, as insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0412] Insulator 580 preferably has an excess oxygen region. By providing insulator 580 that releases oxygen upon heating, oxygen in insulator 580 can be efficiently supplied to oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in insulator 580 is reduced.

[0413] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b. Thereby, conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0414] When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of conductor 560 from decreasing. Therefore, if the film thickness of conductor 560 is increased, conductor 560 can have a high aspect ratio shape. In the present embodiment, since conductor 560 is provided so as to be embedded in the opening of insulator 580, even if conductor 560 has a high aspect ratio shape, it can be formed without collapsing conductor 560 during the process.

[0415] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0416] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0417] In particular, aluminum oxide has high barrier properties, and even in a thin film of 0.5 nm or more and 3.0 nm or less, it can suppress the diffusion of hydrogen and nitrogen. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0418] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0419] Also, conductors 540a and 540b are arranged in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0420] An insulator 582 is provided on an insulator 581. It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0421] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the intrusion of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0422] An insulator 586 is provided on the insulator 582. The same material as that of the insulator 320 can be used for the insulator 586. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0423] Conductors 546 and 548 are embedded in the insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, insulator 574, insulator 581, insulator 582, and insulator 586.

[0424] The conductors 546 and 548 have functions as plugs or wirings that connect to the capacitor 600, the transistor 500, or the transistor 550. The conductors 546 and 548 can be provided using the same materials as the conductors 328 and 330.

[0425] Also, after forming the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and when the above-described insulator having high barrier properties is formed so as to be in contact with the insulator 522 or the insulator 514, it also serves as part of the manufacturing process of the transistor 500, which is preferable. As the insulator having high barrier properties against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.

[0426] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0427] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0428] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-mentioned elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0429] In the present embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the present invention is not limited to this configuration, and a laminated configuration of two or more layers may be used. For example, a conductor having barrier properties, and a conductor having high adhesiveness to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0430] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Note that, as the conductor 620, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when forming simultaneously with other components such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

[0431] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be provided using the same material as the insulator 320. Further, the insulator 640 may function as a planarization film that covers the uneven shape below it.

[0432] By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0433] As substrates that can be used in the semiconductor device according to one aspect of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate, etc.), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. Further, a plastic substrate having heat resistance capable of withstanding the processing temperature of the present embodiment may be used. Examples of the glass substrate include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, or soda lime glass. In addition, crystallized glass or the like can be used.

[0434] Alternatively, as the substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, as an example, synthetic resins such as acrylics. Alternatively, as an example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, as an example, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor deposition film, or papers. In particular, by manufacturing transistors using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured with such transistors, power consumption reduction or high integration of the circuit can be achieved.

[0435] Also, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistors, resistors, and / or capacitors. After partially or fully completing a semiconductor device on the release layer, the release layer can be separated from the substrate and used for transfer onto another substrate. At this time, transistors, resistors, and / or capacitors can be transferred onto substrates with poor heat resistance or flexible substrates. Note that for the above-described release layer, for example, a laminated structure of inorganic films such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on the substrate, a silicon film containing hydrogen, or the like can be used.

[0436] That is, a semiconductor device may be formed on a certain substrate and then transferred onto another substrate. As an example of the substrate onto which the semiconductor device is transferred, in addition to the substrate on which the above-described transistors can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is difficult to break, impart heat resistance, reduce weight, or reduce thickness.

[0437] By providing a semiconductor device on a flexible substrate, it is possible to suppress an increase in weight and provide a semiconductor device that is difficult to break.

[0438] <Modification Example 1 of Transistor> The transistor 500A shown in FIGS. 28A, 28B, and 28C is a modified example of the transistor 500 having the configuration shown in FIGS. 27A and 27B. FIG. 28A is a top view of the transistor 500A, FIG. 28B is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 28C is a cross-sectional view of the transistor 500A in the channel width direction. Note that in the top view of FIG. 28A, the description of some elements is omitted for clarity of the drawing. The configurations shown in FIGS. 28A, 28B, and 28C can also be applied to other transistors included in a semiconductor device according to an aspect of the present invention, such as the transistor 550.

[0439] The transistor 500A having the configuration shown in FIGS. 28A, 28B, and 28C is different from the transistor 500 having the configuration shown in FIGS. 27A and 27B in that it has an insulator 552, an insulator 513, and an insulator 404. Also, the insulator 552 is provided in contact with the side surface of the conductor 540a, and the insulator 552 is provided in contact with the side surface of the conductor 540b, which is different from the transistor 500 having the configuration shown in FIGS. 27A and 27B. Further, it is different from the transistor 500 having the configuration shown in FIGS. 27A and 27B in that it does not have an insulator 520.

[0440] In the transistor 500A having the configuration shown in FIGS. 28A, 28B, and 28C, the insulator 513 is provided on the insulator 512. Also, the insulator 404 is provided on the insulator 574 and on the insulator 513.

[0441] In the transistor 500A having the configuration shown in FIGS. 28A, 28B, and 28C, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 is configured to cover them. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the upper surface of the insulator 513, respectively. Thereby, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 513.

[0442] The insulators 513 and 404 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, as the insulators 513 and 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties. Thereby, since the diffusion of hydrogen or the like into the oxide 530 can be suppressed, the degradation of the characteristics of the transistor 500A can be suppressed. Therefore, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0443] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, the diffusion of impurities such as water or hydrogen from the insulator 580 or the like through the conductor 540a and the conductor 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductor 540a and the conductor 540b can be suppressed. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0444] <Modified Example 2 of Transistor> A configuration example of the transistor 500B will be described with reference to FIGS. 29A, 29B, and 29C. FIG. 29A is a top view of the transistor 500B. FIG. 29B is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 29A. FIG. 29C is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 29A. In the top view of FIG. 29A, the description of some elements is omitted for clarity of the figure.

[0445] Transistor 500B is a modified example of transistor 500 and is a transistor that can be replaced with transistor 500. Therefore, to avoid repeating the description, mainly the differences between transistor 500B and transistor 500 will be described.

[0446] The conductor 560 that functions as the first gate electrode has the conductor 560a and the conductor 560b on the conductor 560a. It is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0447] Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0448] Also, it is preferable to provide the insulator 544 so as to cover the upper surface and the side surface of the conductor 560 and the side surface of the insulator 545. Note that for the insulator 544, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can also be used.

[0449] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. Also, by having the insulator 544, diffusion of impurities such as water and hydrogen that the insulator 580 has into the transistor 500B can be suppressed.

[0450] Since the conductor 560 overlaps a part of the conductor 542a and a part of the conductor 542b in the transistor 500B, the parasitic capacitance is likely to be larger than that of the transistor 500. Therefore, the operating frequency tends to be lower than that of the transistor 500. However, since the process of providing an opening in the insulator 580 and filling the conductor 560, the insulator 545, etc. is unnecessary, the productivity is high as compared with the transistor 500.

[0451] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0452] (Embodiment 3) In this embodiment, an oxide semiconductor which is a kind of metal oxide will be described.

[0453] The metal oxide preferably contains at least indium or zinc. Particularly, it preferably contains indium and zinc. In addition to those, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0454] <Classification of crystal structures> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 30A. FIG. 30A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0455] As shown in FIG. 30A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, "Crystal" includes single crystal and poly crystal.

[0456] Note that the structure within the thick frame shown in FIG. 30A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be paraphrased as a structure that is energetically unstable "Amorphous" or completely different from "Crystal".

[0457] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, FIG. 30B shows the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline". Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 30B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 30B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Further, the thickness of the CAAC-IGZO film shown in FIG. 30B is 500 nm.

[0458] As shown in FIG. 30B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating clear crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in FIG. 30B, the peak near 2θ = 31° is asymmetric about the axis of the angle at which the peak intensity is detected.

[0459] Also, the crystal structure of the film or the substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 30C. FIG. 30C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 30C is near In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0460] As shown in FIG. 30C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0461] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 30A. For example, the oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. The non-single-crystalline oxide semiconductor includes polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0462] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0463] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Here, the specific direction means the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Further, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0464] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0465] In an In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Here, indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0466] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0467] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0468] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the non-dense arrangement of oxygen atoms in the a-b plane direction and the change in the interatomic bond distance due to the substitution of metal atoms.

[0469] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility by capturing carriers. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that to form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0470] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0471] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nano crystals. Also, nc-OS does not show regularity in the crystal orientation between different nano crystals. Therefore, no orientation is seen in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam with a probe diameter larger than the nano crystal (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nano crystal (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0472] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0473] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0474] [CAC-OS] The CAC-OS is, for example, a constitution of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0475] Furthermore, the CAC-OS is a constitution in which the material is separated into a first region and a second region to form a mosaic state, and the first region is a constitution distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a constitution in which the first region and the second region are mixed.

[0476] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0477] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0478] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0479] For example, in the CAC-OS in the In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0480] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (on / off function) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be achieved.

[0481] Oxide semiconductors have various structures, each with different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductor, polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0482] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0483] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0484] For a transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, still more preferably 1×10 11 cm -3 or less, even more preferably 1×10 10 cm -3 less than, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0485] In addition, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low.

[0486] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0487] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0488] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0489] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0490] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0491] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0492] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen that binds to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bind to oxygen that binds to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, still more preferably less than 1×10 18 atoms / cm 3 less than.

[0493] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0494] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments and examples.

[0495] (Embodiment 4) In this embodiment, application examples of the semiconductor device described above will be described.

[0496] [Semiconductor Wafer, Chip] FIG. 31A shows a top view of a substrate 701 before dicing processing. As the substrate 701, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 702 are provided on the substrate 701. In the circuit region 702, a semiconductor device according to one aspect of the present invention, a CPU, an RF tag, an image sensor, or the like can be provided.

[0497] A plurality of circuit regions 702 are each surrounded by a separation region 703. A separation line (also referred to as a "dicing line") 704 is set at a position overlapping the separation region 703. By cutting the substrate 701 along the separation line 704, the chip 705 including the circuit region 702 can be cut out from the substrate 701. An enlarged view of the chip 705 is shown in FIG. 31B.

[0498] Also, a conductive layer or a semiconductor layer may be provided in the separation region 703. By providing a conductive layer or a semiconductor layer in the separation region 703, ESD that may occur during the dicing process can be mitigated, and a reduction in the yield of the dicing process can be prevented. Also, generally, the dicing process is performed while flowing pure water with a reduced resistivity by dissolving carbon dioxide gas or the like to the cutting part for the purpose of cooling the substrate, removing chips, preventing charging, etc. By providing a conductive layer or a semiconductor layer in the separation region 703, the usage amount of the pure water can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Also, the productivity of the semiconductor device can be increased.

[0499] As the semiconductor layer provided in the separation region 703, it is preferable to use a material having a band gap of 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.5 eV or less. By using such a material, the accumulated charge can be slowly discharged, so that a rapid movement of charge due to ESD can be suppressed, and electrostatic breakdown can be made less likely to occur.

[0500] 〔Electronic Component〕 An example of applying the chip 705 to an electronic component will be described with reference to FIGS. 32A and 32B. Note that an electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for electronic components depending on the terminal extraction direction and the shape of the terminals.

[0501] In the assembly process (post-process), the electronic component is completed by combining the semiconductor device shown in the above embodiment and components other than the semiconductor device.

[0502] The subsequent processes will be described using the flowchart shown in FIG. 32A. After the element substrate having the semiconductor device shown in the above embodiment is completed in the previous process, a "back grinding process" is performed to grind the back surface of the element substrate (the surface on which no semiconductor device or the like is formed) (step S721). By thinning the element substrate by grinding, warping of the element substrate can be reduced, and miniaturization of the electronic component can be achieved.

[0503] Next, a "dicing process" is performed to separate the element substrate into a plurality of chips (chip 705) (step S722). Then, a "die bonding process" is performed to individually pick up the separated chips and bond them onto the lead frame (step S723). For the bonding between the chip and the lead frame in the die bonding process, an appropriate method suitable for the product, such as bonding with resin or bonding with tape, is selected. Note that the chip may be bonded onto an interposer substrate instead of the lead frame.

[0504] Next, a "wire bonding process" is performed to electrically connect the leads of the lead frame and the electrodes on the chip with a thin metal wire (wire) (step S724). As the thin metal wire, a silver wire or a gold wire can be used. Also, for wire bonding, ball bonding or wedge bonding can be used.

[0505] The wire-bonded chip is subjected to a "sealing process (molding process)" using an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, and the circuit portion built in the chip and the wire connecting the chip and the lead can be protected from mechanical external forces, and deterioration of characteristics (reduction in reliability) due to moisture and dust can be reduced.

[0506] Next, a "lead plating process" for plating the leads of the lead frame is performed (step S726). The plating process can prevent the leads from rusting and enable more reliable soldering when later mounting on a printed circuit board. Next, a "shaping process" for cutting and shaping the leads is performed (step S727).

[0507] Next, a "marking process" for performing printing processing (marking) on the surface of the package is carried out (step S728). Then, through an "inspection process" (step S729) for examining the quality of the external shape, the presence or absence of malfunction, etc., the electronic component is completed.

[0508] Also, a perspective schematic diagram of the completed electronic component is shown in FIG. 32B. In FIG. 32B, as an example of the electronic component, a perspective schematic diagram of a QFP (Quad Flat Package) is shown. The electronic component 750 shown in FIG. 32B shows leads 755 and a semiconductor device 753. As the semiconductor device 753, the semiconductor devices shown in the above embodiments can be used.

[0509] The electronic component 750 shown in FIG. 32B is mounted on a printed circuit board 752, for example. A plurality of such electronic components 750 are combined, and each is electrically connected on the printed circuit board 752 to complete a board (mounted board 754) on which the electronic components are mounted. The completed mounted board 754 is used in electronic devices and the like.

[0510] 〔Electronic Device〕 Next, an example of an electronic device including the semiconductor device or the above-described electronic component according to one aspect of the present invention will be described with reference to FIG. 33.

[0511] As an electronic device using the semiconductor device or electronic component according to one aspect of the present invention, there are a display device such as a television or a monitor, a lighting device, a desktop or notebook personal computer, a word processor, an image playback device that plays back still images or moving images stored on a recording medium such as a DVD (Digital Versatile Disc), a portable CD player, a radio, a tape recorder, a headphone stereo, a stereo, a table clock, a wall clock, a cordless telephone handset, a transceiver, a mobile phone, a car phone, a portable game machine, a tablet terminal, a large game machine such as a pachinko machine, a calculator, a portable information terminal (also referred to as a "portable information device"), an electronic notebook, an e-book terminal, an electronic translator, a voice input device, a video camera, a digital still camera, a high-frequency heating device such as an electric shaver or a microwave oven, an electric rice cooker, an electric washing machine, an electric vacuum cleaner, a water heater, a fan, a hair dryer, air conditioning equipment such as an air conditioner, a humidifier, and a dehumidifier, a dishwasher, a dish dryer, a clothes dryer, a futon dryer, an electric refrigerator, an electric freezer, an electric refrigerator-freezer, a freezer for DNA storage, a flashlight, a tool such as a chain saw, a smoke detector, a medical device such as a dialysis device, and the like. Further, there are industrial devices such as induction lamps, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids.

[0512] In addition, a moving body propelled by an electric motor using the power from the power storage device is also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHV), a tracked vehicle obtained by changing the tire wheels of these into endless tracks, a motorized bicycle including an electric assist bicycle, a motorcycle, an electric wheelchair, a golf cart, a small or large ship, a submarine, a helicopter, an airplane, a rocket, an artificial satellite, a space exploration vehicle, a planetary exploration vehicle, a spaceship, and the like.

[0513] The semiconductor device or electronic component according to one aspect of the present invention can be used for a communication device or the like built in these electronic devices.

[0514] The electronic device may have sensors (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0515] The electronic device can have various functions. For example, it can have functions such as displaying various information (such as still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading programs or data recorded on a recording medium, etc.

[0516] Figures 33 and 34A to 34F show an example of an electronic device. In Figure 33, the display device 8000 is an example of an electronic device using the semiconductor device 8004 according to one aspect of the present invention. Specifically, the display device 8000 corresponds to a display device for receiving TV broadcasts and has a housing 8001, a display unit 8002, a speaker unit 8003, a semiconductor device 8004, a power storage device 8005, etc. The semiconductor device 8004 according to one aspect of the present invention is provided inside the housing 8001. The semiconductor device 8004 can hold control information, control programs, etc. Further, the semiconductor device 8004 has a communication function and can make the display device 8000 function as an IoT device. Also, the display device 8000 can receive power supply from a commercial power source or use the power stored in the power storage device 8005.

[0517] For the display unit 8002, a display device such as a liquid crystal display device, a light-emitting display device having a light-emitting element such as an organic EL element in each pixel, an electrophoretic display device, a DMD (Digital Micromirror Device), a PDP (Plasma Display Panel), an FED (Field Emission Display), etc. can be used.

[0518] In addition, the display device includes all display devices for information display, such as for TV broadcast reception, personal computers, and advertising display.

[0519] In FIG. 33, the installed lighting device 8100 is an example of an electronic device using the semiconductor device 8103 according to one aspect of the present invention. Specifically, the lighting device 8100 includes a housing 8101, a light source 8102, a semiconductor device 8103, a power storage device 8105, and the like. In FIG. 33, the case where the semiconductor device 8103 is provided inside the ceiling 8104 where the housing 8101 and the light source 8102 are installed is illustrated, but the semiconductor device 8103 may be provided inside the housing 8101. The semiconductor device 8103 can hold information such as the emission luminance of the light source 8102 and a control program. Further, the semiconductor device 8103 has a communication function and can make the lighting device 8100 function as an IoT device. Also, the lighting device 8100 can receive power supply from a commercial power source or use the power stored in the power storage device.

[0520] Note that in FIG. 33, the installed lighting device 8100 provided on the ceiling 8104 is illustrated, but the semiconductor device according to one aspect of the present invention can also be used for installed lighting devices provided on, for example, side walls 8405, floors 8406, windows 8407, etc., other than the ceiling 8104, or for desktop lighting devices.

[0521] Also, as the light source 8102, an artificial light source that artificially obtains light using power can be used. Specifically, incandescent bulbs, discharge lamps such as fluorescent lamps, and light emitting elements such as LEDs and organic EL elements can be cited as examples of the above artificial light sources.

[0522] In FIG. 33, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a semiconductor device 8203 according to one aspect of the present invention. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a semiconductor device 8203, a power storage device 8205, and the like. In FIG. 33, the case where the semiconductor device 8203 is provided in the indoor unit 8200 is illustrated, but the semiconductor device 8203 may be provided in the outdoor unit 8204. Alternatively, the semiconductor device 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The semiconductor device 8203 can hold control information of the air conditioner, a control program, and the like. Further, the semiconductor device 8203 has a communication function and can make the air conditioner function as an IoT device. Also, the air conditioner can receive power supply from a commercial power source or use the power stored in the power storage device 8205.

[0523] Note that in FIG. 33, a separate type of air conditioner composed of an indoor unit and an outdoor unit is illustrated, but a semiconductor device according to one aspect of the present invention can also be used in an integrated type of air conditioner having the functions of the indoor unit and the outdoor unit in one housing.

[0524] In FIG. 33, an electric refrigerator-freezer 8300 is an example of an electronic device using a semiconductor device 8304 according to one aspect of the present invention. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, a power storage device 8305, and the like. In FIG. 33, the power storage device 8305 is provided inside the housing 8301. The semiconductor device 8304 can hold control information of the electric refrigerator-freezer 8300, a control program, and the like. Further, the semiconductor device 8304 has a communication function and can make the electric refrigerator-freezer 8300 function as an IoT device. Also, the electric refrigerator-freezer 8300 can receive power supply from a commercial power source or use the power stored in the power storage device 8305.

[0525] Fig. 34A shows an example of a wristwatch-type portable information terminal. The portable information terminal 6100 includes a housing 6101, a display unit 6102, a band 6103, operation buttons 6105, etc. Further, the portable information terminal 6100 includes a secondary battery and a semiconductor device or an electronic component according to an aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to an aspect of the present invention in the portable information terminal 6100, the portable information terminal 6100 can function as an IoT device.

[0526] Fig. 34B shows an example of a mobile phone. The portable information terminal 6200 includes an operation button 6203, a speaker 6204, a microphone 6205, etc. in addition to a display unit 6202 incorporated in a housing 6201.

[0527] Further, the portable information terminal 6200 includes a fingerprint sensor 6209 in a region overlapping the display unit 6202. The fingerprint sensor 6209 may be an organic optical sensor. Since fingerprints vary from person to person, a fingerprint pattern can be acquired by the fingerprint sensor 6209 to perform personal authentication. The light emitted from the display unit 6202 can be used as a light source for acquiring a fingerprint pattern by the fingerprint sensor 6209.

[0528] Also, the portable information terminal 6200 includes a secondary battery and a semiconductor device or an electronic component according to an aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to an aspect of the present invention in the portable information terminal 6200, the portable information terminal 6200 can function as an IoT device.

[0529] Fig. 34C shows an example of a cleaning robot. The cleaning robot 6300 has a display unit 6302 arranged on the upper surface of a housing 6301, a plurality of cameras 6303 arranged on the side surface, a brush 6304, operation buttons 6305, various sensors, etc. Although not shown, the cleaning robot 6300 is provided with tires, a suction port, etc. The cleaning robot 6300 can move automatically, detect dust 6310, and suck the dust from a suction port provided on the lower surface.

[0530] For example, the cleaning robot 6300 can analyze the images captured by the camera 6303 and determine the presence or absence of obstacles such as walls, furniture, or steps. Also, when an object that is likely to get caught in the brush 6304, such as wiring, is detected by image analysis, the rotation of the brush 6304 can be stopped. The cleaning robot 6300 includes a secondary battery and a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the cleaning robot 6300, the cleaning robot 6300 can be made to function as an IoT device.

[0531] Figure 34D shows an example of a robot. The robot 6400 shown in Figure 34D includes an arithmetic unit 6409, an illuminance sensor 6401, a microphone 6402, an upper camera 6403, a speaker 6404, a display unit 6405, a lower camera 6406, an obstacle sensor 6407, and a moving mechanism 6408.

[0532] The microphone 6402 has a function of detecting the user's voice and environmental sounds, etc. Also, the speaker 6404 has a function of emitting sound. The robot 6400 can communicate with the user by using the microphone 6402 and the speaker 6404.

[0533] The display unit 6405 has a function of displaying various information. The robot 6400 can display the information desired by the user on the display unit 6405. The display unit 6405 may be equipped with a touch panel. Also, the display unit 6405 may be a removable information terminal, and by installing it at a fixed position of the robot 6400, charging and data transfer can be enabled.

[0534] The upper camera 6403 and the lower camera 6406 have the function of imaging the surroundings of the robot 6400. Also, the obstacle sensor 6407 can detect the presence or absence of obstacles in the traveling direction when the robot 6400 moves forward using the moving mechanism 6408. The robot 6400 can recognize the surrounding environment and move safely using the upper camera 6403, the lower camera 6406, and the obstacle sensor 6407. The light-emitting device according to one aspect of the present invention can be used for the display unit 6405.

[0535] The robot 6400 includes a secondary battery and a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the robot 6400, the robot 6400 can be made to function as an IoT device.

[0536] FIG. 34E shows an example of an aircraft. The aircraft 6500 shown in FIG. 34E has a propeller 6501, a camera 6502, a battery 6503, etc., and has the function of autonomous flight.

[0537] For example, the image data captured by the camera 6502 is stored in the electronic component 6504. The electronic component 6504 can analyze the image data and detect the presence or absence of obstacles when moving. Also, the remaining battery level can be estimated from the change in the storage capacity of the battery 6503 by the electronic component 6504. The aircraft 6500 includes a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the aircraft 6500, the aircraft 6500 can be made to function as an IoT device.

[0538] FIG. 34F shows an example of an automobile. The automobile 7160 has an engine, tires, brakes, a steering device, a camera, etc. The automobile 7160 includes a semiconductor device or an electronic component according to one aspect of the present invention inside thereof. By using the semiconductor device or the electronic component according to one aspect of the present invention in the automobile 7160, the automobile 7160 can be made to function as an IoT device.

[0539] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments and examples.

Example

[0540] In this example, an acceleration sensor is used as a sensor element of one aspect of the present invention, and a semiconductor device having the sensor element is placed on a housing having a fan, showing an example of evaluating vibration.

[0541] FIG. 35 shows photographs of a semiconductor device 900, a housing 901, and a housing 902 as the configuration used in the evaluation of this example. Fans are built into the housing 901 and the housing 902, respectively.

[0542] A sensor circuit 903 and a processing device 904 are mounted on the semiconductor device 900 shown in FIG. 35. ADXL362 of ANALOG DEVICES is used as the sensor circuit. ADXL362 is a circuit having a MEMS acceleration sensor. Further, ADXL362 has a 12-bit analog-to-digital conversion circuit. The waveform detected by the acceleration sensor is processed by the analog-to-digital conversion circuit etc. of the sensor circuit and then given to the processing device 904.

[0543] A battery is mounted on the semiconductor device 900.

[0544] The semiconductor device 900 can wirelessly transmit and receive signals with a personal computer via Bluetooth (registered trademark).

[0545] FIG. 36A shows an enlarged photograph of the semiconductor device 900 shown in FIG. 35. The semiconductor device 900 has a first block 900A, a second block 900B, and a third block 900C.

[0546] FIG. 36B shows external photographs of the first block 900A to the third block 900C. The first block 900A has a processing device 904. The second block 900B has a sensor circuit 903. The third block 900C has a socket 905 for installing a battery.

[0547] As objects, a housing 901 incorporating a first fan and a housing 902 incorporating a second fan were used. The first fan and the second fan have a plurality of blades in the radial direction from the rotation axis. It is known in advance that the second fan may have larger vibrations during rotation than the first fan. For housings having fans with different vibration magnitudes in advance, evaluations were made using semiconductor devices. A battery was installed in the socket 905.

[0548] First, the semiconductor device 900 was placed on the housing 901, and a waveform obtained by processing a signal detected by an acceleration sensor by a sensor circuit is shown in FIG. 37A. The horizontal axis of the graph shown in FIG. 37A is time, and the vertical axis is acceleration. Also, a fast Fourier transform of the waveform shown in FIG. 37A is shown in FIG. 37B. The horizontal axis of FIG. 37B is frequency, and the vertical axis is intensity.

[0549] Next, the semiconductor device 900 was placed on the second fan, and a waveform obtained by processing a signal detected by an acceleration sensor by a sensor circuit is shown in FIG. 38A. The horizontal axis of the graph shown in FIG. 38A is time, and the vertical axis is acceleration. Also, a fast Fourier transform of the waveform shown in FIG. 38A is shown in FIG. 38B. The horizontal axis of FIG. 38B is frequency, and the vertical axis is intensity.

[0550] In this embodiment, for simplicity, the same semiconductor device was placed on two fans in sequence for evaluation. However, if two semiconductor devices are prepared, one semiconductor device can be installed on each fan.

[0551] In Fig. 38A, it was found that the amplitude intensity is higher compared to Fig. 37A. For example, when the normal range is set as -10 [g] or more and +10 [g] or less, and it is determined as abnormal if it deviates from this range, the state of the second fan is determined as abnormal. Also, in Fig. 38B, a feature of having a large peak near 100 Hz is observed, and it can be estimated as abnormal. By analyzing the characteristics of the waveform after fast Fourier transform, the state of the fan can be estimated.

Explanation of Signs

[0552] ACTV: Activation function circuit, BKC1: Circuit, BKC2: Circuit, BKC10: Circuit, BKC20: Circuit, C1: Capacitor element, C3: Capacitor element, C6: Capacitor element, C11: Capacitor element, C21: Capacitor element, CB1: Capacitor element, CB2: Capacitor element, CB11: Capacitor element, CB12: Capacitor element, CE: Signal, CLD: Circuit, CLKM: Reference clock signal, CLK: Clock signal, CM: Current mirror circuit, CS: Current source circuit, D: Data signal, DB: Data signal, FN1: Node, FN2: Node, GCLK2: Clock signal, INT: Signal, INV11: Inverter circuit, INV12: Inverter circuit, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M5: Transistor, M6: Transistor, M11: Transistor, M12: Transistor, MA1: Transistor, MAC: Semiconductor device, MC: Memory cell, MCref: Memory cell, MC1: Transistor, MC2: Transistor, MemC1: Circuit, MemC2: Circuit, MR1: Transistor, MW1: Transistor, MW11: Transistor, MW2: Transistor, MW12: Transistor, Na: Node, Nb: Node, NB1: Node, ND: Node, NET1: Node, NET2: Node, NK1: Node, NM: Node, NMref: Node, NP: Node, NPref: Node, NR1: Node, OC: Circuit, OFST: Offset circuit, OSC: Signal, OSG: Signal, OSR: Signal, OSS: Signal, RESET: Signal, PCC10: Circuit, PSE5: Signal, PSE6: Signal, R1: Resistor element, RTC10: Circuit, SLC: Signal, SLP: Signal, SMC20: Circuit, SN1: Node, SN2: Node, SN3: Node, Tr11: Transistor, Tr12: Transistor, Tr21: Transistor, Tr22: Transistor, Tr23: Transistor, WDD: Circuit, WLD: Circuit, WE: Signal, 10: Power supply circuit, 11: Memory cell, 15: Memory cell, 16: Memory cell, 20: PU, 21: PU, 30: Processor core, 31: Memory circuit, 32: Circuit, 35: Power supply line, 40: Cache, 41: Memory array, 42: Peripheral circuit, 43: Control circuit, 45: Memory cell, 60: PMU, 61: Circuit, 65: Clock control circuit, 70: PSW, 71: PSW, 80: Terminal, 81: Terminal, 82: Terminal, 83: Terminal,90: Terminal, 91: Terminal, 92: Terminal, 93: Terminal, 93a: Terminal, 93b: Terminal, 94: Terminal, 100: Memory circuit, 110: FF, 120: Memory cell, 121: Buffer circuit, 122: Transistor, 123: Capacitor element, 130: Processor core, 131: Control device, 132: Program counter, 133: Pipeline register, 134: Pipeline register, 135: Register file, 136: ALU, 137: Data bus, 202: Cache memory device, 203: Cache memory device, 240: NOSRAM, 242: Power domain, 243: Power domain, 245: Power switch, 247: Power switch, 250: Memory cell array, 251: Control circuit, 252: Row circuit, 253: Column circuit, 301: Sensor circuit, 301a: Sensor circuit, 301b: Sensor circuit, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 351: DOSRAM, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 361: Memory cell array, 362: Insulator, 364: Insulator, 365: Peripheral circuit, 366: Conductor, 370: Insulator, 371: Power switch, 372: Insulator, 373: Power switch, 374: Insulator, 376: Conductor, 380: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 401: Antenna, 402: Communication circuit, 404: Insulator, 500: Transistor, 500A: Transistor, 500B: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 545: Insulator, 546: Conductor, 548: Conductor, 550: Transistor, 552: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 580: Insulator, 581: Insulator, 582: Insulator,586: Insulator, 600: Capacitance, 610: Conductor, 612: Conductor, 620: Conductor, 630: Insulator, 640: Insulator, 700: Semiconductor device, 701: Substrate, 702: Circuit region, 703: Isolation region, 704: Isolation line, 705: Chip, 710: Sensor element, 710c: Sensor element, 710d: Sensor element, 711: Detection unit, 711a: Detection unit, 711b: Detection unit, 712: Judgment circuit, 712a: Judgment circuit, 712b: Judgment circuit, 713: Analog-to-digital conversion circuit, 713a: Analog-to-digital conversion circuit, 713b: Analog-to-digital conversion circuit, 714: Sample-and-hold circuit, 714A: Sample-and-hold circuit, 714B: Sample-and-hold circuit, 714c: Sample-and-hold circuit, 714C: Sample-and-hold circuit, 714d: Sample-and-hold circuit, 715: Memory, 717: Control device, 750: Electronic component, 752: Printed circuit board, 753: Semiconductor device, 754: Mounting substrate, 755: Lead, 799: Object, 900: Semiconductor device, 900A: Block, 900B: Block, 900C: Block, 901: Housing, 902: Housing, 903: Sensor circuit, 904: Processing device, 905: Socket, 6100: Portable information terminal, 6101: Housing, 6102: Display unit, 6103: Band, 6105: Operation button, 6200: Portable information terminal, 6201: Housing, 6202: Display unit, 6203: Operation button, 6204: Speaker, 6205: Microphone, 6209: Fingerprint sensor, 6300: Cleaning robot, 6301: Housing, 6302: Display unit, 6303: Camera, 6304: Brush, 6305: Operation button, 6310: Dust, 6400: Robot, 6401: Illuminance sensor, 6402: Microphone, 6403: Upper camera, 6404: Speaker, 6405: Display unit, 6406: Lower camera, 6407: Obstacle sensor, 6408: Moving mechanism, 6409: Arithmetic unit, 6500: Aircraft, 6501: Propeller, 6502: Camera, 6503: Battery, 6504: Electronic component, 7160: Automobile, 8000: Display device, 8001: Housing, 8002: Display unit, 8003: Speaker unit, 8004: Semiconductor device, 8005: Power storage device, 8100: Lighting device, 8101: Housing, 8102: Light source, 8103: Semiconductor device, 8104: Ceiling, 8105: Power storage device, 8200: Indoor unit, 8201: Housing, 8202: Air outlet, 8203: Semiconductor device,8204: Outdoor unit, 8205: Power storage device, 8300: Electric refrigerator-freezer, 8301: Cabinet, 8302: Refrigerator door, 8303: Freezer door, 8304: Semiconductor device, 8305: Power storage device, 8405: Side wall, 8406: Floor, 8407: Window

Claims

1. A power supply control device comprising a sensor circuit, a power management device, and a processing circuit, the sensor circuit includes a sensor element, a determination circuit, and a memory; the power management device has a function of controlling the power supply to the arithmetic processing circuit, the arithmetic processing circuit includes a first circuit having a first storage circuit and a second circuit having a second storage circuit; the first circuit has a function of holding first data in the first memory circuit while power is being supplied to the arithmetic processing circuit; the second circuit has a function of reading the first data stored in the first storage circuit and writing the first data to the second storage circuit while power is being supplied to the arithmetic processing circuit, and a function of storing the first data in the second storage circuit while power supply to the arithmetic processing circuit is stopped; the sensor circuit has a function of providing second data from the determination circuit to the power management device when the determination circuit compares the detection signal from the sensor element with reference data and determines that an abnormality has occurred; the second data includes a signal requesting an interrupt process; the power management device has a function of resuming power supply to the arithmetic processing circuit in accordance with the second data; the memory includes a first transistor having an oxide semiconductor in a channel formation region, a second transistor having silicon in a channel formation region, and a capacitor; a gate of the second transistor is electrically connected to one of the source and the drain of the first transistor and a first electrode of the capacitor element; The reference data is stored in the memory.

2. In claim 1, The oxide semiconductor includes In, Ga, and Zn.

3. In claim 1 or 2, The sensor element is a semiconductor device having a function of measuring one or more selected from force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, and infrared rays.

Images