Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of improving a film shape, and a manufacturing method thereof.SOLUTION: A semiconductor device according to an embodiment comprises a laminate, a semiconductor layer, a first insulation film, a charge storage film, a second insulation film, a third insulation film, and an insulation part. The laminate is a stack in which electrode layers and insulation layers are alternately laminated in a first direction. The semiconductor layer is arranged in the laminate along the first direction. The first insulation film is arranged along the first direction between the laminate and the semiconductor layer. The charge storage film is arranged along the first direction between the laminate and the first insulation film. The second insulation film is arranged along the first direction between the laminate and the charge storage film. The third insulation film is arranged between the insulation layer and the second insulation film. The insulation part is arranged at an end of the third insulation film side of the insulation layer, and overlaps the electrode layer when viewed from the first direction. The film density of the insulation part differs from the film density of the insulation layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This embodiment relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known as a semiconductor device. In this NAND flash memory, a memory hole penetrating the stacked body is provided in a stacked body in which a plurality of electrode layers and insulating layers are alternately stacked. By providing a charge storage layer and a semiconductor layer in this memory hole, a memory string in which a plurality of memory cells are connected in series is formed. Data is stored in the memory cell by controlling the amount of charge held in the charge storage layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device and a method for manufacturing the same that can improve the film shape.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a laminate, a semiconductor layer, a first insulating film, a charge storage film, a second insulating film, a third insulating film, and an insulating portion. The laminate is a laminate in which an electrode layer and an insulating layer are alternately laminated in a first direction. The semiconductor layer is disposed in the laminate along the first direction. The first insulating film is disposed between the laminate and the semiconductor layer along the first direction. The charge storage film is disposed between the laminate and the first insulating film along the first direction. The second insulating film is disposed between the laminate and the charge storage film along the first direction. The third insulating film is disposed between the insulating layer and the second insulating film. The insulating portion is disposed at an end of the insulating layer on the side of the third insulating film and overlaps with the electrode layer when viewed from the first direction. The film density of the insulating portion is different from the film density of the insulating layer.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments according to the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratios of the respective parts are not necessarily the same as those in reality. In the specification and the drawings, the same reference numerals are given to the same elements as those described above with respect to the already shown drawings, and the detailed description thereof will be omitted as appropriate.

[0008] (First Embodiment) The semiconductor device of the first embodiment is a 3D NAND flash memory.

[0009] FIGS. 1A and 1B are schematic cross-sectional views of the memory cell array 100 of the semiconductor device of the first embodiment. FIGS. 1A and 1B show the cross-sections of a plurality of memory cells MC in one memory string in the memory cell array 100.

[0010] FIG. 1A is a yz cross-sectional view of the memory cell array 100. FIG. 1A is a cross-section taken along line BB' of FIG. 1B. FIG. 1B is an xy cross-sectional view of the memory cell array 100. FIG. 1B is a cross-section taken along line AA' of FIG. 1A. In FIG. 1A, the region surrounded by the dashed line is one memory cell MC.

[0011] As shown in FIGS. 1A and 1B, the memory cell array 100 includes a plurality of word lines 40, a semiconductor layer 32, a plurality of insulating layers 21, a plurality of insulating portions 21a, a tunnel insulating film 30, a charge storage film 28, a plurality of block films 37a, a plurality of block films 37, a plurality of insulating films 41, and a core insulating film 33. The plurality of word lines 40 and the plurality of insulating layers 21 form a stack 20. The "electrode layer" includes the word line 40 and the block film 37.

[0012] The memory cell array 100 is provided, for example, on a semiconductor substrate (not shown). The semiconductor substrate has a surface parallel to the x and y directions.

[0013] The word line 40 and the insulating layer 21 are alternately stacked in the z direction (the first direction) on the semiconductor substrate. The word lines 40 are spaced apart in the z direction. The word lines 40 are repeatedly arranged in the z direction while being spaced apart from each other. The plurality of word lines 40 and the plurality of insulating layers 21 form a stack 20. The word line 40 functions as a control electrode of the memory cell transistor.

[0014] The word line 40 is a plate-shaped conductor. The word line 40 is, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line 40 is, for example, tungsten (W). The thickness of the word line 40 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0015] The insulating layer 21 separates the word line 40 from the word line 40. The insulating layer 21 electrically separates the word line 40 from the word line 40.

[0016] The insulating layer 21 is, for example, an oxide, an oxynitride, or a nitride. The insulating layer 21 includes, for example, silicon oxide. The thickness of the insulating layer 21 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0017] The insulating portion 21a is provided at the end of the insulating layer 21 on the insulating film 41 side. The insulating portion 21a is provided between the insulating layer 21 and the insulating film 41. The insulating portion 21a overlaps, when viewed in the z direction, the portion of the block film 37 that extends in the z direction. The insulating portion 21a includes, for example, silicon oxide.

[0018] The semiconductor layer 32 is provided in the laminate 20. The semiconductor layer 32 extends in the z direction. The semiconductor layer 32 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0019] The semiconductor layer 32 is provided so as to penetrate the laminate 20. The semiconductor layer 32 is surrounded by a plurality of word lines 40. The semiconductor layer 32 is, for example, cylindrical. The semiconductor layer 32 functions as a channel of a memory cell transistor.

[0020] The semiconductor layer 32 is, for example, a polycrystalline semiconductor. The semiconductor layer 32 is, for example, polycrystalline silicon.

[0021] The tunnel insulating film 30 is provided between the semiconductor layer 32 and the word line 40. The tunnel insulating film 30 is provided between the semiconductor layer 32 and the charge storage film 28.

[0022] The tunnel insulating film 30 has a function of passing charges in accordance with a voltage applied between the word line 40 and the semiconductor layer 32.

[0023] The tunnel insulating film 30 includes, for example, silicon (Si) and oxygen (O). The tunnel insulating film 30 includes, for example, silicon (Si), oxygen (O), and nitrogen (N).

[0024] The tunnel insulating film 30 includes, for example, silicon oxide or silicon oxynitride. The tunnel insulating film 30 is, for example, a silicon oxide film, a silicon oxynitride film, or a laminated film of silicon oxide films.

[0025] The thickness of the tunnel insulating film 30 in the y direction is, for example, 3 nm or more and 8 nm or less.

[0026] The charge storage film 28 is provided between the tunnel insulating film 30 and the block film 37a. The charge storage film 28 extends in the z direction.

[0027] The charge storage film 28 contains silicon (Si) and nitrogen (N). The charge storage film 28 contains, for example, silicon nitride. The charge storage film 28 is, for example, a silicon nitride film.

[0028] The charge storage film 28 contains, for example, silicon (Si), nitrogen (N), and oxygen (O). The charge storage film 28 contains, for example, silicon oxynitride.

[0029] The thickness of the charge storage film 28 in the y direction is, for example, 1 nm or more and 5 nm or less.

[0030] The charge storage film 28 has a function of trapping and storing charges. The charges are, for example, electrons. The threshold voltage of the memory cell transistor changes according to the amount of charges stored in the charge storage film 28. By utilizing this change in the threshold voltage, one memory cell MC can store data.

[0031] For example, when the threshold voltage of the memory cell transistor changes, the voltage at which the memory cell transistor turns on changes. For example, if a state with a high threshold voltage is defined as data "0" and a state with a low threshold voltage is defined as data "1", the memory cell MC can store 1-bit data of "0" and "1".

[0032] The block film 37a is provided so as to continuously extend in the z direction along the charge storage film 28.

[0033] The block film 37a has a function of blocking the current flowing between the charge storage film 28 and the word line 40.

[0034] The block film 37a contains, for example, silicon oxide. The block film 37a is, for example, a silicon oxide film.

[0035] The block film 37 is provided between the block film 37a and the word line 40. The block film 37 is in contact with the insulating layer 21 in the z direction.

[0036] The block film 37 has a function of blocking the current flowing between the charge storage film 28 and the word line 40.

[0037] The block film 37 contains, for example, aluminum oxide. The block film 37 is, for example, an aluminum oxide layer.

[0038] The insulating film 41 is provided between the insulating layer 21 and the block film 37a. The insulating film 41 contains, for example, silicon oxide. The insulating film 41 is, for example, a silicon oxide film.

[0039] The core insulating film 33 is provided in the laminate 20. The core insulating film 33 extends in the z direction. The core insulating film 33 is provided so as to penetrate the laminate 20. The core insulating film 33 is surrounded by the semiconductor layer 32. The core insulating film 33 is surrounded by a plurality of word lines 40. The core insulating film 33 is columnar. The core insulating film 33 is, for example, cylindrical.

[0040] The core insulating film 33 is, for example, an oxide, an oxynitride, or a nitride. The core insulating film 33 contains, for example, silicon oxide. The core insulating film 33 is, for example, a silicon oxide layer.

[0041] A method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 2 to 10. The semiconductor device of this embodiment is manufactured, for example, by the method shown below. First, as shown in FIG. 2, an insulating layer 21 and a sacrificial layer 22 are alternately laminated on a semiconductor substrate 10. Thereby, a laminate 20 laminated in the z direction (the vertical direction in the figure) is formed. The insulating layer 21 is, for example, a silicon oxide layer. The sacrificial layer 22 is, for example, a silicon nitride layer.

[0042] The insulating layer 21 and the sacrificial layer 22 are formed, for example, by a CVD (Chemical Vapor Deposition) method. A part of the insulating layer 21 becomes an interlayer insulating layer.

[0043] Next, as shown in FIG. 3, a memory hole 24 is formed in the laminate 20 along the z direction. In the drawings below FIG. 3, the semiconductor substrate 10 is omitted. This memory hole 24 penetrates the laminate 20 composed of the insulating layer 21 and the sacrificial layer 22. This memory hole 24 is formed, for example, using a lithography method and an RIE (Reactive Ion Etching) method. In the following description, since it is a cross section symmetric with respect to the center line C-C shown in FIG. 3, the cross section on the left side of the center line C-C will be described.

[0044] Next, as shown in FIG. 4, an insulating portion 21a overlapping the sacrificial layer 22 when viewed from the z direction is formed at the end of the insulating layer 21 exposed from the inner surface of the memory hole 24. That is, the insulating portion 21a is disposed inside the laminate 20 rather than at the end face of the laminate 20. The Z-Y cross-sectional shape of the insulating portion 21a is, for example, substantially rectangular.

[0045] As shown in FIG. 4 and later, there may be a transition layer formed at the boundary between the insulating layer 21 and the sacrificial layer 22 in the Z direction, as shown by gray hatching in FIG. 4. The transition layer may be, for example, a layer in which SiN and SiO2 are mixed, or a layer in which SiN penetrates into the insulating layer 21 of SiO2 or a layer in which SiO2 penetrates into the sacrificial layer 22 of SiN. The transition layer may contain, for example, SiON. Therefore, the central portion of the insulating layer 21 contains substantially single-composition SiO2, while the transition layer contains other compositions than SiO2.

[0046] Therefore, as shown in FIG. 4, an insulating portion 21a having substantially single-composition SiO2 is formed. Thereby, the transition layer exposed on the inner surface of the memory hole 24 can be eliminated.

[0047] The insulating portion 21a is formed by performing an oxidation treatment on the inner surface of the memory hole 24. By the oxidation treatment, the insulating layer 21 and the transition layer exposed from the inner surface of the memory hole 24 are oxidized. The oxidation treatment is, for example, dry oxidation or radical oxidation. In radical oxidation, for example, oxidation is performed using radicals derived from H2O, O2 or / and H2 gas. Note that the surface of the sacrificial layer 22 may also be oxidized. In this case, surface exposure is performed by etch-back. The oxidation amount of the sacrificial layer 22 may be different depending on dry oxidation or radical oxidation. For example, the oxidation amount of the sacrificial layer 22 by radical oxidation is larger than the oxidation amount of the sacrificial layer 22 by dry oxidation.

[0048] Next, as shown in FIG. 5, an insulating film 41 is selectively formed on the insulating portion 21a on the inner surface of the memory hole 24. More specifically, the insulating film 41 is selectively grown from the insulating portion 21a (with the surface of the insulating portion 21a as a base point) by area selective deposition (ASD). Thereby, an opening of the insulating film 41 is formed in the region corresponding to the sacrificial layer 22.

[0049] By forming the insulating portion 21a as the base of the insulating film 41, the insulating film 41 can be formed in a more appropriate shape as will be described later. As a result, the film shape of the insulating film 41 can be improved.

[0050] Next, as shown in FIG. 6, a block film 37a is formed on the sacrificial layer 22 and the insulating film 41.

[0051] Next, as shown in FIG. 7, a charge storage film 28 is formed on the block film 37a. After the formation of the charge storage film 28, a part of the charge storage film 28 is removed. The removal of a part of the charge storage film 28 is performed, for example, by CDE (Chemical Dry Etching).

[0052] Also, in the process shown in FIG. 7, the thickness of the charge storage film 28 in the y direction in the region corresponding to the insulating film 41 is smaller than the thickness of the charge storage film 28 in the y direction formed at the position of the opening of the insulating film 41. That is, the charge storage film 28 is continuous in the extending direction (z direction) of the semiconductor layer 32, but is thinned in the y direction by the insulating film 41. Therefore, a pseudo-segmented structure of the charge storage film 28 is formed.

[0053] Next, as shown in FIG. 8, a tunnel insulating film 30 is formed on the charge storage film 28.

[0054] Next, as shown in FIG. 9, a semiconductor layer 32 is formed on the tunnel insulating film 30, and a core insulating film 33 (not shown) is formed on the semiconductor layer 32.

[0055] Thereafter, a groove penetrating the laminate 20 is opened around the memory hole 24, and the sacrificial layer 22 is removed from this groove. By removing the sacrificial layer 22, the block film 37a is exposed. For the removal of the sacrificial layer 22, a phosphoric acid chemical solution heated normally is used. By this chemical solution treatment, voids are generated in the trace of the removed silicon nitride layer. Voids tracing the shape of the original sacrificial layer 22 are generated. Note that the above-described transition layer may be removed.

[0056] Next, a block film 37 containing, for example, aluminum oxide is formed so as to cover the bottom surface and side surfaces of the gap. Incidentally, a barrier metal containing, for example, TiN may be formed so as to cover the block film 37.

[0057] Next, the gap is filled with a wiring material, for example, W (tungsten), to form a word line (electrode) 40. As a result, as shown in FIGS. 1 and 10, the semiconductor device is completed.

[0058] As described above, in the first embodiment, an insulating portion 21a is provided at an end portion of the insulating layer 21 on the insulating film 41 side as a base of the insulating film 41. Thereby, the insulating film 41 can be formed in a more appropriate shape. As a result, the film shape of the insulating film 41 can be improved.

[0059] The film density of the insulating portion 21a is different from that of the insulating layer 21. The film density of the insulating portion 21a is higher than that of the insulating layer 21. This is because, for example, impurities escape due to an oxidation process, resulting in a higher film density of the insulating portion 21a. The relationship between the film densities of the insulating portion 21a, the insulating layer 21, and the insulating film 41 is represented by insulating portion 21a > insulating layer 21 > insulating film 41. For example, the film density of the insulating portion 21a may be greater than 2.30 (g / cc), and the film density of the insulating film 41 may be less than 2.05 (g / cc).

[0060] Also, the charge storage film 28 is continuous along the direction (z direction) in which the semiconductor layer 32 serving as a channel extends. However, the thickness of the charge storage film 28 in the y direction is reduced by the insulating film 41, and the thick charge storage film 28 in the y direction is divided in the direction (z direction) in which the semiconductor layer 32 serving as a channel extends. Therefore, it is possible to suppress the leakage of charges in the direction (z direction) in which the semiconductor layer 32 serving as a channel extends. According to this embodiment, deterioration of the charge holding characteristics can be suppressed.

[0061] Also, the pseudo-segmented structure of the charge storage film 28 was described. However, the charge storage film 28 in the region corresponding to the insulating film 41 may not be provided. That is, the charge storage film 28 may have a structure that is completely segmented in the z direction. For example, by increasing the removal amount of the charge storage film 28 in the process shown in FIG. 7, the charge storage film 28 is segmented in the z direction.

[0062] (Comparative Example) FIGS. 11 to 13 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a comparative example. The comparative example is different from the first embodiment in that the insulating portion 21a is not formed. The process shown in FIG. 11 is performed after the same processes as those in FIGS. 2 and 3.

[0063] After forming the memory hole 24 (see FIG. 3), as shown in FIG. 11, an insulating film 41 is selectively formed on the insulating layer 21 on the inner surface of the memory hole 24. More specifically, the insulating film 41 is selectively grown from the insulating layer 21 (with the surface of the insulating layer 21 as a reference point).

[0064] Next, as shown in FIG. 12, a block film 37a is formed on the sacrificial layer 22 and the insulating film 41, and a charge storage film 28 is formed on the block film 37a.

[0065] Next, as shown in FIG. 13, a part of the charge insulating film 29 is removed. A part of the charge storage film 28 is removed, for example, by CDE.

[0066] Here, the cross-sectional shape of the insulating film 41 shown in FIG. 11 is convex lens-shaped. This is because the transition layer contains a composition other than SiO2, and it is difficult for the insulating film 41 on the transition layer to grow. As a result, it becomes difficult to appropriately form a step by the insulating film 41. As shown in FIG. 13, it becomes difficult to appropriately form the pseudo-segmented structure of the charge storage film 28.

[0067] In contrast, in the first embodiment, by forming the insulating portion 21a containing SiO2 of substantially a single composition on the end face of the insulating layer 21, the transition layer exposed from the inner surface of the memory hole 24 can be eliminated. As a result, as shown in FIG. 5, the cross-sectional shape of the insulating film 41 can be made more rectangular. That is, the film shape of the insulating film 41 can be improved. As a result, the pseudo-segmented structure of the charge storage film 28 can be formed more appropriately.

[0068] (Second Embodiment) FIGS. 14 to 16 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment. The second embodiment is different from the first embodiment in that the degree (amount) of oxidation of the sacrificial layer 22 is large and the word line 40 is recessed by the insulating portion 21a to form a step. The process shown in FIG. 14 is performed after the same processes as those shown in FIGS. 2 and 3.

[0069] After forming the memory hole 24 (see FIG. 3), as shown in FIG. 14, the insulating portion 21a is formed at the end of the insulating layer 21 exposed from the inner surface of the memory hole 24.

[0070] The insulating portion 21a is formed, for example, by dry oxidation or radical oxidation in the same manner as the process shown in FIG. 4. Further, in the process shown in FIG. 14, the degree of oxidation of the sacrificial layer 22 is larger than that in the process shown in FIG. 4. The insulating portion 21a shown in FIG. 14 protrudes longer in the z direction compared to the insulating portion 21a shown in FIG. 4 and reaches the inside of the sacrificial layer 22.

[0071] Next, as shown in FIG. 15, the insulating film 41 is selectively formed on the insulating portion 21a on the inner surface of the memory hole 24. Note that the process shown in FIG. 15 is the same as the process shown in FIG. 5.

[0072] Thereafter, the same processes as those shown in FIGS. 6 to 10 are performed. As a result, the semiconductor device shown in FIG. 16 is completed.

[0073] As shown in FIG. 16, the insulating portion 21a is provided so as to protrude in the z direction beyond the interface between the word line 40 and the insulating layer 21. The word line 40 has a concave portion corresponding to the insulating portion 21a that protrudes beyond the interface between the word line 40 and the insulating layer 21. Thereby, a step is formed in the cross-sectional shape of the word line 40.

[0074] In the second embodiment, similar to the first embodiment, the film density of the insulating portion 21a is different from that of the insulating layer 21. The film density of the insulating portion 21a is higher than that of the insulating layer 21. This is because, for example, impurities escape by an oxidation treatment and the film density of the insulating portion 21a becomes high. The relationship between the film densities of the insulating portion 21a, the insulating layer 21, and the insulating film 41 is represented by insulating portion 21a > insulating layer 21 > insulating film 41. For example, the film density of the insulating portion 21a may be greater than 2.30 (g / cc), and the film density of the insulating film 41 may be less than 2.05 (g / cc).

[0075] As in the second embodiment, the degree of oxidation of the sacrificial layer 22 may be large, and the word line 40 may be depressed by the insulating portion 21a to form a step. The semiconductor device according to the second embodiment can obtain the same effects as the first embodiment.

[0076] (Third Embodiment) FIGS. 17 to 20 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the third embodiment. In the third embodiment, the method for forming the insulating portion 21a is different from that in the first embodiment. The process shown in FIG. 17 is performed after the same processes as those in FIGS. 2 and 3.

[0077] After the formation of the memory hole 24 (see FIG. 3), as shown in FIG. 17, the end portion of the insulating layer 21 exposed from the inner surface of the memory hole 24 is removed. The transition layer exposed from the inner surface of the memory hole 24 is removed together with the insulating layer 21. The removal of the end portion of the insulating layer 21 is performed, for example, by an HF-based wet process. Incidentally, the removal of the end portion of the insulating layer 21 may be performed by CDE as long as the selectivity between the insulating layer 21 and the sacrificial layer 22 can be achieved. The cross-sectional shape of the region where the end portion of the insulating layer 21 has been removed is lens-shaped. This is because the etching rate of the transition layer is lower than the etching rate at the central portion of the insulating layer 21.

[0078] Next, as shown in FIG. 18, an insulating portion 21a is selectively formed in the region (void) where the end portion of the insulating layer 21 has been removed. More specifically, the insulating portion 21a is selectively grown from the remaining insulating layer 21 by selective growth (with the surface of the insulating layer 21 as a reference point). The end face of the insulating portion 21a on the memory hole 24 side in the Z-Y cross section is nearly flat. This is because the growth of the insulating portion 21a in the vicinity of the transition layer is slower than the growth of the insulating portion 21a at the central portion of the insulating layer 21.

[0079] In the third embodiment, the film density of the insulating portion 21a may be the same as or different from the film density of the insulating layer 21. For example, the film density of the insulating portion 21a may be lower than the film density of the insulating layer 21. Also, the film density of the insulating portion 21a may be the same as or different from the film density of the insulating film 41. For example, the film density of the insulating portion 21a may be higher than the film density of the insulating film 41.

[0080] Next, as shown in FIG. 19, an insulating film 41 is selectively formed on the insulating portion 21a on the inner surface of the memory hole 24. Incidentally, the process shown in FIG. 15 is the same as the process shown in FIG. 5.

[0081] Thereafter, the same processes as those shown in FIGS. 6 to 10 are performed. As a result, the semiconductor device shown in FIG. 20 is completed.

[0082] As in the third embodiment, the method of forming the insulating portion 21a may be changed. The semiconductor device according to the third embodiment can obtain the same effects as the first embodiment.

[0083] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0084] 10 Semiconductor substrate, 20 Stacked body, 21 Insulating layer, 21a Insulating portion, 22 Sacrificial layer, 24 Memory hole, 28 Charge storage film, 30 Tunnel insulating film, 32 Semiconductor layer, 37 Block film, 37a Block film, 40 Word line, 41 Insulating film

Claims

1. A laminate in which an electrode layer and an insulating layer are alternately laminated in a first direction, A semiconductor layer disposed in the laminate along the first direction, A first insulating film disposed between the laminate and the semiconductor layer along the first direction, A charge storage film disposed between the laminate and the first insulating film along the first direction, A second insulating film disposed between the laminate and the charge storage film along the first direction, A third insulating film disposed between the insulating layer and the second insulating film, An insulating portion disposed at an end of the insulating layer on the side of the third insulating film and overlapping the electrode layer when viewed from the first direction, Comprising, A semiconductor device in which the film density of the insulating portion is different from the film density of the insulating layer.

2. The electrode layer includes a fourth insulating film having a first portion disposed along the first direction and a second portion disposed along a second direction intersecting the first direction, and a conductor surrounded by the fourth insulating film, The semiconductor device according to claim 1, wherein the first portion overlaps the insulating portion when viewed from the first direction.

3. The semiconductor device according to claim 1, wherein the film density of the insulating portion is higher than the film density of the insulating layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the film density of the insulating portion is higher than the film density of the third insulating film.

5. The semiconductor device according to claim 1, wherein the insulating portion is provided so as to protrude in the first direction beyond an interface between the electrode layer and the insulating layer.

6. The semiconductor device according to claim 5, wherein the electrode layer has a concave portion corresponding to the insulating portion protruding beyond the interface.

7. Forming a laminate in which a sacrificial layer and an insulating layer are alternately laminated in a first direction, Forming a hole penetrating the laminate in the first direction, Forming an insulating portion overlapping the sacrificial layer when viewed from the first direction at an end of the insulating layer exposed from the hole, Selectively forming a first film on the insulating portion, Forming a second film of an insulator on the sacrificial layer and the first film, Forming a charge storage film on the second film, Removing a part of the charge storage film, Forming a third film of an insulator on the charge storage film, Forming a semiconductor layer on the third film, Comprising, A method for manufacturing a semiconductor device in which the film density of the insulating portion is different from the film density of the insulating layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein forming the insulating portion includes performing an oxidation treatment on an inner surface of the hole.

9. The method of manufacturing a semiconductor device according to claim 8, wherein performing the oxidation treatment includes oxidizing a transition layer between the sacrificial layer and the insulating layer exposed from the hole.

10. The method of manufacturing a semiconductor device according to claim 8 or claim 9, wherein the oxidation treatment is dry oxidation or radical oxidation.

11. Forming the insulating portion includes removing an end portion of the insulating layer exposed from the hole, and selectively forming the insulating portion on the remaining insulating layer. The method of manufacturing a semiconductor device according to claim 7.

12. The method of manufacturing a semiconductor device according to claim 11, wherein removing the end portion of the insulating layer includes removing a transition layer between the sacrificial layer and the insulating layer exposed from the hole.

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