Circuit arrangement

Abstract

To provide a circuit arrangement that has an electrostatic protection function, and has a wide application range for achieving commonality of manufacturing processes.SOLUTION: A circuit arrangement 10 includes a first terminal T1, a second terminal T2, a thyristor circuit 20, a voltage hold circuit 30, a trigger transistor TT, a predetermined capacitor CS, and a predetermined resistor RS. The thyristor circuit 20 is provided between the first terminal T1 and a node NA that is a first node. The voltage hold circuit 30 is provided between the node NA that is the first node and the second terminal T2. The trigger transistor TT causes a trigger current to flow in the thyristor circuit 20. The predetermined capacitor CS is provided between the first terminal T1 and a gate of the trigger transistor TT. The predetermined resistor RS is provided between the gate of the trigger transistor TT and the second terminal T2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit device and the like.

Background Art

[0002] Conventionally, semiconductor devices in which various circuit devices such as a circuit device including an electrostatic protection circuit are mixedly mounted have been proposed. In manufacturing these semiconductor devices, it is desirable from the viewpoint of manufacturing efficiency to be able to form a plurality of circuit elements in a single manufacturing process. Patent Document 1 discloses an electrostatic protection circuit device using an inverter. Patent Document 2 discloses a method for simplifying a manufacturing process by forming a gate film of any transistor in a gate film forming process corresponding to a transistor having a thinner gate film when forming different types of transistors on the same substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The electrostatic protection circuit device disclosed in Patent Document 1 newly requires a high - breakdown - voltage CMOS (Complementary Metal - Oxide - Semiconductor), and since the gate film thickness of all transistors cannot be made common, the method of Patent Document 2 cannot be applied. Therefore, a proposal for a circuit device with a wide application range of a method for simplifying the manufacturing process is desired.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a circuit device including a first terminal, a second terminal, a thyristor circuit provided between the first terminal and a first node, a voltage holding circuit provided between the first node and the second terminal, a trigger transistor that passes a trigger current through the thyristor circuit, a capacitor provided between the first terminal and the gate of the trigger transistor, and a resistor provided between the gate of the trigger transistor and the second terminal.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the embodiments described below do not unduly limit the content described in the claims, and not all of the configurations described in the embodiments are essential constituent elements.

[0008] FIG. 1 is a configuration example of a circuit device 10 according to the method of the present embodiment. The circuit device 10 of the present embodiment includes a first terminal T1, a second terminal T2, a thyristor circuit 20, a voltage hold circuit 30, a trigger transistor TT, a predetermined capacitor CS, and a predetermined resistor RS. Note that the method of the present embodiment can also be realized as a semiconductor device. For example, a semiconductor device may be configured to include the circuit device 10 illustrated in FIG. 1 and an internal circuit (not shown). Specifically, for example, when the semiconductor device is a motor driver IC, the internal circuit includes a control circuit including a constant voltage circuit, a pre-driver, an H-bridge circuit, and the like. Although illustration of the H-bridge circuit is omitted, it is a known circuit including, for example, a P-type DMOS (Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) and an N-type DMOS.

[0009] The circuit device 10 of the present embodiment functions as an electrostatic protection circuit that protects the above-described internal circuit from a surge when an ESD surge is applied. Although details will be described later, when the voltage of the surge exceeds the trigger voltage, the trigger transistor TT flows a trigger current, and the thyristor TH included in the thyristor circuit 20 is turned on, so that the current of the surge can be prevented from reaching the internal circuit. Then, the on-state of the thyristor TH is maintained while the applied voltage exceeds the hold voltage of the circuit device 10. That is, the circuit device 10 is configured such that the hold voltage of the circuit device 10 of the present embodiment is higher than the voltage for operating the internal circuit. Otherwise, a voltage signal to be supplied to the internal circuit thereafter is absorbed by the circuit device 10, and the internal circuit does not function.

[0010] The first terminal T1 and the second terminal T2 are external connection terminals of the circuit device 10, and are configured as, for example, pads of the circuit device 10 or pads of a semiconductor device. In the region related to the pads, a metal layer is exposed from a passivation film which is an insulating layer, and the pads which are terminals of the circuit device 10 are formed by this exposed metal layer. The first terminal T1 of the present embodiment is one of a power supply terminal on the high potential side and a power supply terminal on the low potential side, and the second terminal T2 is the other power supply terminal of the power supply terminal on the high potential side and the power supply terminal on the low potential side. In the following description, it will be described that the first terminal T1 is a power supply terminal on the high potential side and the second terminal T2 is a power supply terminal on the low potential side. The method of the present embodiment relates to discharge in the direction from the power supply line connected to the first terminal T1 to the power supply line connected to the second terminal T2.

[0011] Note that the circuit device 10 of the present embodiment may further include a diode shown in A0. The diode shown in A0 is a diode whose forward direction is from the power supply line connected to the second terminal T2 to the power supply line connected to the first terminal T1. By doing so, it can function as a discharge element in the discharge path in the direction from the power supply line connected to the second terminal T2 to the power supply line connected to the first terminal T1.

[0012] Also, for the sake of easy understanding, specific numerical values such as voltages may be shown, but they are merely examples. In the following description, unless otherwise specified, the maximum operating voltage between the power supply line connected to the first terminal T1 and the power supply line connected to the second terminal T2 is 24V, and the absolute maximum rated voltage is 40V. That is, the maximum operating voltage of the internal circuit is 24V. Also, the voltage of the ESD surge applied to the first terminal T1 side is 40V. Further, the maximum operating voltage between the source and drain of the PMOS (P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) in this embodiment is 5.5V, the absolute maximum rated voltage is assumed to be 7V, and the breakdown voltage and the hold voltage are assumed to be 8V. Also, the maximum operating voltage between the source and drain of the DMOS in this embodiment is 24V, the absolute maximum rated voltage is assumed to be 40V, the maximum operating voltage between the gate and source is 5.5V, and the absolute maximum rated voltage is assumed to be 7V. That is, in the DMOS included in the semiconductor device of this embodiment, the breakdown voltage between the gate and source is lower than the breakdown voltage between the source and drain. This is because the gate film formation process is made common for the DMOS and the PMOS in the same manner as the method described in Patent Document 2.

[0013] The thyristor circuit 20 includes a thyristor TH, a first resistor R1, and a second resistor R2. The structure of the thyristor TH is equivalent to a circuit including a transistor Q1 which is a PNP bipolar transistor and a transistor Q2 which is an NPN bipolar transistor. Hereinafter, the thyristor TH will be described using the equivalent circuit. The emitter of the transistor Q1 is connected to a node NF which is a node of the first terminal T1. The base of the transistor Q1 is connected to a node NC which is a node of the collector of the transistor Q2. The collector of the transistor Q1 is connected to a node NE which is a node of the base of the transistor Q2. The emitter of the transistor Q2 is connected to the node NA. One end of the first resistor R1 is connected to the node NF, and the other end is connected to the node NC. In other words, one end of the first resistor R1 is connected to the first terminal T1, and the other end is connected to the collector of the transistor Q2. One end of the second resistor R2 is connected to the node NE, and the other end is connected to the node NA.

[0014] The voltage holding circuit 30 is provided between the node NA and the second terminal T2. That is, the voltage holding circuit 30 is connected in series with the thyristor circuit 20 in the discharge path of the circuit device 10 that functions as an electrostatic protection circuit. Thereby, the holding voltage of the circuit device 10 can be set to a desired voltage. Specifically, for example, when the internal circuit operates at 24V, it is necessary to set the holding voltage of the circuit device 10 to a voltage higher than 24V. However, the holding voltage of the thyristor TH is only about 2V. With only the holding voltage of the thyristor circuit 20, after the application of the ESD surge, the thyristor TH remains in the on state, and even if the voltage for operating the internal circuit is supplied to the semiconductor device thereafter, current continues to flow through the thyristor TH and the internal circuit cannot operate. In this regard, as in this embodiment, by connecting the voltage holding circuit 30 and the thyristor circuit 20 in series, the sum of the holding voltage of the thyristor TH and the holding voltage of the voltage holding circuit 30 can be made equal to the holding voltage of the circuit device 10. Thereby, the holding voltage of the circuit device 10 can be set to a desired voltage. As a result, for example, the circuit device 10 can function as an electrostatic protection circuit for an internal circuit that needs to supply a high voltage to drive a load. Even when the operating voltage of the internal circuit is not high, the circuit device 10 of this embodiment may be applied. In this case, the voltage holding circuit 30 may be configured so that the holding voltage is low. That is, it can be said that the circuit device 10 of this embodiment has a wide range of applications as an electrostatic protection circuit.

[0015] In this embodiment, as will be described later, the circuit device 10 functions as an electrostatic protection circuit, and the thyristor circuit 20 and the voltage holding circuit 30 are provided in series on the discharge path when an ESD surge is applied. In this embodiment, on the discharge path, the connection node between the thyristor circuit 20 and the voltage holding circuit 30 is referred to as the first node. Specifically, for example, in the circuit device 10 of FIG. 1, the node NA corresponds to the first node, and in the circuit device 10 of FIG. 17 described later, the node NF corresponds to the first node.

[0016] The voltage holding circuit 30 includes a holding element. Specifically, for example, in FIG. 1, the voltage holding circuit 30 is configured to include a first holding element 31, a second holding element 32, and a third holding element 33. However, the number of holding elements is not limited to three, and it can be generalized that the voltage holding circuit 30 includes n holding elements. Also, as an example of the holding element shown in FIG. 1, an SGPMOS (Source Connected Gate P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) is illustrated. However, the holding element that can be adopted in this embodiment is not limited to SGPMOS, and details will be described later with reference to FIG. 7. Further, in FIG. 1, the first holding element 31, the second holding element 32, and the third holding element 33 are connected in series to each other. By doing so, the holding voltage of the voltage holding circuit 30 can be made the sum of the holding voltages of the respective holding elements, so that the holding voltage of the voltage holding circuit 30 can be set to a desired voltage. For example, as shown in FIG. 1, assume that the first holding element 31, the second holding element 32, and the third holding element 33 are all the same SGPMOS. In this case, since the holding voltage of the circuit device 10 is the sum of 2V which is the holding voltage of the thyristor TH of the thyristor circuit 20 and 24V (= 8V × 3) which is the holding voltage of the voltage holding circuit 30, the holding voltage of the circuit device 10 becomes 26V, which is a voltage higher than 24V as the voltage for operating the internal circuit.

[0017] The trigger transistor TT constitutes a trigger circuit together with a predetermined capacitor CS and a predetermined resistor RS. Further, the predetermined capacitor CS constitutes an RC circuit together with the predetermined resistor RS. When an ESD surge is applied to the first terminal T1, the trigger circuit turns on the thyristor TH by a method described later. The trigger transistor TT in FIG. 1 is, for example, an N-type transistor, the drain of which is connected to a node ND which is the other end side node of the first resistor R1, and the source of which is connected to the second terminal T2. In the example of the circuit device 10 described later with reference to FIG. 17, a P-type transistor can also be employed. Specifically, for example, when protecting an internal circuit that drives a load, the trigger transistor TT may be constituted by, for example, an N-type DMOS. Similarly, in the circuit device 10 described later with reference to FIG. 17, it may be constituted by a P-type DMOS. By doing so, the DMOS included in the internal circuit and the manufacturing process can be made common.

[0018] The predetermined capacitor CS is provided between the first terminal T1 and a node NB which is the gate node of the trigger transistor TT. Note that the predetermined capacitor CS can employ, for example, a MOM capacitor, and details will be described later with reference to FIG. 13. One end of the predetermined resistor RS is connected to the node NB, and the other end is connected to the second terminal T2. In other words, the predetermined resistor RS is provided between the gate of the trigger transistor TT and the second terminal T2.

[0019] The semiconductor device including the circuit device 10 operates by an external power supply shown in A10 of FIG. 2 during normal operation. The power supply voltage of the external power supply shown in A10 is set to 24V. Further, the second terminal T2 is connected to the ground GND, and the ground voltage is assumed to be 0V.

[0020] A voltage of 24V is supplied between the drain and source of the trigger transistor TT. However, by configuring the trigger transistor TT with the aforementioned N-type DMOS, the trigger transistor TT will not be damaged. That is, the voltage on the drain side of the trigger transistor TT is 24V, which is equal to the voltage of the power supply line connected to the first terminal T1, and the voltage on the source side of the trigger transistor TT is maintained at 0V, which is equal to the voltage of the power supply line connected to the second terminal T2. Also, during normal operation, the predetermined resistor RS functions as a pull-down resistor, and the potential of the gate of the trigger transistor TT becomes 0V, which is equal to the voltage of the power supply line connected to the second terminal T2. Therefore, there is no potential difference between the gate and source of the trigger transistor TT, and the trigger transistor TT is in the off state. As a result, the thyristor TH is also in the off state. Also, each source of the SGPMOS of the first hold element 31 in the voltage hold circuit 30 is in a high-impedance state. The same applies to the SGPMOS of the second hold element 32 and the third hold element 33. Thus, in FIG. 2, there is no path for current to flow from the first terminal T1 to the second terminal T2.

[0021] The operation of the circuit device 10 when an ESD surge is applied to the power supply line side connected to the first terminal T1 will be described with reference to FIG. 3. Also, in FIG. 3, the arrows shown at A1, A2, A3, A4, and A5 are shown to schematically indicate the main current paths for ease of understanding, and the detailed current paths may be additionally described. The same applies to the arrows shown at A11, A12, A13, A14, and A15 in FIG. 18, the arrows shown at A21, A22, A23, A24, and A25 in FIG. 23, the arrows shown at A31, A32, A33, A34, and A35 in FIG. 25, the arrows shown at A41, A42, A43, A51, A52, and A53 in FIG. 27, and the arrows shown at A61, A62, A63, A71, A72, and A73 in FIG. 29.

[0022] Suppose the potential of the first terminal T1 rises to, for example, 40V. At this time, due to the capacitive coupling of the predetermined capacitor CS, the potential of the node NB rises. That is, the potential on the gate side of the trigger transistor TT rises. As a result, a potential difference is generated between the gate and source of the trigger transistor TT, so the trigger transistor TT turns on and current flows in the direction of the arrow shown in A1. Note that the arrow shown in A1, more precisely, goes in the order of the first terminal T1, node NF, first resistor R1, node ND, drain of the trigger transistor TT, source of the trigger transistor TT, and second terminal T2. Thereby, current flows through the first resistor R1, and the potential of the node ND connected to the base of the transistor Q1 becomes lower than the potential of the first terminal T1 (node NF) connected to the emitter of the transistor Q1. Thereby, current flows in the direction of the arrow shown in A2. Note that the arrow shown in A2, more precisely, goes in the order of the first terminal T1, node NF, emitter of the transistor Q1, base of the transistor Q1, node NC, node ND, drain of the trigger transistor TT, source of the trigger transistor TT, and second terminal T2. As a result, the base current of the transistor Q1 flows, so the transistor Q1 turns on.

[0023] As a result, a current flows in the direction of the arrow shown in A3. Note that the arrow shown in A3 more precisely goes in the order of the first terminal T1, node NF, emitter of transistor Q1, collector of transistor Q1, node NE, second resistor R2, node NA, voltage hold circuit 30, and second terminal T2. As a result, a current flows through the second resistor R2, and the potential of node NE connected to the base of transistor Q2 becomes higher than the potential of node NA connected to the emitter of transistor Q2. As a result, a current flows in the direction of the arrow shown in A4. Note that the arrow shown in A4 more precisely goes in the order of the first terminal T1, node NF, emitter of transistor Q1, collector of transistor Q1, node NE, emitter of transistor Q2, node NA, voltage hold circuit 30, and second terminal T2. As a result, a base current of transistor Q2 flows, and since transistor Q2 turns on, a current flows in the direction of the arrow shown in A5. Note that the arrow shown in A5 more precisely goes in the order of the first terminal T1, node NF, emitter of transistor Q1, base of transistor Q1, node NC, collector of transistor Q2, emitter of transistor Q2, node NA, voltage hold circuit 30, and second terminal T2. That is, the thyristor TH turns on.

[0024] When the thyristor TH thus turns on, the circuit device 10 including the thyristor circuit 20 operates as an electrostatic protection circuit. That is, the ESD surge current applied to the first terminal T1 flows toward the second terminal TS2 side, protecting an internal circuit (not shown).

[0025] With reference to FIGS. 4 and 5, the thyristor TH of this embodiment will be described in more detail. FIG. 4 is a diagram for explaining the nodes connected to the thyristor TH. As shown in FIG. 4, the thyristor TH is connected to four nodes. The node shown as D1 in FIG. 4 is the node of the first gate of the thyristor TH, the node shown as D2 is the node of the second gate of the thyristor TH, the node shown as DA is the node of the anode of the thyristor TH, and the node of DC is the node of the cathode of the thyristor TH. Note that the first gate corresponds to the base of the transistor Q1 described above, and the second gate corresponds to the base of the transistor Q2 described above. The state in which current flows from the node shown as DA to the node shown as DC corresponds to the on state of the thyristor TH.

[0026] FIG. 5(A) is a cross-sectional schematic view of the thyristor TH of this embodiment, and FIG. 5(B) is a plan schematic view of the thyristor TH of this embodiment. Note that, for convenience of explanation, FIG. 5(A) shows a cross-sectional schematic view at the time when the so-called front-end process is completed, and illustration of wiring layers, insulating layers, etc. formed in the so-called back-end process is omitted. The same applies to FIGS. 6(A), 8(A), 9(A), 10(A), 11(A), and 12(A). Also, FIGS. 5(A) and 5(B) are both schematic diagrams for convenience of explanation, and do not accurately show the dimensions of each component. The same applies to FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B), 10(A), 10(B), 11(A), 11(B), 12(A), and 12(B).

[0027] In the thyristor TH, a well of a second conductivity type shown at B1 and a well of a first conductivity type shown at B2 are formed with respect to the underlying substrate shown at B0 in FIG. 5(A). The underlying substrate is, for example, a silicon substrate containing impurities of a second conductivity type such as boron, that is, a so-called P-type substrate. Note that examples of the impurities of the first conductivity type described later include phosphorus and the like. Note that the region shown by the dotted line frame of C0 in FIG. 5(B) corresponds to the region of the underlying substrate shown at B0 in FIG. 5(A). Further, in FIG. 5(B), the ring-shaped region between the dotted line frame of C0 and the dotted line frame of C1 corresponds to the region of the well of the second conductivity type shown at B1 in FIG. 5(A). Further, in FIG. 5(B), the region of the dotted line frame of C2 corresponds to the region of the well of the first conductivity type shown at B2 in FIG. 5(A).

[0028] Note that the well in this embodiment is a region into which impurities are implanted and is a region provided under a circuit element or another well. The well in this embodiment may be realized by a so-called buried diffusion layer in which N-type impurities or P-type impurities are implanted by, for example, an ion implantation method or the like and thermally diffused under predetermined conditions, or may be realized by a so-called epitaxial layer formed by a vapor phase growth method.

[0029] Further, in this embodiment, the first conductivity type refers to one of the positive and negative conductivity types, and the second conductivity type refers to the other of the positive and negative conductivity types. For example, the well of the first conductivity type shown at B2 in FIG. 5(A) described above can also be referred to as an N-type well, and the well of the second conductivity type shown at B1 in FIG. 5(A) can also be referred to as a P-type well. Hereinafter, for convenience of explanation, the well of the first conductivity type, the transistor of the first conductivity type, etc. will be described as an N-type well, an N-type transistor, etc. Similarly, the well of the second conductivity type, the transistor of the second conductivity type, etc. will be described as a P-type well, a P-type transistor, etc.

[0030] Also, in FIG. 5(A), the downward direction with respect to the plane including the lower base plate is defined as the first direction DR1. The downward direction is the direction from the front surface to the back surface in the thickness direction of the lower base plate. The direction opposite to the first direction DR1, that is, the upward direction with respect to the plane including the lower base plate is defined as the third direction DR3. That is, the first direction DR1 and the third direction DR3 are perpendicular to the lower base plate. And the direction along the plane including the lower base plate, in which the cathode region 2C and the second gate region 22 described later are alternately arranged, is defined as the second direction DR2. Also, the direction along the plane including the lower base plate and perpendicular to the second direction DR2 is defined as the fourth direction DR4. The same applies to FIGS. 6(A), 7(A), 8(A), 9(A), 10(A), 11(A), 12(A), and 13(A).

[0031] The N-type well shown at B3 in FIG. 5(A) is formed, and the P-type well shown at B8 in FIG. 5(A) is formed. In FIG. 5(B), the region within the dotted line frame of C1 corresponds to the region of the N-type well shown at B3 in FIG. 5(A). Also, in FIG. 5(B), the ring-shaped region between the dotted line frames of C0 and C1 corresponds to the region of the P-type well shown at B8 in FIG. 5(A).

[0032] Also, in FIG. 5(A), the first well 41 which is an N-type well and the second well 42 which is a P-type well are provided in the N-type well shown at B3. In FIG. 5(B), the ring-shaped region between the dotted line frames of C2 and C4 corresponds to the region of the first well 41 in FIG. 5(A). Also, in FIG. 5(B), the region within the dotted line frame of C5 corresponds to the region of the second well 42 in FIG. 5(A).

[0033] Also, after the P-type well shown at B8, the first well 41, and the second well 42 are formed and planarized, a layer of a pattern of an N-type impurity diffusion region and a layer of a pattern of a P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the first gate region 21 and the pattern of the cathode region 2C. The pattern of the P-type impurity diffusion region includes the pattern of the second gate region 22, the pattern of the anode region 2A, and the pattern of the region shown at B9.

[0034] The first gate region 21 is an impurity diffusion region doped with N-type impurity elements and is provided in the first well 41. The first gate region 21 is connected to the node shown as D1 in FIG. 4 via a contact (not shown). That is, the first gate region 21 is connected to the first terminal T1 via the aforementioned first resistor R1. Also, in the plan view of FIG. 5(B), the first gate region 21 is provided in a ring shape surrounding the anode region 2A, the second gate region 22, and the cathode region 2C.

[0035] The anode region 2A is an impurity diffusion region doped with P-type impurity elements and is provided in the first well 41. The anode region 2A is connected to the node shown as DA in FIG. 4 via a contact (not shown). That is, the anode region 2A is connected to the first terminal T1.

[0036] The second gate region 22 is an impurity diffusion region doped with P-type impurity elements and is provided in the second well 42. The second gate region 22 is connected to the node shown as D2 in FIG. 4 via a contact (not shown). That is, the second gate region 22 is connected to the second terminal T2 via the aforementioned second resistor R2.

[0037] The cathode region 2C is an impurity diffusion region doped with N-type impurity elements and is provided in the second well 42. The cathode region 2C is connected to the node shown as DC in FIG. 4 via a contact (not shown). That is, the cathode region 2C is connected to the second terminal T2.

[0038] Here, a configuration including a P-type anode region 2A, an N-type first well 41, and a P-type second well 42 can be regarded as a PNP bipolar transistor, that is, transistor Q1, with the anode region 2A as the emitter, the first well 41 as the base, and the second well 42 as the collector. Also, a configuration including the N-type first well 41, the P-type second well 42, and the N-type cathode region 2C can be regarded as an NPN bipolar transistor, that is, transistor Q2, with the cathode region 2C as the emitter, the second well 42 as the base, and the first well 41 as the collector. Thus, the anode region 2A, the first well 41, the second well 42, and the cathode region 2C shown in the cross-sectional schematic diagram shown in FIG. 5(A) function as a thyristor TH as a PNPN thyristor.

[0039] Note that the region shown at B9 in FIG. 5(A) is an impurity diffusion region doped with a P-type impurity element and is provided on the P-type well shown at B8. Also, in the plan view of FIG. 5(B), the ring-shaped region shown at C9 corresponds to the region shown at B9 in FIG. 5(A).

[0040] Also, the breakdown voltage of the thyristor TH depends on the space between the first well 41 and the second well 42, as shown at BA in FIG. 5(A). For example, increasing the space between the well 41 and the second well 42 can increase the breakdown voltage of the thyristor TH.

[0041] FIG. 6(A) is a schematic cross-sectional view of the aforementioned P-type DMOS, and FIG. 6(B) is also a schematic cross-sectional view of the aforementioned P-type DMOS. B10 in FIG. 6(A) is the underlying substrate and corresponds to the region shown by the dotted line frame of C10 in FIG. 6(B). In FIG. 6(A), a P-type well shown as B11 and an N-type well shown as B12 are formed on the underlying substrate shown as B10. Also, in FIG. 6(B), the ring-shaped region between the dotted line frames of C10 and C11 corresponds to the region of the P-type well shown as B11 in FIG. 6(A). Further, in FIG. 6(B), the region of the dotted line frame of C12 corresponds to the region of the N-type well shown as B12 in FIG. 6(A). Then, an N-type well shown as B13 in FIG. 6(A) is formed, and a P-type well shown as B18 is formed. In FIG. 6(B), the region of the dotted line frame of C11 corresponds to the region of the N-type well shown as B13 in FIG. 6(A). Also, in FIG. 6(B), the ring-shaped region between the dotted line frames of C10 and C11 corresponds to the region of the P-type well shown as B18 in FIG. 6(A). And in FIG. 6(A), an N-type well shown as B14 and a P-type well shown as B15 are provided in the N-type well shown as B13. In FIG. 6(B), the ring-shaped region between the dotted line frames of C12 and C14 corresponds to the region of the N-type well shown as B14 in FIG. 6(A). Also, in FIG. 6(B), the region of the dotted line frame of C15 corresponds to the region of the P-type well shown as B15 in FIG. 6(A).

[0042] After the N-type well shown as B14, the P-type well shown as B15, and the P-type well shown as B18 are formed and planarized, a layer of the pattern of the N-type impurity diffusion region and a layer of the pattern of the P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown as B16-1 in FIG. 6(A). The pattern of the P-type impurity diffusion region includes the pattern of the region shown as B16-2 in FIG. 6(A), the pattern of the region shown as B17, and the pattern of the region shown as B19.

[0043] The N-type impurity diffusion region shown as B16-1 in FIG. 6(A) is formed in a ring shape surrounding the regions shown as C16-2 and C17, as shown as C16-1 in FIG. 6(B). Also, the P-type impurity diffusion region shown as B16-2 in FIG. 6(A) corresponds to the region shown as B16-2 in the plan view of FIG. 6(B), and the P-type impurity diffusion region shown as B17 in FIG. 6(A) corresponds to the region shown as C17 in the plan view of FIG. 6(B). Note that the P-type impurity diffusion region shown as B19 in FIG. 6(A) corresponds to the ring-shaped region shown as C19 in the plan view of FIG. 6(B). And in FIG. 16(A), the N-type diffusion region shown as B16-1 is a region for setting the potential of the substrate, the P-type diffusion region shown as B16-2 is connected to the source node, and the P-type diffusion region shown as B17 is connected to the drain node.

[0044] Comparing FIGS. 5 and 6, the regions shown as B0, B1, B2, B3, B8 in FIG. 5(A) are common to the regions shown as B10, B11, B12, B13, B18 in FIG. 6(A), the region related to the first well 41 in FIG. 5(A) is common to the region related to B14 in FIG. 6(A), and the region related to the second well 42 in FIG. 5(A) is common to the region related to B15 in FIG. 6(A). That is, in the thyristor TH in the present embodiment, the regions shown as B0, B1, B2, B3, B8 in FIG. 5(A), the region related to the first well 41, and the region related to the second well 42 are formed by the same manufacturing process as the P-type DMOS shown in FIG. 6(A).

[0045] In addition, the pattern formation process for the first gate region 21 and the cathode region 2C in FIG. 5(A) is common to the pattern formation process and manufacturing process of the N-type impurity diffusion region shown in B16-1 of FIG. 6(A). In other words, the N-type diffusion region that functions as the first gate region 21 and the cathode region 2C of the thyristor TH shown in FIG. 5(A) is formed by the same manufacturing process as the N-type diffusion region of the substrate of the P-type DMOS shown in FIG. 6(A). Similarly, the pattern formation process for the second gate region 22 and the anode region 2A in FIG. 5(A) is common to the pattern formation process and manufacturing process of the P-type impurity diffusion region shown in B16-2 and B17 of FIG. 6(A). In other words, the second gate region 22 and the anode region 2A of the thyristor TH shown in FIG. 5(A) are formed by the same manufacturing process as the N-type diffusion regions of the source and drain of the P-type DMOS shown in FIG. 6(A). Thus, the thyristor TH of this embodiment can be manufactured by a process common to that of the P-type DMOS. Note that, as will be described later, elements other than the thyristor TH included in the circuit device 10 of this embodiment can also be manufactured by a process common to that of the P-type DMOS.

[0046] From the above, the circuit device 10 of this embodiment includes a first terminal T1, a second terminal T2, a thyristor circuit 20, a voltage holding circuit 30, a trigger transistor TT, a predetermined capacitor CS, and a predetermined resistor RS. The thyristor circuit 20 is provided between the first terminal T1 and a node NA which is a first node. The voltage holding circuit 30 is provided between the first node, i.e., the node NA, and the second terminal T2. The trigger transistor TT supplies a trigger current to the thyristor circuit 20. The predetermined capacitor CS is provided between the first terminal T1 and the gate of the trigger transistor TT. The predetermined resistor RS is provided between the gate of the trigger transistor TT and the second terminal T2.

[0047] As described above, since the circuit device 10 of the present embodiment includes the first terminal T1, the second terminal T2, the thyristor circuit 20, the trigger transistor TT, the predetermined capacitor CS, and the predetermined resistor RS, it can be used as an electrostatic protection circuit including a trigger circuit that supplies a trigger current to the thyristor circuit 20. Further, since the thyristor circuit 20 and the voltage hold circuit 30 are provided in series between the first terminal T1 and the second terminal T2, the hold voltage between the power supply line including the first terminal T1 and the power supply line including the second terminal T2 can be set to a desired voltage. Thereby, an electrostatic protection circuit can be constructed in which the voltage range for driving the internal circuit between the first terminal T1 and the second terminal T2 is wide and the manufacturing process can be shared. In the circuit device of Patent Document 1, since a CMOS with a high gate breakdown voltage is required, it is difficult to share the gate film thickness with other devices. However, since the circuit device 10 of the present embodiment does not require a transistor with a high gate breakdown voltage, the manufacturing process can be shared and an increase in manufacturing cost can be prevented.

[0048] Also, in the circuit device 10 of the present embodiment, the trigger transistor TT may be a transistor having a DMOS structure. By doing so, the trigger transistor TT can be included in the circuit device 10 driven at a high voltage. As described above, in the present embodiment, the DMOS as the trigger transistor TT needs to have a high breakdown voltage between the source and the drain, but the breakdown voltage between the gate and the source can be made common with other transistors. Thereby, in the circuit device 10 driven at a high voltage, the manufacturing processes of the DMOS and other elements can be shared. Thereby, an increase in the manufacturing cost of the semiconductor device driven at a high voltage can be prevented.

[0049] In the circuit device 10 of the present embodiment, the trigger transistor TT is a transistor having a DMOS structure of the first conductivity type or a transistor having a DMOS structure of the second conductivity type, and the anode region 2A of the thyristor circuit 20, the source region and the drain region of the DMOS structure of the second conductivity type may be the same layer of the second conductivity type impurity diffusion region. By doing so, the anode region 2A can be formed together with the DMOS of the second conductivity type.

[0050] In the circuit device 10 of the present embodiment, the cathode region 2C of the thyristor circuit 20 and the region for setting the potential of the substrate of the transistor having a DMOS structure of the second conductivity type may be the same first conductivity type impurity diffusion region. By doing so, the cathode region 2C can be formed together with the DMOS of the second conductivity type.

[0051] In the circuit device 10 of the present embodiment, the first terminal T1 may be one of the power supply terminals on the high potential side and the power supply terminals on the low potential side, and the second terminal T2 may be the other of the power supply terminals on the high potential side and the power supply terminals on the low potential side. By doing so, the thyristor circuit 20 and the voltage hold circuit 30 can be arranged between the power supply terminal on the high potential side and the power supply terminal on the low potential side.

[0052] Also, in the circuit device 10 of the present embodiment, the thyristor circuit 20 may include an anode region 2A of a second conductivity type, a cathode region 2C of a first conductivity type, a first gate region 21 of a first conductivity type, and a second gate region 22 of a second conductivity type. Further, the anode region 2A of the second conductivity type may be provided in the first well 41 of the first conductivity type and electrically connected to the first terminal T1. Also, the cathode region 2C of the first conductivity type may be provided in the second well 42 of the second conductivity type and electrically connected to the second terminal T2. Also, the first gate region 21 of the first conductivity type may be provided in the first well 41 and electrically connected to the first terminal T1 via a first resistor R1 having one end on the first terminal T1 side. Also, the second gate region 22 of the second conductivity type may be provided in the second well 42 and electrically connected to the second terminal T2 via a second resistor R2. Also, the trigger transistor TT may be provided between the other end of the first resistor R1 of the thyristor circuit 20 and the second terminal T2. Thus, since the thyristor circuit 20 of the present embodiment includes the above-described first gate region 21, second gate region 22, anode region 2A, and cathode region 2C, it can function as a thyristor TH. Also, since the trigger transistor TT is provided between the other end of the first resistor R1 and the second terminal T2, when the trigger transistor TT is turned on, current can flow through the first gate. As a result, the transistor (transistor Q1) related to the first gate is turned on, and the transistor (transistor Q2) related to the second gate can be turned on. Thereby, the thyristor TH can be turned on.

[0053] FIG. 7 shows an example of an element that can be adopted as the hold element of the present embodiment. The element shown in D10 is an SGPMOS when the node shown in D11 is the high-potential side node and the node shown in D12 is the low-potential side node, which is the same as the first hold element 31, the second hold element 32, and the third hold element 33 in FIG. 1. The element shown in D20 is a PNP bipolar transistor when the node shown in D21 is the high-potential side node and the node shown in D22 is the low-potential side node. The element shown in D30 is a GGNMOS (Grounded Gate N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor) when the node shown in D31 is the high-potential side node and the node shown in D32 is the low-potential side node. The element shown in D40 is an NPN bipolar transistor when the node shown in D41 is the high-potential side node and the node shown in D42 is the low-potential side node. The element shown in D50 is a forward diode when the node shown in D51 is the high-potential side node and the node shown in D52 is the low-potential side node. The element shown in D60 is a reverse diode when the node shown in D61 is the high-potential side node and the node shown in D62 is the low-potential side node.

[0054] Also, the elements shown in D10, D20, D30, D40, D50, and D60 may be mixed in the voltage hold circuit 30. If the hold voltages of the elements shown in D10, D20, D30, D40, D50, and D60 are different, any hold voltage can be set by appropriately combining them.

[0055] Also, for the elements shown in D10, D20, D30, D40, D50, and D60, the methods described above with reference to FIGS. 5 and 6 may also be applied. FIG. 8(A) is a cross-sectional schematic diagram of a PMOS when the method of this embodiment is applied, and FIG. 8(B) is a plan schematic diagram of a PMOS when the method of this embodiment is applied. B20 in FIG. 8(A) is the underlying substrate and corresponds to the region shown by the dotted line frame of C20 in FIG. 8(B). In FIG. 8(A), a P-type well shown by B21 and an N-type well shown by B22 are formed on the underlying substrate shown by B20. Also, in FIG. 8(B), the ring-shaped region between the dotted line frames of C20 and C21 corresponds to the region of the P-type well shown by B21 in FIG. 8(A). Further, in FIG. 8(B), the region of the dotted line frame of C22 corresponds to the region of the N-type well shown by B22 in FIG. 8(A). Then, an N-type well shown by B23 in FIG. 8(A) is formed, and a P-type well shown by B28 is formed. In FIG. 8(B), the region of the dotted line frame of C21 corresponds to the region of the N-type well shown by B23 in FIG. 8(A). Also, in FIG. 8(B), the ring-shaped region between the dotted line frames of C20 and C21 corresponds to the region of the P-type well shown by B28 in FIG. 8(A). Then, in FIG. 8(A), an N-type well shown by B24 is provided in the N-type well shown by B23. In FIG. 8(B), the region of the dotted line frame of C22 corresponds to the region of the N-type well shown by B24 in FIG. 8(A).

[0056] An N-type well shown by B24 and a P-type well shown by B18 are formed and, after planarization, a layer of a pattern of an N-type impurity diffusion region and a layer of a pattern of a P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown by B26 in FIG. 8(A). The pattern of the P-type impurity diffusion region includes the patterns of the regions shown by B27-1, B27-2, and B29 in FIG. 8(A).

[0057] The N-type impurity diffusion region shown at B26 in FIG. 8(A) is formed in a ring shape surrounding the region shown at C27-1 and the region shown at C27-2 as shown at C26 in the plan view of FIG. 8(B). Also, the P-type impurity diffusion region shown at B27-1 in FIG. 8(A) corresponds to the region shown at C27-1 in the plan view of FIG. 8(B), and the P-type impurity diffusion region shown at B27-1 in FIG. 8(A) corresponds to the region shown at C27-1 in the plan view of FIG. 8(B). Note that the P-type impurity diffusion region shown at B29 in FIG. 8(A) corresponds to the ring-shaped region shown at C29 in the plan view of FIG. 8(B).

[0058] In FIG. 8(A), the N-type impurity diffusion region shown at B26 is connected to the node of the substrate, the P-type impurity diffusion region shown at B27-1 is connected to the node of the source, and the P-type impurity diffusion region shown at B27-2 is connected to the node of the drain, thereby functioning as a PMOS.

[0059] Comparing FIG. 8 with the aforementioned FIG. 6, the regions shown at B20, B21, B22, B23, B24, B28 in FIG. 8(A) are common to the regions shown at B10, B11, B12, B13, B24, B28 in FIG. 6(A). Also, the pattern formation process of the N-type impurity diffusion region shown at B26 in FIG. 8(A) has the same manufacturing process as the pattern formation process of the N-type impurity diffusion region shown at B16-1 in FIG. 6(A). Similarly, the pattern formation processes of the N-type impurity diffusion regions shown at B27-1, B27-2, B29 in FIG. 8(A) have the same manufacturing processes as the pattern formation processes of the P-type impurity diffusion regions shown at B16-2, B17, B29 in FIG. 6(A). That is, the SGPMOS shown at D10 in FIG. 7 can be manufactured by the same process as the P-type DMOS in FIG. 6.

[0060] FIG. 9(A) is a cross-sectional schematic view of a PNP bipolar transistor when the method of the present embodiment is applied, and FIG. 9(B) is a plan schematic view of the PNP bipolar transistor when the method of the present embodiment is applied. B30 in FIG. 9(A) is a lower base plate and corresponds to the region shown by the dotted line frame of C30 in FIG. 9(B). In FIG. 9(A), a P-type well shown by B31 and an N-type well shown by B32 are formed on the lower base plate shown by B30. Further, in FIG. 9(B), the ring-shaped region between the dotted line frames of C30 and C31 corresponds to the region of the P-type well shown by B31 in FIG. 9(A). Further, in FIG. 9(B), the region of the dotted line frame of C32 corresponds to the region of the N-type well shown by B32 in FIG. 9(A). Then, an N-type well shown by B33 in FIG. 9(A) is formed, and a P-type well shown by B38 is formed. In FIG. 9(B), the region of the dotted line frame of C31 corresponds to the region of the N-type well shown by B33 in FIG. 9(A). Further, in FIG. 9(B), the ring-shaped region between the dotted line frames of C30 and C31 corresponds to the region of the P-type well shown by B38 in FIG. 9(A). Then, in FIG. 9(A), an N-type well shown by B34 is provided in the N-type well shown by B33. In FIG. 9(B), the region of the dotted line frame of C32 corresponds to the region of the N-type well shown by B34 in FIG. 9(A).

[0061] After the N-type well shown by B34 and the P-type well shown by B38 are formed and planarized, a layer of a pattern of an N-type impurity diffusion region and a layer of a pattern of a P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown by B36 in FIG. 9(A). The pattern of the P-type impurity diffusion region includes the patterns of the regions shown by B37-1, B37-2, and B39 in FIG. 9(A).

[0062] The N-type impurity diffusion region shown at B36 in Fig. 9(A) is formed in a ring shape surrounding the regions shown at C37-1 and C37-2 as shown at C36 in the plan view of Fig. 9(B). Also, the P-type impurity diffusion region shown at B37-1 in Fig. 9(A) corresponds to the region shown at C37-1 in the plan view of Fig. 9(B), and the P-type impurity diffusion region shown at B27-1 in Fig. 9(A) corresponds to the region shown at C37-1 in the plan view of Fig. 9(B). Note that the P-type impurity diffusion region shown at B39 in Fig. 9(A) corresponds to the ring-shaped region shown at C39 in the plan view of Fig. 9(B).

[0063] In Fig. 9(A), the N-type impurity diffusion region shown at B36 is connected to the base node, the P-type impurity diffusion region shown at B37-1 is connected to the emitter node, and the P-type impurity diffusion region shown at B37-2 is connected to the collector node, thereby functioning as a PNP bipolar transistor.

[0064] Comparing Fig. 9 with the aforementioned Fig. 6, the regions shown at B30, B31, B32, B33, B34, B38 in Fig. 9(A) are common to the regions shown at B10, B11, B12, B13, B24, B28 in Fig. 6(A). Also, the pattern formation process of the N-type impurity diffusion region shown at B36 in Fig. 9(A) has the same manufacturing process as the pattern formation process of the N-type impurity diffusion region shown at B16-1 in Fig. 6(A). Similarly, the pattern formation processes of the N-type impurity diffusion regions shown at B37-1, B37-2, B39 in Fig. 9(A) have the same manufacturing processes as the pattern formation processes of the P-type impurity diffusion regions shown at B16-2, B17, B29 in Fig. 6(A). That is, the SGPMOS shown at D20 in Fig. 7 can be manufactured by the same process as the P-type DMOS in Fig. 6.

[0065] FIG. 10(A) is a schematic cross-sectional view of a diode when the method of this embodiment is applied, and FIG. 10(B) is a schematic plan view of the diode when the method of this embodiment is applied. B40 in FIG. 10(A) is a lower base plate, which corresponds to the region indicated by the dotted line frame of C40 in FIG. 10(B). In FIG. 10(A), a P-type well shown as B41 and an N-type well shown as B42 are formed on the lower base plate shown as B40. Further, in FIG. 10(B), the ring-shaped region between the dotted line frames of C40 and C41 corresponds to the region of the P-type well shown as B41 in FIG. 10(A). Also, in FIG. 10(B), the region of the dotted line frame of C42 corresponds to the region of the N-type well shown as B42 in FIG. 10(A). Then, an N-type well shown as B43 in FIG. 10(A) is formed, and a P-type well shown as B48 is formed. In FIG. 10(B), the region of the dotted line frame of C41 corresponds to the region of the N-type well shown as B43 in FIG. 10(A). Also, in FIG. 10(B), the ring-shaped region between the dotted line frames of C40 and C41 corresponds to the region of the P-type well shown as B48 in FIG. 10(A). Then, in FIG. 10(A), an N-type well shown as B44 is provided in the N-type well shown as B43. In FIG. 10(B), the region of the dotted line frame of C42 corresponds to the region of the N-type well shown as B44 in FIG. 10(A).

[0066] After the N-type well shown as B44 and the P-type well shown as B48 are formed and planarized, a layer of a pattern of an N-type impurity diffusion region and a layer of a pattern of a P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown as B46 in FIG. 10(A). The pattern of the P-type impurity diffusion region includes the pattern of the region shown as B47 in FIG. 10(A) and the pattern of the region shown as B39 in FIG. 10(A).

[0067] The N-type impurity diffusion region shown at B46 in Fig. 10(A) is formed in a ring shape surrounding the region shown at C47, as shown at C46 in the plan view of Fig. 10(B). Also, the P-type impurity diffusion region shown at B47 in Fig. 10(A) corresponds to the region shown at C47 in the plan view of Fig. 10(B), and the P-type impurity diffusion region shown at B49 in Fig. 10(A) corresponds to the ring-shaped region shown at C49 in the plan view of Fig. 10(B).

[0068] The N-type impurity diffusion region shown at B46 in Fig. 10(A) is connected to the cathode node, and the P-type impurity diffusion region shown at B47 is connected to the anode region. Thereby, it functions as a diode.

[0069] When comparing Fig. 10 with Fig. 6, the regions shown at B40, B41, B42, B43, B44, B48 in Fig. 10(A) are common to the regions shown at B10, B11, B12, B13, B24, B28 in Fig. 6(A). Also, the pattern formation process of the N-type impurity diffusion region shown at B46 in Fig. 10(A) has the same manufacturing process as the pattern formation process of the N-type impurity diffusion region shown at B16-1 in Fig. 6(A). Similarly, the pattern formation process of the N-type impurity diffusion region shown at B47 in Fig. 10(A) has the same manufacturing process as the pattern formation processes of the P-type impurity diffusion regions shown at B16-2, B17, B29 in Fig. 6(A). That is, the diodes shown at D50, D60 in Fig. 10 can be manufactured by the same process as the P-type DMOS in Fig. 6. Note that the diode shown at A0 in Fig. 1 can also be manufactured by the same process as the P-type DMOS in Fig. 6.

[0070] FIG. 11(A) is a cross-sectional schematic view of an NMOS when the method of this embodiment is applied, and FIG. 11(B) is a plan schematic view of the NMOS when the method of this embodiment is applied. B50 in FIG. 11(A) is the underlying substrate and corresponds to the region shown by the dotted line frame of C50 in FIG. 11(B). In FIG. 11(A), a P-type well shown by B51 and an N-type well shown by B52 are formed on the underlying substrate shown by B50. Also, in FIG. 11(B), the ring-shaped region between the dotted line frames of C50 and C51 corresponds to the region of the P-type well shown by B51 in FIG. 11(A). Also, in FIG. 11(B), the region of the dotted line frame of C52 corresponds to the region of the N-type well shown by B52 in FIG. 11(A). Then, an N-type well shown by B53 in FIG. 11(A) is formed, and a P-type well shown by B58 is formed. In FIG. 11(B), the region of the dotted line frame of C51 corresponds to the region of the N-type well shown by B53 in FIG. 11(A). Also, in FIG. 11(B), the ring-shaped region between the dotted line frames of C50 and C51 corresponds to the region of the P-type well shown by B58 in FIG. 11(A). And in FIG. 11(A), an N-type well shown by B54 and a P-type well shown by B55 are provided in the N-type well shown by B53. In FIG. 11(B), the ring-shaped region between the dotted line frames of C52 and C54 corresponds to the region of the N-type well shown by B54 in FIG. 11(A). Also, in FIG. 11(B), the region of the dotted line frame of C55 corresponds to the region of the P-type well shown by B55 in FIG. 11(A).

[0071] In FIG. 11(A), after the N-type well shown by B54, the P-type well shown by B55, and the P-type well shown by B58 are formed and planarized, a layer of the pattern of the N-type impurity diffusion region and a layer of the pattern of the P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown by B56-1 in FIG. 11(A), the pattern of the region shown by B56-2, and the pattern of the region shown by B53-1. The pattern of the P-type impurity diffusion region includes the pattern of the region shown by B57 in FIG. 11(A) and the pattern of the region shown by B59.

[0072] The N-type impurity diffusion regions shown as B56-1, B56-2, and B56-3 in Fig. 11(A) are formed in a ring shape surrounding the regions shown as C56-2, C56-3, and C57, as shown by C56-1 in the plan view of Fig. 11(B). Also, the P-type impurity diffusion region shown as B57 in Fig. 11(A) is formed in a ring shape surrounding the regions shown as C56-2 and C56-3, as shown by C57 in the plan view of Fig. 6(B). Note that the P-type impurity diffusion region shown as B59 in Fig. 11(A) corresponds to the region provided in a ring shape shown as C59 in the plan view of Fig. 11(B).

[0073] In Fig. 11(A), the P-type impurity diffusion region shown as B57 is connected to the node of the substrate, the N-type impurity diffusion region shown as B56-2 is connected to the node of the source, and the N-type impurity diffusion region shown as B56-3 is connected to the node of the drain, thereby functioning as an NMOS.

[0074] Comparing Fig. 11 with Fig. 6, the regions shown as B50, B51, B52, B53, B54, B55, and B58 in Fig. 11(A) are common to the regions shown as B10, B11, B12, B13, B14, B15, and B18 in Fig. 6(A). Also, the pattern formation process of the N-type impurity diffusion regions shown as B56-1, B56-2, and B56-3 in Fig. 11(A) has the same manufacturing process as the pattern formation process of the N-type impurity diffusion region shown as B16-1 in Fig. 6(A). Similarly, the pattern formation process of the N-type impurity diffusion regions shown as B57 and B59 in Fig. 11(A) has the same manufacturing process as the pattern formation process of the P-type impurity diffusion regions shown as B16-2, B17, and B19 in Fig. 6(A). That is, the NMOS shown as D30 in Fig. 7 can be manufactured by the same process as the P-type DMOS in Fig. 6.

[0075] FIG. 12(A) is a cross-sectional schematic view of an NPN bipolar transistor when the method of the present embodiment is applied, and FIG. 12(B) is a plan schematic view of the NPN bipolar transistor when the method of the present embodiment is applied. B60 in FIG. 12(A) is a lower base plate and corresponds to the region shown by the dotted line frame of C60 in FIG. 12(B). In FIG. 12(A), a P-type well shown by B61 and an N-type well shown by B62 are formed on the lower base plate shown by B60. Further, in FIG. 12(B), the ring-shaped region between the dotted line frames of C60 and C61 corresponds to the region of the P-type well shown by B61 in FIG. 12(A). Also, in FIG. 12(B), the region of the dotted line frame of C62 corresponds to the region of the N-type well shown by B62 in FIG. 12(A). Then, an N-type well shown by B63 in FIG. 12(A) is formed, and a P-type well shown by B68 is formed. In FIG. 12(B), the region of the dotted line frame of C61 corresponds to the region of the N-type well shown by B63 in FIG. 12(A). Also, in FIG. 12(B), the ring-shaped region between the dotted line frames of C60 and C61 corresponds to the region of the P-type well shown by B68 in FIG. 12(A). And in FIG. 12(A), an N-type well shown by B64 and a P-type well shown by B65 are provided in the N-type well shown by B63. In FIG. 12(B), the ring-shaped region between the dotted line frames of C62 and C64 corresponds to the region of the N-type well shown by B64 in FIG. 12(A). Also, in FIG. 12(B), the region of the dotted line frame of C65 corresponds to the region of the P-type well shown by B65 in FIG. 12(A).

[0076] In FIG. 12(A), after the N-type well shown by B64, the P-type well shown by B65, and the P-type well shown by B68 are formed and flattened, a layer of a pattern of an N-type impurity diffusion region and a layer of a pattern of a P-type impurity diffusion region are formed. The pattern of the N-type impurity diffusion region includes the pattern of the region shown by B66-1 in FIG. 12(A), the pattern of the region shown by B66-2, and the pattern of the region shown by B63-1. The pattern of the P-type impurity diffusion region includes the pattern of the region shown by B67 in FIG. 12(A) and the pattern of the region shown by B69.

[0077] The N-type impurity diffusion region shown as B66-1 in Fig. 12(A) is formed in a ring shape surrounding the regions shown as C66-2, C66-3, and C67, as shown as C66-1 in the plan view of Fig. 11(B). Also, the P-type impurity diffusion region shown as B67 in Fig. 12(A) is formed in a ring shape surrounding the regions shown as C66-2 and C66-3, as shown as C67 in the plan view of Fig. 12(B). Note that the P-type impurity diffusion region shown as B69 in Fig. 11(A) corresponds to the ring-shaped region shown as C69 in the plan view of Fig. 11(B).

[0078] In Fig. 12(A), the P-type impurity diffusion region shown as B67 is connected to the node of the substrate, the N-type impurity diffusion region shown as B66-2 is connected to the node of the source, and the N-type impurity diffusion region shown as B66-3 is connected to the node of the drain, thereby functioning as an NPN bipolar transistor.

[0079] Comparing Fig. 12 with Fig. 6, the regions shown as B60, B61, B62, B63, B64, B65, B68 in Fig. 12(A) are common to the regions shown as B10, B11, B12, B13, B14, B15, B18 in Fig. 6(A). Also, the pattern formation process of the N-type impurity diffusion regions shown as B66-1, B66-2, B66-3 in Fig. 12(A) has the same manufacturing process as the pattern formation process of the N-type impurity diffusion region shown as B16-1 in Fig. 6(A). Similarly, the pattern formation process of the N-type impurity diffusion regions shown as B67, B69 in Fig. 12(A) has the same manufacturing process as the pattern formation process of the P-type impurity diffusion regions shown as B16-2, B17, B19 in Fig. 6(A). That is, the NPN bipolar transistor shown as D40 in Fig. 7 can be manufactured by the same process as the P-type DMOS in Fig. 6.

[0080] Also, regarding the predetermined capacitor CS in FIG. 1, similarly, the manufacturing process can be shared. FIG. 13(A) is a schematic cross-sectional view of the predetermined capacitor CS of the present embodiment, FIG. 13(B) is a plan view of the E2-E2 plane of FIG. 13(A), and FIG. 13(C) is a plan view of the E3-E3 plane of FIG. 13(A). Note that the layer shown at E1 in FIG. 13(A) is a layer schematically showing a wiring layer formed by a back-end process, and for convenience of explanation, an insulating layer and the like are appropriately omitted. The insulating layer is formed of an oxide film such as silicon oxide. The regions shown as B80, B81, B82, B83, B84, B85, B86, B87, B88, and B89 in FIG. 13 are pattern regions of the wiring layer. In the present embodiment, the wiring layer related to the wiring regions shown as B80, B81, B82, B83, and B84 is referred to as the first metal layer, and the wiring layer related to the wiring regions shown as B85, B86, B87, B88, and B89 is referred to as the second metal layer.

[0081] In FIG. 13(A), the layer shown as B70 is a layer of the underlying substrate, the layer shown as B71 is a layer composed of a P-well region similar to B11 in FIG. 6(A), and the layer shown as B78 is a layer composed of a P-well region similar to B18 in FIG. 6(A). That is, the front-end process in the manufacture of the predetermined capacitor CS in FIG. 1 includes, among the front-end processes of the P-type DMOS and FIG. 6, the step of forming the P-well region of B11 and the step of forming the P-well region of B11. Thereby, the front-end process of the predetermined capacitor CS can be shared with the front-end process of the P-type DMOS.

[0082] In a plan view of FIG. 13(B), as shown at C80, C81, C82, C83, and C84, a wiring layer patterned in a comb shape and, in a plan view of FIG. 13(C), as shown at C85, C86, C87, C88, and C89, a wiring layer patterned in a comb shape face each other to form a capacitor. Note that the wirings shown at C80, C81, C82, C83, and C84 in FIG. 13(B) respectively correspond to the wirings shown at B80, B81, B82, B83, and B84 in a cross-sectional view of FIG. 13(A). Similarly, the wirings shown at C85, C86, C87, C88, and C89 in FIG. 13(C) respectively correspond to the wirings shown at B85, B86, B87, B88, and B89 in a cross-sectional view of FIG. 13(A). In the present embodiment, the wiring layer shown in FIG. 13(B) will be referred to as the first electrode, and the wiring layer shown in FIG. 13(C) will be referred to as the second electrode.

[0083] From the above, the predetermined capacitor CS of the present embodiment constitutes a MOM (Metal oxide Metal) capacitor. Thus, in the circuit device 10 of the present embodiment, the predetermined capacitor CS is a MOM capacitor. By doing so, the manufacturing process of the predetermined capacitor CS and the manufacturing process of other transistors can be shared. Further, in the circuit device 10 of the present embodiment, the MOM capacitor is provided in a first metal layer and includes a first electrode in a comb shape in a plan view and a second electrode provided in a second metal layer, facing the first electrode and in a comb shape in a plan view. By doing so, it is possible to increase the capacitance of the predetermined capacitor CS while preventing an increase in the chip area related to the predetermined capacitor CS.

[0084] Also, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 14. FIG. 14 is different from the configuration example of FIG. 1 in that it further includes a gate protection circuit 50 that protects the gate of the trigger transistor TT. Specifically, for example, in FIG. 14, the gate protection circuit 50 is disposed between the node NG1 and the second terminal T2. In other words, the gate protection circuit 50 is provided between the gate of the trigger transistor TT and the second terminal T2. When the trigger transistor TT is the DMOS described above, since the breakdown voltage between the gate and source of the DMOS is configured to be lower than the breakdown voltage between the source and drain, when an ESD surge is applied to the first terminal T1, if the potential of the node NB suddenly increases, the gate of the trigger transistor TT may be damaged. In that regard, by applying the method of the present embodiment, the gate of the trigger transistor TT can be protected from overvoltage, so that the circuit device 10 can function properly.

[0085] In FIG. 14, an SGPMOS is illustrated as an element constituting the gate protection circuit 50. However, it may be a PNP bipolar transistor shown by D20 in FIG. 7, a GGNMOS shown by D30, an NPN bipolar transistor shown by D40, a reverse diode shown by D50, or the like. Specifically, it may be appropriately determined based on the breakdown voltage between the gate and source of the trigger transistor TT and the like, and the voltage to be clamped. In this way, the circuit device 10 of the present embodiment includes a gate protection circuit 50 provided between the gate of the trigger transistor TT and the second terminal T2. By doing so, in addition to the above-described effects, the gate-source interval of the trigger transistor TT can be protected from overvoltage.

[0086] Alternatively, for example, by configuring the circuit device 10 of the present embodiment as in the configuration examples shown in FIGS. 15 and 16, the gate of the trigger transistor TT may be protected from overvoltage using the holding element of the voltage holding circuit 30. In this case, the gate of the trigger transistor TT may be connected to the connection node between the n-th holding element and the n+1-th holding element. Specifically, for example, in the case of FIG. 15, since the node NG2 connected to the gate of the trigger transistor TT is connected to the node NJ2 which is the connection node between the second holding element 32 and the third holding element 33, n = 2. When the third holding element 33 is the aforementioned SGPMOS, since the breakdown voltage is 8V, the gate of the trigger transistor TT is clamped at a voltage of 8V and protected. Also, for example, in the case of FIG. 16, since the node NG2 is connected to the node NJ1 which is the connection node between the first holding element 31 and the second holding element 32, n = 1. When the second holding element 32 and the third holding element 33 are the aforementioned SGPMOS, the gate of the trigger transistor TT is clamped at a voltage of 16V and protected. In this way, by connecting the gate of the trigger transistor TT to the connection node between the n-th holding element and the n+1-th holding element and appropriately determining the holding element such as the n+1-th holding element, the gate-source interval of the trigger transistor TT can be clamped at a desired voltage and protected.

[0087] Thus, in the circuit device 10 of the present embodiment, the voltage holding circuit 30 includes a plurality of holding elements connected in series, and the connection node between the n-th holding element and the n+1-th holding element among the plurality of holding elements is connected to the gate of the trigger transistor TT. By doing so, the gate-source interval of the trigger transistor TT can be protected from overvoltage, and an increase in the chip area related to the circuit device 10 can be prevented. In the case of the configuration example of FIG. 14, a gate protection circuit 50 is required, but in the configuration examples of FIGS. 15 and 16, the gate-source interval of the trigger transistor TT can be protected from overvoltage without using the gate protection circuit 50.

[0088] Also, for example, in the circuit device 10 of the present embodiment, the trigger transistor TT may be composed of a P-type DMOS. Specifically, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 17. In FIG. 17, the voltage hold circuit 30 includes a plurality of hold elements directly connected in the same manner as in FIG. 1, and is provided between the first terminal T1 and the node NF. Further, the thyristor circuit 20 is provided between the node NF and the node NA. The node NA is connected to the second terminal T2. That is, in FIG. 17, the point that the thyristor circuit 20 and the voltage hold circuit 30 are connected in series between the first terminal T1 and the second terminal T2 is the same as in FIG. 1, and in the circuit device 10 shown in FIG. 17, the node NF functions as the first node.

[0089] Also, in FIG. 17, the point that the trigger circuit is constituted by the trigger transistor TT, the predetermined capacitor CS, and the predetermined resistor RS is the same as in FIG. 1. In FIG. 17, one end of the predetermined resistor RS is connected to the first terminal T1, and the other end is connected to the node NB. The source of the trigger transistor TT is connected to the first terminal T1, the drain of the trigger transistor TT is connected to the node NL which is one end side node of the second resistor R2 of the thyristor circuit 20, and the gate of the trigger transistor TT is connected to the node NK. The predetermined capacitor CS is provided between the node NB and the second terminal T2.

[0090] When the circuit device 10 of FIG. 17 is operated normally, that is, when the potential of the second terminal T2 is 0V as the ground voltage and a voltage of 24V is applied to the first terminal T1, a voltage of 24V is generated between the source and gate of the trigger transistor TT. However, as described above, since the trigger transistor TT is a P-type DMOS, it will not be damaged. After the predetermined capacitor CS is charged, since the predetermined resistor RS functions as a pull-up resistor, the potential of the node NB is maintained at 24V of the first terminal T1. That is, since no potential difference occurs between the gate and source of the trigger transistor TT, the trigger transistor TT is in the off state.

[0091] FIG. 18 is a diagram for explaining the operation of the circuit device 10 when an ESD surge is applied. For example, assume that a surge voltage of 40V is applied to the first terminal T1. At this time, due to capacitive coupling, the potential of the gate is maintained at the voltage just before the ESD surge is applied. More specifically, the voltage between the source and drain of the trigger transistor TT becomes 40V, but the time constant of the RC circuit is set to be sufficiently large, and the potential of the node NB is maintained at a low level until the time constant elapses. As a result, the trigger transistor TT turns on, and a current flows as indicated by the arrow A11. Note that the arrow shown in A11 more precisely indicates the direction from the first terminal T1, the source of the trigger transistor TT, the drain of the trigger transistor TT, the node NL, the second resistor R2, the node NA, to the second terminal T2. Thereby, since a current flows through the second resistor R2, the potential of the node NE, which is the base node of the transistor Q2, becomes higher than that of the node NA, and a current flows as indicated by the arrow A12. Note that the arrow shown in A12 more precisely indicates the direction from the first terminal T1, the source of the trigger transistor TT, the drain of the trigger transistor TT, the node NL, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, to the second terminal T2. As a result, since the transistor Q2 turns on, a current flows as indicated by the arrow A13. Note that the arrow shown in A13 more precisely indicates the direction from the first terminal T1, the voltage hold circuit 30, the node NF, the first resistor R1, the node NC, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, to the second terminal T2. Thereby, a current flows through the first resistor R1, and the potential of the node NC, which is the base node of the transistor Q1, becomes lower than the potential of the node NF. As a result, a current flows as indicated by the arrow A14. Note that the arrow shown in A14 more precisely indicates the direction from the first terminal T1, the voltage hold circuit 30, the node NF, the emitter of the transistor Q1, the base of the transistor Q1, the node NC, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, to the second terminal T2. As a result, since the base current of the transistor Q1 flows, the transistor Q1 turns on.As a result, current flows as indicated by the arrow shown in A15. Note that the arrow shown in A15 more precisely indicates the direction from the first terminal T1, through the voltage holding circuit 30, the node NF, the emitter of the transistor Q1, the collector of the transistor Q1, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, to the second terminal T2. That is, the thyristor TH is turned on.

[0092] Further, the method described above with reference to FIG. 14 may be combined with the circuit device 10 of FIG. 17. That is, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 19. In FIG. 19, a gate protection circuit 50 is provided between the first terminal T1 and the node NK1. The node NK1 is a node between the predetermined resistor RS and the predetermined capacitor CS. Thereby, the gate of the trigger transistor TT is protected by the gate protection circuit 50.

[0093] Further, the method described above with reference to FIG. 15 may be combined with the circuit device 10 of FIG. 17. That is, in the circuit device 10 of the present embodiment, the gate of the trigger transistor TT may be connected to the connection node between the n-th holding element and the (n + 1)-th holding element of the voltage holding circuit 30. Specifically, for example, in FIG. 20, since the gate of the trigger transistor TT is connected to the node NJ1 which is the connection node between the first holding element 31 and the second holding element 32, n = 1.

[0094] Further, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 21. In FIG. 21, the difference from the configuration example of FIG. 17 is that a first predetermined element 61 and a second predetermined element 62 as predetermined elements are connected in series to the drain of the trigger transistor TT which is a P-type DMOS. Note that the number of the predetermined elements is not limited to two and can be determined as appropriate. Also, in FIG. 21, an SGPMOS is illustrated as the predetermined element, but other elements can be adopted in consideration of the breakdown voltage value and the like.

[0095] By using the circuit device 10 as shown in FIG. 21, the breakdown voltage of the trigger transistor TT can be reduced as compared with the circuit device 10 in FIG. 17. Specifically, for example, when the absolute maximum rated voltage between the first terminal T1 and the second terminal T2 is 40V as described above, the sum of the absolute maximum rated voltages of the trigger transistor TT, the first predetermined element 61, and the second predetermined element 62 may be 40V. That is, since the absolute maximum rated voltage of the SGPMOS is 7V as described above, the absolute maximum rated voltage between the source and drain of the trigger transistor TT may be 26V. The circuit devices 10 in FIGS. 1, 14, 15, 17, 19, and 20 are all configured such that the voltage applied between the source and drain of the trigger transistor TT is equal to the voltage applied between the first terminal T1 and the second terminal T2. In other words, the absolute maximum rated voltage between the source and drain of the trigger transistor TT according to the above-described method had to be equal to or higher than the maximum rated voltage (=40V) between the first terminal T1 and the second terminal T2. In that regard, the circuit device 10 in FIG. 21 can employ a trigger transistor TT with a reduced absolute maximum rated voltage between the source and drain.

[0096] Also, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 22. FIG. 22 shows the voltage hold circuit 30 divided into a first voltage hold circuit 301 and a second voltage hold circuit 302. The first voltage hold circuit 301 corresponds to the voltage hold circuit 30 of FIG. 21 and is provided between the first terminal T1 and the node NF. The second voltage hold circuit 302 is provided between the node NA and the second terminal T2. Similar to the voltage hold circuit 30 of FIG. 17, the first voltage hold circuit 301 of FIG. 22 has a function of increasing the hold voltage of the circuit device 10. In addition to having a function of increasing the hold voltage of the circuit device 10, the second voltage hold circuit 302 of FIG. 22 has a function of lowering the lower limit value of the absolute maximum rated voltage between the source and drain of the trigger transistor TT, similar to the predetermined element of FIG. 21. In FIG. 22, the first voltage hold circuit 301 is configured to include the first hold element 31, and the second voltage hold circuit 302 is configured to include the second hold element 32 and the third hold element 33, but the number of hold elements is not limited. Thus, the circuit device 10 of the present embodiment includes the second voltage hold circuit 302 provided between the second terminal T2 and the thyristor circuit 20. By doing so, the trigger transistor TT with a reduced breakdown voltage between the source and drain can be used in the circuit device 10.

[0097] FIG. 23 is a diagram for explaining the operation when an ESD surge is applied to the circuit device 10 shown in FIG. 22. For example, it is assumed that a surge voltage of 40 V is applied to the first terminal T1. At this time, due to capacitive coupling, the potential of the gate is maintained at the voltage immediately before the ESD surge is applied. More specifically, the voltage between the source and drain of the trigger transistor TT becomes 40 V, but the time constant of the RC circuit is set to be sufficiently large, and the potential of the node NB is maintained at a low level until the time constant elapses. As a result, the trigger transistor TT turns on, and a current flows as indicated by the arrow A21. Note that the arrow shown in A21 more accurately indicates the direction from the first terminal T1, the source of the trigger transistor TT, the drain of the trigger transistor TT, the node NL, the second resistor R2, the node NA, the second voltage holding circuit 302, to the second terminal T2. As a result, a current flows through the second resistor R2, so that the potential of the node NE, which is the base node of the transistor Q2, becomes higher than the potential of the node NA, and a current flows as indicated by the arrow A22. Note that the arrow shown in A22 more accurately indicates the direction from the first terminal T1, the source of the trigger transistor TT, the drain of the trigger transistor TT, the node NL, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, to the second terminal T2. As a result, the transistor Q2 turns on, and a current flows as indicated by the arrow A23. Note that the arrow shown in A13 more accurately indicates the direction from the first terminal T1, the first voltage holding circuit 301, the node NF, the first resistor R1, the node NC, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, to the second terminal T2. As a result, a current flows through the first resistor R1, and the potential of the node NC, which is the base node of the transistor Q1, becomes lower than the potential of the node NF. As a result, a current flows as indicated by the arrow A24.Note that the arrow shown in A24 is, more precisely, directed in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the base of the transistor Q1, the node NC, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, and the second terminal T2. As a result, the base current of the transistor Q1 flows, causing the transistor Q1 to turn on. Thereby, current flows as shown by the arrow in A25. Note that the arrow shown in A25 is, more precisely, directed in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the collector of the transistor Q1, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, and the second terminal T2. That is, the thyristor TH turns on.

[0098] Also, FIG. 22 shows an example in which the above-described method is applied when the trigger transistor TT is a P-type DMOS as shown in FIG. 17, but it may also be applied when the trigger transistor TT is an N-type DMOS. That is, the method described in FIG. 22 may be applied to the configuration example of the circuit device 10 in FIG. 1, and specifically, for example, the circuit device 10 shown in the configuration example of FIG. 24 may be used. Comparing FIG. 24 with FIG. 1, the voltage hold circuit 30 is divided into a first voltage hold circuit 301 and a second voltage hold circuit 302. The first voltage hold circuit 301 corresponds to the voltage hold circuit 30 in FIG. 1 and is provided between the node NA and the second terminal T2. The second voltage hold circuit 302 is provided between the first terminal T1 and the node NF. Similar to the voltage hold circuit 30 in FIG. 1, the first voltage hold circuit 301 in FIG. 24 has a function of raising the hold voltage of the circuit device 10. In addition to having a function of raising the hold voltage of the circuit device 10, the second voltage hold circuit 302 in FIG. 24 has a function of lowering the lower limit value of the absolute maximum rated voltage between the source and drain in the trigger transistor TT, similar to the predetermined element in FIG. 21. Thus, the circuit device 10 of the present embodiment includes a second voltage hold circuit 302 provided between the first terminal T1 and the thyristor circuit 20. By doing so, a trigger transistor TT with a reduced breakdown voltage between the source and drain can be used in the circuit device 10.

[0099] FIG. 25 is a diagram for explaining the operation when an ESD surge is applied to the circuit device 10 shown in FIG. 24. Assume that the potential of the first terminal T1 has risen to, for example, 40V. At this time, due to the capacitive coupling of the predetermined capacitor CS, the potential of the node NB rises. That is, the potential on the gate side of the trigger transistor TT rises. As a result, a potential difference is generated between the gate and source of the trigger transistor TT, so that the trigger transistor TT turns on and a current flows in the direction of the arrow shown in A31. Note that the arrow shown in A31 more accurately goes in the order of the first terminal T1, the second voltage holding circuit 302, the node NF, the first resistor R1, the node ND, the drain of the trigger transistor TT, the source of the trigger transistor TT, and the second terminal T2. Thereby, a current flows through the first resistor R1, and the potential of the node ND connected to the base of the transistor Q1 becomes lower than the potential of the node NF. Thereby, a current flows in the direction of the arrow shown in A32. Note that the arrow shown in A32 more accurately goes in the order of the first terminal T1, the second voltage holding circuit 302, the node NF, the emitter of the transistor Q1, the base of the transistor Q1, the node NC, the node ND, the drain of the trigger transistor TT, the source of the trigger transistor TT, and the second terminal T2. Thereby, since the base current of the transistor Q1 flows, the transistor Q1 becomes in an on state.

[0100] As a result, a current flows in the direction of the arrow shown by A33. Note that the arrow shown by A33 more precisely goes in the order of the first terminal T1, the second voltage hold circuit 302, the node NF, the emitter of the transistor Q1, the collector of the transistor Q1, the node NE, the second resistor R2, the node NA, the first voltage hold circuit 301, and the second terminal T2. As a result, a current flows through the second resistor R2, and the potential of the node NE connected to the base of the transistor Q2 becomes higher than the potential of the node NA. As a result, a current flows in the direction of the arrow shown by A34. Note that the arrow shown by A34 more precisely goes in the order of the first terminal T1, the second voltage hold circuit 302, the node NF, the emitter of the transistor Q1, the collector of the transistor Q1, the node NE, the emitter of the transistor Q2, the node NA, the first voltage hold circuit 301, and the second terminal T2. As a result, a base current of the transistor Q2 flows, and since the transistor Q2 is turned on, a current flows in the direction of the arrow shown by A35. Note that the arrow shown by A35 more precisely goes in the order of the first terminal T1, the first voltage hold circuit 301, the node NF, the emitter of the transistor Q1, the node NC, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, the first voltage hold circuit 301, and the second terminal T2. That is, the thyristor TH is turned on.

[0101] Also, the above is a configuration example in which a thyristor circuit 20 is supplied with a trigger current by one trigger circuit, but it may be a configuration example in which the thyristor circuit 20 is supplied with a trigger current by, for example, two trigger circuits. Specifically, for example, the circuit device 10 of the present embodiment may be configured as shown in the configuration example of FIG. 26. The circuit device 10 of FIG. 26 differs from the circuit device 10 of FIG. 24 in that it further includes a second trigger circuit. The first trigger circuit includes a first trigger transistor TT1, a first predetermined capacitor CS1, and a first predetermined resistor RS1, and corresponds to the trigger circuit of FIG. 24. The second trigger circuit includes a second trigger transistor TT2, a second predetermined capacitor CS2, and a second predetermined resistor RS2. The second trigger transistor TT2 is, for example, a P-type DMOS. The source is connected to the first terminal T1, the drain is connected to the node NL of the thyristor circuit 20, and the gate is connected to the node NB2. The second predetermined resistor RS2 is provided between the first terminal T1 and the node NB2. The second predetermined capacitor CS2 is provided between the node NB2 and the second terminal T2.

[0102] FIG. 27 is a diagram for explaining the operation when an ESD surge is applied to the circuit device 10 shown in FIG. 26. Assume that the potential of the first terminal T1 has risen to, for example, 40V. At this time, due to the capacitive coupling of the first predetermined capacitor CS1, the potential of the node NB1 rises. That is, the potential on the gate side of the first trigger transistor TT1 rises. As a result, a potential difference is generated between the gate and source of the first trigger transistor TT1, so that the first trigger transistor TT1 turns on and current flows in the direction of the arrow shown by A41. Note that the arrow shown by A41 more precisely goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the first resistor R1, the node ND, the drain of the first trigger transistor TT1, the source of the trigger transistor TT, and the second terminal T2. Also, due to the capacitive coupling of the second predetermined capacitor CS2, the potential of the node NB2 is maintained at the voltage just before the ESD surge is applied. More specifically, the voltage between the source and drain of the trigger transistor TT becomes 40V, but the time constant of the RC circuit is set to be sufficiently large, and the potential of the node NB2 is maintained at a low level until the time constant elapses. As a result, the second trigger transistor TT2 turns on and current flows as shown by the arrow of A51. Note that the arrow shown by A51 more precisely goes in the order of the first terminal T1, the source of the second trigger transistor TT2, the drain of the second trigger transistor TT2, the node NL, the second resistor R2, the node NA, the second voltage holding circuit 302, and the second terminal T2.

[0103] As a result, a current flows through the first resistor R1, and the potential of the node ND connected to the base of the transistor Q1 becomes lower than the potential of the node NF. At the same time, a current flows through the second resistor R2, and the potential of the node NE connected to the base of the transistor Q2 becomes higher than the potential of the node NA. As a result, a current flows in the direction of the arrow shown in A42 and a current also flows in the direction of the arrow shown in A52. Note that the arrow shown in A42, more precisely, goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the base of the transistor Q1, the node NC, the node ND, the drain of the first trigger transistor TT1, the source of the first trigger transistor TT1, and the second terminal T2. Also, the arrow shown in A52, more precisely, goes in the order of the first terminal T1, the source of the second trigger transistor TT2, the drain of the second trigger transistor TT2, the node NL, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, the first voltage holding circuit 301, and the second terminal T2.

[0104] As a result, a current flows in the direction of the arrow shown in A43 and a current also flows in the direction of the arrow shown in A53. Note that the arrow shown in A43, more precisely, goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the collector of the transistor Q1, the node NE, the second resistor R2, the node NA, the second voltage holding circuit 302, and the second terminal T2. Also, the arrow shown in A53, more precisely, goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the first resistor R1, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, and the second terminal T2. That is, the thyristor TH turns on.

[0105] Thus, in the circuit device 10 of FIG. 26, the operation steps from the timing when the ESD surge current flows to the timing when the thyristor TH turns on include the step of the potential of the first terminal T1 or the like rising, the step of generating the current indicated by the arrows of A41 and A51, the step of generating the current indicated by the arrows of A42 and A52, and the step of generating the current indicated by the arrows of A43 and A53. On the other hand, in the case of FIG. 1, the operation steps include the step of the potential of the first terminal T1 or the like rising, the step of generating the current indicated by the arrow of A1, the step of generating the current indicated by the arrow of A2, the step of generating the current indicated by the arrow of A3, the step of generating the current indicated by the arrow of A4, and the step of generating the current indicated by the arrow of A5. That is, in the configuration example of FIG. 1, the number of operation steps required until the thyristor TH turns on is 6, but in the configuration example of FIG. 26, the number of operation steps required until the thyristor TH turns on is 4. Thus, by configuring as in the circuit device 10 of FIG. 26, the time required from the timing when the ESD surge current flows to the timing when the thyristor TH turns on can be shortened. Thereby, the internal circuit can be more reliably protected from static electricity. Whether to configure as the circuit device 10 of FIG. 1 or as the circuit device 10 of FIG. 26 may be appropriately determined in consideration of the chip size or the like of the semiconductor device.

[0106] Also, the circuit device 10 of the present embodiment may be configured as in the configuration example shown in FIG. 28. FIG. 28 is different from FIG. 26 in that one predetermined capacitor CS drives the gates of the first trigger transistor TT1 and the second trigger transistor TT2.

[0107] FIG. 29 is a diagram for explaining the operation when an ESD surge is applied to the circuit device 10 shown in FIG. 28. Assume that the potential of the first terminal T1 has risen to, for example, 40V. At this time, due to the capacitive coupling of the predetermined capacitor CS, the potential of the node NB1 rises. That is, the potential on the gate side of the first trigger transistor TT1 rises. As a result, a potential difference is generated between the gate and source of the first trigger transistor TT1, so that the first trigger transistor TT1 turns on and current flows in the direction of the arrow shown in A61. Note that the arrow shown in A61 more precisely goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the first resistor R1, the node ND, the drain of the first trigger transistor TT1, the source of the first trigger transistor TT1, and the second terminal T2. Also, due to the capacitive coupling of the predetermined capacitor CS, the potential of the node NB2 is maintained at the voltage just before the ESD surge is applied. More specifically, the voltage between the source and drain of the second trigger transistor TT2 becomes 40V, but the time constant of the RC circuit is set to be sufficiently large, and the potential of the node NB2 is maintained at a low level until the time constant elapses. As a result, the second trigger transistor TT2 turns on and current flows as shown by the arrow in A71. Note that the arrow shown in A71 more precisely goes in the order of the first terminal T1, the source of the second trigger transistor TT2, the drain of the second trigger transistor TT2, the node NL, the second resistor R2, the node NA, the second voltage holding circuit 302, and the second terminal T2.

[0108] As a result, a current flows through the first resistor R1, and the potential of the node ND connected to the base of the transistor Q1 becomes lower than the potential of the node NF. At the same time, a current flows through the second resistor R2, and the potential of the node NE connected to the base of the transistor Q2 becomes higher than the potential of the node NA. As a result, a current flows in the direction of the arrow shown by A62 and a current flows in the direction of the arrow shown by A72. Note that the arrow shown by A62 more precisely goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the base of the transistor Q1, the node NC, the node ND, the drain of the first trigger transistor TT1, the source of the first trigger transistor TT1, and the second terminal T2. Also, the arrow shown by A72 more precisely goes in the order of the first terminal T1, the source of the second trigger transistor TT2, the drain of the second trigger transistor TT2, the node NL, the node NE, the base of the transistor Q2, the emitter of the transistor Q2, the node NA, the first voltage holding circuit 301, and the second terminal T2.

[0109] As a result, a current flows in the direction of the arrow shown by A63 and a current flows in the direction of the arrow shown by A73. Note that the arrow shown by A63 more precisely goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the emitter of the transistor Q1, the collector of the transistor Q2, the second resistor R2, the node NA, the second voltage holding circuit 302, and the second terminal T2. Also, the arrow shown by A73 more precisely goes in the order of the first terminal T1, the first voltage holding circuit 301, the node NF, the first resistor R1, the collector of the transistor Q2, the emitter of the transistor Q2, the node NA, the second voltage holding circuit 302, and the second terminal T2. That is, the thyristor TH becomes in an on state.

[0110] Thus, in the circuit device 10 of FIG. 28, the number of operation steps from the timing when the ESD surge current flows to the timing when the thyristor TH turns on is four steps, namely, the step in which the potential of the first terminal T1 etc. rises, the step in which the current indicated by the arrows of A61 and A71 occurs, the step in which the current indicated by the arrows of A62 and A62 occurs, and the step in which the current indicated by the arrows of A63 and A73 occurs, which is the same as in FIG. 26. That is, by configuring the circuit device 10 as shown in FIG. 28, in addition to being able to shorten the time required from the timing when the ESD surge current flows to the timing when the thyristor TH turns on, the number of capacitors that function as the circuit device 10 can be reduced, so that the chip area related to the circuit device 10 can be reduced.

[0111] As described above, the circuit device of the present embodiment includes a first terminal, a second terminal, a thyristor circuit, a voltage holding circuit, a trigger transistor, a predetermined capacitor, and a predetermined resistor. The thyristor circuit is provided between the first terminal and the first node. The voltage holding circuit is provided between the first node and the second terminal. The trigger transistor supplies a trigger current to the thyristor circuit. The predetermined capacitor is provided between the first terminal and the gate of the trigger transistor. The predetermined resistor is provided between the gate of the trigger transistor and the second terminal.

[0112] By doing so, an electrostatic protection circuit can be constructed in which the voltage range for driving the internal circuit between the first terminal and the second terminal is wide and the manufacturing process can be shared. Since the circuit device of the present embodiment does not require a transistor with a high gate breakdown voltage, the manufacturing process can be shared, and an increase in manufacturing cost can be prevented.

[0113] Further, the voltage holding circuit may include a plurality of holding elements connected in series, and the connection node between the n-th holding element and the n + 1-th holding element among the plurality of holding elements may be connected to the gate of the trigger transistor.

[0114] By doing so, it is possible to protect the gate-source of the trigger transistor from overvoltage and prevent an increase in the chip area related to the circuit device.

[0115] Also, the trigger transistor may be a transistor having a DMOS structure.

[0116] By doing so, it is possible to include a trigger transistor in a circuit device driven at a high voltage.

[0117] Also, the trigger transistor may be a transistor having a DMOS structure of a first conductivity type or a transistor having a DMOS structure of a P type, and the anode region of the thyristor circuit and the source region and drain region of the DMOS structure of the second conductivity type may be impurity diffusion regions of the second conductivity type in the same layer.

[0118] By doing so, the anode region can be formed together with the DMOS of the second conductivity type.

[0119] Also, the cathode region of the thyristor circuit and the region for setting the potential of the substrate of the transistor having a DMOS structure of the second conductivity type may be the same impurity diffusion region of the first conductivity type.

[0120] By doing so, the cathode region can be formed together with the DMOS of the second conductivity type.

[0121] Also, the first terminal may be one of the power supply terminals on the high potential side and the power supply terminals on the low potential side, and the second terminal may be the other power supply terminal of the power supply terminals on the high potential side and the power supply terminals on the low potential side.

[0122] By doing so, it is possible to arrange the thyristor circuit and the voltage hold circuit between the power supply terminal on the high potential side and the power supply terminal on the low potential side.

[0123] Further, the circuit device may include a second voltage holding circuit provided between the first terminal and the thyristor circuit.

[0124] By doing so, a trigger transistor with a reduced breakdown voltage between the source and drain can be used in the circuit device.

[0125] Also, the predetermined capacitor may be a MOM capacitor.

[0126] By doing so, the manufacturing process of the predetermined capacitor and the manufacturing process of other transistors can be shared.

[0127] Also, the MOM capacitor may be provided in the first metal layer and include a first electrode in a comb shape in plan view, and a second electrode provided in the second metal layer, facing the first electrode and in a comb shape in plan view.

[0128] By doing so, it is possible to increase the capacitance of the predetermined capacitor while preventing an increase in the chip area related to the predetermined capacitor.

[0129] Further, the circuit device may include a gate protection circuit provided between the gate of the trigger transistor and the second terminal.

[0130] By doing so, it is possible to protect the gate-source of the trigger transistor from overvoltage.

[0131] Further, the thyristor circuit may include an anode region of a second conductivity type, a cathode region of a first conductivity type, a first gate region of the first conductivity type, and a second gate region of the second conductivity type. Further, the anode region of the second conductivity type may be provided in a first well of the first conductivity type and electrically connected to a first terminal. Further, the cathode region of the first conductivity type may be provided in a second well of the second conductivity type and electrically connected to a second terminal. Further, the first gate region of the first conductivity type may be provided in the first well and electrically connected to the first terminal via a first resistor having one end on the first terminal side. Further, the second gate region of the second conductivity type may be provided in the second well and electrically connected to the second terminal via a second resistor. Further, the trigger transistor may be provided between the other end of the first resistor of the thyristor circuit and the second terminal.

[0132] By doing so, when the trigger transistor is turned on, the potential of the node connected to the first gate region is raised, and current can flow through the first gate. As a result, the transistor related to the first gate is turned on, and the transistor related to the second gate can be turned on. Thereby, the thyristor can be turned on.

[0133] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications that do not substantially depart from the novel matters and effects of the present disclosure are possible. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with the different term anywhere in the specification or drawings. Also, all combinations of the present embodiment and the modifications are included in the scope of the present disclosure. Further, the configuration and operation of the circuit device and the like are not limited to those described in the present embodiment, and various modified implementations are possible.

Description of Reference Numerals

[0134] 10... Circuit device 10... Thyristor circuit, 21... First gate region, 22... Second gate region, 2A... Anode region, 2C... Cathode region, 30... Voltage hold circuit, 31... First hold element, 32... Second hold element, 33... Third hold element, 41... First well, 42... Second well, 50... Gate protection circuit, 61... First predetermined element, 62... Second predetermined element, 301... First voltage hold circuit, 302... Second voltage hold circuit, CS... Predetermined capacitor, CS1... First predetermined capacitor, CS2... Second predetermined capacitor, DR1... First direction, DR2... Second direction, DR3... Third direction, DR4... Fourth direction, GND... Ground, NA, NB, NB1, NB2, NC, ND, NE, NF, NG, NJ1, NJ2, NK, NL... Nodes, Q1, Q2... Transistors, R1... First resistor, R2... Second resistor, RS... Predetermined resistor, RS1... First predetermined resistor, RS2... Second predetermined resistor, T1... First terminal, T2... Second terminal, TH... Thyristor, TT... Trigger transistor, TT1... First trigger transistor, TT2... Second trigger transistor

Claims

1. A first terminal, a second terminal, a thyristor circuit provided between the first terminal and a first node, a voltage holding circuit provided between the first node and the second terminal, a trigger transistor that passes a trigger current through the thyristor circuit, a predetermined capacitor provided between the first terminal and the gate of the trigger transistor, a predetermined resistor provided between the gate of the trigger transistor and the second terminal, A circuit device, characterized by including the above.

2. In the circuit device according to Claim 1, the voltage holding circuit includes a plurality of holding elements connected in series, A circuit device, characterized in that a connection node between an n-th holding element and an (n + 1)-th holding element among the plurality of holding elements is connected to the gate of the trigger transistor.

3. In the circuit device according to Claim 1, the trigger transistor is a transistor having a DMOS structure.

4. In the circuit device according to Claim 3, the trigger transistor is a transistor of the DMOS structure of a first conductivity type or a transistor of the DMOS structure of a second conductivity type, the anode region of the thyristor circuit and the source region and drain region of the DMOS structure of the second conductivity type are impurity diffusion regions of the second conductivity type in the same layer.

5. In the circuit device according to Claim 3, the cathode region of the thyristor circuit and the region for setting the potential of the substrate of the transistor of the DMOS structure of the second conductivity type are the same impurity diffusion region of the second conductivity type.

6. the first terminal is one of a power supply terminal on the high potential side and a power supply terminal on the low potential side, the second terminal is the other of the power supply terminal on the high potential side and the power supply terminal on the low potential side.

7. In the circuit device according to Claim 1, A circuit device, characterized by including a second voltage holding circuit provided between the first terminal and the thyristor circuit.

8. In the circuit device according to Claim 1, the capacitor is a MOM capacitor.

9. In the circuit device according to Claim 8, the MOM capacitor provided on the first metal layer and being a comb-shaped first electrode in a plan view, provided on the second metal layer, facing the first electrode, and being a comb-shaped second electrode in the plan view, A circuit device, characterized by including the above.

10. In the circuit device according to Claim 1, A circuit device, characterized by including a gate protection circuit provided between the gate of the trigger transistor and the second terminal.

11. In the circuit device according to any one of Claims 1 to 10, The thyristor circuit is provided in a first well of a first conductivity type and has an anode region of a second conductivity type electrically connected to the first terminal, is provided in a second well of a second conductivity type and has a cathode region of a first conductivity type electrically connected to the second terminal, is provided in the first well and has a first gate region of a first conductivity type electrically connected to the first terminal via a first resistor with one end on the first terminal side, is provided in the second well and has a second gate region of a second conductivity type electrically connected to the second terminal via a second resistor, and includes The trigger transistor is provided between the other end of the first resistor of the thyristor circuit and the second terminal. A circuit device, characterized by this.

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