Latch unit, multi-bit latch, integrated circuit and preparation method therefor

Abstract

A latch unit, a multi-bit latch, an integrated circuit and a preparation method therefor. The multi-bit latch comprises a first latch group, a second latch group, a padding row, a third latch group and a fourth latch group, which are sequentially arranged on a substrate in an X direction, wherein each latch group comprises eight latch rows sequentially arranged in the X direction; each latch row comprises one latch unit; one latch row adjacent to the padding row is further provided with one first-level clock unit; two latch rows at the middle position of each latch group are each further provided with one second-level clock unit; and the first-level clock unit and the latch unit in the same latch row, and the second-level clock unit and the latch unit in the same latch row are both sequentially arranged in a Y direction. The latch unit, the multi-bit latch and the integrated circuit in the embodiments of the present disclosure offer reliable operation, a small area and high efficiency.

Description

Latch unit, multi-bit latch, integrated circuit and preparation method thereof Technical Field

[0001] The present disclosure relates to, but is not limited to, electronic technology, and more particularly to a latch unit, a multi-bit latch, an integrated circuit, and a method for manufacturing the same. Background Art

[0002] A latch is a level-triggered storage unit. Data storage is determined by the level of the enable signal; the output changes with the input only when the latch is enabled. A multibit latch is used to store and transmit multiple bits of data. It consists of a clock circuit and multiple latch circuits, each capable of storing a single bit. The clock circuit generates a clock signal and an inverted clock signal that serve as the enable signal for each latch circuit. Multibit latches are often used to store transient data.

[0003] The layout design of multi-bit latches in integrated circuits also needs to be improved to optimize the area, operational reliability, efficiency, and energy-saving performance of the multi-bit latches.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] An embodiment of the present disclosure provides a latch unit including a substrate and eight MOS transistors. The substrate includes an NMOS region and a PMOS region. The direction from the NMOS region to the PMOS region is a first direction. Four PMOS transistors Q12, Q11, Q7, and Q13 are sequentially arranged in the PMOS region along a second direction. Four NMOS transistors Q9, Q10, Q8, and Q14 are sequentially arranged in the NMOS region along the second direction. The second direction intersects the first direction.

[0007] Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11 and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter; Q12 and Q9, Q11 and Q8, and Q13 and Q14 are respectively arranged opposite each other, and the gates of the two oppositely arranged MOS are connected to each other; a filling structure is formed at a position opposite to Q10 in the PMOS region and a position opposite to Q7 in the NMOS region, and a filling structure is formed between Q7 and Q13 and between Q8 and Q14;

[0008] The transmission gate blocks the input 1-bit data d or outputs it to the input end of the CMOS inverter based on clk and clkb; the CMOS inverter inverts d to obtain an inverted signal Output to the input of the clocked inverter, which converts Block or After inversion, it is output to the input end of the CMOS inverter; wherein, clk and clkb are both clock signals input to the latch unit, and clkb is the inverted signal of clk.

[0009] An embodiment of the present disclosure further provides a multi-bit latch, comprising a first latch group, a second latch group, a padding row, a third latch group, and a fourth latch group sequentially arranged along the X direction on a substrate, each latch group comprising eight latch rows sequentially arranged along the X direction, each latch row comprising a latch unit, wherein:

[0010] A latch row adjacent to the filling row is further provided with a primary clock unit, wherein the primary clock unit is configured to receive a clock signal clkin and output an inverted signal clkout of clkin;

[0011] The two latch rows in the middle of each latch group are each provided with a secondary clock unit, wherein one secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk;

[0012] The latch unit is configured to latch and output the input 1-bit data based on clk and clkb;

[0013] The primary clock unit and the latch units in the same latch row, and the secondary clock unit and the latch units in the same latch row are sequentially arranged along the Y direction, and the Y direction intersects the X direction.

[0014] An embodiment of the present disclosure further provides an integrated circuit, comprising the multi-bit latch as described in any embodiment of the present disclosure.

[0015] An embodiment of the present disclosure also provides a method for preparing a multi-bit latch, comprising: forming a primary clock unit, 8 secondary clock units, and 32 latch units on a substrate; on a plane parallel to the substrate, the multi-bit latch comprises a first latch group, a second latch group, a padding row, a third latch group, and a fourth latch group sequentially arranged along the X direction on the substrate, each latch group comprising 8 latch rows sequentially arranged along the X direction, each latch row comprising one latch unit; wherein a latch row adjacent to the padding row is further provided with the primary clock unit, the primary clock unit being configured to receive a clock signal clkin and output a clock signal clk in the inverted signal clkout; the two latch rows in the middle position of each latch group are also each provided with a secondary clock unit, one of the secondary clock units is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk; the latch unit is configured to latch and output the input 1-bit data based on clk and clkb; wherein the primary clock unit and the latch units in the same latch row, and the secondary clock unit and the latch units in the same latch row are arranged in sequence along the Y direction, and the Y direction and the X direction intersect.

[0016] ]Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0018] FIG1 is a circuit block diagram of a multi-bit latch according to an embodiment of the present disclosure;

[0019] FIG2 is an equivalent circuit diagram of a primary clock circuit, a secondary clock circuit, and a latch circuit according to an embodiment of the present disclosure;

[0020] FIG3 is a schematic diagram of a latch circuit according to an embodiment of the present disclosure;

[0021] FIG4 is a schematic structural diagram of a multi-bit latch according to an embodiment of the present disclosure;

[0022] 5A, 5B, 5C, and 5D are schematic structural diagrams of a first latch group, a second latch group, a third latch group, and a fourth latch group in a multi-bit latch according to an embodiment of the present disclosure;

[0023] FIG6 is a schematic diagram showing the distribution of input signal terminals and output signal terminals of a multi-bit latch chip according to an embodiment of the present disclosure;

[0024] 7A and 7B are schematic diagrams of clock signal routing for a multi-bit latch according to an embodiment of the present disclosure;

[0025] 8A is a top view of a latch unit after forming a first insulating layer and a polysilicon layer according to an embodiment of the present disclosure;

[0026] 8B is a top view of a latch unit after a trench contact layer is formed according to an embodiment of the present disclosure;

[0027] 8C is a top view of the latch unit after forming a gate contact layer according to an embodiment of the present disclosure;

[0028] 8D is a top view of the latch unit after forming a first contact hole pattern according to an embodiment of the present disclosure;

[0029] FIG8E is a top view of a first metal layer of a latch unit formed in accordance with an embodiment of the present disclosure;

[0030] FIG8F is a top view of a latch unit after forming a first metal layer according to an embodiment of the present disclosure;

[0031] 8G is a top view of the latch unit after forming a second contact hole pattern according to an embodiment of the present disclosure;

[0032] 8H is a top view of the second metal layer of the latch unit formed in one embodiment of the present disclosure;

[0033] FIG8I is a top view of a latch unit after forming a second metal layer according to an embodiment of the present disclosure;

[0034] FIG8J is a top view of the latch unit after forming a third contact hole pattern according to an embodiment of the present disclosure;

[0035] 8K is a schematic diagram of a second metal layer, a third contact hole pattern, and a third metal layer of a latch unit formed in one embodiment of the present disclosure;

[0036] 9A is a top view of the Buffer1 unit + Latch1 unit after forming the first insulating layer and the polysilicon layer according to an embodiment of the present disclosure;

[0037] FIG9B is a top view of the Buffer1 unit + Latch1 unit after forming the trench contact layer according to an embodiment of the present disclosure;

[0038] FIG9C is a top view of the Buffer1 unit + Latch1 unit after forming the gate contact layer according to an embodiment of the present disclosure;

[0039] FIG9D is a top view of the Buffer1 unit + Latch1 unit after forming the first contact hole pattern according to an embodiment of the present disclosure;

[0040] FIG9E is a top view of the first metal layer of the Buffer1 unit+Latch1 unit formed in one embodiment of the present disclosure;

[0041] FIG9F is a top view of the Buffer1 unit + Latch1 unit after forming the first metal layer according to an embodiment of the present disclosure;

[0042] 10A is a top view of a B1L1 latch row (Buffer1 unit + Latch1 unit) and a B2L2 latch row (Buffer2 unit + Latch2 unit) after forming a second contact hole pattern according to an embodiment of the present disclosure, wherein the B1L1 latch row is above the B2L2 latch row;

[0043] FIG10B is a top view of the second metal layer of the B1L1 latch row and the B2L2 latch row formed in one embodiment of the present disclosure;

[0044] 10C is a top view of the B1L1 latch row and the B2L2 latch row after forming the second metal layer according to an embodiment of the present disclosure;

[0045] 10D is a top view of the B1L1 latch row and the B2L2 latch row after forming a third contact hole pattern according to an embodiment of the present disclosure;

[0046] 10E is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of the B1L1 latch row and the B2L2 latch row formed in one embodiment of the present disclosure;

[0047] 11A is a top view of a B2L2 latch row and a B1L1 latch row after forming a second contact hole pattern according to an embodiment of the present disclosure, wherein the B2L2 latch row is above the B1L1 latch row;

[0048] FIG11B is a top view of the second metal layer of the B2L2 latch row and the B1L1 latch row formed in one embodiment of the present disclosure;

[0049] FIG11C is a top view of the B2L2 latch row and the B1L1 latch row after forming the second metal layer according to an embodiment of the present disclosure;

[0050] 11D is a top view of the B2L2 latch row and the B1L1 latch row after forming a third contact hole pattern according to an embodiment of the present disclosure;

[0051] 11E is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of the B2L2 latch row and the B1L1 latch row formed in one embodiment of the present disclosure;

[0052] FIG12A is a top view of the IL2 latch row after forming a second contact hole pattern according to an embodiment of the present disclosure;

[0053] 12B is a top view of an IL2 latch row where a second metal layer and a third contact hole pattern are formed according to an embodiment of the present disclosure;

[0054] FIG. 12C is a top view of the second metal layer, the third contact hole pattern, and the third metal layer of the IL2 latch row formed according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The following will describe in detail the embodiments of the present disclosure in conjunction with the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any way.

[0056] In the accompanying drawings, the size of one or more components, the thickness of a layer, or the area of ​​a layer are sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings. Ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion between components and are not intended to limit the number. "Multiple" in this disclosure refers to two or more. In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "center," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of components vary appropriately depending on the direction in which the components are described. Therefore, the words and phrases are not limited to those described in the specification, and can be appropriately replaced according to circumstances.

[0057] In this disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate component, or a connection between the two components. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "electrical connection" includes the situation where the constituent elements are connected together through an element with a certain electrical function. There is no special restriction on "elements with a certain electrical function" as long as they can transmit and receive electrical signals between the connected constituent elements. Examples of "elements with a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions. In this article, the connection between the gate, drain and source of a transistor such as MOS, between the gate, drain and source of MOS and a conductor (such as various electrodes or other conductive lines, pins, etc. formed by metal, polysilicon, etc.), and between conductors refers to electrical connection.

[0058] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (also referred to as a drain terminal, a drain region, or a drain electrode) and its source (also referred to as a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In the present disclosure, to distinguish the two electrodes of a transistor other than the gate, one electrode may be referred to as the first electrode and the other electrode may be referred to as the second electrode. The first electrode may be the source or drain electrode, and the second electrode may be the drain or source electrode. In addition, the gate of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. In the present disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included. In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced by "conductive film." Similarly, "insulating film" may sometimes be replaced by "insulating layer." "Approximately" and "substantially" in the present disclosure do not strictly define the boundaries and allow for situations within the range of process and measurement errors.

[0060] An embodiment of the present disclosure provides a multi-bit latch (MultibitLatch), as shown in Figure 1, the multi-bit latch includes a primary clock circuit (also called an INV circuit), a secondary clock circuit (also called a Buffer circuit) and a latch circuit (also called a Latch circuit), each primary clock circuit is connected to 2n secondary clock circuits, and each secondary clock circuit is connected to 8 1-bit latch circuits, where n is a positive integer. The latch shown in the figure can be a separate latch or a latch in an integrated circuit. The integrated circuit can have multiple latches with the same or different bit numbers to implement data storage functions. Although the primary clock circuit in the figure is connected to 4 secondary clock circuits, that is, n=2, the present disclosure is not limited to this, and n can also be equal to 1, 3, 4 or a larger value.

[0061] The multi-bit latch of this embodiment can be constructed using MOS transistors. FIG2 shows the corresponding equivalent circuit diagram. For convenience, the figure only shows one primary clock circuit (also called an INV circuit), one secondary clock circuit (also called a buffer circuit), and one latch circuit (also called a latch circuit) in FIG1 . The remaining secondary clock circuits and latch circuits in FIG1 have the same structure as the secondary clock circuit and latch circuit shown in FIG2 .

[0062] As shown in Figures 1 and 2, the primary clock circuit includes an inverter configured to receive the input clock signal of the 32-bit latch (denoted as clkin, also known as the clkin signal) and output the inverted signal of the clkin signal (denoted as clkout, also known as the clkout signal). A primary clock circuit is connected to four secondary clock circuits. Each secondary clock circuit includes two inverters in series, configured to invert the input clkout signal once and output the inverted signal of the clkout signal (denoted as clk, also known as the clk signal), and to invert the clk signal once more and output the inverted signal of the clk signal (denoted as clkb, also known as the clkb signal). Each secondary clock circuit is connected to eight latch circuits, outputting the clk signal and the clkb signal to each latch circuit as the enable signal of the latch circuit. Each latch circuit latches and transmits the input 1-bit data based on the clk signal and the clkb signal. The inverters in the primary and secondary clock circuits are all CMOS inverters.

[0063] As shown in Figure 2, the inverter of the first-level clock circuit includes a first transistor Q1 and a second transistor Q2, where Q1 is a PMOS and Q2 is an NMOS. The gates of Q1 and Q2 are connected as the input of the first-level clock circuit to receive the input clock signal clkin of the 32-bit latch; the drain of Q1 and Q2 are connected as the output of the first-level clock circuit to output the inverted signal clkout of clkin. The source of Q1 is connected to the power supply (denoted as VCC), and the source of Q2 is grounded (denoted as VSSX). The first inverter in the second-level clock circuit includes a third transistor Q3 and a fourth transistor Q4, and the second inverter includes a fifth transistor Q5 and a sixth transistor Q6. Q3 and Q5 are PMOS, and Q4 and Q6 are NMOS. The sources of Q3 and Q5 are connected to the power supply, the sources of Q4 and Q6 are grounded, and the gates of Q3 and Q4 are connected, serving as the input of the secondary clock circuit (also the input of the first inverter) to receive clkout. The drains of Q3 and Q4 are connected, serving as the output of the first inverter to output clk. The gates of Q5 and Q6 are connected, serving as the input of the second inverter to receive clk. The drains of Q5 and Q6 are connected, serving as the output of the second inverter to output clkb. In the secondary clock circuit, the outputs of the first and second inverters are both outputs of the secondary clock circuit. The outputs clk and clkb are transmitted to each latch circuit connected to the secondary clock circuit.

[0064] Exemplarily, the latch circuit is a transmission-gated D latch, as shown in FIG3 , comprising a transmission gate 31, a clocked inverter 32, and a CMOS inverter 33. The input of the transmission gate 31 receives 1 bit of input data (denoted as d, also referred to as a d signal), and the output of the transmission gate 31 is connected to the output of the clocked inverter 32 and the input of the CMOS inverter 33. The on / off state of the transmission gate 31 can be controlled based on the levels of clk and clkb. The input of the clocked inverter 32 is connected to the output of the CMOS inverter 33. The clocked inverter 32 performs state control based on clk and clkb, and can operate in an inverter state or an off state. The output of the CMOS inverter 33 outputs 1 bit of data (denoted as on, also referred to as an on signal). In the latch circuit, the output of the transmission gate 31, the output of the clocked inverter 32, and the input of the CMOS inverter 33 are connected together.

[0065] The latch circuit of this embodiment is implemented using MOS transistors. (See Figures 2 and 3 .) Transmission gate 31 includes a seventh transistor Q7 and an eighth transistor Q8. Clocked inverter 32 includes a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, and a twelfth transistor Q12. CMOS inverter 33 includes a thirteenth transistor Q13 and a fourteenth transistor Q14. Q7, Q9, Q11, and Q13 are PMOS transistors, while Q8, Q10, Q12, and Q14 are NMOS transistors. Among them: in the transmission gate 31, the gate 107 of Q7 receives clkb, and the gate 108 of Q8 receives clk; the drain of Q7 and the drain of Q8 are connected as the input of the transmission gate to receive the d signal, and the source of Q7 and the source of Q8 are connected as the output of the transmission gate, and its output signal is marked as nk1 in Figure 2; in the clocked inverter 32, the source of Q12 is connected to the power supply, the gate of Q12 and the gate 109 of Q9 are connected as the input of the clock inverter connected to the output of the CMOS inverter to receive the on signal, and the drain of Q12 is connected to the source of Q11; the gate of Q11 receives clk, and the drain of Q11 and the drain of Q10 are connected as the output of the clocked inverter; the gate of Q10 receives clkb, and the source of Q10 and the drain of Q9 are connected; the source of Q9 is grounded. In the CMOS inverter 33, the source of Q13 is connected to the power supply, the gate of Q13 and the gate of Q14 are connected as the input of the CMOS inverter, connected to the output of the transmission gate and the output of the clocked inverter to receive nk1; the drain of Q13 and the drain of Q14 are connected as the output of the CMOS inverter, connected to the input of the clocked inverter, and output the latched 1-bit data, i.e., the on signal.

[0066] In the aforementioned primary clock circuit, secondary clock circuit, and latch circuit, the substrate of the PMOS transistor is connected to the power supply, and the substrate of the NMOS transistor is grounded. The PMOS transistor is turned off when the gate voltage is high and turned on when the gate voltage is low; the NMOS transistor is turned on when the gate voltage is high and turned off when the gate voltage is low.

[0067] In the 32-bit multi-bit latch of this embodiment, each latch circuit latches and outputs 1 bit of data, and 32 latch circuits can latch and output 32 bits of data. The latching and outputting process of a latch circuit for 1 bit of data is as follows: when the clk signal is 1 (clkb signal is 0), the transmission gate 31 is turned on, the clocked inverter 32 is turned off, and the input 1 bit of data d is written to the input end of the CMOS inverter; when the clk signal is 0 (clkb signal is 1), the transmission gate 31 is turned off, the clocked inverter 32 works in the inverter state and forms a bistable circuit with the CMOS inverter to latch the 1 bit of data d. The CMOS inverter 33 outputs the inverted signal of d. The output end of the CMOS inverter 33 can be connected to a tri-state gate to control the output of data.

[0068] The transistors and wiring in the multi-bit latch described above can be constructed by forming multiple film layers on a substrate. Specifically, a primary clock circuit can be implemented by a primary clock unit formed on the substrate, a secondary clock unit can be implemented by two secondary clock units formed on the substrate, and a latch circuit can be implemented by a latch unit formed on the substrate. The following describes the physical layout, or layout, of the multi-bit latch according to an embodiment of the present disclosure.

[0069] An embodiment of the present disclosure provides a multi-bit latch, comprising a padding row formed on a substrate, M latch groups sequentially arranged along an X direction on one side of the padding row, and K latch groups sequentially arranged along the opposite direction of the X direction on the other side of the padding row, where M and K are positive integers, and each latch group comprises eight latch rows sequentially arranged in the X direction, each latch row comprising one latch unit, wherein:

[0070] A latch row adjacent to the filling row is further provided with a primary clock unit (also referred to as an INV unit), wherein the primary clock unit is configured to receive a clock signal clkin and output an inverted signal clkout of clkin;

[0071] The two latch rows in the middle position of each latch group are each provided with a secondary clock unit (also called a Buffer unit), one of which is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk; the two secondary clock units constitute a secondary clock circuit.

[0072] The latch unit (also called a latch unit) is configured to latch and output input 1-bit data based on clk and clkb.

[0073] In an exemplary embodiment of the present disclosure, M=K=2, that is, this embodiment provides a multi-bit latch, as shown in FIG4 and FIG5A to FIG5D . The multi-bit latch includes a first latch group, a second latch group, a padding row, a third latch group, and a fourth latch group sequentially arranged along the X direction on a substrate. Each latch group includes eight latch rows sequentially arranged along the X direction. Each latch row includes one latch unit, wherein:

[0074] A latch row adjacent to the filling row is further provided with a primary clock unit, wherein the primary clock unit is configured to receive a clock signal clkin and output an inverted signal clkout of clkin;

[0075] The two latch rows in the middle of each latch group are each provided with a secondary clock unit, wherein one secondary clock unit is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk;

[0076] The latch unit is configured to latch and output the input 1-bit data based on clk and clkb;

[0077] The primary clock unit and the latch units in the same latch row are arranged in sequence along the Y direction, and the secondary clock unit and the latch units in the same latch row are arranged in sequence along the Y direction, and the Y direction and the X direction intersect and are perpendicular to each other.

[0078] Although the example in the figure is to set the first-level clock unit (1NV unit) in the adjacent latch row above the filling row, in other embodiments, it can also be set in the adjacent latch row below the filling row.

[0079] In an exemplary embodiment of the present disclosure, each latch row is divided into a first region and a second region arranged in the Y direction. In Figures 5A to 5D, the portion to the left of the dashed line extending in the X direction is the first region, and the portion to the right of the dashed line is the second region. The first and second regions of different latch rows are aligned in the X direction. The latch units are all located in the second region of their respective latch rows. The input signals b, clk, and clkb of all latch units can be configured to be input from the side closest to the first region (the left side in the figure), and the latched 1-bit data is output from the side away from the first region (the right side in the figure). The primary and secondary clock units are both located in the first region of their respective latch rows. Except for the latch rows equipped with the primary and secondary clock units, the first regions of other latch rows are equipped with filler units (such as filler units). Filler units are placeholder elements used to fill blank areas on the chip. They can be composed of metal layers, polysilicon layers, etc., and have specific functions but can also optimize the manufacturing process, such as improving chemical mechanical polishing (CMP) uniformity, reducing "voids" in the layout, and improving production yield.

[0080] In an exemplary embodiment of the present disclosure, the width W of each latch row in the X direction is equal, and the length L of each latch row in the Y direction is equal, 0.486μm≤W≤0.594μm, 1.1664μm≤L≤1.4256μm. In one example, the padding row located in the middle of all latch rows is a Decap unit, and the width of the Decap unit in the X direction is equal to W. The length in the Y direction is equal to L, W=0.54μm, L=1.296μm. The length of the entire 32-bit latch is 1.296μm, the width is 17.82μm, and the area is 23.09472μm 2The decap unit can be used as a placeholder element to reduce chip power noise. It can be composed of a polysilicon layer and a metal layer formed on a substrate to increase the chip's decoupling capacitor, reduce noise propagation and interference, and ensure normal operation of the chip.

[0081] In an exemplary embodiment of the present disclosure, the substrates of the first and second regions in each latch row are formed with a PMOS region and an NMOS region, the PMOS region has a PMOS substrate, and the NMOS region has an NMOS substrate; in any two adjacent latch rows, the NMOS region and the PMOS region of one latch row are arranged in sequence in the X direction, and the first direction of the latch unit in the latch row (the direction from the NMOS region to the PMOS region) is the same as the X direction, which is called the first latch unit; the NMOS region and the PMOS region of the other latch row are arranged in sequence in the opposite direction of the X direction, and the first direction of the latch unit in the latch row is the same as the opposite direction of the X direction, which is called the second latch unit; the first latch unit and the second latch unit each constitute a 1-bit latch circuit; the second direction of the first latch unit and the second latch unit (perpendicular to the first direction) are both the same as the Y direction. In one example, the transistor positions of the first latch unit and the second latch unit in the two adjacent latch rows are mirror-symmetrical with respect to the boundary line extending along the Y direction of the two latch rows. Other structures, such as the positions of various electrodes, can also be mirror-symmetrical with respect to the boundary line, but are not limited to this. In a reference system based on the X direction and the Y direction, the latch unit can be divided into a first latch unit and a second latch unit, but in a reference system based on the first direction and the second direction, the structures of the first latch unit and the second latch unit both conform to the description of the latch unit-related embodiments below.

[0082] In an exemplary embodiment of the present disclosure, as shown in Figures 4 and 5A to 5D, two secondary clock units each include a PMOS transistor provided in a PMOS region of a first region of a latch row and an NMOS transistor provided in an NMOS region of a first region of a latch row. The NMOS region and the PMOS region of one secondary clock unit are arranged sequentially in the X direction (i.e., the direction from the NMOS region to the PMOS region is the same as the X direction), which is referred to as a first secondary clock unit (also referred to as a Buffer1 unit herein); the NMOS region and the PMOS region of the other secondary clock unit are arranged sequentially in the opposite direction of the X direction (i.e., the direction from the NMOS region to the PMOS region is the same as the opposite direction of the X direction), which is referred to as a second secondary clock unit (also referred to as a Buffer2 unit herein); referring to Figure 2, the PMOS transistor of the first secondary clock unit is the third transistor Q3, and the NMOS transistor is the fourth transistor Q4. Q3 and Q4 are connected to form a CMOS inverter to receive clkout and output clk; the PMOS transistor of the second secondary clock unit is the fifth transistor Q5, and the NMOS transistor is the sixth transistor Q6. Q5 and Q6 are connected to form a CMOS inverter to receive clk and output clkb.

[0083] 4 and 5A , the first latch group in the figure includes 8 latch rows. These latch rows can be divided into multiple types according to the different combined units. One is a latch row composed of a filler unit (Filler unit) and a first latch unit (Latch1 unit), marked as FL1; one is a latch row composed of a filler unit (Filler unit) and a second latch unit (Latch2 unit), marked as FL2; one is a latch row composed of a first and second secondary clock unit (Buffer1 unit) and a first latch unit (Latch1 unit), marked as B1L1; one is a latch row composed of a second and second secondary clock unit (Buffer2 unit) and a second latch unit (Latch2 unit), marked as B2L2; the fill row in FIG4 is marked as Decap. In the second latch group, as shown in FIG5B , the above four types of latch rows are also included. As shown in FIG5C , in addition to the four types of latch rows mentioned above, the latch row adjacent to Decap in the third latch group is another type of latch row composed of a primary clock unit (INV unit) and a second latch unit (Latch2 unit), labeled IL2.

[0084] In this embodiment, the latch units in the two latch rows adjacent to the padding row are second latch units; however, in other embodiments, the positions of different types of latch rows may vary. For example, the position of the N-well (N-vell) in each latch row in FIG4 (the position of the N-vell is the position of the PMOS region) can be shifted in the X direction by the width of one latch row (the size of the latch row in the X direction) relative to the illustrated embodiment. In FIG4 , the upper half of the Decap unit is the PMOS region, and the lower half is the NMOS region; after the shift, the lower half of the Decap unit is the PMOS region, and the upper half is the NMOS region. At this time, the latch units in the two latch rows adjacent to the padding row are first latch units. On either side of the padding row (Decap unit), in any two adjacent latch rows, the latch unit in one latch row is the first latch unit, and the latch unit in the other latch row is the second latch unit. In other embodiments, the first and second level clock units may also include Q5 and Q6 in Figure 2, that is, configured to receive clk and output clkb; the second and second level clock units include Q3 and Q4 in Figure 2, configured to receive clkout and output clk; at this time, the clock signal routing between the units can be adjusted accordingly.

[0085] In an exemplary embodiment of the present disclosure, in a direction perpendicular to the substrate, the multi-bit latch includes a polysilicon layer pattern and a source region and a drain region of the MOS, a trench contact layer, a gate contact layer, a first contact hole, a first metal layer, a second contact hole, a second metal layer, a third contact hole and a third metal layer, which are sequentially formed on the substrate; the clock signal lines between different latch rows are arranged in the third metal layer, the clock signal lines transmitted between the first clock unit and the latch unit of the same latch row, and between the second clock unit and the latch unit are arranged in the second metal layer, and the connections between the first clock unit, the second clock unit and the internal transistors of the latch unit are arranged in the first metal layer and the second metal layer, or in the gate contact layer, the first metal layer and the second metal layer.

[0086] In an exemplary embodiment of the present disclosure, a first insulating layer and a polysilicon layer are sequentially formed on a substrate of a secondary clock unit, and the polysilicon layer includes:

[0087] Three electrodes extending along the X direction in the PMOS region, the three electrodes being sequentially spaced apart in the Y direction, wherein the third electrode serves as the PMOS gate and the other two electrodes serve as dummy gates;

[0088] Three electrodes extending along the X direction in the NMOS region, the three electrodes being sequentially spaced apart in the Y direction, wherein the third electrode serves as the NMOS gate and the other two electrodes serve as dummy gates;

[0089] The three electrodes in the PMOS region and the three electrodes in the NMOS region are arranged opposite to each other in the Y direction, and the PMOS gate and the NMOS gate are formed as one piece.

[0090] The PMOS region and NMOS region of the secondary clock unit (ie, the PMOS region and NMOS region of the first region) can be integrally formed with the PMOS region and NMOS region of the second region in the same latch row, and both can be set as rectangular regions.

[0091] 9A to 9F show the structure of the first metal layer and the layers below the first metal layer of the latch row composed of the Buffer1 unit and the Latch1 unit. The structure of the Buffer1 unit is first introduced here, and the structure of the Latch1 unit will be introduced in the embodiment of the latch unit below.

[0092] As shown in the figure, the PMOS gate of the Buffer1 unit is the Q3 gate 103, the NMOS gate is the Q4 gate 104, and the others are virtual gates 100. In the Buffer2 unit, the PMOS gate is the Q5 gate, and the NMOS gate is the Q6 gate. The structure of the first metal layer and the layers below the first metal layer of the Buffer2 unit can also be seen in Figures 9A to 9F, but Q3 needs to be replaced by Q5, and Q4 needs to be replaced by Q6. The settings of the virtual gate and virtual electrode can be the same as those of the Buffer1 unit. The structure of the film layers above the first metal layer of the Buffer1 unit and the Buffer2 unit can be seen in Figures 10A to 10E, and Figures 11A to 11E. In Figure 10E, the Latch1 unit is marked as 81, the Latch2 unit is marked as 82, the Buffer1 unit is marked as 83, and the Buffer2 unit is marked as 84.

[0093] In an exemplary embodiment of the present disclosure, in the secondary clock unit, in the Y direction, a PMOS drain and a PMOS source are respectively formed on both sides of the PMOS gate, and an NMOS drain and an NMOS source are respectively formed on both sides of the NMOS gate, and the PMOS drain and the PMOS source, as well as the NMOS drain and the NMOS source are all arranged in sequence in the Y direction; as shown in Figure 9B, in the secondary clock unit, in the Y direction, a second virtual electrode 220 is provided between the first virtual gate 100 and the second virtual gate 100 on the side of the PMOS gate away from the latch unit, and a third virtual electrode 217 is provided between the first virtual gate 100 and the second virtual gate 100 on the side of the NMOS gate away from the latch unit.

[0094] In an exemplary embodiment of the present disclosure, in a secondary clock unit, a gate contact layer is formed on the polysilicon layer, and the gate contact layer includes a plurality of gate contact electrodes extending along the Y direction. Referring to FIG. 9C , the gate contact electrodes include: a seventh gate contact electrode 307 overlapped with the virtual gate and connected to the PMOS drain 219 and the second virtual electrode 220, an eighth gate contact electrode 308 overlapped with the virtual gate and connected to the PMOS source 218 and the Q12 source 208, a ninth gate contact electrode 309 overlapped with the virtual gate and connected to the NMOS source 215 and the Q9 source 206, and a ninth gate contact electrode 309 overlapped with the virtual gate and connected to the NMOS source 215 and the Q9 source 206. The tenth gate contact electrode 310 connects the third dummy electrode 217 and the NMOS drain 216, and the eleventh gate contact electrode 311 overlaps the NMOS gate 104 and the PMOS gate 103; wherein the seventh gate contact electrode 307 and the eighth gate contact electrode 308 are located in the PMOS region, and the ninth gate contact electrode 309 and the tenth gate contact electrode 310 are located in the NMOS region; in the X direction, the eleventh gate contact electrode 311 is located between the seventh gate contact electrode 307 and the tenth gate contact electrode 310, and also between the eighth gate contact electrode 308 and the ninth gate contact electrode 309.

[0095] In an exemplary embodiment of the present disclosure, in a secondary clock unit, a second insulating layer and a first metal layer are formed on the gate contact layer. The second insulating layer is formed with a plurality of first contact holes, as shown in FIG9D to FIG9F . The first metal layer includes:

[0096] A power connection electrode VCC located on a side of the PMOS region away from the NMOS region, the power connection electrode being connected to a power connection electrode VCC in a latch unit of the same latch row, and the two may be integrally formed;

[0097] A ground connection electrode VSSX located on a side of the NMOS region away from the PMOS region, the ground connection electrode being connected to a ground connection electrode VSSX in a latch unit of the same latch row, and the two may be integrally formed;

[0098] a twelfth connecting electrode 412 connected to the PMOS gate through the first contact hole and the eleventh gate contact electrode 311, wherein the twelfth connecting electrode 412 is used as an input terminal of the CMOS inverter in the secondary clock unit;

[0099] a thirteenth connection electrode 413 connected to the second dummy electrode 220 and the third dummy electrode 217 through the first contact hole, wherein the thirteenth connection electrode 413 is used as an output end of the CMOS inverter in the secondary clock unit;

[0100] The first contact hole connected to the eleventh gate contact electrode 311 is located between the PMOS gate and the first dummy gate on the side of the PMOS gate away from the latch unit (left side in the figure) in the Y direction;

[0101] Both VCC and VSSX can be strip patterns extending along the Y direction, the twelfth connecting electrode 412 and the thirteenth connecting electrode 413 can be strip patterns extending along the X direction, and the twelfth connecting electrode 412 is located between the thirteenth connecting electrode 413 and the latch units of the same latch row, that is, the twelfth connecting electrode 412 is closer to the latch units of the same latch row than the thirteenth connecting electrode 413.

[0102] In this embodiment, the PMOS gate and the NMOS gate are integrally formed and are the same strip pattern of the polysilicon layer. For example, the strip patterns indicated by 103 and 104 extending along the X direction in FIG. 9C are the gates Q3 and Q4.

[0103] In an exemplary embodiment of the present disclosure, in a secondary clock unit, a third insulating layer and a second metal layer are formed on the first metal layer, and a plurality of second contact holes are formed in the third insulating layer. Figures 10A to 10C show the structure of a latch row consisting of a first secondary clock unit and a first latch unit, and a latch row consisting of a second secondary clock unit and a second latch unit. As shown in the figure:

[0104] The second metal layer in the first secondary clock unit includes: a CLKOUT lead-in line 505, configured to be connected to the twelfth connection electrode 412 through a second contact hole; and a CLK lead-out line 506, configured to be connected to the thirteenth connection electrode 413 through a second contact hole, and connected to the CLK transmission line 502 provided on the second metal layer in the first latch unit of the same latch row, and can be integrally formed;

[0105] The second metal layer in the second secondary clock unit includes: a CLK lead-in line 508, which is configured to be connected to the twelfth connecting electrode 412 through a second contact hole, and is connected to the CLK transmission line 502 provided in the second metal layer in the second latch unit of the same latch row; and a CLKB lead-out line 507, which is configured to be connected to the thirteenth connecting electrode 413 through a second contact hole, and is connected to the CLKB transmission line 503 provided in the second metal layer in the second latch unit of the same latch row.

[0106] For the structures in the latch unit involved in the embodiments of the multi-bit latch, such as transistors, connecting electrodes, connecting lines, etc., refer to the description in the relevant embodiments of the latch unit.

[0107] In an exemplary embodiment of the present disclosure, in the second-stage clock unit, a fourth insulating layer and a third metal layer are formed on the second metal layer, and a plurality of third contact holes are formed in the fourth insulating layer, as shown in FIG. 10D to FIG. 10E , wherein:

[0108] The third metal layer in the first secondary clock unit includes: a CLKOUT connection line 603 extending to the primary clock unit along the X direction or the reverse direction of the X direction, and configured to be connected to the CLKOUT lead-in line 505 through a third contact hole to transmit clkout to the gates of Q3 and Q4;

[0109] When the first secondary clock unit is provided on the side of the second secondary clock unit away from the filling row, the third metal layer of the second secondary clock unit is provided with the CLKOUT connection line 603.

[0110] In an exemplary embodiment of the present disclosure, the first-level clock unit includes a first transistor Q1 set in a PMOS area of ​​the first area of ​​the latch row and a second transistor Q2 set in an NMOS area of ​​the first area of ​​the latch row; Q1 is PMOS, Q2 is NMOS, and the CMOS inverter formed by connecting Q1 and Q2 is configured to receive clkin, output clkout and transmit it to the CLKOUT connection line 603.

[0111] The structure of the primary clock unit in this embodiment is similar to that of the secondary clock unit. The structure of the first metal layer and the film layer below the metal layer formed by the latch row composed of the primary clock unit and the second latch unit can be referenced to the structure of the latch row composed of the secondary clock unit and the second latch unit. The structure of the second contact hole, second metal layer, third contact hole, and third metal layer formed by the latch row composed of the primary clock unit and the second latch unit can be referenced to Figures 12A to 12C. Clkin can be input from the clock signal input pin of the chip where the multi-bit latch is located.

[0112] In an exemplary embodiment of the present disclosure, the CLKOUT connection line 603 is arranged on the third metal layer of multiple latch units. The CLKOUT connection line 603 includes a first section extending from the first-level clock unit along the X direction to the first and second-level clock units of the fourth latch group, and a second section extending from the first-level clock unit along the opposite direction of the X direction to the first and second-level clock units of the first latch group; these two sections can be disconnected at the first-level clock unit or connected as a whole.

[0113] Referring to FIG. 12C , FIG. 11E , FIG. 11B and FIG. 7A and FIG. 7B , the clk output by the first secondary clock unit is transmitted to the CLK connection line 601 of the other latch units in the latch group via the CLK lead-out line 506 and the CLK transmission line 502 and CLK connection line 601 of the first latch unit in the same latch row, and then transmitted to the CLK lead-in line 508 of the second secondary clock unit in the latch group via the CLK transmission line 502 of the second latch unit in the same latch row as the second secondary clock unit in the latch group; clk is transmitted to the CLK connection line 601 of the second secondary clock unit in the latch group; It can be input into the transistor gate of the latch unit for receiving clk, and clk can be input into the transistor gate of the second secondary clock unit for receiving clk through the CLK lead-in line 508; the clkb output by the second secondary clock unit is transmitted to the CLKB connection lines of other latch units in the latch group via the CLKB lead-out line 507 and the CLKB transmission line 503 and CLKB connection line 602 of the second latch unit in the same latch row, and clkb can be input into the transistor gate of the latch unit for receiving clkb through the CLKB connection line 602 of the latch unit.

[0114] In this embodiment, as shown in Figures 7A and 7B, the third metal layer of each latch unit in a latch group is provided with a CLK connection line 601 and a CLKB connection line 602 extending along the X direction; the CLK connection lines 601 of all latch units in the same latch group are connected in sequence as if they can be formed as one piece, and the CLKB connection lines 602 of all latch units in the same latch group are connected in sequence as if they can be formed as one piece.

[0115] The multi-bit latch of the above-described embodiment of the present disclosure has multiple latch units arranged sequentially in the X direction. The input signal of each latch unit is input from the side closest to the first area, and the output signal is output from the side away from the first area. This facilitates the arrangement of external input and output signal lines and reduces the overall area. The secondary clock units are essentially symmetrically distributed relative to the primary clock units, and the two secondary clock units that constitute the second-stage clock circuit are located in the middle position in the X direction of their latch group, that is, arranged in the fourth and fifth latch rows of a latch group. This ensures that the clock signals received by each latch unit remain as consistent as possible, reducing errors caused by different clock signal arrival times due to the different positions of the latch units, thereby improving the performance of the multi-bit latch.

[0116] The multi-bit latch (MultibitLatch) of the disclosed embodiment can be widely used in various chips that require latch circuits. It has the characteristics of reliable operation, small area, and high efficiency, and can greatly improve at least one of the physical security, flexibility, accuracy, and energy saving of the latch circuit and the multi-bit latch. Figure 6 is a schematic diagram of the distribution of the input signal terminal and output terminal signal of the multi-bit latch of the disclosed embodiment. The 32-bit latch input signal terminal includes a power signal terminal VCC, a ground signal terminal VSSX, an input clock signal terminal clk, and 32 1-bit data input terminals d0 to d31; the output signal terminal of the 32-bit latch includes 32 1-bit data output terminals o1n to o31n. Each 1-bit data input terminal is used to receive 1-bit data to be latched, and each 1-bit data output terminal is used to output the latched 1-bit data.

[0117] An embodiment of the present disclosure further provides an integrated circuit, comprising the multi-bit latch described in any embodiment of the present disclosure, such as one or more 32-bit latches.

[0118] An embodiment of the present disclosure further provides a method for preparing a multi-bit latch, comprising: forming a primary clock unit, 8 secondary clock units, and 32 latch units on a substrate; wherein, on a plane parallel to the substrate, the multi-bit latch comprises a first latch group, a second latch group, a padding row, a third latch group, and a fourth latch group sequentially arranged along the X direction on the substrate, each latch group comprising 8 latch rows sequentially arranged along the X direction, each latch row comprising one latch unit; a latch row adjacent to the padding row is further provided with the primary clock unit, the primary clock unit being configured to receive a clock signal clkin and output clki n's inverted signal clkout; the two latch rows in the middle position of each latch group are also each provided with a secondary clock unit, one of the secondary clock units is configured to receive clkout and output the inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output the inverted signal clkb of clk; the latch unit is configured to latch and output the input 1-bit data based on clk and clkb; wherein the primary clock unit and the latch units in the same latch row, and the secondary clock unit and the latch units in the same latch row are arranged in sequence along the Y direction, and the Y direction and the X direction intersect.

[0119] One embodiment of the present disclosure provides a latch unit, as shown in Figures 8A to 8I , which includes a substrate and eight MOS transistors. The substrate includes an NMOS region and a PMOS region, with the direction from the NMOS region to the PMOS region being a first direction. Four PMOS transistors Q12, Q11, Q7, and Q13 are sequentially arranged in the PMOS region along a second direction, and four NMOS transistors Q9, Q10, Q8, and Q14 are sequentially arranged in the NMOS region along the second direction, with the second direction intersecting the first direction. Wherein:

[0120] Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11, and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter. Q12 is arranged opposite Q9, Q11 is arranged opposite Q8, and Q13 is arranged opposite Q14, with the gates of the two opposing MOS transistors connected to each other. A filling structure (labeled DUMMY1) is formed in the PMOS region opposite Q10, and a filling structure (labeled DUMMY2) is formed in the NMOS region opposite Q7. Filling structures are also formed between Q7 and Q13, and between Q8 and Q14. The source region of Q7 and the drain region of Q11 share a P-type doped region, the drain region of Q9 and the source region of Q10 share an N-type doped region, and the source region of Q8 and the drain region of Q10 share an N-type doped region. This sharing simplifies the structure and connections, reducing the chip size.

[0121] The transmission gate blocks the input 1-bit data d or outputs it to the input end of the CMOS inverter based on clk and clkb; the CMOS inverter inverts d to obtain an inverted signal Output to the input of the clocked inverter, which converts Block or After inversion, it is output to the input end of the CMOS inverter; wherein, clk and clkb are both clock signals input to the latch unit, and clkb is the inverted signal of clk.

[0122] In this embodiment, the first direction of the reference system used by the latch unit is represented as the A-axis direction in Figures 8A to 8I, and the second direction is represented as the B-axis direction perpendicular to the A-axis. As mentioned above, if the latch unit is the first latch unit (Latch1 unit), the first direction is the same as the X-direction, and the second direction is the same as the Y-direction. If the latch unit is the second latch unit (Latch2 unit), the first direction is the same as the opposite direction of the X-direction, and the second direction is still the same as the Y-direction. The NMOS region and the PMOS region in the above-mentioned latch unit are the NMOS region and the PMOS region of the second area in the latch row where the latch unit is located, and can be a rectangular area. In the example shown in the figure, the PMOS region of the latch unit is the area where the N-well (N-vell) is located on the substrate, and the NMOS region is the other area on the P-type doped silicon substrate except the N-vell.

[0123] In this embodiment, the filling structure in the latch unit can adopt a DUMMY unit. The DUMMY unit is a virtual element used to fill the blank area of ​​the polysilicon layer (POLY). It is usually made of polysilicon material. It can have part or all of the structures of the transistor gate, source and drain but does not have the corresponding functions. It plays the role of filling and occupying a place to avoid mutual interference and short circuit between transistors. The DUMMY unit is added in the blank area to make the polysilicon layer as flat and continuous as possible, thereby facilitating subsequent processing steps and reducing defects.

[0124] In an exemplary embodiment of the present disclosure, as shown in Figures 8B and 8C, the gate of each of the eight MOSs extends along the first direction, and the source (denoted as S) and drain (denoted as D) of the MOS are formed on both sides of the gate of each MOS, and the source and drain of the MOS are arranged sequentially in the second direction; among them, the source of Q7 also serves as the drain of Q11 (such as the two are formed as one piece), the drain of Q9 also serves as the source of Q10, and the source of Q8 also serves as the drain of Q10.

[0125] In an exemplary embodiment of the present disclosure, a first insulating layer and a polysilicon layer are sequentially formed on the substrate, and the polysilicon layer includes a plurality of strip-shaped electrodes extending along a first direction, as shown in FIG8A , wherein:

[0126] In the PMOS region, nine electrodes are sequentially spaced apart in the second direction, wherein the second electrode is the Q12 gate 112, the fourth electrode is the Q11 gate, the fifth electrode is the Q7 gate 107, and the eighth electrode is the Q13 gate 113; in the NMOS region, nine electrodes are sequentially spaced apart in the second direction, wherein the second electrode is the Q9 gate 109, the third electrode is the Q10 gate 110, the fourth electrode is the Q8 gate 108, and the eighth electrode is the Q14 gate 114; the other electrodes in the PMOS region and the NMOS region are all virtual gates 100 and do not have the function of transistor gates;

[0127] The nine electrodes in the PMOS region and the nine electrodes in the NMOS region are arranged opposite each other. Q12 gate 112 is integrally formed with Q9 gate 109, Q11 gate 111 is integrally formed with Q8 gate 108, and Q13 gate 113 is integrally formed with Q14 gate 114. In this document, when a stripe pattern in a polysilicon layer serves as an integrally formed first and second gates, the stripe pattern may be referred to as either the first gate or the second gate.

[0128] In an exemplary embodiment of the present disclosure, as shown in FIG8C , a gate contact layer is formed on the polysilicon layer. The gate contact layer includes a plurality of gate contact electrodes extending along a second direction. The gate contact electrodes include: a first gate contact electrode 301 overlapping the Q7 gate 107; a second gate contact electrode 302 overlapping the Q11 gate 111; a third gate contact electrode 303 overlapping the Q12 gate 112; a fourth gate contact electrode 304 overlapping the Q10 gate 110; a fifth gate contact electrode 305 overlapping the Q14 gate 114; and a sixth gate contact electrode 306 overlapping the dummy gate and connecting the Q12 drain to the Q11 source. In one example, the second gate contact electrode 302, the third gate contact electrode 303, and the sixth gate contact electrode 306 can be located in a PMOS region, with the second gate contact electrode 302 located on the side of the Q11 drain closer to the NMOS region, and the third gate contact electrode 303 located on the side of the Q12 source closer to the NMOS region. Optionally, the second gate contact electrode 302 and the third gate contact electrode 303 are aligned in the second direction; the fourth gate contact electrode 304 is located on the side of the Q10 source and Q10 drain in the NMOS region that is closer to the PMOS region; and optionally, the first gate contact electrode 301 and the fifth gate contact electrode 305 are aligned in the second direction and located between the fourth gate contact electrode 304 and the second gate contact electrode 302. In this context, the two gate contact electrodes are aligned in the second direction, which means that the two stripe patterns that constitute the two gate contact electrodes completely or partially overlap after being infinitely extended in the second direction and in a direction opposite to the second direction.

[0129] In an exemplary embodiment of the present disclosure, as shown in FIG8D to FIG8F , a second insulating layer and a first metal layer are formed on the gate contact layer, and a plurality of first contact holes are formed in the second insulating layer. The first metal layer includes:

[0130] A power connection electrode VCC located on a side of the PMOS region away from the NMOS region, connected to the source of Q12 and the source of Q13 through a first contact hole. In the illustrated example, VCC is located on a side of the PMOS region away from the NMOS region in the first direction (the upper side in the figure), includes a strip-shaped body extending in the second direction, a first branch 409 connected to the source of Q12, and a second branch 410 connected to the source of Q13. The first branch 409 and the second branch 410 may be strip-shaped patterns extending in the first direction.

[0131] A ground connection electrode VSSX is located on a side of the NMOS region away from the PMOS region, connected to the source of Q9 and the source of Q14 through a first contact hole. In the illustrated example, VSSX is located on a side of the NMOS region away from the PMOS region in the first direction (the lower side in the figure), includes a strip-shaped body extending in the second direction, a first branch 408 connected to the source of Q9, and a second branch 411 connected to the source of Q14. The first branch 408 and the second branch 411 may be strip-shaped patterns extending in the first direction.

[0132] a first connection electrode 401, which is connected to the gate 109 of Q9 and the gate 112 of Q12 through the first contact hole and the third gate contact electrode 303, and is used as an input terminal of the clocked inverter;

[0133] A second connecting electrode 402 , connected to the gate 108 of Q8 and the gate 111 of Q11 through the first contact hole and the second gate contact electrode 302 , for receiving clk;

[0134] a third connection electrode 403 , a first end of which is connected to the Q7 gate 107 through the first contact hole and the first gate contact electrode 301 , and a second end of which is connected to the Q10 gate 110 through the first contact hole and the fourth gate contact electrode 304 , for receiving clkb;

[0135] a fourth connection electrode 404, a first end of the fourth connection electrode 404 being connected to the source of Q7 and the drain of Q11 through a first contact hole, and a second end of the fourth connection electrode 404 being connected to the source of Q8 and the drain of Q10 through a first contact hole, and being used as an output end of the transmission gate and an output end of the clocked inverter;

[0136] a fifth connecting electrode 405 , a first end of which is connected to the drain of Q13 through a first contact hole, and a second end of which is connected to the drain of Q14 through a first contact hole, and is used as an output end of the CMOS inverter;

[0137] a sixth connection electrode 406 , connected to the gate 113 of Q13 and the gate 114 of Q14 through the first contact hole and the fifth gate contact electrode 305 , and used as an input terminal of the CMOS inverter;

[0138] The seventh connection electrode 407 has a first end connected to the drain of Q7 through a first contact hole, and a second end connected to the drain of Q8 through a first contact hole, and is used as an input end of the transmission gate.

[0139] In one example, as shown in Figures 8C to 8D, in the second direction, the first contact hole connected to the first gate contact electrode 301 is located between the Q7 gate 107 and the Q11 gate 111; the first contact hole connected to the second gate contact electrode 302 is located between the Q7 gate 107 and the Q11 gate 111; the first contact hole connected to the third gate contact electrode 303 is located between the Q12 gate 112 and the first virtual gate of Q12 away from Q11; the first contact hole connected to the fourth gate contact electrode 304 is located between the Q10 gate 110 and the Q8 gate 108; and the first contact hole connected to the fifth gate contact electrode 305 is located between the first pair of virtual gates and the second pair of virtual gates on the side of the Q13 gate close to Q7. As shown in FIG8E , the first connection electrode 401 , the fifth connection electrode 405 , and the sixth connection electrode 406 are stripe patterns extending along the first direction; the second connection electrode 402 is a stripe pattern extending along the second direction; the third connection electrode 403 and the seventh connection electrode 407 are L-shaped, and the fourth connection electrode 404 is C-shaped;

[0140] The fourth connection electrode 404 and the seventh connection electrode 407 form a rectangular pattern with a gap. The second connection electrode 402 and the third connection electrode 403 are located in the rectangular pattern. The third connection electrode 403 is located on a side of the second connection electrode 402 close to the NMOS region.

[0141] In an example of this embodiment, as shown in Figures 8B to 8D, a first virtual electrode is further provided between the first pair of virtual gates and the second pair of virtual gates on the side of the Q8 gate close to Q14, and the middle portion of the seventh connection electrode is further connected to the first virtual electrode through a first contact hole.

[0142] In an exemplary embodiment of the present disclosure, as shown in FIG8G to FIG8I , a third insulating layer and a second metal layer are formed on the first metal layer, a plurality of second contact holes are formed in the third insulating layer, and the second metal layer includes:

[0143] The ON output line 501 may be located in the NMOS region and is configured to be connected to the first connection electrode 401 and the fifth connection electrode 405 through the second contact hole, so as to connect the input end of the clocked inverter and the output end of the CMOS inverter, and to transmit the output signal of the CMOS inverter to the CMOS inverter. Leading out, such as leading out to the data output terminal of the latch unit;

[0144] The CLK transmission line 502 is configured to be connected to the second connection electrode 402 through the second contact hole;

[0145] The CLKB transmission line 503 is configured to be connected to the third connection electrode 403 through the second contact hole;

[0146] A D transmission line 504 may be located in the PMOS region and is configured to be connected to the fourth connection electrode 404 and the sixth connection electrode 406 respectively through the second contact hole to connect the output terminal of the transmission gate and the output terminal of the clocked inverter to the input terminal of the CMOS inverter;

[0147] The ON output line 501 , the CLKB transmission line 503 , the CLK transmission line 502 , and the D transmission line 504 may be sequentially arranged in the first direction and may be in a stripe pattern extending along the second direction.

[0148] In an exemplary embodiment of the present disclosure, as shown in FIG8J to FIG8K , a fourth insulating layer and a third metal layer are formed on the second metal layer, a plurality of third contact holes are formed in the fourth insulating layer, and the third metal layer includes:

[0149] a CLK connection line 601 , configured to be connected to the CLK transmission line 502 through a third contact hole, so as to introduce the CLK signal into the transmission gate and the clocked inverter through the CLK transmission line 502 ;

[0150] a CLKB connection line 602 , configured to be connected to the CLKB transmission line 503 through a third contact hole, so as to introduce clkb into the transmission gate and the clocked inverter through the CLKB transmission line 503 ;

[0151] The CLK connection lines 601 and the CLKB connection lines 602 may be stripe-shaped patterns extending along the first direction, and the CLK connection lines 601 and the CLKB connection lines 602 may be arranged sequentially in the second direction.

[0152] In some embodiments, the structures of adjacent first latch units and second latch units can be mirror-symmetrical relative to the boundary line extending between the two along the Y-axis, but the present disclosure is not limited to this. The structures of the first latch unit and the second latch unit can conform to the description of the latch unit in this embodiment, but are not required to fully meet the requirements of mirror symmetry.

[0153] The latch circuit, multi-bit latch, and integrated circuit of the above-mentioned embodiments of the present disclosure have at least one of the following advantages: reliable operation, small area, and high efficiency.

[0154] The following is an illustrative description of the preparation process of a multi-bit latch. The "patterning process" referred to in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials; and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be performed by any one or more of spraying, spin coating, and inkjet printing. Etching can be performed by any one or more of dry etching and wet etching, which is not limited in this disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate or other layer of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The components of the "layer" after the patterning process can be called patterns, and the "layer" includes at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the integrated circuit. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0155] In one exemplary embodiment, a method for fabricating a latch unit is described. The latch unit is used to implement a 1-bit latch circuit and includes a transmission gate formed by connecting four PMOS transistors and four NMOS transistors, a clocked inverter, and a CMOS inverter. The connection relationship between the MOS transistors is shown in Figures 8A to 8I and the description above.

[0156] The manufacturing process of the latch unit in this embodiment may include the following steps:

[0157] (1) Forming a substrate on a base. In an exemplary embodiment, a small amount of trivalent elements (such as boron, indium, gallium, or aluminum) can be doped into a silicon substrate to obtain a P-type semiconductor. Then, a small amount of pentavalent elements (such as phosphorus, antimony, arsenic, etc.) can be doped into the region where the PMOS is to be generated to form an n-vell (N well). The n-vell can serve as the substrate for the PMOS, and the remaining region can serve as the substrate for the NMOS.

[0158] (2) Forming polysilicon layer patterns and MOS source and drain regions.

[0159] In an exemplary embodiment, forming a polysilicon layer pattern and the source and drain regions of a MOS electrode may include sequentially depositing a first insulating film and a polysilicon film on a silicon substrate, and patterning the first insulating film and the polysilicon film through a patterning process to form a pattern of a first insulating layer covering the silicon substrate and a pattern of a polysilicon layer disposed on the first insulating layer, as shown in FIG8A . During the patterning process, a grayscale mask may be used for exposure (delineating the polysilicon pattern and the source and drain regions of the MOS electrode). After development, fully exposed areas (without photoresist, corresponding to the source and drain regions) are formed, partially exposed areas (with half the photoresist thickness, corresponding to the areas outside the polysilicon layer pattern, source and drain regions), and unexposed areas (with the photoresist thickness unchanged, corresponding to the polysilicon layer pattern). The pattern of the first insulating layer can define the boundaries of the source and drain regions of the MOS electrode. After development, based on the first insulating layer and the polysilicon layer thereon, and the photoresist barrier, the PMOS region can be doped with P-type to form the PMOS source and drain regions, and the NMOS region can be doped with N-type to form the NMOS source and drain regions. In this step, the polysilicon layer can also be doped simultaneously to convert the higher-resistance polysilicon layer into a lower-resistance conductive layer, forming the gates of multiple transistors.

[0160] In the latch unit, as shown in Figure 8A, the polysilicon layer includes 9 strip patterns, i.e., 9 electrodes, arranged in sequence along the second direction (from left to right in the figure) in the PMOS region. The 9 electrodes themselves extend along the first direction, wherein the first electrode is called the first electrode, the second electrode is called the second electrode, and so on, the ninth electrode is called the ninth electrode. The polysilicon layer also includes 9 strip patterns, i.e., 9 electrodes, arranged in sequence along the second direction in the NMOS region. The 9 electrodes themselves extend along the first direction, wherein the first electrode is called the tenth electrode, the second electrode is called the eleventh electrode, and so on, the ninth electrode is called the eighteenth electrode. The structure and function of these electrodes can be seen in the accompanying drawings and the description in the above embodiment of the latch unit, and will not be repeated here.

[0161] In the example shown in Figure 8A, the gate of Q7 extends from the PMOS region into the NMOS region to facilitate wiring. The gates of the other NMOS electrodes are located in the NMOS region, and the gates of the other PMOS electrodes are located in the PMOS region. The 18 electrodes are arranged in nine columns in the second direction, with each column forming a gate group. For example, the first and tenth electrodes form the first gate group, the second and eleventh electrodes form the second gate group, the third and twelfth electrodes form the third gate group, and so on, with the last gate group consisting of the ninth and eighteenth electrodes. Figure 8A omits the pattern of the insulating layer (such as the field oxide layer or gate oxide layer) between the polysilicon layer and the substrate, which can define the source and drain regions on both sides of the polysilicon layer.

[0162] (3) Forming a trench contact layer (TCN) pattern.

[0163] In an exemplary embodiment, forming a trench contact layer pattern may include depositing a trench contact film on the silicon substrate having the aforementioned pattern formed thereon, and patterning the trench contact film through a patterning process to form a trench contact layer pattern. FIG8B illustrates a TCN pattern formed on both sides of a polysilicon layer. The trench contact layer may be made of polycrystalline silicon (poly-Si). The TCN includes a plurality of contact strips formed on the source and drain regions, which may form the source and drain of the MOS.

[0164] As shown in the figure, the trench contact layer pattern includes first contact strips 201 to fourteenth contact strips 214. In the second direction, the fourteen contact strips are arranged on either side of the corresponding gate, covering the source or drain region, providing a vertical current transmission path. Each contact strip can be a strip-shaped pattern extending along the first direction. Specifically, the first contact strip 201 serves as the drain of Q7; the second contact strip 202 serves as the source of Q7 and the drain of Q11; the third contact strip 203 serves as the source of Q8 and the drain of Q10; the fourth contact strip 204 serves as the drain of Q8; the fifth contact strip 205 serves as the source of Q10 and the drain of Q9; and the sixth contact strip 206 serves as the source of Q9. The seventh contact strip 207 serves as the source of Q11; the eighth contact strip 208 serves as the source of Q12; the ninth contact strip 209 serves as the drain of Q12; the tenth contact strip 210 serves as the source of Q13; the eleventh contact strip 211 serves as the drain of Q13; the twelfth contact strip 212 serves as the drain of Q14; and the thirteenth contact strip 213 serves as the source of Q14. Furthermore, the fourteenth contact strip 214 is located on the side of the dummy gate 100 where DUMMY2 is located, close to Q14. The fourteenth contact strip 214 and the fourth contact strip 204 are connected to the middle dummy gate 100 via the upper pattern, forming a dummy MOS (Dummy MOS) that serves as a filler, labeled Dummy2 in the figure. Similarly, the ninth contact strip 209 and the seventh contact strip 207 are connected to the middle dummy gate 100 via the upper pattern, forming a Dummy MOS, labeled Dummy1.

[0165] (4) Forming a gate contact layer (GCN) pattern.

[0166] In an exemplary embodiment, forming a gate contact layer pattern may include depositing a gate contact film on the silicon substrate having the aforementioned pattern formed thereon, and patterning the gate contact film through a patterning process to form a gate contact layer pattern, as shown in FIG8C . The gate contact layer may be made of a metal material such as copper, and the gate contact layer establishes a stable electrical contact between the upper first metal layer and the underlying polysilicon gate and enables current transmission.

[0167] As shown in FIG8C , the gate contact layer pattern may include six gate contact electrodes, each of which may be a stripe pattern extending along the second direction.

[0168] The first gate contact electrode 301 has a first end overlapping the Q7 gate 107 , and a second end disposed between the Q7 gate 107 and the Q11 gate in the second direction.

[0169] The first end of the second gate contact electrode 302 overlaps the gate of Q11, and the second end is disposed in the second direction between the gate of Q11 and the gate of Q7 107. In the first direction, the second gate contact electrode 302 is closer to the source of Q7 than the first gate contact electrode 301.

[0170] A first end of the third gate contact electrode 303 is overlapped with the Q12 gate 112 , and a second end is arranged in the second direction between the Q12 gate 112 and the first gate group on the side of the Q12 gate 112 away from Q11 .

[0171] The fourth gate contact electrode 304 overlaps the Q10 gate 110. The first end of the fourth gate contact electrode 304 is disposed between the Q9 gate 109 and the Q10 gate 110 in the second direction, and the second end is disposed between the Q8 gate 108 and the Q10 gate 110 in the second direction.

[0172] The fifth gate contact electrode 305 overlaps the Q14 gate 114. A first end of the fifth gate contact electrode 305 is disposed in the second direction between the Q14 gate 114 and the first gate group on the side of Q14 away from Q8, and a second end is disposed in the second direction between the first gate group and the second gate group on the side of Q14 closer to Q8. The fifth gate contact electrode 305 and the first gate contact electrode 301 may be aligned in the second direction. The fifth gate contact electrode 305 may be located in the middle of the latch unit in the first direction, either on one side of the NMOS region, or on one side of the PMOS region, or partially in the PMOS region and partially in the NMOS region.

[0173] The sixth gate contact electrode 306 is located between the Q12 gate 112 and the Q11 gate in the second direction and overlaps the dummy gate 100 at the location of DUMMY1. A first end of the sixth gate contact electrode 306 overlaps the Q12 drain 209, and a second end overlaps the Q11 source 207. The sixth gate contact electrode 306 enables connection between the Q12 drain 209 and the Q11 source 207.

[0174] (5) Form a first contact hole (V0) pattern.

[0175] In an exemplary embodiment, forming the first contact hole pattern may include: depositing a second insulating film on the silicon substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer covering the aforementioned pattern, and providing a plurality of via holes on the second insulating layer, as shown in FIG. 8D .

[0176] The plurality of vias on the second insulating layer may include a first via V1 to a sixteenth via V16, see also FIG8C and FIG8D , wherein: the first via V1 corresponds to the first contact bar 201, the second via V2 corresponds to the second contact bar 202, the third via V3 corresponds to the third contact bar 203, the fourth via V4 corresponds to the fourth contact bar 204, the fifth via V5 corresponds to the sixth contact bar 206, the sixth via V6 corresponds to the eighth contact bar 208, the seventh via V7 corresponds to the tenth contact bar 210, the eighth via V8 corresponds to the eleventh contact bar 211, the ninth via V9 corresponds to the twelfth contact bar 212, the tenth via V10 corresponds to the thirteenth contact bar 213, and the eleventh via V11 corresponds to the fourteenth contact bar 214. The corresponding vias and contact bars have the following relationship: the orthographic projections of the pair of vias on the silicon substrate at least partially overlap with the orthographic projections of the contact bar on the silicon substrate, and the second insulating layer at the via hole locations is removed, exposing the surface of the contact bar. The twelfth via hole V12 and the first gate contact electrode 301, the thirteenth via hole V13 and the second gate contact electrode 302, the fourteenth via hole V14 and the third gate contact electrode 303, the fifteenth via hole V15 and the fourth gate contact electrode 304, and the sixteenth via hole V16 and the fifth gate contact electrode 305 all correspond to each other in position, and the following relationship exists between the corresponding via holes and the gate contact electrodes: the orthographic projection of the via hole on the silicon substrate at least partially overlaps with the orthographic projection of the second end of the gate contact electrode on the silicon substrate, and the second insulating layer at the position of the via hole is removed to expose the surface of the second end of the gate contact electrode.

[0177] (6) Forming a first metal layer (M1) pattern.

[0178] In an exemplary embodiment, forming a first metal layer pattern may include: depositing a first metal film on the silicon substrate on which the aforementioned pattern is formed, patterning the first metal film through a patterning process, and forming a first metal layer pattern on the second insulating layer, as shown in FIG8F , and FIG8E is a schematic diagram of the first metal layer in FIG8F .

[0179] 8E and 8F , the pattern of the first metal layer may include a power line, a ground line, and first to eleventh connection electrodes 401 to 411 , wherein:

[0180] The first connection electrode 401 is connected to the second end of the third gate contact electrode 303 through the fourteenth via hole V14, and is configured as an input electrode (i.e., an input end) of the clocked inverter, and needs to be connected to the ON output electrode of the latch unit;

[0181] The second connection electrode 402 is connected to the second end of the second gate contact electrode 302 through the thirteenth via hole V13. The clk input electrode configured as a transmission gate and a clocked inverter needs to be connected to the CLK input electrode of the latch unit;

[0182] The first end of the third connection electrode 403 is connected to the second end of the first gate contact electrode 301 through the twelfth via hole V12, and the second end is connected to the second end of the fourth gate contact electrode 304 through the fifteenth via hole V15. The clkb input electrode configured as a transmission gate and a clocked inverter needs to be connected to the CLKB input electrode of the latch unit;

[0183] The first end of the fourth connection electrode 404 is connected to the second contact bar 202 through the second via V2, and the second end is connected to the third contact bar 203 through the third via V3. The fourth connection electrode 404 is configured as an output electrode (i.e., an output end) of a transmission gate and a clocked inverter and needs to be connected to an input electrode of a CMOS inverter.

[0184] The first end of the fifth connection electrode 405 is connected to the eleventh contact bar 211 through the eighth via V8, and the second end is connected to the twelfth contact bar 212 through the ninth via V9. It is configured as the output electrode of the CMOS inverter, leading out the output signal ON of the Latch1 circuit, which can be connected to the corresponding signal output terminal of the multi-bit latch;

[0185] The sixth connection electrode 406 is connected to the fifth gate contact electrode 305 through the sixteenth via hole V16. It is configured as the input electrode of the CMOS inverter and needs to be connected to the output electrode of the transmission gate and the output electrode of the clocked inverter;

[0186] The first end of the seventh connection electrode 407 is connected to the first contact bar 201 via the first via V1, the second end is connected to the fourth contact bar 204 via the fourth via V4, and the middle region between the first and second ends is connected to the fourteenth contact bar 214 via the eleventh via V11. The seventh connection electrode 407 is configured as the input electrode of the transmission gate. The 1-bit data signal d of the input latch unit is introduced and can be connected to the corresponding signal input terminal of the multi-bit latch.

[0187] The eighth connection electrode 408 may be a stripe pattern extending along the first direction. A first end of the eighth connection electrode 408 is connected to the ground line, and a second end of the eighth connection electrode 408 is connected to the sixth contact bar 206 via a fifth via V5. Because the sixth contact bar 206 is configured as the source of Q9, the eighth connection electrode 408 connects the source of Q9 to the ground line. The eighth connection electrode 408 and the ground line may be integrally formed.

[0188] The first end of the ninth connection electrode 409 is connected to the power line, and the second end is connected to the eighth contact bar 208 through the sixth via V6. This realizes the connection between the source of Q12 and the power line. The ninth connection electrode 409 and the power line can be formed integrally;

[0189] The first end of the tenth connection electrode 410 is connected to the power line, and the second end is connected to the tenth contact bar 210 through the seventh via V7. This realizes the connection between the source of Q13 and the power line. The tenth connection electrode 410 and the power line can be formed integrally;

[0190] The first end of the eleventh connection electrode 411 is connected to the ground line, and the second end is connected to the thirteenth contact bar 213 through the tenth via V10. This realizes the connection between the source of Q14 and the ground line. The eleventh connection electrode 411 and the ground line can be formed integrally;

[0191] The integrally formed power line VCC, the ninth connection electrode 409 and the tenth connection electrode 410 are collectively referred to as power connection electrodes, and the integrally formed ground line, the eighth connection electrode 408 and the eleventh connection electrode 411 are collectively referred to as ground connection electrodes.

[0192] (7) Form a second contact hole (V1) pattern.

[0193] In an exemplary embodiment, forming the second contact hole pattern may include: depositing a third insulating film on the silicon substrate on which the aforementioned pattern is formed, patterning the third insulating film through a patterning process to form a third insulating layer covering the first metal layer, and providing a plurality of vias on the third insulating layer, as shown in FIG. 8G .

[0194] The multiple vias on the third insulating layer may include a twenty-first via V21 to a twenty-sixth via V26, wherein: the twenty-first via V21 and the first connecting electrode 401, the twenty-second via V22 and the second connecting electrode 402, the twenty-third via V23 and the third connecting electrode 403, the twenty-fourth via V24 and the fourth connecting electrode 404, the twenty-fifth via V25 and the fifth connecting electrode 405, and the twenty-sixth via V26 and the sixth connecting electrode 406 all correspond to each other in position, and the following relationship exists between the corresponding vias and the connecting electrodes: the orthographic projection of the via on the silicon substrate at least partially overlaps with the orthographic projection of the connecting electrode on the silicon substrate, and the third insulating layer at the position of the via V21 is removed to expose the surface of the connecting electrode.

[0195] (8) Forming a second metal layer (M2) pattern.

[0196] In an exemplary embodiment, forming the second metal layer pattern may include depositing a second metal film on the silicon substrate having the aforementioned pattern formed thereon, patterning the second metal film through a patterning process, and forming the second metal layer pattern on the third insulating layer, as shown in FIG8I . FIG8H is a schematic diagram of the second metal layer in FIG8I .

[0197] In an exemplary embodiment, the second metal layer pattern may include an ON output line 501, a CLK transmission line 502, a CLKB transmission line 503, and a d transmission line 504 of the Latch1 circuit. The first end of the ON output line 501 is connected to the first connection electrode 401 through the 21st via V21, and the second end is connected to the fifth connection electrode 405 through the 25th via V25, i.e., the connection to the input electrode of the clocked inverter and the output electrode of the CMOS inverter, for outputting the latched 1-bit data. The CLK transmission line 502 is connected to the second connection electrode 402 through the 22nd via V22. The clk signal can be input to the transmission gate and the clocked inverter. The CLKB transmission line 503 is connected to the third connection electrode 403 through the 23rd via V23. The clkb signal can be input to the transmission gate and the clocked inverter. The first end of the d transmission line 504 is connected to the fourth connection electrode 404 through the 24th via V24, and the second end is connected to the sixth connection electrode 406 through the 26th via V26, which can realize the connection between the output electrode of the transmission gate and the clocked inverter and the input electrode of the CMOS inverter.

[0198] (9) Form a third contact hole (V2) pattern.

[0199] In an exemplary embodiment, forming the third contact hole pattern may include: depositing a fourth insulating film on the silicon substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film through a patterning process to form a fourth insulating layer covering the second metal layer, wherein the fourth insulating layer is provided with a plurality of contact holes, as shown in FIG8J . The plurality of contact holes on the fourth insulating layer may include vias 27 to 28. Vias 28 and 27 are offset in the second direction, such as by the width of at least one MOS active region. The polysilicon-covered channel region of a MOS, and the source and drain regions on both sides of the channel region are collectively referred to as the active region of the MOS.

[0200] (10) Forming a pattern of the third metal layer (M3).

[0201] In an exemplary embodiment, forming the third metal layer pattern may include depositing a third metal film on the silicon substrate having the aforementioned pattern formed thereon, patterning the third metal film through a patterning process, and forming the third metal layer pattern on the fourth insulating layer, as shown in FIG8K . For ease of viewing, FIG8K only illustrates the second metal layer, the third contact hole, and the pattern of the third metal layer of the latch unit.

[0202] The third metal layer pattern may include a CLK connection line 601 and a CLKB connection line 602 of a multi-latch.

[0203] The CLKB connection line 601 can be a strip pattern extending along the first direction and can pass through the latch unit. The CLKB connection line 601 is connected to the CLKB transmission line 503 through the twenty-seventh via V27, and is used to transmit the clkb signal output by the secondary clock unit to the Q7 gate 107 and the Q10 gate 110 in the latch unit.

[0204] The CLK connection line 602 can be a bar pattern extending along the first direction and can pass through the latch unit. The CLK connection line 602 is connected to the CLK transmission line 502 through the twenty-eighth via V28, and is used to transmit the clk signal output by the secondary clock unit to the Q8 gate 108 and Q11 gate 111 in the latch unit.

[0205] The above describes the preparation process of the latch unit. As mentioned above, there are two types of latch units, one is the Latch1 unit and the other is the Latch2 unit. The CLKB transmission line and CLK transmission line on the second metal layer of both need to extend to the adjacent secondary clock unit. The shapes may be slightly different, but both can be produced using the above preparation method. The structure and preparation process shown in this exemplary embodiment are only an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the composition process can be increased or decreased according to actual needs.

[0206] In the following exemplary embodiments, the latching behavior composed of the Buffer1 unit and the Latch1 unit is taken as an example to illustrate the integrated circuit manufacturing method.

[0207] As shown in Figures 9A to 9L, in the Buffer1 unit, Q3 and Q4 are positioned opposite each other in the X direction and their gates are integrally formed. Q3 is located on the side of Q12 close to the Buffer1 unit, and Q4 is located on the side of Q9 close to the Buffer1 unit. In the Y direction, a fourth filling structure DUMMY4 is provided between Q3 and Q12, and a sixth filling structure DUMMY6 is provided between Q4 and Q9. DUMMY4 and DUMMY6 and their right sides can be regarded as the first area where the Latch1 unit is located, and the left sides of DUMMY4 and DUMMY6 can be regarded as the first area where the Buffer1 unit is located. There is also a connecting structure such as a gate contact electrode between the two areas. The third filling structure DUMMY3 is provided at the adjacent position of Q3 away from the side of Q12, and the fifth filling structure DUMMY5 is provided at the adjacent position of Q4 away from the side of Q9. In an exemplary embodiment, in the Y direction, the source of Q3, Q4 is arranged on the side of the gate of Q3, Q4 close to the adjacent latch unit (the direction from the gate to the source is consistent with the Y direction), and the drain of Q3, Q4 is arranged on the side of the gate of Q3, Q4 away from the adjacent latch unit.

[0208] The preparation process of the latch row composed of the Buffer1 unit and the Latch1 unit in this embodiment may include the following steps. The preparation process of the latch unit has been described in detail above. Here, the preparation process of the Buffer1 unit in the latch row and the relationship between the Buffer1 unit and the Latch1 unit are supplemented based on the preparation process of the latch unit:

[0209] (1) A substrate is formed on a base.

[0210] In this exemplary embodiment, a P-type doped silicon substrate is used as the NMOS substrate, and an N-vell is used as the PMOS substrate. The PMOS transistor Q3 of the Buffer 1 unit and the four PMOS transistors of the Latch 1 unit are built on the same N-vell N-type substrate. The NMOS transistor Q4 of the Buffer 1 unit and the four NMOS transistors of the Latch 1 unit are built on a P-type substrate composed of a P-type doped silicon substrate.

[0211] (2) Forming polysilicon layer patterns and MOS source and drain regions.

[0212] The method of forming the polysilicon layer pattern is described in the preparation method of the latch unit and will not be described in detail.

[0213] As shown in Figure 9A, the polysilicon layer of the Buffer1 unit includes three strip patterns arranged in sequence along the Y direction in the PMOS region and three strip patterns arranged in sequence along the Y direction in the CMOS region. The six strip patterns themselves extend along the X direction and are called the nineteenth electrode to the twenty-fourth electrode, wherein: the nineteenth electrode serves as a virtual gate 100; the twentieth electrode serves as a virtual gate 100 (marked with DUMMY3); the twenty-first electrode serves as the Q3 gate 103; the twenty-second electrode and the twenty-third electrode (marked with DUMMY5) both serve as virtual gates 100; the twenty-third electrode serves as a virtual gate 100; the twenty-fourth electrode serves as the Q4 gate 104, and the Q3 gate and the Q4 gate are formed as one piece; in addition, DUMMY4 includes the first electrode in the Latch1 unit, DUMMY6 includes the tenth electrode in the Latch1 unit, and the first electrode and the second electrode are also virtual gates 100.

[0214] (3) Forming a trench contact layer (TCN) pattern.

[0215] The method of forming the trench contact layer pattern is described in the preparation method of the latch unit and will not be described in detail.

[0216] In the Buffer1 unit, the TCN pattern includes the fifteenth contact strip 215 to the twentieth contact strip 220. In the Y direction, the six contact strips are respectively arranged on both sides of the corresponding gate and cover the source region or drain region at the location to provide a current transmission path in the vertical direction. Each contact strip can be a strip pattern extending along the X direction. As shown in Figure 9B: the fifteenth contact strip 215 serves as the source of Q4; the sixteenth contact strip 216 serves as the drain of Q4; the seventeenth contact strip 217 can be connected to the drain of Q4 through the upper pattern; the eighteenth contact strip 218 serves as the source of Q3; the nineteenth contact strip 219 serves as the drain of Q3; and the twentieth contact strip 220 can be connected to the drain of Q3 through the upper pattern.

[0217] The twentieth contact strip 220 and the seventeenth contact strip 217 may be used as virtual electrodes and do not have the function of a source or a drain of a MOS tube, but may be used for connection.

[0218] (4) Forming a gate contact layer (GCN) pattern.

[0219] The method of forming the gate contact layer pattern is described in the preparation method of the latch unit and will not be described in detail.

[0220] In the Buffer1 unit, the gate contact layer pattern may include five gate contact electrodes, from the seventh gate contact electrode 307 to the eleventh gate contact electrode 311, each of which may be a stripe pattern extending along the Y direction. Specifically, the middle portion of the seventh gate contact electrode 307 overlaps the dummy gate 100 at the DUMMY3 position, with its ends respectively connected to the drain of Q3 and the twentieth contact strip 220; the middle portion of the eighth gate contact electrode 308 overlaps the dummy gate 100 at the DUMMY4 position, with its ends respectively connected to the source of Q3 and the source of Q12; the middle portion of the ninth gate contact electrode 309 overlaps the dummy gate 100 at the DUMMY6 position, with its ends respectively connected to the source of Q4 and the source of Q9; the middle portion of the tenth gate contact electrode 310 overlaps the dummy gate 100 at the DUMMY5 position, with its ends respectively connected to the drain of Q4 and the seventeenth contact strip 217; and the middle portion of the eleventh gate contact electrode 311 overlaps the gate 104 of Q4. The eleventh gate contact electrode 311 and the first gate contact electrode 301 may be aligned in the X direction (their X coordinate ranges at least partially overlap) to facilitate routing of subsequently formed metal layers.

[0221] (5) Form a first contact hole (V0) pattern.

[0222] The method of forming the first contact hole pattern is described in the preparation method of the latch unit and will not be described in detail, as shown in FIG9D .

[0223] In the Buffer1 unit, the multiple vias on the second insulating layer may include seventeenth vias V17 to nineteenth vias V19. As an example, please refer to Figures 9C and 9D simultaneously, wherein: the second insulating layer at the position of the seventeenth via V17 is removed, exposing the surface of the eleventh gate contact electrode 311. The seventeenth via V17 and the twelfth via V12 can be aligned in the Y direction. The second insulating layer at the position of the eighteenth via V18 is removed, exposing the surface of the seventeenth contact strip 217. The second insulating layer at the position of the nineteenth via V19 is removed, exposing the surface of the twentieth contact strip 220.

[0224] (6) Forming a first metal layer (M1) pattern.

[0225] The method of forming the first metal layer pattern is described in the preparation method of the latch unit, which will not be repeated here, as shown in FIG9F . FIG9E is a schematic diagram of the first metal layer in FIG9F .

[0226] In the Buffer1 unit, the pattern of the first metal layer may include a power connection electrode (also known as a power line) VCC, a ground connection electrode (also known as a ground line) VSSX, a twelfth connection electrode 412, and a thirteenth connection electrode 413. The twelfth connection electrode 412 is connected to the gate contact electrode 311 through the seventeenth via V17 and is configured as the clkout input electrode (i.e., the input terminal) of the CMOS inverter formed by the connection of Q3 and Q4. The first end of the thirteenth connection electrode 413 is connected to the seventeenth contact layer 217 through the eighteenth via V18. The second end is connected to the twentieth contact layer 220 through the nineteenth via V19 and is configured as the clk output electrode of the CMOS inverter formed by the connection of Q3 and Q4, which can serve as the output terminal of the CMOS inverter.

[0227] If it is in the latch row composed of the Buffer2 unit and the Latch2 unit, please refer to the Buffer2 unit in the lower left corner of Figure 10A. Since the PMOS in the Buffer2 unit is Q5 and the NMOS is Q6, the input end of the CMOS formed by the connection of Q5 and Q6 is used to receive clk, and the output end is used to output clkb. The twelfth connecting electrode 412 can be used as the clk input electrode of the CMOS inverter, and the thirteenth connecting electrode 413 can be used as the clkb output electrode, which is the output end of the CMOS inverter. In an exemplary embodiment, the structure of the first metal layer and the layers below the Buffer1 unit and the Buffer2 unit can be mirror-symmetric about the boundary line along the Y direction, and there may be some differences in other layers. The latch row composed of the Buffer1 unit + Latch1 unit and the latch row composed of the Buffer2 unit + Latch2 unit are put together below to describe the subsequent processes of the Buffer1 unit and the Buffer2 unit.

[0228] (7) Form a second contact hole (V1) pattern.

[0229] The method of forming the second contact hole pattern is described in the preparation method of the latch unit and will not be described in detail, as shown in FIG10A .

[0230] In the Buffer 1 unit, the third insulating layer includes via holes 27 to 28, wherein the third insulating layer at the location of the 27th via hole V27 is removed, exposing the surface of the 13th connecting electrode 413. The third insulating layer at the location of the 28th via hole V28 is removed, exposing the surface of the 12th connecting electrode 412.

[0231] In the Buffer2 unit, the third insulating layer includes via holes 27 through 28, wherein the third insulating layer at the location of the 27th through 27th via holes V27' is removed, exposing the surface of the 13th connecting electrode 413. The third insulating layer at the location of the 28th through 28' is removed, exposing the surface of the 12th connecting electrode 412.

[0232] In an exemplary embodiment, as shown in Figures 10A to 10E, the twenty-seventh via V27' in the Buffer2 unit is closer to the side of the NMOS region away from the PMOS region relative to the twenty-seventh via V27 in the Buffer1 unit. The thirteenth connecting electrode 413 in the Buffer2 unit that overlaps with the twenty-seventh via V27' is used as the clkb output electrode and needs to be connected to the CLKB transmission line 503 in the Latch2 unit through the twenty-seventh via V27'; while the thirteenth connecting electrode 413 in the Buffer1 unit that overlaps with the twenty-seventh via V27 is used as the clk output electrode and needs to be connected to the CLK transmission line 502 in the Latch1 unit through the twenty-seventh via V27. As shown in the figure, the twenty-seventh via V27' in the Buffer2 unit and the CLKB transmission line 503 in the Latch2 unit can be aligned in the X direction (the ranges of the X-axis coordinates of the two at least partially overlap).

[0233] Similarly, the twenty-eighth via V28' in the Buffer2 unit is closer to the side of the PMOS region away from the NMOS region than the twenty-eighth via V28 in the Buffer1 unit. The twelfth connection electrode 412 in the Buffer2 unit that overlaps with the twenty-eighth via V28' is used as the clk input electrode and needs to be connected to the CLK transmission line 502 in the Latch2 unit through the twenty-eighth via V28'; while the twelfth connection electrode 412 in the Buffer1 unit that overlaps with the twenty-eighth via V28 serves as the clkout input electrode and needs to be connected to the CLKOUT connection line of the third metal layer of this unit through the third contact hole (see Figure 10E). As shown in the figure, the twenty-eighth via V28' in the Buffer2 unit and the CLK transmission line 502 in the Latch2 unit can be aligned in the X direction.

[0234] (8) Forming a second metal layer (M2) pattern.

[0235] The method of forming the second metal layer pattern is described in the latch unit manufacturing method, which will not be described in detail, as shown in Figure 10C. Figure 10B is a schematic diagram of the second metal layer in Figure 10C.

[0236] In the Buffer1 unit, as shown in FIG10C , the pattern of the second metal layer of the Buffer1 unit includes a CLKOUT lead-in line 505 and a CLK lead-out line 506 of the Buffer1 unit. The CLKOUT lead-in line 505 can be connected to the twelfth connecting electrode 412 through the twenty-eighth via V28. The CLKOUT lead-in line 505 can introduce the clkout signal output by the primary clock circuit into the Q3 gate and Q4 gate in the Buffer1 unit as the input clock signal of the primary clock circuit. The CLKOUT lead-in line 505 and the CLKB transmission line 503 in the Latch1 unit can be aligned in the X direction. The CLK lead-out line 506 can be integrally formed with the CLK transmission line 502 of the Latch1 unit. The CLK lead-out line 506 is connected to the thirteenth connecting electrode 413 through the twenty-seventh via V27, and can transmit the clk signal output by the CMOS inverter of the Buffer1 unit to the CLK transmission line 502.

[0237] In the Buffer2 unit, in an exemplary embodiment, as shown in FIG10C , the pattern of the second metal layer of the Buffer2 unit includes a CLK lead-in line 508 and a CLKB lead-out line 507 of the Buffer2 unit.

[0238] The CLK lead-in line 508 can be integrally formed with the CLK transmission line 502 of the Latch2 unit. The CLK lead-in line 508 is connected to the twelfth connection electrode 412 through the twenty-eighth via V28', and can lead the clk signal output by the CMOS inverter of the Buffer1 unit to the input terminals of the CMOS inverter in the Buffer1 unit, namely, the gates Q3 and Q4.

[0239] The CLKB lead line 507 can be integrally formed with the CLKB transmission line 503 of the Latch1 unit. The CLKB lead line 507 is connected to the thirteenth connection electrode 413 through the twenty-seventh via hole V27 ′ and can transmit the clkb signal output by the CMOS inverter of the Buffer2 unit to the CLKB transmission line 503 .

[0240] The CLKOUT lead-in line and the CLK lead-out line in the Buffer1 unit and the Buffer2 unit may both be stripe patterns extending along the Y direction.

[0241] A schematic diagram of the B1L1 latch row and the B2L2 latch row stacked from the substrate to the second metal layer is shown in FIG10C .

[0242] (9) Form a third contact hole (V2) pattern.

[0243] The method of forming the third contact hole pattern is described in the preparation method of the latch unit and will not be described in detail, as shown in FIG10D .

[0244] In the Buffer1 unit, the contact holes on the fourth insulating layer include a thirty-first via hole V31, and the fourth insulating layer at the location of the thirty-first via hole V31 is removed to expose the surface of the CLKOUT lead-in line 505. The third contact hole may not be provided in the Buffer2 unit.

[0245] (10) Forming a pattern of the third metal layer (M3).

[0246] The method of forming the third metal layer pattern is described in the latch unit manufacturing method, which is not described in detail, as shown in Figure 10E. For ease of viewing, Figure 10E only shows the second metal layer, the third contact hole and the pattern of the third metal layer, as well as part of the second contact hole.

[0247] In the Buffer1 unit, the pattern of the third metal layer may include a CLKOUT connection line 603 of the multi-way latch. The CLKOUT connection line 603 may be a strip pattern extending along the X direction. The CLKOUT connection line 603 is connected to the CLKOUT lead-in line 505 through the thirty-first via V31, and is used to transmit the clkout signal output by the primary clock unit to the input end of the COMS in the Buffer1 unit. If there are other Buffer1 units of the latch group on the side of the Buffer1 unit away from the fill row, the CLKOUT connection line 603 may pass through the Buffer1 unit. If there are no other Buffer1 units of the latch group on the side of the Buffer1 unit away from the latch row, the CLKOUT connection line 603 extends to the thirty-first via V31 in the Buffer1 unit and ends. If there is a Buffer1 unit on the side of the Buffer2 unit away from the Decap unit, the Buffer2 unit is provided with a CLKOUT connection line 603 on the third metal layer to transmit clkout. If not, the third metal layer pattern may not be provided.

[0248] The above Figures 10A to 10E show the situation where the latch row of the Latch1 unit of the Buffer1 unit is on the top, and the latch row composed of the Buffer2 unit and the Latch2 unit is on the bottom. In the multi-way latch, there is also a situation where the B1L1 latch row is on the bottom and the B2L2 unit is on the top. As shown in Figures 11A to 11E, the basic structure of the Buffer1 unit and the Buffer2 unit can remain unchanged. Considering these two latch rows as a whole, the wiring can be adjusted.

[0249] In a multi-way latch, when a primary clock unit and a Latch2 unit are combined, the structure of the primary clock unit and the Buffer2 unit in the first metal layer and the layers below can be essentially the same. Q5 needs to be replaced with Q1, and Q6 needs to be replaced with Q2. As shown in Figures 12A and 12B, the first metal layer pattern of the primary clock unit includes a twelfth connecting electrode 412 and a thirteenth connecting electrode 413. The input clock signal clkin of the primary clock circuit can be transmitted from the clk signal input terminal of the multi-way latch to the twelfth connecting electrode 412. The thirteenth connecting electrode 413 extends in the X direction and is used to transmit the clkout signal output by the primary clock unit to the CLKOUT connecting line 603.

[0250] In the primary clock unit, when forming the third contact hole (V2) pattern, a twenty-ninth via hole V29 and a thirtieth via hole V30 can be formed to overlap the thirteenth connection electrode 413. These two via holes are located in the PMOS region and the NMOS region, respectively, as shown in FIG12B. When forming the second metal layer (M2) pattern, a first CLKOUT lead line 510 and a second CLKOUT lead line 509 can be formed. The first CLKOUT lead line 510 is connected to the thirteenth connection electrode 413 through the twenty-ninth via hole V29, and the second CLKOUT lead line 509 is connected to the thirteenth connection electrode 413 through the thirtieth via hole V30. As shown in Figure 12C, the first CLKOUT lead-out line 510 and the second CLKOUT lead-out line 509 are both used to lead out the clkout signal. One end of the first CLKOUT lead-out line 510 is connected to the twenty-ninth via V29, and the other end extends along the Y direction to a position where it can intersect with the CLKOUT connection line 603; one end of the second CLKOUT lead-out line 509 is connected to the thirtieth via V30, and the other end also extends along the Y direction to a position where it can intersect with the CLKOUT connection line 603.

[0251] In the primary clock unit, when forming the fourth contact hole ( V2 ) pattern, a thirty-second via hole V32 and a thirty-third via hole V33 connected to the CLKOUT connection line 603 may be formed, as shown in FIG. 12B .

[0252] In the first-level clock unit, when forming the third metal layer (M3) pattern, two CLKOUT connection lines 603 can be formed. The first CLKOUT connection line 603 is connected to the first CLKOUT lead line 510 through the thirty-third via V33, and the clkout signal is transmitted to the Buffer1 unit on the side away from the Decap unit. The second CLKOUT connection line 603 is connected to the second CLKOUT lead line 509 through the thirty-second via V32, and the clkout signal is transmitted to the Buffer1 unit on the side close to the Decap unit. As shown in Figure 12C. The CLKB connection line 602 and the CLB connection line 601 in the figure are used to transmit the clk signal and clkb signal output by the upper Buffer1 unit and Buffer2 unit to the Latch2 unit of this latch row, and do not need to pass through the Latch2 unit. In another embodiment, the first-level clock unit can also be combined with the Latch1 unit in a latch row. The relevant structure can be seen in Figures 12A to 12c, which will not be repeated here.

[0253] In the above exemplary embodiments, each metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals.

[0254] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment and is well compatible with existing preparation processes. The process is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0255] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments.

[0256] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A latch unit, comprising a substrate and eight MOSs. The substrate includes an NMOS region and a PMOS region, and the direction from the NMOS region to the PMOS region is the first direction; four PMOS transistors Q12, Q11, Q7, and Q13 are sequentially arranged in the PMOS region along the second direction, and four NMOS transistors Q9, Q10, Q8, and Q14 are sequentially arranged in the NMOS region along the second direction. The second direction intersects the first direction; wherein: Q7 and Q8 are connected to form a transmission gate, Q9, Q10, Q11, and Q12 are connected to form a clocked inverter, and Q13 and Q14 are connected to form a CMOS inverter; and Q12 and Q9, Q11 and Q8, Q13 and Q14 are respectively arranged opposite to each other, and the gates of the two opposite MOSs are connected to each other; filling structures are formed at the positions opposite to Q10 in the PMOS region and at the positions opposite to Q7 in the NMOS region, and filling structures are formed between Q7 and Q13 and between Q8 and Q14; The transmission gate blocks or outputs the input 1-bit data d to the input end of the CMOS inverter based on clk and clkb; the CMOS inverter inverts d to obtain the inverted signal Output to the input terminal of the clocked inverter, and the clocked inverter is based on clk and clkb to Block or transfer After inversion, it is output to the input end of the CMOS inverter; wherein, clk and clkb are both clock signals input to the latch unit, and clkb is the inverted signal of clk.

2. The latch unit according to claim 1, wherein: The gate of each of the eight MOSs extends along the first direction, the source and drain of the MOS are formed on both sides of the MOS gate, and the source to drain of the MOS are sequentially arranged in the second direction; wherein, the source of Q7 is simultaneously the drain of Q11, the drain of Q9 is simultaneously the source of Q10, and the source of Q8 is simultaneously the drain of Q10.

3. The latch unit according to claim 2, wherein: A first insulating layer and a polysilicon layer are sequentially formed on the substrate. The polysilicon layer includes a plurality of strip-shaped electrodes extending along the first direction, wherein: Nine electrodes are sequentially arranged at intervals in the second direction in the PMOS region. The second electrode is the gate of Q12, the fourth electrode is the gate of Q11, the fifth electrode is the gate of Q7, and the eighth electrode is the gate of Q13; nine electrodes are sequentially arranged at intervals in the second direction in the NMOS region. The second electrode is the gate of Q9, the third electrode is the gate of Q10, the fourth electrode is the gate of Q8, and the eighth electrode is the gate of Q14; the other electrodes in the PMOS region and the NMOS region are all dummy gates; The nine electrodes in the PMOS region and the nine electrodes in the NMOS region are arranged opposite to each other one by one. The gate of Q12 and the gate of Q9 are integrally formed, the gate of Q11 and the gate of Q8 are integrally formed, and the gate of Q13 and the gate of Q14 are integrally formed.

4. The latch unit according to claim 3, wherein: A gate contact layer is formed on the polysilicon layer. The gate contact layer includes a plurality of gate contact electrodes extending along the second direction. The gate contact electrodes include: A first gate contact electrode overlapping with the gate of Q7; a second gate contact electrode overlapping with the gate of Q11; a third gate contact electrode overlapping with the gate of Q12; a fourth gate contact electrode overlapping with the gate of Q10; a fifth gate contact electrode overlapping with the gate of Q14; and a sixth gate contact electrode overlapping with the dummy gate and connecting the drain of Q12 to the source of Q11; Wherein, the second gate contact electrode, the third gate contact electrode and the sixth gate contact electrode are located in the PMOS region. The second gate contact electrode is located on the side of the drain of Q11 close to the NMOS region, the third gate contact electrode is located on the side of the source of Q12 close to the NMOS region, and the second gate contact electrode and the third gate contact electrode are aligned in the second direction; the fourth gate contact electrode is located on the side of the source and drain of Q10 in the NMOS region close to the PMOS region; the first gate contact electrode and the fifth gate contact electrode are aligned in the second direction and are located between the fourth gate contact electrode and the second gate contact electrode.

5. The latch unit according to claim 4, wherein: A second insulating layer and a first metal layer are formed on the gate contact layer. The second insulating layer is formed with a plurality of first contact holes. The first metal layer includes: A power connection electrode located on the side of the PMOS region away from the NMOS region, and the power connection electrode is connected to the source of Q12 and the source of Q13 through the first contact hole; A ground connection electrode located on the side of the NMOS region away from the PMOS region, and the ground connection electrode is connected to the source of Q9 and the source of Q14 through the first contact hole; A first connection electrode, which is connected to the gates of Q9 and Q12 through the first contact hole and the third gate contact electrode and is used as the input end of the clocked inverter; A second connection electrode, which is connected to the gates of Q8 and Q11 through the first contact hole and the second gate contact electrode and is used to receive clk; A third connection electrode, the first end of which is connected to the gate of Q7 through the first contact hole and the first gate contact electrode, and the second end of which is connected to the gate of Q10 through the first contact hole and the fourth gate contact electrode and is used to receive clkb; A fourth connection electrode, the first end of which is connected to the source of Q7 and the drain of Q11 through the first contact hole, and the second end of which is connected to the source of Q8 and the drain of Q10 through the first contact hole and is used as the output end of the transmission gate and the output end of the clocked inverter; A fifth connection electrode, the first end of which is connected to the drain of Q13 through the first contact hole, and the second end of which is connected to the drain of Q14 through the first contact hole and is used as the output end of the CMOS inverter; A sixth connection electrode, which is connected to the gates of Q13 and Q14 through the first contact hole and the fifth gate contact electrode and is used as the input end of the CMOS inverter; A seventh connection electrode, the first end of which is connected to the drain of Q7 through the first contact hole and the second end of which is connected to the drain of Q8 through the first contact hole and is used as the input end of the transmission gate.

6. The latch unit according to claim 5, wherein: The first contact hole connected to the first gate contact electrode is located between the Q7 gate and the Q11 gate in the second direction; The first contact hole connected to the second gate contact electrode is located between the Q7 gate and the Q11 gate in the second direction; The first contact hole connected to the third gate contact electrode is located between the Q12 gate and the first dummy gate on the side of Q12 away from Q11 in the second direction; The first contact hole connected to the fourth gate contact electrode is located between the Q10 gate and the Q8 gate in the second direction; The first contact hole connected to the fifth gate contact electrode is located between the first pair of dummy gates and the second pair of dummy gates on the side of the Q13 gate close to Q7 in the second direction.

7. The latch unit according to claim 5, wherein: The first connection electrode, the fifth connection electrode, and the sixth connection electrode are strip-shaped patterns extending in the first direction; the second connection electrode is a strip-shaped pattern extending in the second direction; the third connection electrode and the seventh connection electrode are L-shaped, and the fourth connection electrode is C-shaped; The fourth connection electrode and the seventh connection electrode enclose a rectangular pattern with a notch, the second connection electrode and the third connection electrode are located within the rectangular pattern, and the third connection electrode is located on the side of the second connection electrode close to the NMOS region.

8. The latch unit according to claim 7, wherein: A first dummy electrode is further provided between the first pair of dummy gates and the second pair of dummy gates on the side of the Q8 gate close to Q14, and the middle of the seventh connection electrode is further connected to the first dummy electrode through a first contact hole.

9. The latch unit according to claim 5, wherein: A third insulating layer and a second metal layer are formed on the first metal layer, the third insulating layer is formed with a plurality of second contact holes, and the second metal layer includes: The ON output line, located in the NMOS region, is configured to be connected to the first connection electrode and the fifth connection through the second contact hole The access electrodes are respectively connected to connect the input end of the clocked inverter and the output end of the CMOS inverter, and the output signal of the CMOS inverter Lead out; The CLK transmission line is configured to be connected to the second connection electrode through the second contact hole; The CLKB transmission line is configured to be connected to the third connection electrode through the second contact hole; The D transmission line, located in the PMOS region, is configured to be connected to the fourth connection electrode and the sixth connection electrode respectively through the second contact hole to connect the output end of the transmission gate and the output end of the clocked inverter to the input end of the CMOS inverter; The ON output line, the CLKB transmission line, the CLK transmission line, and the D transmission line are arranged in sequence in the first direction and are all strip-shaped patterns extending in the second direction.

10. The latch unit according to claim 9, wherein: A fourth insulating layer and a third metal layer are formed on the second metal layer, the fourth insulating layer is formed with a plurality of third contact holes, and the third metal layer includes: The CLK connection line is configured to be connected to the CLK connection line through the third contact hole to introduce clk into the transmission gate and the clocked inverter through the CLK transmission line; The CLKB connection line is configured to be connected to the CLKB transmission line through the third contact hole to introduce clkb into the transmission gate and the clocked inverter through the CLKB transmission line; Both the CLK connection line and the CLKB connection line are strip patterns extending in the first direction and are arranged in sequence in the second direction.

11. A multi-bit latch, comprising a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group sequentially arranged on a substrate in the X direction. Each latch group includes 8 latch rows sequentially arranged in the X direction, and each latch row includes a latch unit, where: A latch row adjacent to the fill row is further provided with a primary clock unit, and the primary clock unit is configured to receive a clock signal clkin and output an inverted signal clkout of clkin; Two latch rows at the middle position of each latch group are each further provided with a secondary clock unit. One secondary clock unit is configured to receive clkout and output an inverted signal clk of clkout, and the other secondary clock unit is configured to receive clk and output an inverted signal clkb of clk; The latch unit is configured to latch and output the input 1-bit data based on clk and clkb; The primary clock unit and the latch units in the same latch row are arranged in sequence in the Y direction, and the secondary clock unit and the latch units in the same latch row are all arranged in sequence in the Y direction, and the Y direction and the X direction intersect.

12. The multi-bit latch according to claim 11, wherein: Each latch row is divided into a first region and a second region arranged in the Y direction; The latch units are all arranged in the second region of the latch row where they are located. The input signals b, clk, and clkb of all latch units are input from the side close to the first region, and the latched 1-bit data is output from the side far from the first region; The primary clock unit and the secondary clock unit are both arranged in the first region of the latch row where they are located; except for the latch rows provided with the primary clock unit and the secondary clock unit, the first regions of other latch rows are provided with fill units.

13. The multi-bit latch according to claim 11, wherein: The width W of each latch row in the X direction is equal, and the length L of each latch row in the Y direction is equal, 0.486μm ≤ W ≤ 0.594μm, 1.1664μm ≤ L ≤ 1.4256μm; The fill row uses Decap units, and the width of the Decap unit in the X direction is equal to W, and the length in the Y direction is equal to L.

14. The multi-bit latch according to claim 11, wherein: The latch unit uses the latch unit according to any one of claims 1 to 10; PMOS regions and NMOS regions are formed on the substrates of the first region and the second region of each latch row; among any two adjacent latch rows, the NMOS region and the PMOS region of one latch row are arranged in sequence in the X direction, and the first direction of the latch unit in this latch row is the same as the X direction, which is called the first latch unit; the NMOS region and the PMOS region of the other latch row are arranged in sequence in the opposite direction of the X direction, and the first direction of the latch unit in this latch row is the same as the opposite direction of the X direction, which is called the second latch unit; The second directions of the first latch unit and the second latch unit are both the same as the Y direction, and the transistor positions of the first latch unit and the second latch unit in adjacent two latch rows are mirror-symmetrical with respect to the boundary line extending along the Y direction of the two latch rows.

15. The multi-bit latch according to claim 14, wherein: Both of the two secondary clock units include a PMOS disposed in the PMOS region of the first area of the latch row where it is located and an NMOS disposed in the NMOS region of the first area of the latch row where it is located. The NMOS region and the PMOS region of one of the secondary clock units are arranged in sequence in the X direction, and it is called the first secondary clock unit; The other secondary clock unit has its NMOS region and PMOS region arranged in sequence in the opposite direction of the X direction, and it is called the second secondary clock unit; The PMOS of the first secondary clock unit is the third transistor Q3, and the NMOS is the fourth transistor Q4. Q3 and Q4 are connected to form a CMOS inverter to receive clkout and output clk; the PMOS transistor of the second secondary clock unit is the fifth transistor Q5, and the NMOS is the sixth transistor Q6. Q5 and Q6 are connected to form a CMOS inverter to receive clk and output clkb.

16. The multi-bit latch according to claim 15, wherein: In the direction perpendicular to the substrate, the multi-bit latch includes a polysilicon layer, the source and drain regions of the MOS, a trench contact layer, a gate contact layer, a first contact hole, a first metal layer, a second contact hole, a second metal layer, a third contact hole, and a third metal layer formed in sequence on the substrate; The clock signal lines between different latch rows are disposed on the third metal layer. The clock signal lines transmitted between the first clock unit and the latch unit, and between the second clock unit and the latch unit in the same latch row are disposed on the second metal layer. The connections between the first clock unit, the second clock unit, and the internal transistors of the latch unit are disposed on the first metal layer and the second metal layer, or are disposed on the gate contact layer, the first metal layer, and the second metal layer; The latch units in the two latch rows adjacent to the filling row are the first latch unit or the second latch unit.

17. The multi-bit latch according to claim 15, wherein: A first insulating layer and a polysilicon layer are formed in sequence on the substrate of the secondary clock unit. The polysilicon layer includes: 3 electrodes extending in the X direction in the PMOS region. The 3 electrodes are spaced apart from each other in the Y direction. The third electrode is used as the PMOS gate, and the other 2 electrodes are dummy gates; 3 electrodes extending in the X direction in the NMOS region. The 3 electrodes are spaced apart from each other in the Y direction. The third electrode is used as the NMOS gate, and the other 2 electrodes are dummy gates; The 3 electrodes in the PMOS region and the 3 electrodes in the NMOS region are arranged opposite to each other in the Y direction, and the PMOS gate and the NMOS gate are integrally formed.

18. The multi-bit latch according to claim 17, wherein: In the secondary clock unit, in the Y direction, a PMOS drain and a PMOS source are respectively formed on both sides of the PMOS gate, and an NMOS drain and an NMOS source are respectively formed on both sides of the NMOS gate, and the PMOS drain and the PMOS source, and the NMOS drain and the NMOS source are arranged in sequence in the Y direction; In the secondary clock unit, in the Y direction, a second virtual electrode is provided between the first virtual gate and the second virtual gate on the side of the PMOS gate away from the latch unit, and a third virtual electrode is provided between the first virtual gate and the second virtual gate on the side of the NMOS gate away from the latch unit.

2. The multi-bit latch according to claim 1, wherein: In the secondary clock unit, a gate contact layer is formed on the polysilicon layer, and the gate contact layer includes a plurality of gate contact electrodes extending in the Y direction, and the gate contact electrodes include: A seventh gate contact electrode that overlaps with the virtual gate and connects the PMOS drain and the second virtual electrode, an eighth gate contact electrode that overlaps with the virtual gate and connects the PMOS source and the Q12 source, a ninth gate contact electrode that overlaps with the virtual gate and connects the NMOS source and the Q9 source, a tenth gate contact electrode that overlaps with the virtual gate and connects the third virtual electrode and the NMOS drain, and an eleventh gate contact electrode that overlaps with the NMOS gate and the PMOS gate; Among them, the seventh gate contact electrode and the eighth gate contact electrode are located in the PMOS region, and the ninth gate contact electrode and the tenth gate contact electrode are located in the NMOS region; in the X direction, the eleventh gate contact electrode is located between the seventh gate contact electrode and the tenth gate contact electrode, and is also located between the eighth gate contact electrode and the ninth gate contact electrode.

3. The multi-bit latch according to claim 2, wherein: In the secondary clock unit, a second insulating layer and a first metal layer are formed on the gate contact layer, the second insulating layer is formed with a plurality of first contact holes, and the first metal layer includes: A power connection electrode located on the side of the PMOS region away from the NMOS region, and the power connection electrode is connected to the power connection electrode in the latch unit of the same latch row; A ground connection electrode located on the side of the NMOS region away from the PMOS region, and the ground connection electrode is connected to the ground connection electrode in the latch unit of the same latch row; A twelfth connection electrode connected to the PMOS gate and the NMOS gate through the first contact hole and the eleventh gate contact electrode, and the twelfth connection electrode is used as the input end of the CMOS inverter in the secondary clock unit; A thirteenth connection electrode connected to the second virtual electrode and the third virtual electrode through the first contact hole, and the thirteenth connection electrode is used as the output end of the CMOS inverter in the secondary clock unit; The first contact hole connected to the eleventh gate contact electrode is located in the Y direction between the PMOS gate and the first virtual gate on the side of the PMOS gate away from the latch unit; the twelfth connection electrode and the thirteenth connection electrode are strip-shaped patterns extending in the X direction, and the twelfth connection electrode is located between the thirteenth connection electrode and the latch unit of the same latch row. ​ 21. The multi-bit latch according to claim 20, wherein: In the secondary clock unit, a third insulating layer and a second metal layer are formed on the first metal layer, and a plurality of second contact holes are formed in the third insulating layer; wherein: The second metal layer in the first secondary clock unit includes: a CLKOUT lead wire configured to be connected to the twelfth connection electrode through the second contact hole; and a CLK lead wire configured to be connected to the thirteenth connection electrode through the second contact hole and connected to a CLK transmission line provided in the second metal layer in the first latch unit of the same latch row; The second metal layer in the second secondary clock unit includes: a CLK lead-in wire configured to be connected to the twelfth connection electrode through the second contact hole and connected to a CLK transmission line provided in the second metal layer in the second latch unit of the same latch row; and a CLKB lead-out wire configured to be connected to the thirteenth connection electrode through the second contact hole and connected to a CLKB transmission line in the latch unit of the same latch row.

22. The multi-bit latch according to claim 21, wherein: In the second-level clock unit, a fourth insulating layer and a third metal layer are formed on the second metal layer, and a plurality of third contact holes are formed in the fourth insulating layer, wherein: The third metal layer in the first secondary clock unit includes: a CLKOUT connection line extending in the X direction or the opposite direction of the X direction to the primary clock unit, configured to be connected to the CLKOUT lead wire through the third contact hole to transmit clkout to the Q3 gate and the Q4 gate; When the first secondary clock unit is provided on the side of the second secondary clock unit away from the filling row, the CLKOUT connection line is provided on the third metal layer of the second secondary clock unit.

23. The multi-bit latch according to claim 22, wherein: The primary clock unit includes a first transistor Q1 provided in the PMOS region of the first area of the latch row where it is located and a second transistor Q2 provided in the NMOS region of the first area of the latch row where it is located; Q1 is a PMOS, Q2 is an NMOS, and the CMOS inverter formed by connecting Q1 and Q2 is configured to receive clkin, output clkout, and transmit it to the CLKOUT connection line.

24. The multi-bit latch according to claim 23, wherein: The CLKOUT connection line is provided on the third metal layer of a plurality of latch units, including a first segment extending from the primary clock unit in the X direction to the first secondary clock unit of the fourth latch group, and a second segment extending from the primary clock unit in the opposite direction of the X direction to the first secondary clock unit of the first latch group; The latch unit adopts the latch unit according to claim 10; The clk output by the first and second - stage clock units is transmitted via the CLK lead - out line, the CLK transmission line, and the CLK connection line of the first latch unit in the same latch row to the CLK connection lines of other latch units in the latch group where it is located, and then transmitted via the CLK transmission line of the second latch unit in the same latch row as the second - stage clock unit in this latch group to the CLK input line of the second - stage clock unit in this latch group; The clkb output by the second - stage clock unit is transmitted via the CLKB lead - out line, the CLKB transmission line, and the CLKB connection line of the latch unit in the same latch row to the CLKB connection lines of other latch units in the latch group where it is located; The CLK connection lines of all latch units in the same latch group are connected in sequence, and the CLKB connection lines of all latch units in the same latch group are connected in sequence.

25. An integrated circuit, comprising the multi - bit latch as described in any one of claims 11 to 24.

26. A method for fabricating a multi-bit latch, comprising: One first - stage clock unit, eight second - stage clock units, and thirty - two latch units are formed on a substrate; wherein, in a plane parallel to the substrate, the multi - bit latch includes a first latch group, a second latch group, a fill row, a third latch group, and a fourth latch group arranged in sequence along the X - direction on the substrate. Each latch group includes eight latch rows arranged in sequence along the X - direction, and each latch row includes one of the latch units; a latch row adjacent to the fill row is further provided with the first - stage clock unit, and the first - stage clock unit is configured to receive a clock signal clkin and output an inverted signal clkout of clkin; two latch rows at the middle position of each latch group are each further provided with one of the second - stage clock units. One of the second - stage clock units is configured to receive clkout and output an inverted signal clk of clkout, and the other second - stage clock unit is configured to receive clk and output an inverted signal clkb of clk; the latch unit is configured to latch and output the input 1 - bit data based on clk and clkb; wherein, the first - stage clock unit and the latch units in the same latch row, and the second - stage clock units and the latch units in the same latch row are arranged in sequence along the Y - direction, and the Y - direction and the X - direction intersect.

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