Semiconductor light-emitting device

Abstract

To increase the number of semiconductor light-emitting elements that are mountable to a semiconductor light-emitting device.SOLUTION: A semiconductor light-emitting device 10 comprises: a substrate 20; a plurality of semiconductor light-emitting elements 30 provided on the substrate 20, each composed of an end-face light-emitting element; a plurality of drive circuits 40A-40H provided on the substrate 20, each driving one or more of the plurality of semiconductor light-emitting elements 30; and a light reflection element 50 provided on the substrate 20, for reflecting the light emitted from the plurality of semiconductor light-emitting elements 30 in a direction intersecting the substrate 20.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor light-emitting device.

Background Art

[0002] One type of semiconductor light-emitting device is a semiconductor laser device that includes a semiconductor laser element as a light source. The semiconductor laser device is widely adopted as a light source device mounted on various electronic devices. Patent Document 1 discloses an example of a semiconductor laser device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In recent years, further performance improvement of semiconductor light-emitting devices has been demanded. As an example, when applying a semiconductor light-emitting device to a laser system such as LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) that uses three-dimensional distance measurement, an increase in the viewing angle and an improvement in resolution are required. In response to such requirements, it has been demanded to further increase the number of semiconductor light-emitting elements that can be mounted on the semiconductor light-emitting device.

[0005] A semiconductor light-emitting device according to one aspect of the present disclosure includes a substrate, a plurality of semiconductor light-emitting elements provided on the substrate and each constituted by an edge-emitting element, a plurality of drive circuits provided on the substrate and each driving one or more of the plurality of semiconductor light-emitting elements, and a light reflecting element provided on the substrate and reflecting light emitted from the plurality of semiconductor light-emitting elements in a direction intersecting the substrate.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, some embodiments of the semiconductor light-emitting device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a certain scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] [First Embodiment] The semiconductor light-emitting device 10 of the first embodiment will be described with reference to FIGS. 1 to 12. FIG. 1 shows a schematic plan structure of the semiconductor light-emitting device 10. FIG. 2 shows a schematic plan structure of the central portion of the semiconductor light-emitting device 10. FIGS. 3 to 6 show schematic plan structures of four different portions of the peripheral region of the semiconductor light-emitting device 10. FIG. 7 shows a schematic cross-sectional structure along the line F7-F7 of FIG. 3, and FIG. 8 shows a schematic cross-sectional structure along the line F8-F8 of FIG. 2. FIG. 9 shows a schematic back electrode structure of the semiconductor light-emitting device 10, and FIG. 10 shows a schematic intermediate electrode structure of the semiconductor light-emitting device 10. FIG. 11 is a diagram for explaining the current path of the semiconductor light-emitting device 10, and FIG. 12 shows a schematic circuit of the light-emitting system 200 including the semiconductor light-emitting device 10.

[0010] In the present disclosure, constituent members may be described based on the XYZ axes orthogonal to each other shown in the drawings. The term "plan view" used in the present disclosure means viewing the semiconductor light-emitting device 10 in the Z-axis direction. In the present disclosure, for the purpose of explanation, one direction along the Y-axis (for example, the direction from the lower side to the upper side in FIG. 1) is defined as the first direction D1, and the other direction along the Y-axis, that is, the direction opposite to the first direction D1 is defined as the second direction D2. Also, one direction along the X-axis (for example, the direction from the left side to the right side in FIG. 1) is defined as the third direction D3, and the other direction along the X-axis, that is, the direction opposite to the third direction D3 is defined as the fourth direction D4. However, the first to fourth directions D1 to D4 are not limited to the directions defined here.

[0011] [1-1. Overall Structure of Semiconductor Light-Emitting Device] As shown in FIG. 1, the semiconductor light-emitting device 10 includes a substrate 20, a plurality (for example, 16 in FIG. 1) of semiconductor light-emitting elements 30, a plurality (for example, 8 in FIG. 1) of drive circuits 40A to 40H, and a light reflection element 50. In the following description, when the drive circuits 40A to 40H are not distinguished from each other, the drive circuits 40A to 40H are described as the drive circuit 40 (or each drive circuit 40).

[0012] A plurality of semiconductor light-emitting elements 30, a plurality of drive circuits 40, and a light reflection element 50 are provided on a substrate 20. The semiconductor light-emitting device 10 is embodied as a multi-channel (8 channels in the example of FIG. 1) drive type light-emitting module that drives the plurality of semiconductor light-emitting elements 30 by the plurality of drive circuits 40. Note that the number of semiconductor light-emitting elements 30 and the number of drive circuits 40 can be appropriately changed according to the number of channels.

[0013] The substrate 20 has a rectangular shape in plan view. In the example of FIG. 1, the substrate 20 is square, but may have any shape in plan view. Note that plan view means viewing the semiconductor light-emitting device 10 in the thickness direction of the substrate 20 (the direction perpendicular to the paper surface in FIG. 1). The substrate 20 includes a main surface 21, a back surface 22 (see FIG. 7) on the opposite side thereof, and first to fourth side surfaces 23 to 26. The first and second side surfaces 23 and 24 correspond to both end faces of the substrate 20 in the Y-axis direction. In the example of FIG. 1, the first side surface 23 is located below the paper surface, and the second side surface 24 is located above the paper surface. The third and fourth side surfaces 25 and 26 correspond to both end faces of the substrate 20 in the X-axis direction. In the example of FIG. 1, the third side surface 25 is located on the left side of the paper surface, and the fourth side surface 26 is located on the right side of the paper surface.

[0014] As shown in FIG. 7, for example, a multilayer substrate is used for the substrate 20. In the example of FIG. 7, the substrate 20 is a four-layer substrate and includes first to fourth electrode layers 28A to 28D and first to third base materials 27A to 27C located between the first to fourth electrode layers 28A to 28D. The first to fourth electrode layers 28A to 28D are formed of one or more materials selected from the group including, for example, Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten).

[0015] The first to third substrates 27A to 27C are formed of, for example, an insulating material. An example of the insulating material is a material containing an epoxy resin, and for example, a glass epoxy resin can be used. Another example of the insulating material is a material containing ceramic. As the material containing ceramic, for example, aluminum nitride (AlN) or alumina (Al2O3) can be used. When using the material containing ceramic, the heat dissipation performance of the first to third substrates 27A to 27C is enhanced, thereby suppressing excessive temperature rise in the semiconductor light-emitting device 10.

[0016] The first substrate 27A includes the main surface 21 of the substrate 20. The second substrate 27B includes the back surface 22 of the substrate 20. In other words, the main surface of the first substrate 27A corresponds to the main surface 21 of the substrate 20, and the back surface of the second substrate 27A corresponds to the back surface 22 of the substrate 20. The third substrate 27C is located in the middle between the first substrate 27A and the second substrate 27B. Each of the four side surfaces of the first to third substrates 27A to 27C corresponds to the first to fourth side surfaces 23 to 26 of the substrate 20.

[0017] The main surface 21 of the substrate 20 is covered by the main surface resist layer 29A, and the back surface 22 of the substrate 20 is covered by the back surface resist layer 29B. The main surface resist layer 29A and the back surface resist layer 29B are formed of an insulating material such as, for example, an epoxy resin or a polyimide resin. The main surface resist layer 29A and the back surface resist layer 29B may contain a filler such as silica or alumina.

[0018] Note that the ends of the first to fourth electrode layers 28A to 28D are not exposed on the first to fourth side surfaces 23 to 26 of the substrate 20 (the right end surface in FIG. 7 shows the first side surface 23). As shown in FIG. 7, the end of the first electrode layer 28A located on the main surface 21 of the substrate 20 is covered by the main surface resist layer 29A, and the end of the second electrode layer 28B located on the back surface 22 of the substrate 20 is covered by the back surface resist layer 29B. The ends of the second and third electrode layers 28C and 28D located between the first to third base materials 27A to 27C are covered by the first to third base materials 27A to 27C. In FIG. 7, for the purpose of explanation, the interfaces between the first to third base materials 27A to 27C are shown distinguished by solid lines, but these interfaces may not be clear in actuality.

[0019] [1-2. Semiconductor Light-Emitting Element] Each of the plurality of semiconductor light-emitting elements 30 is composed of an end-face light-emitting element and functions as a light source of the semiconductor light-emitting device 10. Each semiconductor light-emitting element 30 is configured to emit light in a direction parallel to the substrate 20 (main surface 21). For example, each semiconductor light-emitting element 30 is composed of an edge-emitting laser (EEL) element that outputs laser light in a predetermined wavelength band. The configuration of each semiconductor light-emitting element 30 is the same. The laser light may be visible light or laser light having a wavelength longer than visible light such as infrared light.

[0020] As shown in FIG. 1, each semiconductor light-emitting element 30 has a rectangular shape in plan view, and includes two long sides along the Y-axis direction and two short sides along the X-axis direction. The semiconductor light-emitting element 30 is arranged around the light reflection element 50 at a position close to the light reflection element 50. In the example of FIG. 1, eight out of the 16 semiconductor light-emitting elements 30 are arranged in a row along one light incident surface 51A of the light reflection element 50 in plan view. Further, the remaining eight semiconductor light-emitting elements 30 are arranged in a row along the other light incident surface 51B of the light reflection element 50 in plan view. Note that the configuration of the light reflection element 50 will be described later. The semiconductor light-emitting elements 30 arranged in a row along each of the light incident surfaces 51A and 51B have their long sides adjacent to each other and are spaced apart from each other, and are oriented to emit light to the corresponding light incident surfaces 51A and 51B.

[0021] As shown in FIG. 7, each semiconductor light-emitting element 30 includes an element surface 31 and an element back surface 32 on the opposite side thereof. A surface electrode 34 is provided on the element surface 31. A back surface electrode 35 is provided on the element back surface 32. The back surface electrode 35 is formed, for example, over the entire surface of the element back surface 32. The surface electrode 34 corresponds to an anode electrode, and the back surface electrode 35 corresponds to a cathode electrode.

[0022] [1-3. Driving Circuit of Semiconductor Light-Emitting Device] As shown in FIG. 1, the driving circuits 40A to 40H are provided to drive a plurality (16 in FIG. 1) of semiconductor light-emitting elements 30 mounted on the semiconductor light-emitting device 10. Each of these driving circuits 40A to 40H is configured to drive one or more of the plurality of semiconductor light-emitting elements 30. In the example of FIG. 1, two semiconductor light-emitting elements 30 are provided per channel (each driving circuit 40), and the driving circuits 40A to 40H each drive two adjacent semiconductor light-emitting elements 30. Since the configuration of each driving circuit 40 is the same, hereinafter, the driving circuit 40A will be described, and detailed descriptions of the driving circuits 40B to 40H will be omitted.

[0023] The drive circuit 40A includes a switching element 411 and one or more capacitors 421. The switching element 411 is configured to control one or more of the plurality of semiconductor light-emitting elements 30. In the example of FIG. 1, the switching element 411 is configured to control two adjacent semiconductor light-emitting elements 30. The switching element 411 is provided in the vicinity of the two semiconductor light-emitting elements 30 to be controlled. In the example of FIG. 1, the switching element 411 is provided at a position adjacent or close to the two semiconductor light-emitting elements 30 in the Y-axis direction.

[0024] The switching element 411 has a rectangular shape in plan view. In the example of FIG. 1, the switching element 411 is square, but may have any shape in plan view. For example, a vertical transistor is used for the switching element 411. Examples of such vertical transistors include MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), and bipolar transistors. In the first embodiment, for example, an n-type MOSFET is used as the switching element 411.

[0025] As shown in FIG. 7, the switching element 411 includes an element front surface 41A and an element back surface 41B on the opposite side thereof. A source electrode 41S and a gate electrode 41G (see FIG. 3) are provided on the element front surface 41A. The source electrode 41S is disposed, for example, over most of the element front surface 41A. The gate electrode 41G is disposed, for example, near one corner of the element front surface 41A. As shown in FIG. 7, a drain electrode 41D is provided on the element back surface 41B. The drain electrode 41D is disposed, for example, over the entire element back surface 41B.

[0026] Returning to FIG. 1, the capacitor 421 is configured to supply current to one or more of the plurality of semiconductor light-emitting elements 30. In the example of FIG. 1, the drive circuit 40A includes four capacitors 421 connected in parallel, and these four capacitors 421 are configured to supply current to two semiconductor light-emitting elements 30 to be controlled by the switching element 411. The four capacitors 421 are provided in the vicinity of the switching element 411. In the example of FIG. 1, the four capacitors 421 are provided at positions adjacent or close to the switching element 411 in the Y-axis direction. The four capacitors 421 are provided closer to the first side surface 23 of the substrate 20 than the switching element 411 in the Y-axis direction.

[0027] For the capacitor 421, for example, a ceramic capacitor is used. Each capacitor 421 is rectangular in plan view and includes two long sides along the Y-axis direction and two short sides along the X-axis direction. The four capacitors 421 are arranged in a row in the X-axis direction with their long sides adjacent to each other while being spaced apart from each other. As shown in FIG. 7, each capacitor 421 includes a first electrode 42A and a second electrode 42B. The first electrode 42A is located at one end of the capacitor 421 in the Y-axis direction, and the second electrode 42B is located at the other end of the capacitor 421 in the Y-axis direction.

[0028] Note that, similar to the drive circuit 40A, the drive circuits 40B to 40H also each include switching elements 412 to 418 configured in the same manner as the switching element 411 and capacitors 422 to 428 configured in the same manner as the capacitor 421. Also, similar to the drive circuit 40A, the number of capacitors 422 in the drive circuit 40B is, for example, four, and the same applies to the capacitors 423 to 428 of the other drive circuits 40C to 40H.

[0029] [1-4. Light Reflective Element of Semiconductor Light-Emitting Device] The light reflecting element 50 is configured to reflect the light emitted from the semiconductor light emitting element 30 in a direction intersecting the substrate 20. An example of the light reflecting element 50 is a light reflecting mirror configured to reflect light at a predetermined angle with respect to the incident direction. In the first embodiment, for example, a mirror having a reflection angle of 45° and configured to reflect light in a direction perpendicular to the incident direction is used as the light reflecting element 50.

[0030] Note that the light reflecting element 50 is not limited to only a mirror. Another example of the light reflecting element 50 is a diffraction grating configured to diffract light at a predetermined angle with respect to the incident direction. In this case, the diffraction grating may be either a reflection type or a transmission type. In the case of the reflection type, similar to the case of the mirror, the diffraction grating can be configured to reflect light in a direction perpendicular to the incident direction. In the case of the transmission type, the diffraction grating can be configured to emit diffracted light in a direction perpendicular to the incident direction of the light by refraction of the light.

[0031] As shown in FIG. 1, the light reflecting element 50 includes a plurality (for example, two in FIG. 1) of light incident surfaces 51A and 51B. In the first embodiment, for example, 8 out of 16 semiconductor light emitting elements 30 are arranged in a row along the X-axis direction on the light incident surface 51A, and the remaining 8 semiconductor light emitting elements 30 are arranged in a row along the X-axis direction on the light incident surface 51B.

[0032] Here, the light incident surface 51A is an example of a first light incident surface, and the light incident surface 51B is an example of a second light incident surface. Also, each of the plurality (8 in the example of FIG. 1) of semiconductor light emitting elements 30 provided along the light incident surface 51A is an example of a first semiconductor light emitting element, and each of the plurality (8 in the example of FIG. 1) of semiconductor light emitting elements 30 provided along the light incident surface 51B is an example of a second semiconductor light emitting element. Hereinafter, for convenience of explanation, each semiconductor light emitting element 30 provided along the light incident surface 51A may be referred to as "the first semiconductor light emitting element 30", and each semiconductor light emitting element 30 provided along the light incident surface 51B may be referred to as "the second semiconductor light emitting element 30".

[0033] The light reflecting element 50 has a rectangular shape in plan view and includes two long sides along the X-axis direction and two short sides along the Y-axis direction. The light incident surface 51A is located on one long side of the light reflecting element 50, and the light incident surface 51B is located on the other long side (i.e., on the side opposite to the light incident surface 51A). The light reflecting element 50 is located between eight first semiconductor light emitting elements 30 and eight second semiconductor light emitting elements 30 in the Y-axis direction. The light reflecting element 50 is configured to reflect the light emitted from each of the first and second semiconductor light emitting elements 30 in the same direction in the direction intersecting the substrate 20.

[0034] In the example of FIG. 1, the eight first semiconductor light emitting elements 30 are oriented to emit light in a first direction D1 parallel to the main surface 21 of the substrate 20. The light incident surface 51A reflects the light emitted from each of the eight first semiconductor light emitting elements 30 and propagating in the first direction D1 in a direction intersecting the substrate 20. The length of the light incident surface 51A in the X-axis direction has a dimension value that covers the light emitting surfaces of all eight first semiconductor light emitting elements 30 arranged in a row in the X-axis direction along the light incident surface 51A. Therefore, the light incident surface 51A reflects the light emitted from all eight first semiconductor light emitting elements 30.

[0035] On the other hand, the eight second semiconductor light emitting elements 30 are oriented to emit light in a second direction D2 opposite to the first direction D1. The light incident surface 51B reflects the light emitted from each of the eight second semiconductor light emitting elements 30 and propagating in the second direction D2 in a direction intersecting the substrate 20. The length of the light incident surface 51B in the X-axis direction has a dimension value that covers the light emitting surfaces of all eight second semiconductor light emitting elements 30 arranged in a row in the X-axis direction along the light incident surface 51B. Therefore, the light incident surface 51B reflects the light emitted from all eight second semiconductor light emitting elements 30.

[0036] As shown in FIG. 8, each light incident surface 51A, 51B is inclined at an inclination angle of, for example, 45° with respect to the incident direction of the light L1 from each semiconductor light emitting element 30 (the direction parallel to the substrate 20). Therefore, the light reflecting element 50 reflects the light L1 that propagates parallel to the substrate 20 and is incident on each light incident surface 51A, 51B as the reflected light L2 that propagates in the direction perpendicular to the substrate 20.

[0037] [1-5. Protection Diode] As shown in FIG. 1, in addition to the plurality of semiconductor light emitting elements 30, the plurality of drive circuits 40, and the light reflecting element 50 described above, the semiconductor light emitting device 10 includes a plurality (for example, eight in FIG. 1) of protection diodes 70A to 70H that protect the semiconductor light emitting elements 30 mounted on the semiconductor light emitting device 10. The protection diodes 70A to 70H are provided, for example, for each channel (drive circuit 40). Since the configurations of the protection diodes 70A to 70H are the same, hereinafter, the protection diode 70A will be described, and the detailed description of the protection diodes 70B to 70H will be omitted.

[0038] As shown in FIG. 12, the protection diode 70A is connected in anti-parallel to two semiconductor light emitting elements 30 that are controlled by the switching element 411 (drive circuit 40A). However, the number of semiconductor light emitting elements 30 connected to the protection diode 70A is not limited to two. The protection diode 70A can be connected in anti-parallel to one or more semiconductor light emitting elements 30 provided per channel (each drive circuit 40). In FIG. 12, for clarity of illustration, only the drive circuits 40A, 40B, 40G, 40H and the circuit elements related thereto are shown, and the illustration of the drive circuits 40C, 40D, 40E, 40F and the circuit elements related thereto is omitted. Also, the two semiconductor light emitting elements 30 driven by each drive circuit 40 are collectively shown as one diode element symbol.

[0039] [1-6. Electrode Layer of Substrate] Next, the configuration of the plurality of electrode layers of the substrate 20, that is, the first to fourth electrode layers 28A to 28D, will be described. As shown in FIG. 7, the first electrode layer 28A is provided as a surface electrode layer located on the main surface 21 of the substrate 20. The second electrode layer 28B is provided as a back surface electrode layer located on the back surface 22 of the substrate 20. The third and fourth electrode layers 28C and 28D are each provided as intermediate electrode layers located between the first and second electrode layers 28A and 28B in the thickness direction of the substrate 20. Among these, the third electrode layer 28C is provided as a surface-side intermediate electrode layer located closer to the first electrode layer 28A (surface electrode layer), and the fourth electrode layer 28D is provided as a back surface-side intermediate electrode layer located closer to the second electrode layer 28B (back surface electrode layer). In the first embodiment, the third and fourth electrode layers 28C and 28D have, for example, the same structure.

[0040] [1-6A. First Electrode Layer (Surface Electrode Layer)] As shown in FIGS. 1 to 6, the first electrode layer 28A (surface electrode layer) located on the main surface 21 of the substrate 20 includes a plurality of surface electrodes (pattern electrodes) spaced apart from each other. In the first embodiment, the first electrode layer 28A includes first surface electrodes 61A to 61H, second surface electrodes 62A to 62H, third surface electrodes 63A to 63H, fourth surface electrodes 64A to 64D, fifth surface electrodes 65A to 65H, and sixth surface electrode 66.

[0041] The first surface electrodes 61A to 61H are used for mounting a plurality of semiconductor light-emitting elements 30. In the first embodiment, two semiconductor light-emitting elements 30 are mounted on each of the first surface electrodes 61A to 61H. The second surface electrodes 62A to 62H, third surface electrodes 63A to 63H, fourth surface electrodes 64A to 64D, and fifth surface electrodes 65A to 65H are used for mounting drive circuits 40A to 40H. The sixth surface electrode 66 is used for mounting the light reflection element 50.

[0042] As shown in FIG. 2, the sixth surface electrode 66 has a rectangular shape in plan view and includes two long sides along the X-axis direction and two short sides along the Y-axis direction. The sixth surface electrode 66 is located in the central region AC of the substrate 20. Therefore, the light reflecting element 50 is mounted in the central region AC. As shown in FIG. 8, the light reflecting element 50 is mounted on the sixth surface electrode 66 by a conductive bonding material SD. As shown in FIGS. 3 to 6, other surface electrodes other than the sixth surface electrode 66, that is, the first surface electrodes 61A to 61H, the second surface electrodes 62A to 62H, the third surface electrodes 63A to 63H, the fourth surface electrodes 64A to 64D, and the fifth surface electrodes 65A to 65H are located in the peripheral region AP of the substrate 20 outside the sixth surface electrode 66 in plan view.

[0043] As shown in FIG. 2, the first surface electrodes 61A to 61H are arranged around the sixth surface electrode 66 at a position close to the sixth surface electrode 66. The first surface electrodes 61A to 61H are arranged in a row in the X-axis direction along the two long sides of the sixth surface electrode 66, that is, along the two light incident surfaces 51A and 51B of the light reflecting element 50. In the first embodiment, the first surface electrodes 61A to 61D are arranged in a row in the X-axis direction along the light incident surface 51A, and the first surface electrodes 61E to 61H are arranged in a row in the X-axis direction along the light incident surface 51B. Therefore, the 16 semiconductor light emitting elements 30 are intensively arranged in the vicinity of the central region AC where the light reflecting element 50 is located.

[0044] The first surface electrodes 61A to 61H, the second surface electrodes 62A to 62H, the third surface electrodes 63A to 63H, the fourth surface electrodes 64A to 64D, and the fifth surface electrodes 65A to 65H are arranged to have a symmetric relationship in the peripheral region AP of the substrate 20. In the first embodiment, these surface electrodes located in the peripheral region AP are arranged in a line-symmetric relationship with respect to a virtual center line VC extending in the Y-axis direction at the central position of the substrate 20 in the X-axis direction. Also, these surface electrodes located in the peripheral region AP are arranged in a line-symmetric relationship with respect to a virtual center line HC extending in the X-axis direction at the central position of the substrate 20 in the Y-axis direction.

[0045] Here, the peripheral region AP of the substrate 20 is divided into four wiring (electrode) arrangement regions based on the above-described two virtual center lines VC and HC, and includes a first arrangement region AP1, a second arrangement region AP2, a third arrangement region AP3, and a fourth arrangement region AP4 corresponding to the lower right region, lower left region, upper right region, and upper left region of the substrate 20 in FIG. 1, respectively. Hereinafter, the surface electrode layout within the first to fourth arrangement regions AP1 to AP4 will be described.

[0046] As shown in FIG. 3, the first arrangement region AP1 (the lower right region in FIG. 1) is used for the arrangement of the first surface electrodes 61A and 61B, the second surface electrodes 62A and 62B, the third surface electrodes 63A and 63B, the fourth surface electrode 64A, and the fifth surface electrodes 65A and 65B.

[0047] Each of the first surface electrodes 61A and 61B is used for mounting the two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 62A, 63A, 64A, and 65A are used for mounting the drive circuit 40A. The fourth and fifth surface electrodes 64A and 65A are further used for mounting the protection diode 70A. The second to fifth surface electrodes 62B, 63B, 64A, and 65B are used for mounting the drive circuit 40B. The fourth and fifth surface electrodes 64A and 65B are further used for mounting the protection diode 70B.

[0048] Therefore, the fourth surface electrode 64A is shared for mounting the drive circuits 40A and 40B and for mounting the protection diodes 70A and 70B. Thus, the first arrangement region AP1 (the lower right region in FIG. 1) of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40A and 40B, and two protection diodes 70A and 70B.

[0049] The switching element 411 of the drive circuit 40A is mounted on the second surface electrode 62A. The second surface electrode 62A is provided at a position adjacent or close to the first surface electrode 61A in the Y-axis direction. The source electrode 41S of the switching element 411 is connected by a wire W1 to the surface electrodes 34 of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 61A. Note that the back electrodes 35 (see FIG. 7) of the respective semiconductor light-emitting elements 30 mounted on the first surface electrode 61A are joined to the first surface electrode 61A by a conductive bonding material SD (see FIG. 7).

[0050] The source electrode 41S of the switching element 411 is further connected by a wire W2 to the fourth surface electrode 64A. The gate electrode 41G of the switching element 411 is connected by a wire W3 to the third surface electrode 63A. Each of the third and fourth surface electrodes 63A and 64A includes a portion adjacent or close to the second surface electrode 62A (the mounting region of the switching element 411) in the X-axis direction. The drain electrode 41D (see FIG. 7) of the switching element 411 is joined to the second surface electrode 62A by a conductive bonding material SD (see FIG. 7).

[0051] The wires W1 to W3 are bonding wires formed by a wire bonding apparatus, and for example, conductors such as Au, Al, or Cu are used. The number of each of the wires W1 to W3 is not particularly limited, and may be one or more. In the first embodiment, for example, from the viewpoint of reducing the wiring inductance of the entire circuit, the number of the wires W1 located on the current path between the switching element 411 and each semiconductor light-emitting element 30 is plural (for example, four or more).

[0052] The four capacitors 421 of the drive circuit 40A are mounted across both the second and fifth surface electrodes 62A and 65A. The first electrode 42A of each capacitor 421 is joined to the second surface electrode 62A by a conductive bonding material SD (see FIG. 7), and the second electrode 42B of each capacitor 421 is joined to the fifth surface electrode 65A by a conductive bonding material SD (see FIG. 7).

[0053] Although the cross-sectional views are omitted, the protection diode 70A is mounted across both the fourth and fifth surface electrodes 64A and 65A. The protection diode 70A includes an anode electrode 71 and a cathode electrode 72. The anode electrode 71 is joined to the fifth surface electrode 65A by a conductive bonding material, and the cathode electrode 72 is joined to the fourth surface electrode 64A by a conductive bonding material.

[0054] The switching element 412 of the drive circuit 40B is mounted on the second surface electrode 62B. The second surface electrode 62B is provided at a position adjacent or close to the first surface electrode 61B in the X-axis direction. The source electrode 41S of the switching element 412 is connected to the surface electrodes 34 of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 61B by wires W1. Although the cross-sectional views are omitted, the back electrodes 35 of the respective semiconductor light-emitting elements 30 mounted on the first surface electrode 61B are joined to the first surface electrode 61B by a conductive bonding material.

[0055] The source electrode 41S of the switching element 412 is further connected to the fourth surface electrode 64A by a wire W2. The gate electrode 41G of the switching element 412 is connected to the third surface electrode 63B by a wire W3. The third and fourth surface electrodes 63B and 64A each include portions adjacent or close to the second surface electrode 62B (the mounting region of the switching element 412) in the Y-axis direction. Although the cross-sectional views are omitted, the drain electrode 41D of the switching element 412 is joined to the second surface electrode 62B by a conductive bonding material.

[0056] Here, similar to the switching element 411, from the viewpoint of reducing the wiring inductance of the entire circuit, for example, the number of wires W1 located on the current path between the switching element 412 and each semiconductor light-emitting element 30 is plural (for example, four or more).

[0057] The four capacitors 422 of the drive circuit 40B are mounted across both the second and fifth surface electrodes 62B, 65B. Although a cross-sectional view is omitted, the first electrode 42A of each capacitor 422 is joined to the second surface electrode 62B by a conductive bonding material, and the second electrode 42B of each capacitor 422 is joined to the fifth surface electrode 65B by a conductive bonding material.

[0058] Also, although a cross-sectional view is omitted, the protection diode 70B is mounted across both the fourth and fifth surface electrodes 64A, 65B. The anode electrode 71 of the protection diode 70B is joined to the fifth surface electrode 65B by a conductive bonding material, and the cathode electrode 72 of the protection diode 70B is joined to the fourth surface electrode 64A by a conductive bonding material.

[0059] As shown in FIG. 4, the second placement region AP2 (the lower left region in FIG. 1) is used for the placement of the first surface electrodes 61C, 61D, the second surface electrodes 62C, 62D, the third surface electrodes 63C, 63D, the fourth surface electrode 64B, and the fifth surface electrodes 65C, 65D.

[0060] The first surface electrodes 61C, 61D are each used for mounting the two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 62C, 63C, 64B, 65C are used for mounting the drive circuit 40C. The fourth and fifth surface electrodes 64B, 65C are further used for mounting the protection diode 70C. The second to fifth surface electrodes 62D, 63D, 64B, 65D are used for mounting the drive circuit 40D. The fourth and fifth surface electrodes 64B, 65D are further used for mounting the protection diode 70D. Therefore, the fourth surface electrode 64B is shared for mounting the drive circuits 40C, 40D and for mounting the protection diodes 70C, 70D. Thus, the second placement region AP2 (the lower left region in FIG. 1) of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40C, 40D, and two protection diodes 70C, 70D.

[0061] The surface electrodes (and the elements mounted thereon) disposed in the second arrangement region AP2 and the surface electrodes (and the elements mounted thereon) disposed in the first arrangement region AP1 are arranged in a line-symmetric relationship with respect to the virtual center line VC. For this reason, detailed descriptions of the arrangements of the first surface electrodes 61C, 61D, the second surface electrodes 62C, 62D, the third surface electrodes 63C, 63D, the fourth surface electrode 64B, and the fifth surface electrodes 65C, 65D, and the semiconductor light-emitting elements 30, drive circuits 40C, 40D (switching elements 413, 414 and capacitors 423, 424), and protection diodes 70C, 70D mounted on these surface electrodes are omitted.

[0062] As shown in FIG. 5, the third arrangement region AP3 (the upper right region in FIG. 1) is used for the arrangements of the first surface electrodes 61E, 61F, the second surface electrodes 62E, 62F, the third surface electrodes 63E, 63F, the fourth surface electrode 64C, and the fifth surface electrodes 65E, 65F.

[0063] Each of the first surface electrodes 61E, 61F is used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 62E, 63E, 64C, 65E are used for mounting the drive circuit 40E. The fourth and fifth surface electrodes 64C, 65E are further used for mounting the protection diode 70E. The second to fifth surface electrodes 62F, 63F, 64C, 65F are used for mounting the drive circuit 40F. The fourth and fifth surface electrodes 64C, 65F are further used for mounting the protection diode 70F. Therefore, the fourth surface electrode 64C is shared for mounting the drive circuits 40E, 40F and for mounting the protection diodes 70E, 70F. Thus, the third arrangement region AP3 (the upper right region in FIG. 1) of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40E, 40F, and two protection diodes 70E, 70F.

[0064] The surface electrodes (and the elements mounted thereon) disposed in the third arrangement region AP3 and the surface electrodes (and the elements mounted thereon) disposed in the first arrangement region AP1 are arranged in a line-symmetric relationship with respect to the virtual center line HC. For this reason, detailed descriptions of the arrangements of the first surface electrodes 61E, 61F, the second surface electrodes 62E, 62F, the third surface electrodes 63E, 63F, the fourth surface electrode 64C, and the fifth surface electrodes 65E, 65F, as well as the semiconductor light-emitting elements 30, the drive circuits 40E, 40F (switching elements 415, 416 and capacitors 425, 426), and the protection diodes 70E, 70F mounted on these surface electrodes are omitted.

[0065] As shown in FIG. 6, the fourth arrangement region AP4 (the upper left region in FIG. 1) is used for the arrangements of the first surface electrodes 61G, 61H, the second surface electrodes 62G, 62H, the third surface electrodes 63G, 63H, the fourth surface electrode 64D, and the fifth surface electrodes 65G, 65H.

[0066] Each of the first surface electrodes 61G, 61H is used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 62G, 63G, 64D, 65G are used for mounting the drive circuit 40G. The fourth and fifth surface electrodes 64D, 65G are further used for mounting the protection diode 70G. The second to fifth surface electrodes 62H, 63H, 64D, 65H are used for mounting the drive circuit 40H. The fourth and fifth surface electrodes 64D, 65H are further used for mounting the protection diode 70H. Therefore, the fourth surface electrode 64D is shared for mounting the drive circuits 40G, 40H and is also shared for mounting the protection diodes 70G, 70H. Thus, the fourth arrangement region AP4 (the upper left region in FIG. 1) of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40G, 40H, and two protection diodes 70G, 70H.

[0067] The surface electrodes (and the elements mounted thereon) disposed in the fourth arrangement region AP4 and the surface electrodes (and the elements mounted thereon) disposed in the second arrangement region AP2 are arranged in a line-symmetric relationship with respect to the virtual center line HC. Also, the surface electrodes (and the elements mounted thereon) disposed in the fourth arrangement region AP4 and the surface electrodes (and the elements mounted thereon) disposed in the third arrangement region AP3 are arranged in a line-symmetric relationship with respect to the virtual center line VC. For this reason, detailed descriptions of the arrangements of the first surface electrodes 61G, 61H, the second surface electrodes 62G, 62H, the third surface electrodes 63G, 63H, the fourth surface electrode 64D, and the fifth surface electrodes 65G, 65H, and the semiconductor light-emitting elements 30, the drive circuits 40G, 40H (switching elements 417, 418 and capacitors 427, 428), and the protection diodes 70G, 70H mounted on these surface electrodes are omitted.

[0068] As shown in FIG. 7, the main surface resist layer 29A includes a plurality of openings that expose a part of the first electrode layer 28A. Each component of the plurality of semiconductor light-emitting elements 30, the drive circuits 40A to 40H, and the protection diodes 70A to 70H is mounted on the portion of the first electrode layer 28A exposed by the openings of the main surface resist layer 29A. In FIGS. 1 to 6, the openings of the main surface resist layer 29A are indicated by two-dot chain lines.

[0069] [1-6B. Second Electrode Layer (Back Surface Electrode Layer)] As shown in FIG. 9, the second electrode layer 28B (back surface electrode layer) located on the back surface 22 of the substrate 20 includes a plurality of back surface electrodes (pattern electrodes) spaced apart from each other. These back surface electrodes function as external electrode terminals that are electrically connected to the circuit board when the semiconductor light-emitting device 10 is mounted on the circuit board (not shown). In the first embodiment, the second electrode layer 28B includes the first back surface electrodes 81A to 81H, the second back surface electrodes 82A to 82H, the third back surface electrodes 83A to 83H, and the fourth back surface electrodes 84A to 84D.

[0070] The first back electrodes 81A to 81H, the second back electrodes 82A to 82H, the third back electrodes 83A to 83H, and the fourth back electrodes 84A to 84D are located in the peripheral region AP of the substrate 20 and are arranged in a line-symmetric relationship with respect to each of the two virtual center lines VC and HC. As described above, the peripheral region AP includes the first to fourth arrangement regions AP1 to AP4 as four wiring arrangement regions defined based on the virtual center lines VC and HC. When the substrate 20 is viewed from the back surface 22, the first arrangement region AP1, the second arrangement region AP2, the third arrangement region AP3, and the fourth arrangement region AP4 correspond to the lower left region, the lower right region, the upper left region, and the upper right region of the substrate 20 in FIG. 9, respectively. Hereinafter, the back electrode layout in the first to fourth arrangement regions AP1 to AP4 will be described.

[0071] The first arrangement region AP1 (the lower left region in FIG. 9) is used for the arrangement of the first back electrodes 81A and 81B, the second back electrodes 82A and 82B, the third back electrodes 83A and 83B, and the fourth back electrode 84A.

[0072] The first to fourth back electrodes 81A, 82A, 83A, and 84A are provided for electrical connection between the drive circuit 40A (the switching element 411 and the capacitor 421), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40A, and the protection diode 70A.

[0073] The first back electrode 81A is arranged at a position overlapping the first and fifth surface electrodes 61A and 65A (see FIGS. 3 respectively) in a plan view. The first back electrode 81A is formed, for example, in a strip shape extending in the Y-axis direction. The second back electrode 82A is arranged at a position overlapping the second surface electrode 62A (see FIG. 3) in a plan view. The second back electrode 82A is formed, for example, in a strip shape with a dimension shorter than that of the first back electrode 81A in the Y-axis direction and is provided adjacent or close to the first back electrode 81A in the X-axis direction.

[0074] The third back surface electrode 83A is disposed at a position overlapping with the third front surface electrode 63A (see FIG. 3) in plan view. The third back surface electrode 83A is formed, for example, in a bent strip shape with a dimension shorter than that of the first back surface electrode 81A in the Y-axis direction and longer than that of the second back surface electrode 82A in the Y-axis direction, and is provided adjacent or close to the second back surface electrode 82A in the X-axis direction. The fourth back surface electrode 84A is disposed at a position overlapping with the fourth front surface electrode 64A (see FIG. 3) in plan view. The fourth back surface electrode 84A is, for example, rectangular, and is provided adjacent or close to the third back surface electrode 83A in the X-axis direction.

[0075] The first to fourth back surface electrodes 81B, 82B, 83B, 84A are provided for electrical connection between the drive circuit 40B (the switching element 412 and the capacitor 422), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40B, and the protection diode 70B.

[0076] The first back surface electrode 81B is disposed at a position overlapping with the first front surface electrode 61B and the fifth front surface electrode 65B (see FIG. 3 respectively) in plan view. The first back surface electrode 81B is formed, for example, in a strip shape extending in the X-axis direction. The second back surface electrode 82B is disposed at a position overlapping with the second front surface electrode 62B (see FIG. 3) in plan view. The second back surface electrode 82B is formed, for example, in a strip shape with a dimension shorter than that of the first back surface electrode 81B in the X-axis direction, and is provided adjacent or close to the first back surface electrode 81B in the Y-axis direction.

[0077] The third back surface electrode 83B is disposed at a position overlapping with the third front surface electrode 63B (see FIG. 3) in plan view. The third back surface electrode 83B is formed, for example, in a bent strip shape with a dimension shorter than that of the first back surface electrode 81B in the X-axis direction and longer than that of the second back surface electrode 82B in the X-axis direction, and is provided adjacent or close to the second back surface electrode 82B in the Y-axis direction. The fourth back surface electrode 84A is disposed at a position overlapping with the fourth front surface electrode 64A (see FIG. 3) as described above in plan view. The fourth back surface electrode 84A is provided adjacent or close to the third back surface electrode 83A in the X-axis direction and adjacent or close to the third back surface electrode 83B in the Y-axis direction.

[0078] The second arrangement area AP2 (the lower right area in FIG. 9) is used for the arrangement of the first back electrodes 81C, 81D, the second back electrodes 82C, 82D, the third back electrodes 83C, 83D, and the fourth back electrode 84B.

[0079] The first to fourth back electrodes 81C, 82C, 83C, 84B are provided for electrical connection between the drive circuit 40C (the switching element 413 and the capacitor 423), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40C, and the protection diode 70C. The first to fourth back electrodes 81D, 82D, 83D, 84B are provided for electrical connection between the drive circuit 40D (the switching element 414 and the capacitor 424), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40D, and the protection diode 70D.

[0080] The back electrodes arranged in the second arrangement area AP2 and the back electrodes arranged in the first arrangement area AP1 are arranged in a line-symmetric relationship with respect to the virtual center line VC. Therefore, a detailed description of the arrangement of the first back electrodes 81C, 81D, the second back electrodes 82C, 82D, the third back electrodes 83C, 83D, and the fourth back electrode 84B is omitted.

[0081] The third arrangement area AP3 (the upper left area in FIG. 9) is used for the arrangement of the first back electrodes 81E, 81F, the second back electrodes 82E, 82F, the third back electrodes 83E, 83F, and the fourth back electrode 84C.

[0082] The first to fourth back electrodes 81E, 82E, 83E, 84C are provided for electrical connection between the drive circuit 40E (the switching element 415 and the capacitor 425), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40E, and the protection diode 70E. The first to fourth back electrodes 81F, 82F, 83F, 84C are provided for electrical connection between the drive circuit 40F (the switching element 416 and the capacitor 426), the two semiconductor light-emitting elements 30 to be driven by the drive circuit 40F, and the protection diode 70F.

[0083] The back electrodes disposed in the third arrangement region AP3 and the back electrodes disposed in the first arrangement region AP1 are arranged in a line-symmetric relationship with respect to the virtual center line HC. Therefore, detailed descriptions of the arrangements of the first back electrodes 81E, 81F, the second back electrodes 82E, 82F, the third back electrodes 83E, 83F, and the fourth back electrode 84C are omitted.

[0084] The fourth arrangement region AP4 (the upper right region in FIG. 9) is used for the arrangements of the first back electrodes 81G, 81H, the second back electrodes 82G, 82H, the third back electrodes 83G, 83H, and the fourth back electrode 84D.

[0085] The first to fourth back electrodes 81G, 82G, 83G, 84D are provided for electrical connection with the drive circuit 40G (the switching element 417 and the capacitor 427), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40G, and the protection diode 70G. The first to fourth back electrodes 81H, 82H, 83H, 84D are provided for electrical connection with the drive circuit 40H (the switching element 418 and the capacitor 428), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40H, and the protection diode 70H.

[0086] The back electrodes disposed in the fourth arrangement region AP4 and the back electrodes disposed in the second arrangement region AP2 are arranged in a line-symmetric relationship with respect to the virtual center line HC. Also, the back electrodes disposed in the fourth arrangement region AP4 and the back electrodes disposed in the third arrangement region AP3 are arranged in a line-symmetric relationship with respect to the virtual center line VC. Therefore, detailed descriptions of the arrangements of the first back electrodes 81G, 81H, the second back electrodes 82G, 82H, the third back electrodes 83G, 83H, and the fourth back electrode 84D are omitted.

[0087] As shown in FIG. 7, the back resist layer 29B includes a plurality of openings that expose a part of the second electrode layer 28B. The semiconductor light-emitting device 10 is mounted on a circuit board (not shown) by the portion of the second electrode layer 28B exposed by the openings of the back resist layer 29B. Therefore, the semiconductor light-emitting device 10 can be said to be a surface-mount device mounted on a circuit board. In FIG. 9, the openings of the back resist layer 29B are indicated by a two-dot chain line.

[0088] [1-6C. Third and Fourth Electrode Layers (Intermediate Electrode Layers)] As shown in FIG. 7, the third and fourth electrode layers 28C and 28D, which are intermediate electrode layers respectively, are embedded in the substrate 20. The third electrode layer 28C provided as the front-side intermediate electrode layer is located between the first base material 27A including the main surface 21 of the substrate 20 and the third base material 27C located in the middle in the thickness direction of the substrate 20. On the other hand, the fourth electrode layer 28D provided as the back-side intermediate electrode layer is located between the second base material 27B including the back surface 22 of the substrate 20 and the third base material 27C. In the first embodiment, the third electrode layer 28C (front-side intermediate electrode layer) and the fourth electrode layer 28D (back-side intermediate electrode layer) have the same structure. Therefore, hereinafter, the third electrode layer 28C will be described, and the detailed description of the fourth electrode layer 28D will be omitted.

[0089] As shown in FIG. 10, the third electrode layer 28C includes a plurality of intermediate electrodes (pattern electrodes) spaced apart from each other. In the first embodiment, the third electrode layer 28C includes first intermediate electrodes 91A to 91H, second intermediate electrodes 92A to 92H, third intermediate electrodes 93A to 93H, and fourth intermediate electrodes 94A to 94D.

[0090] The first intermediate electrodes 91A to 91H, the second intermediate electrodes 92A to 92H, the third intermediate electrodes 93A to 93H, and the fourth intermediate electrodes 94A to 94D are located in the peripheral region AP of the substrate 20 and are arranged in a line-symmetric relationship with respect to each of the two virtual center lines VC and HC. As described above, the peripheral region AP includes first to fourth arrangement regions AP1 to AP4 as four wiring arrangement regions divided based on the virtual center lines VC and HC. The first arrangement region AP1, the second arrangement region AP2, the third arrangement region AP3, and the fourth arrangement region AP4 respectively correspond to the lower right region, the lower left region, the upper right region, and the upper left region of the substrate 20 in FIG. 10. Hereinafter, the intermediate electrode layout in the first to fourth arrangement regions AP1 to AP4 will be described.

[0091] The first arrangement region AP1 (the lower right region in FIG. 10) is used for the arrangement of the first intermediate electrodes 91A and 91B, the second intermediate electrodes 92A and 92B, the third intermediate electrodes 93A and 93B, and the fourth intermediate electrode 94A.

[0092] The first to fourth intermediate electrodes 91A, 92A, 93A, and 94A are provided for electrical connection between the drive circuit 40A (the switching element 411 and the capacitor 421), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40A, and the protection diode 70A.

[0093] The first intermediate electrode 91A is formed in an elongated shape in the Y-axis direction and is arranged at a position overlapping the first and fifth surface electrodes 61A and 65A (see FIG. 3) in a plan view and also overlapping the first back surface electrode 81A (see FIG. 9). The first intermediate electrode 91A includes, for example, an oval-shaped first opening and a circular second opening. The second intermediate electrode 92A is arranged in the first opening and overlaps the second surface electrode 62A (see FIG. 3) and the second back surface electrode 82A (see FIG. 9) in a plan view. The third intermediate electrode 93A is arranged in the second opening and overlaps the third surface electrode 63A (see FIG. 3) and the third back surface electrode 83A (see FIG. 9) in a plan view. The fourth intermediate electrode 94A overlaps the fourth surface electrode 64A (see FIG. 3) and the fourth back surface electrode 84A (see FIG. 9) in a plan view.

[0094] The first to fourth intermediate electrodes 91B, 92B, 93B, and 94A are provided for electrical connection between the drive circuit 40B (switching element 412 and capacitor 422), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40B, and the protection diode 70B.

[0095] The first intermediate electrode 91B is formed in a long shape in the X-axis direction and is arranged at a position that overlaps with the first and fifth surface electrodes 61B and 65B (see FIG. 1) in plan view and also overlaps with the first back electrode 81B (see FIG. 9). The first intermediate electrode 91B includes, for example, an oval-shaped first opening and a circular second opening. The second intermediate electrode 92B is arranged in the first opening and overlaps with the second surface electrode 62B (see FIG. 3) and the second back electrode 82B (see FIG. 9) in plan view. The third intermediate electrode 93B is arranged in the second opening and overlaps with the third surface electrode 63B (see FIG. 3) and the third back electrode 83B (see FIG. 9) in plan view.

[0096] The second arrangement region AP2 (the lower left region in FIG. 10) is used for arranging the first intermediate electrodes 91C, 91D, the second intermediate electrodes 92C, 92D, the third intermediate electrodes 93C, 93D, and the fourth intermediate electrode 94B.

[0097] The first to fourth intermediate electrodes 91C, 92C, 93C, and 94B are provided for electrical connection between the drive circuit 40C (switching element 413 and capacitor 423), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40C, and the protection diode 70C. The first intermediate electrodes 91D, 92D, 93D, and 94B are provided for electrical connection between the drive circuit 40D (switching element 414 and capacitor 424), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40D, and the protection diode 70D.

[0098] The intermediate electrodes disposed in the second arrangement region AP2 and the intermediate electrodes disposed in the first arrangement region AP1 are arranged in a line-symmetric relationship with respect to the virtual center line VC. Therefore, detailed descriptions of the arrangements of the first intermediate electrodes 91C, 91D, the second intermediate electrodes 92C, 92D, the third intermediate electrodes 93C, 93D, and the fourth intermediate electrode 94B are omitted.

[0099] The third arrangement region AP3 (the upper right region in FIG. 10) is used for the arrangements of the first intermediate electrodes 91E, 91F, the second intermediate electrodes 92E, 92F, the third intermediate electrodes 93E, 93F, and the fourth intermediate electrode 94C.

[0100] The first to fourth intermediate electrodes 91E, 92E, 93E, 94C are provided for electrical connection between the drive circuit 40E (the switching element 415 and the capacitor 425), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40E, and the protection diode 70E. The first to fourth intermediate electrodes 91F, 92F, 93F, 94C are provided for electrical connection between the drive circuit 40F (the switching element 416 and the capacitor 426), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40F, and the protection diode 70F.

[0101] The intermediate electrodes disposed in the third arrangement region AP3 and the intermediate electrodes disposed in the first arrangement region AP1 are arranged in a line-symmetric relationship with respect to the virtual center line HC. Therefore, detailed descriptions of the arrangements of the first intermediate electrodes 91E, 91F, the second intermediate electrodes 92E, 92F, the third intermediate electrodes 93E, 93F, and the fourth intermediate electrode 94C are omitted.

[0102] The fourth arrangement region AP4 (the upper left region in FIG. 10) is used for the arrangements of the first intermediate electrodes 91G, 91H, the second intermediate electrodes 92G, 92H, the third intermediate electrodes 93G, 93H, and the fourth intermediate electrode 94D.

[0103] The first to fourth intermediate electrodes 91G, 92G, 93G, 94D are provided for electrical connection between the drive circuit 40G (switching element 417 and capacitor 427), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40G, and the protection diode 70G. The first to fourth intermediate electrodes 91H, 92H, 93H, 94D are provided for electrical connection between the drive circuit 40H (switching element 418 and capacitor 428), two semiconductor light-emitting elements 30 to be driven by the drive circuit 40H, and the protection diode 70H.

[0104] The intermediate electrodes arranged in the fourth arrangement region AP4 and the intermediate electrodes arranged in the second arrangement region AP2 are arranged in a line-symmetric relationship with respect to the virtual center line HC. Also, the intermediate electrodes arranged in the fourth arrangement region AP4 and the intermediate electrodes arranged in the third arrangement region AP3 are arranged in a line-symmetric relationship with respect to the virtual center line VC. Therefore, detailed description of the arrangement of the first intermediate electrodes 91G, 91H, the second intermediate electrodes 92G, 92H, the third intermediate electrodes 93G, 93H, and the fourth intermediate electrode 94D is omitted.

[0105] [1-7. Connection Structure between Electrode Layers] The substrate 20 includes a plurality of vias (connection conductors) that electrically connect the first electrode layer 28A (surface electrode layer), the second electrode layer 28B (back surface electrode layer), and the third and fourth electrode layers 28C, 28D (each intermediate electrode layer). For example, as shown in FIGS. 3 to 10, the substrate 20 includes first vias 101A to 101H, second vias 102A to 102H, third vias 103A to 103H, fourth vias 104A to 104D, and fifth vias 105A to 105H that penetrate the first to third base materials 27A to 27C and the third and fourth electrode layers 28C, 28D in the thickness direction of the substrate 20. Note that these plurality of vias may penetrate the first and second electrode layers 28A, 28B. These plurality of vias are formed of one or more materials selected from the group including Ti, TiN, Au, Ag, Cu, Al, and W.

[0106] As shown in FIGS. 3 to 6, FIG. 9, and FIG. 10, the first vias 101A to 101H, the second vias 102A to 102H, the third vias 103A to 103H, the fourth vias 104A to 104D, and the fifth vias 105A to 105H are located in the peripheral region AP of the substrate 20 and are arranged in a line-symmetric relationship with respect to each of the two virtual center lines VC and HC. As described above, the peripheral region AP includes first to fourth arrangement regions AP1 to AP4 defined based on the virtual center lines VC and HC. Hereinafter, the layout of a plurality of vias in the first to fourth arrangement regions AP1 to AP4 will be described.

[0107] The first arrangement region AP1 includes the first vias 101A and 101B, the second vias 102A and 102B, the third vias 103A and 103B, the fourth via 104A, and the fifth vias 105A and 105B.

[0108] The first via 101A electrically connects the first surface electrode 61A of the first electrode layer 28A, the first back surface electrode 81A of the second electrode layer 28B, and the first intermediate electrode 91A of the third and fourth electrode layers 28C and 28D. The number of the first vias 101A is not particularly limited. For example, there may be one or more per one semiconductor light-emitting element 30, that is, two or more at positions where the first surface electrode 61A, the first back surface electrode 81A, and the two first intermediate electrodes 91A overlap.

[0109] The second via 102A electrically connects the second surface electrode 62A of the first electrode layer 28A, the second back surface electrode 82A of the second electrode layer 28B, and the second intermediate electrode 92A of the third and fourth electrode layers 28C and 28D. The number of the second vias 102A is not particularly limited. For example, there may be one or more at positions where the second surface electrode 62A, the second back surface electrode 82A, and the two second intermediate electrodes 92A overlap.

[0110] The third via 103A electrically connects the third surface electrode 63A of the first electrode layer 28A, the third back surface electrode 83A of the second electrode layer 28B, and the third intermediate electrode 93A of the third and fourth electrode layers 28C and 28D. The number of the third vias 103A is not particularly limited, and for example, there may be one or more at a position where the third surface electrode 63A, the third back surface electrode 83A, and the two third intermediate electrodes 93A overlap.

[0111] The fourth via 104A electrically connects the fourth surface electrode 64A of the first electrode layer 28A, the fourth back surface electrode 84A of the second electrode layer 28B, and the fourth intermediate electrode 94A of the third and fourth electrode layers 28C and 28D. The number of the fourth vias 104A is not particularly limited, and for example, there may be one or more at a position where the fourth surface electrode 64A, the fourth back surface electrode 84A, and the two fourth intermediate electrodes 94A overlap. In the first embodiment, for example, a large number of fourth vias 104A are arranged in a matrix (for example, 5×9) using substantially the entire region of the electrode overlapping portion available for the arrangement of the fourth vias 104A.

[0112] The fifth via 105A electrically connects the fifth surface electrode 65A of the first electrode layer 28A, the first back surface electrode 81A of the second electrode layer 28B, and the first intermediate electrode 91A of the third and fourth electrode layers 28C and 28D. The number of the fifth vias 105A is not particularly limited, and for example, there may be one or more at a position where the fifth surface electrode 65A, the first back surface electrode 81A, and the two first intermediate electrodes 91A overlap. In the first embodiment, for example, a large number of fifth vias 105A are arranged in a matrix (for example, 3×3) using the region of the electrode overlapping portion available for the arrangement of the fifth vias 105A.

[0113] In the first arrangement region AP1, the first to third vias 101B, 102B, 103B and the fifth via 105B are arranged in the same manner as the first to third vias 101A, 102A, 103A and the fifth via 105A described above. Therefore, detailed descriptions of the first to third vias 101B, 102B, 103B and the fifth via 105B are omitted.

[0114] The second configuration region AP2 includes first vias 101C, 101D, second vias 102C, 102D, third vias 103C, 103D, fourth via 104B, and fifth vias 105C, 105D. The third configuration region AP3 includes first vias 101E, 101F, second vias 102E, 102F, third vias 103E, 103F, fourth via 104C, and fifth vias 105E, 105F. The fourth configuration region AP4 includes first vias 101G, 101H, second vias 102G, 102H, third vias 103G, 103H, fourth via 104D, and fifth vias 105G, 105H. Since the arrangement of these vias in the second to fourth configuration regions AP2, AP3, AP4 is the same as the arrangement of the vias in the first configuration region AP1 described above, detailed description thereof is omitted.

[0115] [1-8. Current Path of Semiconductor Light-Emitting Device] The semiconductor light-emitting device 10 is embodied as a multi-channel drive type light-emitting module in which a plurality of drive circuits 40 each drive one or more (two in the first embodiment) semiconductor light-emitting elements 30. As described above, in the semiconductor light-emitting device 10, the drive circuit 40 is mounted on the substrate 20 together with the semiconductor light-emitting element 30. Therefore, the current path between each drive circuit 40 and the semiconductor light-emitting element 30 to be driven thereby is formed in the substrate 20.

[0116] FIG. 11 shows a current path CP (a path indicated by an arrow) of a current flowing through the drive circuit 40A (the switching element 411 and the capacitor 421) and the semiconductor light-emitting element 30 to be driven by the drive circuit 40A.

[0117] The current path CP is configured in a loop shape through which current flows in the order of the first electrode 42A of the capacitor 421, the second surface electrode 62A of the first electrode layer 28A (surface electrode layer), the drain electrode 41D of the switching element 411, the source electrode 41S of the switching element 411, the wire W1, the surface electrode 34 (anode electrode) of the semiconductor light-emitting element 30, the back electrode 35 (cathode electrode), the first surface electrode 61A of the first electrode layer 28A, the first via 101A, the first intermediate electrode 91A of the third electrode layer 28C (surface-side intermediate electrode layer), the fifth via 105A, the fifth surface electrode 65A of the first electrode layer 28A, and the second electrode 42B of the capacitor 421.

[0118] Here, the protection diode 70A (see FIG. 3) is arranged so as to straddle between the fourth and fifth surface electrodes 64A and 65A. The anode electrode 71 of the protection diode 70A is mounted on the fifth surface electrode 65A, and the cathode electrode 72 is mounted on the fourth surface electrode 64A. Therefore, the anode electrode 71 of the protection diode 70A is electrically connected to the second electrode 42B of the capacitor 421 by the fifth surface electrode 65A. Also, the anode electrode 71 of the protection diode 70A and the second electrode 42B of the capacitor 421 are electrically connected to the back electrode 35 (cathode electrode) of the semiconductor light-emitting element 30. The fourth surface electrode 64A is provided as a ground wiring, and the fourth back electrode 84A is provided as a ground terminal. Therefore, the cathode electrode 72 of the protection diode 70A (and the source electrode 41S of the switching element 411) is connected to the ground.

[0119] Although detailed description is omitted here, for each of the other drive circuits 40B to 40H, the same electrical connection as that of the drive circuit 40A is realized, and a loop-shaped current path similar to the above-described current path CP is individually configured. Also, for each of the other protection diodes 70B to 70H, the same electrical connection as that of the protection diode 70A is realized.

[0120] [1-9. Circuit Configuration of Semiconductor Light-Emitting Device] As shown in FIG. 12, a light-emitting system 200 including a semiconductor light-emitting device 10 includes a DC power supply 201, a capacitor 202 connected in parallel with the DC power supply 201, a current-limiting resistor 203, backflow prevention diodes 204A to 204H, gate drivers 205A to 205H, pulse generators 206A to 206H, and control power supplies 207A to 207H. For clarity of illustration, in FIG. 12, the drive circuits 40C to 40F, the semiconductor light-emitting elements 30 to be driven by the drive circuits 40C to 40F, the protection diodes 70C to 70F, the backflow prevention diodes 204C to 204F, the gate drivers 205C to 205F, the pulse generators 206C to 206F, and the control power supplies 207C to 207F are not shown. The backflow prevention diodes 204A to 204H, the gate drivers 205A to 205H, the pulse generators 206A to 206H, and the control power supplies 207A to 207H are provided corresponding to the drive circuits 40A to 40H, respectively.

[0121] The DC power supply 201, the capacitor 202, and the current-limiting resistor 203 are configured to supply current to a plurality of semiconductor light-emitting elements 30 and drive circuits 40A to 40H. The DC power supply 201, the capacitor 202, and the current-limiting resistor 203 are an example of a power input unit. The first terminal of the current-limiting resistor 203 is electrically connected to the positive electrode of the DC power supply 201.

[0122] The anodes of the backflow prevention diodes 204A to 204H are electrically connected to the second terminal of the current-limiting resistor 203. The cathodes of the backflow prevention diodes 204A to 204H are electrically connected to the drain electrodes 41D of the switching elements 411 to 418 and the first electrodes 42A of the capacitors 421 to 428 via the second back electrodes 82A to 82H.

[0123] The gate drivers 205A to 205H are electrically connected to the gate electrodes 41G of the switching elements 411 to 418 of the drive circuits 40A to 40H, respectively. In the first embodiment, the gate drivers 205A to 205H are electrically connected to the third back electrodes 83A to 83H that are electrically connected to the gate electrodes 41G of the switching elements 411 to 418, respectively. The gate drivers 205A to 205H are configured to individually drive the switching elements 411 to 418 by applying gate voltage signals to the gate electrodes 41G of the switching elements 411 to 418, respectively.

[0124] The pulse generators 206A to 206H and the control power supplies 207A to 207H are electrically connected to the gate drivers 205A to 205H, respectively. The pulse generators 206A to 206H are configured to output pulse signals for controlling the switching elements 411 to 418 to the gate drivers 205A to 205H, respectively. The control power supplies 207A to 207H are configured to apply operating voltages to the gate drivers 205A to 205H, respectively.

[0125] The negative electrodes of the DC power supply 201, the capacitors 202, the pulse generators 206A to 206H, and the negative electrodes of the control power supplies 207A to 207H are electrically connected to the fourth back electrodes 84A to 84D that function as ground terminals.

[0126] The source electrodes 41S of the switching elements 411 to 418 are electrically connected to the surface electrodes 34 (anode electrodes) of the corresponding two semiconductor light-emitting elements 30 to be controlled and the cathode electrodes 72 of the protection diodes 70A to 70H, respectively. The second electrodes 42B of the capacitors 421 to 428 and the anode electrodes 71 of the protection diodes 70A to 70H are electrically connected to the back electrodes 35 (cathode electrodes) of the corresponding two semiconductor light-emitting elements 30, respectively.

[0127] The source electrodes 41S of the switching elements 411 to 418 and the cathode electrodes 72 of the protection diodes 70A to 70H are electrically connected to the ground terminals (the fourth back electrodes 84A to 84D of the second electrode layer 28B) via ground wirings (the fourth surface electrodes 64A to 64D of the first electrode layer 28A, and the fourth intermediate electrodes 94A to 94D of the third and fourth electrode layers 28C and 28D). The fourth back electrodes 84A to 84D provided as the ground terminals are connected to the ground.

[0128] In the semiconductor light-emitting device 10 configured as described above, when the switching elements 411 to 418 of the drive circuits 40A to 40H are in the off state, the capacitors 421 to 428 are charged by the DC power supply 201. Then, when the switching elements 411 to 418 are switched from the off state to the on state, current flows from the capacitors 421 to 428 to the respective semiconductor light-emitting elements 30 to be controlled through the switching elements 411 to 418. As a result, laser light that is pulse-emitted from the semiconductor light-emitting elements 30 is emitted. In this way, each of the drive circuits 40A to 40H is configured to individually drive one or more (two in the first embodiment) of the plurality of semiconductor light-emitting elements 30.

[0129] As an example, the drive circuits 40A to 40H drive the semiconductor light-emitting elements 30 to be driven in sequence. In this case, for example, compared with a semiconductor light-emitting device including only one semiconductor light-emitting element, the pulse emission of each semiconductor light-emitting element 30 can be adjusted so that the pulse interval of the laser light emitted from the semiconductor light-emitting device 10 becomes shorter. Therefore, an increase in the number of pulses per unit time can be achieved. Further, since the semiconductor light-emitting elements 30 to be driven by the drive circuits 40A to 40H emit light in sequence, heat generation of each semiconductor light-emitting element 30 can be suppressed compared with a semiconductor light-emitting device including only one semiconductor light-emitting element.

[0130] Next, the operation of the semiconductor light-emitting device 10 of the first embodiment will be described. In recent years, there has been an increasing demand for higher output power in semiconductor light-emitting devices. For example, when applying a semiconductor light-emitting device to a laser system such as LiDAR, an expansion of the viewing angle and an improvement in resolution are required. To meet such requirements, the semiconductor light-emitting device 10 of the first embodiment is embodied as a multi-channel (8 channels in the first embodiment) drive type light-emitting module that drives a plurality of semiconductor light-emitting elements 30 by a plurality of (8 in the first embodiment) drive circuits 40A to 40H.

[0131] Here, in the first embodiment, a light reflecting element 50 is disposed in the central region AC of the substrate 20, and a plurality of (16 in the first embodiment) semiconductor light-emitting elements 30 are disposed around it. In this configuration, while adopting an end-face light-emitting element for the semiconductor light-emitting element 30, the light emitted from the semiconductor light-emitting element 30 can be reflected in a direction intersecting the substrate 20 (for example, a direction perpendicular to the substrate 20). Therefore, compared with the case where a plurality of semiconductor light-emitting elements 30 constituted by end-face light-emitting elements are disposed at the ends of the substrate 20, more semiconductor light-emitting elements 30 can be mounted on the semiconductor light-emitting device 10. Thereby, it is possible to increase the number of channels and expand the viewing angle and improve the resolution as required in LiDAR, for example.

[0132] The semiconductor light-emitting device 10 of the first embodiment has the following advantages. (1-1) The semiconductor light-emitting device 10 includes a light reflecting element 50 disposed in the central region AC of the substrate 20. The light reflecting element 50 reflects the light from a plurality of semiconductor light-emitting elements 30 constituted by end-face light-emitting elements in a direction intersecting the substrate 20. Thereby, compared with the case where the semiconductor light-emitting elements 30 are disposed at the ends of the substrate 20, more semiconductor light-emitting elements 30 can be mounted on the semiconductor light-emitting device 10.

[0133] (1-2) Since a plurality of semiconductor light-emitting elements 30 are intensively disposed near the center of the substrate 20 around the light reflecting element 50, the degree of freedom in the wiring design of the drive circuits 40A to 40H for driving the plurality of semiconductor light-emitting elements 30 and related circuit elements is improved. As a result, it becomes possible to further increase the number of channels.

[0134] (1-3) By arranging the light reflection element 50 in the central region AC of the substrate 20, a plurality of semiconductor light emitting elements 30 can be arranged on both sides of the light reflection element 50. As a result, not only can more semiconductor light emitting elements 30 be mounted on the semiconductor light emitting device 10, but also the drive circuits 40A to 40H can be symmetrically arranged on the substrate 20 with the light reflection element 50 as the center. Thereby, while increasing the number of channels, the wiring design can be facilitated.

[0135] (1-4) For the light reflection element 50, for example, a light reflection type mirror having a reflection angle of 45° can be adopted. Therefore, while simplifying the configuration of the light reflection element 50, the number of semiconductor light emitting elements 30 can be increased.

[0136] (1-5) The semiconductor light emitting device 10 includes a plurality of semiconductor light emitting elements 30 and drive circuits 40A to 40H for driving the plurality of semiconductor light emitting elements 30. In this configuration, since the current path CP of the current flowing through each drive circuit 40 and the semiconductor light emitting element 30 to be driven by it is formed on the substrate 20, the current path CP is shorter than the case where the drive circuits 40A to 40H are provided outside the semiconductor light emitting device 10. Thereby, the inductance caused by the length of the current path CP can be reduced, and the variation in the inductance of each current path CP can be reduced. As a result, the pulse width of the laser light emitted by each semiconductor light emitting element 30 can be made shorter, and the variation in the pulse width can be reduced.

[0137] (1-6) Each drive circuit 40 includes a plurality of capacitors connected in parallel. For example, the drive circuit 40A includes four capacitors 421 connected in parallel, and the same number of capacitors are provided in the other drive circuits 40B to 40H. In this configuration, the inductance can be reduced compared to the case where each drive circuit 40 includes a single capacitor.

[0138] (1-7) The semiconductor light-emitting device 10 includes protection diodes 70A to 70H that are each connected in reverse parallel to one or more (two in the first embodiment) semiconductor light-emitting elements 30 provided in each channel. With this configuration, it is possible to suppress an excessive reverse bias from being applied to the semiconductor light-emitting element 30 and increase the peak light output of each semiconductor light-emitting element 30.

[0139] (1-8) The number of wires W1 located on the current path CP between the switching element of each drive circuit 40 (for example, the switching element 411 of the drive circuit 40A) and the semiconductor light-emitting element 30 to be controlled is plural (for example, four or more in the first embodiment). With this configuration, the inductance in the entire semiconductor light-emitting device 10 can be reduced.

[0140] [Second Embodiment] Next, with reference to FIGS. 13 to 22, the semiconductor light-emitting device 10 of the second embodiment will be described. The semiconductor light-emitting device 10 of the second embodiment is mainly different from the semiconductor light-emitting device 10 of the first embodiment in that the configurations of the drive circuits 40A to 40H are changed. Hereinafter, the second embodiment will be described centering on the differences from the semiconductor light-emitting device 10 of the first embodiment, and the same reference numerals will be given to the components common to the first embodiment and the detailed description thereof will be omitted.

[0141] FIG. 13 shows a schematic plan structure of the semiconductor light-emitting device 10 of the second embodiment. FIG. 14 shows a schematic plan structure of the central portion of the semiconductor light-emitting device 10 of FIG. 13. FIGS. 15 to 18 show schematic plan structures of four different portions of the peripheral region of the semiconductor light-emitting device 10 of FIG. 13. FIG. 19 shows a schematic back electrode structure of the semiconductor light-emitting device 10 of FIG. 13. FIG. 20 shows a schematic surface-side intermediate electrode structure of the semiconductor light-emitting device 10 of FIG. 13, and FIG. 21 shows a schematic back-side intermediate electrode structure of the semiconductor light-emitting device 10 of FIG. 13. FIG. 22 shows a schematic circuit of the light-emitting system 200 including the semiconductor light-emitting device 10 of FIG. 13. In FIGS. 13 to 18, the openings of the main surface resist layer 29A are indicated by two-dot chain lines, and in FIG. 19, the openings of the back surface resist layer 29B are indicated by two-dot chain lines.

[0142] [2-1. Overall Structure of the Semiconductor Light-Emitting Device of the Second Embodiment] As shown in FIG. 13, the semiconductor light-emitting device 10 of the second embodiment includes a plurality (for example, 16 in FIG. 13) of semiconductor light-emitting elements 30, a plurality (for example, 8 in FIG. 13) of drive circuits 40A to 40D, and a light reflection element 50. In the following description, when the drive circuits 40A to 40H are not distinguished from each other, the drive circuits 40A to 40H are described as drive circuits 40 (or each drive circuit 40).

[0143] The plurality of semiconductor light-emitting elements 30, the plurality of drive circuits 40, and the light reflection element 50 are provided on the substrate 20. The semiconductor light-emitting device 10 is embodied as a multi-channel (8-channel in the example of FIG. 13) drive type light-emitting module that drives the plurality of semiconductor light-emitting elements 30 by the plurality of drive circuits 40. Note that the number of semiconductor light-emitting elements 30 and the number of drive circuits 40 can be appropriately changed according to the number of channels.

[0144] The semiconductor light-emitting device 10 further includes gate drivers 205A to 205H and capacitors 208A to 208H. Note that the semiconductor light-emitting device 10 of the second embodiment does not include the protection diodes 70A to 70H (see FIG. 1) mounted on the substrate 20 in the first embodiment. In the second embodiment, such protection diodes 70A to 70H can be mounted on, for example, a circuit board (not shown) on which the semiconductor light-emitting device 10 is mounted.

[0145] In the semiconductor light-emitting device 10 of the second embodiment, different from the first embodiment, lateral transistors are used for the switching elements 411 to 418 of the drive circuits 40A to 40H. An example of such a lateral transistor is a nitride semiconductor transistor using a nitride semiconductor (for example, gallium nitride (GaN)). In the second embodiment, for example, a high electron mobility transistor (HEMT) using a nitride semiconductor is used. Note that as long as it is a lateral transistor, MOSFETs may be used for the switching elements 411 to 418.

[0146] As shown in FIGS. 15 to 18, gate drivers 205A to 205H are electrically connected to gate electrodes 41G of switching elements 411 to 418 of drive circuits 40A to 40H, respectively. The gate drivers 205A to 205H are configured to individually drive the switching elements 411 to 418 by applying gate voltage signals to the gate electrodes 41G of the switching elements 411 to 418, respectively. Capacitors 208A to 208H are electrically connected to the gate drivers 205A to 205H, respectively.

[0147] [2-2. Electrode Layers of Substrate] Next, the configurations of the first to fourth electrode layers 28A to 28D of the substrate 20 will be described. In the second embodiment, the configurations of the first to fourth electrode layers 28A to 28D are different from each other.

[0148] [2-2A. First Electrode Layer (Surface Electrode Layer)] As shown in FIGS. 13 to 18, the first electrode layer 28A (surface electrode layer) located on the main surface 21 of the substrate 20 includes a plurality of surface electrodes (pattern electrodes) spaced apart from each other. In the second embodiment, the first electrode layer 28A includes first surface electrodes 301A to 301H, second surface electrodes 302A to 302H, a third surface electrode 303, fourth surface electrodes 304A to 304H, fifth surface electrodes 305A to 305H, sixth surface electrodes 306A to 306H, seventh surface electrodes 307A to 307H, eighth surface electrodes 308A to 308D, ninth surface electrodes 309A to 309D, tenth surface electrodes 310A to 310D, and an eleventh surface electrode 311.

[0149] The first surface electrodes 301A to 301H are used for mounting a plurality of semiconductor light-emitting elements 30. In the second embodiment, two semiconductor light-emitting elements 30 are mounted on each of the first surface electrodes 301A to 301H. The second surface electrodes 302A to 302H, the third surface electrode 303, the fourth surface electrodes 304A to 304H, and the fifth surface electrodes 305A to 305H are used for mounting the drive circuits 40A to 40H. The fifth surface electrodes 305A to 305H, the sixth surface electrodes 306A to 306H, and the seventh surface electrodes 307A to 307H are used for mounting the gate drivers 205A to 205H.

[0150] The eighth surface electrodes 308A to 308D and the ninth surface electrodes 309A to 309D are provided for electrical connection with pulse generators 206A to 206H (see FIG. 22) located outside the semiconductor light-emitting device 10. Each of the eighth surface electrodes 308A to 308D and the ninth surface electrodes 309A to 309D is electrically connected to one of the seventh surface electrodes 307A to 307H via a conduction path using the second to fourth electrode layers 28B to 28D.

[0151] The tenth surface electrodes 310A to 310D are provided for electrical connection with control power supplies 207A to 207H (see FIG. 22) located outside the semiconductor light-emitting device 10. Each of the tenth surface electrodes 310A to 310D is electrically connected to two of the sixth surface electrodes 306A to 306H via a conduction path using the second to fourth electrode layers 28B to 28D.

[0152] The eleventh surface electrode 311 is used for mounting the light reflection element 50. The eleventh surface electrode 311 is configured in the same manner as the sixth surface electrode 66 of the first embodiment. Similar to the first embodiment, the eleventh surface electrode 66 has a rectangular shape in plan view and includes two long sides along the X-axis direction and two short sides along the Y-axis direction. The eleventh surface electrode 66 is located in the central region AC of the substrate 20. Therefore, the light reflection element 50 is mounted in the central region AC.

[0153] As shown in FIGS. 13 and 15 to 18, other surface electrodes other than the eleventh surface electrode 311, that is, the first surface electrodes 301A to 301H, the second surface electrodes 302A to 302H, the third surface electrode 303, the fourth surface electrodes 304A to 304H, the fifth surface electrodes 305A to 305H, the sixth surface electrodes 306A to 306H, the seventh surface electrodes 307A to 307H, the eighth surface electrodes 308A to 308D, the ninth surface electrodes 309A to 309D, and the tenth surface electrodes 310A to 310D are located in the peripheral region AP of the substrate 20, which is outside the eleventh surface electrode 311 in plan view.

[0154] As shown in FIG. 14, the first surface electrodes 301A to 301H are arranged around the eleventh surface electrode 311 at positions close to the eleventh surface electrode 311. The first surface electrodes 301A to 301H are arranged in a row in the X-axis direction along the two long sides of the eleventh surface electrode 311, that is, along the two light incident surfaces 51A and 51B of the light reflecting element 50. In the second embodiment, the first surface electrodes 301A to 301D are arranged in a row in the X-axis direction along the light incident surface 51A, and the first surface electrodes 301E to 301H are arranged in a row in the X-axis direction along the light incident surface 51B. Therefore, the 16 semiconductor light emitting elements 30 are intensively arranged in the vicinity of the central region AC where the light reflecting element 50 is located.

[0155] The first surface electrodes 301A to 301H and the second surface electrodes 302A to 302H are arranged so as to have a symmetric relationship in the peripheral region AP of the substrate 20. In the second embodiment, the first surface electrodes 301A to 301H and the second surface electrodes 302A to 302H are arranged in a line-symmetric relationship with respect to each of the two virtual center lines VC and HC.

[0156] The third surface electrode 303 is formed in a rectangular frame shape surrounding the second surface electrodes 302A to 302H in a plan view. The third surface electrode 303 includes a central opening at the center of the substrate 20, and the first surface electrodes 301A to 301H, the second surface electrodes 302A to 302H, and the eleventh surface electrode 311 are arranged in this central opening.

[0157] Similar to the first embodiment, the peripheral region AP of the substrate 20 is divided into four wiring (electrode) arrangement regions based on the two virtual center lines VC and HC, and corresponds to the first arrangement region AP1, the second arrangement region AP2, the third arrangement region AP3, and the fourth arrangement region AP4 in the lower right region, the lower left region, the upper right region, and the upper left region of the substrate 20 in FIG. 13, respectively. Hereinafter, the surface electrode layout in the first to fourth arrangement regions AP1 to AP4 will be described.

[0158] As shown in FIGS. 13 and 15, the first arrangement region AP1 (the lower right region in FIG. 13) is used for the arrangement of the first surface electrodes 301A and 301B, the second surface electrodes 302A and 302B, the fourth surface electrodes 304A and 304B, the fifth surface electrodes 305A and 305B, the sixth surface electrodes 306A and 306B, the seventh surface electrodes 307A and 307B, the eighth surface electrode 308A, the ninth surface electrode 309A, and the tenth surface electrode 310A. The first arrangement region AP1 also includes a part of the third surface electrode 303 (the lower right region in FIG. 13).

[0159] The first surface electrodes 301A and 301B are each used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 302A, 303, 304A, and 305A are used for mounting the drive circuit 40A, and the third surface electrode 303 and the fifth to seventh surface electrodes 305A, 306A, and 307A are used for mounting the gate driver 205A. Also, the third and sixth surface electrodes 303 and 306A are used for mounting the capacitor 208A.

[0160] Similarly, the second to fifth surface electrodes 302B, 303, 304B, and 305B are used for mounting the drive circuit 40B, and the third surface electrode 303 and the fifth to seventh surface electrodes 305B, 306B, and 307B are used for mounting the gate driver 205B. Also, the third and sixth surface electrodes 303 and 306B are used for mounting the capacitor 208B.

[0161] The eighth surface electrode 308A is provided for electrical connection with the pulse generator 206A (see FIG. 22), and the ninth surface electrode 309A is provided for electrical connection with the pulse generator 206B (see FIG. 22). The tenth surface electrode 310A is provided for electrical connection with the control power supplies 207A and 207B.

[0162] Therefore, the third surface electrode 303 is shared for mounting the drive circuits 40A and 40B, the gate drivers 205A and 205B, and the capacitors 208A and 208B. The first placement region AP1 of the substrate 20 is allocated for mounting four semiconductor light-emitting elements 30, two drive circuits 40A and 40B, two gate drivers 205A and 205B, and two capacitors 208A and 208B.

[0163] The first surface electrode 301A is disposed closer to the virtual center line VC within the first placement region AP1. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301A are each connected to the second surface electrode 302A by a wire W4. The second surface electrode 302A is provided at a position adjacent or close to the first surface electrode 301A in the Y-axis direction. Note that the number of the wires W4 is not particularly limited and may be one or more. In the second embodiment, for example, from the viewpoint of reducing the wiring inductance of the entire circuit, the number of the wires W4 is plural (for example, four or more).

[0164] The four capacitors 421 of the drive circuit 40A are mounted across both the second and third surface electrodes 302A and 303. The first electrode 42A of each capacitor 421 is joined to the second surface electrode 302A by a conductive bonding material, and the second electrode 42B of each capacitor 421 is joined to the third surface electrode 303 by a conductive bonding material. The four capacitors 421 are arranged in a row in the X-axis direction with their long sides adjacent to each other while being spaced apart from each other. Note that, similar to the first embodiment, each capacitor 421 may be, for example, a ceramic capacitor.

[0165] The switching element 411 of the drive circuit 40A is mounted across the third to fifth surface electrodes 303, 304A, 305A. The third surface electrode 303 includes two peripheral openings within the first arrangement region AP1, and the fourth to seventh surface electrodes 304A, 305A, 306A, 307A are arranged in one of the peripheral openings, and the fourth to seventh surface electrodes 304B, 305B, 306B, 307B are arranged in the other peripheral opening. The fourth surface electrode 304A has an oval shape extending in the Y-axis direction, and the fifth surface electrode 305A has a rectangular shape extending in the X-axis direction. The fifth surface electrode 305A is provided at a position adjacent or close to the fourth surface electrode 304A in the X-axis direction.

[0166] The source electrode 41S of the switching element 411 is mounted on the third surface electrode 303 by a conductive bonding material, and the drain electrode 41D of the switching element 411 is mounted on the fourth surface electrode 304A by a conductive bonding material. The gate electrode 41G of the switching element 411 is mounted on the fifth surface electrode 305A by a conductive bonding material. The switching element 411 is provided at a position adjacent or close to the four capacitors 421 in the Y-axis direction. The switching element 411 is provided closer to the first side surface 23 of the substrate 20 than the capacitor 421 in the Y-axis direction.

[0167] The gate driver 205A is mounted across the third surface electrode 303 and the fifth to seventh surface electrodes 305A, 306A, 307A. The sixth and seventh surface electrodes 306A, 307A are provided adjacent or close to the fifth surface electrode 305A in the X-axis direction. The third surface electrode 303 includes an extension portion located between the sixth and seventh surface electrodes 306A, 307A, and the sixth and seventh surface electrodes 306A, 307A are provided close to each other in the Y-axis direction with the extension portion of the third surface electrode 303 therebetween. The gate driver 205A includes a plurality of terminals 205P that are individually mounted on and electrically connected to the third surface electrode 303 and the fifth to seventh surface electrodes 305A, 306A, 307A.

[0168] The gate driver 205A is electrically connected to the gate electrode 41G of the switching element 411 via the fifth surface electrode 305A. As will be described later, power from the control power supply 207A (see FIG. 22) is supplied to the gate driver 205A via a conduction path formed by the sixth and tenth surface electrodes 306A and 310A and the second to fourth electrode layers 28B to 28D. Further, the gate driver 205A is electrically connected to the pulse generator 206A (see FIG. 22) via a conduction path formed by the seventh and eighth surface electrodes 307A and 308A and the second to fourth electrode layers 28B to 28D.

[0169] The capacitor 208A is mounted across both the third and sixth surface electrodes 303 and 306A. The capacitor 208A is provided at a position adjacent or close to the gate driver 205A in the X-axis direction. The gate driver 205A is positioned between the switching element 411 and the capacitor 208A in the X-axis direction. The capacitor 208A includes a first electrode 208P electrically connected to the sixth surface electrode 306A and a second electrode 208Q electrically connected to the third surface electrode 303. Therefore, the capacitor 208A is electrically connected to the gate driver 205A.

[0170] The second surface electrode 302B is disposed adjacent to the first surface electrode 301A in the X-axis direction within the first arrangement region AP1. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the second surface electrode 302B are each connected to the second surface electrode 302B by a wire W4. The second surface electrode 302B is provided at a position adjacent or close to the first surface electrode 301B in both the X-axis and Y-axis directions.

[0171] The four capacitors 422 of the drive circuit 40B are mounted across both the second and third surface electrodes 302B and 303. The first electrode 42A of each capacitor 422 is joined to the second surface electrode 302B by a conductive bonding material, and the second electrode 42B of each capacitor 422 is joined to the third surface electrode 303 by a conductive bonding material. The four capacitors 422 are arranged in a row in the Y-axis direction with their long sides adjacent to each other while being spaced apart from each other. Note that, similar to the first embodiment, each capacitor 422 may be, for example, a ceramic capacitor.

[0172] The switching element 412 of the drive circuit 40B is mounted across the third to fifth surface electrodes 303, 304B, and 305B. The fourth surface electrode 304B has an oval shape extending in the X-axis direction, and the fifth surface electrode 305B has a rectangular shape extending in the Y-axis direction. The fifth surface electrode 305B is provided at a position adjacent or close to the fourth surface electrode 304B in the Y-axis direction.

[0173] The source electrode 41S of the switching element 412 is mounted on the third surface electrode 303 by a conductive bonding material, the drain electrode 41D of the switching element 412 is mounted on the fourth surface electrode 304B by a conductive bonding material, and the gate electrode 41G of the switching element 412 is mounted on the fifth surface electrode 305B by a conductive bonding material. The switching element 412 is provided at a position adjacent or close to the four capacitors 422 in the X-axis direction. The switching element 412 is provided closer to the fourth side surface 26 of the substrate 20 than the capacitor 422 in the X-axis direction.

[0174] The gate driver 205B is mounted across the third surface electrode 303 and the fifth to seventh surface electrodes 305B, 306B, 307B. The sixth and seventh surface electrodes 306B, 307B are provided adjacent to or in proximity to the fifth surface electrode 305B in the Y-axis direction. The third surface electrode 303 includes an extending portion located between the sixth and seventh surface electrodes 306B, 307B, and the sixth and seventh surface electrodes 306B, 307B are provided close to each other in the X-axis direction with the extending portion of the third surface electrode 303 therebetween. The gate driver 205B includes a plurality of terminals 205P that are individually mounted to and electrically connected to the third surface electrode 303 and the fifth to seventh surface electrodes 305A, 306A, 307A.

[0175] The gate driver 205B is electrically connected to the gate electrode 41G of the switching element 412 via the fifth surface electrode 305B. As will be described later, power from the control power supply 207B (see FIG. 22) is supplied to the gate driver 205B via a conduction path formed by the sixth and tenth surface electrodes 306B, 310A and the second to fourth electrode layers 28B to 28D. Further, the gate driver 205B is electrically connected to the pulse generator 206B (see FIG. 22) via a conduction path formed by the seventh and ninth surface electrodes 307B, 309A and the second to fourth electrode layers 28B to 28D.

[0176] The capacitor 208B is mounted across both the third and sixth surface electrodes 303, 306B. The capacitor 208B is provided at a position adjacent to or in proximity to the gate driver 205B in the Y-axis direction. The gate driver 205B is located between the switching element 412 and the capacitor 208B in the X-axis direction. The capacitor 208B includes a first electrode 208P electrically connected to the sixth surface electrode 306B and a second electrode 208Q electrically connected to the third surface electrode 303. Accordingly, the capacitor 208B is electrically connected to the gate driver 205B.

[0177] As shown in FIGS. 13 and 16, the second placement region AP2 (the lower left region in FIG. 13) is used for the placement of the first surface electrodes 301C, 301D, the second surface electrodes 302C, 302D, the fourth surface electrodes 304C, 304D, the fifth surface electrodes 305C, 305D, the sixth surface electrodes 306C, 306D, the seventh surface electrodes 307C, 307D, the eighth surface electrode 308B, the ninth surface electrode 309B, and the tenth surface electrode 310B. The second placement region AP2 also includes a part of the third surface electrode 303 (the lower left region in FIG. 13).

[0178] The first surface electrodes 301C, 301D are each used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 302C, 303, 304C, 305C are used for mounting the drive circuit 40C, and the third surface electrode 303 and the fifth to seventh surface electrodes 305C, 306C, 307C are used for mounting the gate driver 205C. Also, the third and sixth surface electrodes 303, 306C are used for mounting the capacitor 208C.

[0179] Similarly, the second to fifth surface electrodes 302D, 303, 304D, 305D are used for mounting the drive circuit 40D, and the third surface electrode 303 and the fifth to seventh surface electrodes 305D, 306D, 307D are used for mounting the gate driver 205D. Also, the third and sixth surface electrodes 303, 306D are used for mounting the capacitor 208D.

[0180] The eighth surface electrode 308B is provided for electrical connection with the pulse generator 206C (see FIG. 22), and the ninth surface electrode 309B is provided for electrical connection with the pulse generator 206D (see FIG. 22). The tenth surface electrode 310B is provided for electrical connection with the control power supplies 207C, 207D.

[0181] Therefore, the third surface electrode 303 is shared for mounting the drive circuits 40C and 40D, the gate drivers 205C and 205D, and the capacitors 208C and 208D. The second placement area AP2 of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40C and 40D, two gate drivers 205C and 205D, and two capacitors 208C and 208D.

[0182] The first surface electrode 301C is arranged closer to the virtual center line VC within the second placement area AP2. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301C are each connected to the second surface electrode 302C by a wire W4. The second surface electrode 302C is provided at a position adjacent or close to the first surface electrode 301C in the Y-axis direction.

[0183] The first surface electrode 301D is arranged adjacent to the first surface electrode 301C in the X-axis direction within the second placement area AP2. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301D are each connected to the second surface electrode 302D by a wire W4. The second surface electrode 302D is provided at a position adjacent or close to the first surface electrode 301D in both the X-axis direction and the Y-axis direction.

[0184] The layout of some of the surface electrodes (and the elements mounted thereon) located within the second placement area AP2 corresponds to the layout of some of the corresponding surface electrodes (and the elements mounted thereon) located within the first placement area AP1 rotated 90° clockwise in plan view.

[0185] For example, the layout of the fourth to seventh surface electrodes 304C, 305C, 306C, 307C in the second arrangement region AP2 corresponds to that of the fourth to seventh surface electrodes 304B, 305B, 306B, 307B in the first arrangement region AP1 rotated clockwise by 90°. Therefore, the layout of the drive circuit 40C (capacitor 423 and switching element 413), gate driver 205C, and capacitor 208C in the second arrangement region AP2 corresponds to that of the drive circuit 40B (capacitor 422 and switching element 412), gate driver 205B, and capacitor 208B in the first arrangement region AP1 rotated clockwise by 90°. For this reason, detailed descriptions of the arrangements of the fourth to seventh surface electrodes 304C, 305C, 306C, 307C, as well as the drive circuit 40C (capacitor 423 and switching element 413), gate driver 205C, and capacitor 208C, are omitted.

[0186] Similarly, the layout of the fourth to seventh surface electrodes 304D, 305D, 306D, 307D in the second arrangement region AP2 corresponds to that of the fourth to seventh surface electrodes 304A, 305A, 306A, 307A in the first arrangement region AP1 rotated clockwise by 90°. Therefore, the layout of the drive circuit 40D (capacitor 424 and switching element 414), gate driver 205D, and capacitor 208D in the second arrangement region AP2 corresponds to that of the drive circuit 40A (capacitor 421 and switching element 411), gate driver 205A, and capacitor 208A in the first arrangement region AP1 rotated clockwise by 90°. For this reason, detailed descriptions of the arrangements of the fourth to seventh surface electrodes 304D, 305D, 306D, 307D, as well as the drive circuit 40D (capacitor 424 and switching element 414), gate driver 205D, and capacitor 208D, are omitted.

[0187] Note that the gate driver 205C is supplied with power from the control power supply 207C (see FIG. 22) via a conduction path formed by the sixth and tenth surface electrodes 306C and 310B and the second to fourth electrode layers 28B to 28D. Also, the gate driver 205C is electrically connected to the pulse generator 206C (see FIG. 22) via a conduction path formed by the seventh and eighth surface electrodes 307C and 308B and the second to fourth electrode layers 28B to 28D.

[0188] Also, the gate driver 205D is supplied with power from the control power supply 207D (see FIG. 22) via a conduction path formed by the sixth and tenth surface electrodes 306D and 310B and the second to fourth electrode layers 28B to 28D. Also, the gate driver 205D is electrically connected to the pulse generator 206D (see FIG. 22) via a conduction path formed by the seventh and ninth surface electrodes 307D and 309B and the second to fourth electrode layers 28B to 28D.

[0189] As shown in FIGS. 13 and 17, the third placement region AP3 (the upper right region in FIG. 13) is used for the placement of the first surface electrodes 301E and 301F, the second surface electrodes 302E and 302F, the fourth surface electrodes 304E and 304F, the fifth surface electrodes 305E and 305F, the sixth surface electrodes 306E and 306F, the seventh surface electrodes 307E and 307F, the eighth surface electrode 308C, the ninth surface electrode 309C, and the tenth surface electrode 310C. The third placement region AP3 also includes a part of the third surface electrode 303 (the upper right region in FIG. 13).

[0190] Each of the first surface electrodes 301E and 301F is used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 302E, 303, 304E, and 305E are used for mounting the drive circuit 40E, and the third surface electrode 303 and the fifth to seventh surface electrodes 305E, 306E, and 307E are used for mounting the gate driver 205E. Also, the third and sixth surface electrodes 303 and 306E are used for mounting the capacitor 208E.

[0191] Similarly, the second to fifth surface electrodes 302F, 303, 304F, 305F are used for mounting the drive circuit 40F, and the third surface electrode 303 and the fifth to seventh surface electrodes 305F, 306F, 307F are used for mounting the gate driver 205F. Also, the third and sixth surface electrodes 303, 306F are used for mounting the capacitor 208F.

[0192] The eighth surface electrode 308C is provided for electrical connection with the pulse generator 206E (see FIG. 22), and the ninth surface electrode 309C is provided for electrical connection with the pulse generator 206F (see FIG. 22). The tenth surface electrode 310C is provided for electrical connection with the control power supplies 207E, 207F.

[0193] Therefore, the third surface electrode 303 is shared for mounting the drive circuits 40E, 40F, the gate drivers 205E, 205F, and the capacitors 208E, 208F. The third placement region AP3 of the substrate 20 is allocated for mounting four semiconductor light-emitting elements 30, two drive circuits 40E, 40F, two gate drivers 205E, 205F, and two capacitors 208E, 208F.

[0194] The first surface electrode 301E is arranged closer to the virtual center line VC within the third placement region AP3. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301E are each connected to the second surface electrode 302E by a wire W4. The second surface electrode 302E is provided at a position adjacent or close to the first surface electrode 301E in the Y-axis direction.

[0195] The first surface electrode 301F is arranged adjacent to the first surface electrode 301E in the X-axis direction within the third placement region AP2. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301F are each connected to the second surface electrode 302F by a wire W4. The second surface electrode 302F is provided at a position adjacent or close to the first surface electrode 301F in both the X-axis direction and the Y-axis direction.

[0196] The layout of some surface electrodes (and the elements mounted thereon) located within the third arrangement region AP3 corresponds to the layout of some corresponding surface electrodes (and the elements mounted thereon) located within the first arrangement region AP1 rotated counterclockwise by 90° in plan view.

[0197] For example, the layout of the fourth to seventh surface electrodes 304E, 305E, 306E, 307E within the third arrangement region AP3 corresponds to the layout of the fourth to seventh surface electrodes 304B, 305B, 306B, 307B within the first arrangement region AP1 rotated counterclockwise by 90°. Therefore, the layout of the drive circuit 40E (capacitor 425 and switching element 415), gate driver 205E, and capacitor 208E within the third arrangement region AP3 corresponds to the layout of the drive circuit 40B (capacitor 422 and switching element 412), gate driver 205B, and capacitor 208B within the first arrangement region AP1 rotated counterclockwise by 90°. For this reason, a detailed description of the arrangement of the fourth to seventh surface electrodes 304E, 305E, 306E, 307E, as well as the arrangement of the drive circuit 40E (capacitor 425 and switching element 415), gate driver 205E, and capacitor 208E, will be omitted.

[0198] Similarly, the layout of the fourth to seventh surface electrodes 304F, 305F, 306F, 307F in the third arrangement region AP3 corresponds to the layout of the fourth to seventh surface electrodes 304A, 305A, 306A, 307A in the first arrangement region AP1 rotated counterclockwise by 90°. Therefore, the layout of the drive circuit 40F (capacitor 426 and switching element 416), gate driver 205F, and capacitor 208F in the third arrangement region AP3 corresponds to the layout of the drive circuit 40A (capacitor 421 and switching element 411), gate driver 205A, and capacitor 208A in the first arrangement region AP1 rotated counterclockwise by 90°. For this reason, detailed descriptions of the arrangement of the fourth to seventh surface electrodes 304F, 305F, 306F, 307F and the arrangement of the drive circuit 40F (capacitor 426 and switching element 416), gate driver 205F, and capacitor 208F are omitted.

[0199] Note that power from the control power supply 207E (see FIG. 22) is supplied to the gate driver 205E through a conduction path formed by the sixth and tenth surface electrodes 306E, 310C and the second to fourth electrode layers 28B to 28D. Also, the gate driver 205E is electrically connected to the pulse generator 206E (see FIG. 22) through a conduction path formed by the seventh and eighth surface electrodes 307E, 308C and the second to fourth electrode layers 28B to 28D.

[0200] Also, power from the control power supply 207F (see FIG. 22) is supplied to the gate driver 205F through a conduction path formed by the sixth and tenth surface electrodes 306F, 310C and the second to fourth electrode layers 28B to 28D. Also, the gate driver 205F is electrically connected to the pulse generator 206F (see FIG. 22) through a conduction path formed by the seventh and ninth surface electrodes 307F, 309C and the second to fourth electrode layers 28B to 28D.

[0201] As shown in FIGS. 13 and 18, the fourth arrangement region AP4 (the upper left region in FIG. 13) is used for the arrangement of the first surface electrodes 301G, 301H, the second surface electrodes 302G, 302H, the fourth surface electrodes 304G, 304H, the fifth surface electrodes 305G, 305H, the sixth surface electrodes 306G, 306H, the seventh surface electrodes 307G, 307H, the eighth surface electrode 308D, the ninth surface electrode 309D, and the tenth surface electrode 310D. The fourth arrangement region AP4 also includes a part of the third surface electrode 303 (the upper left region in FIG. 13).

[0202] The first surface electrodes 301G, 301H are each used for mounting two semiconductor light-emitting elements 30 as described above. The second to fifth surface electrodes 302G, 303, 304G, 305G are used for mounting the drive circuit 40G, and the third surface electrode 303 and the fifth to seventh surface electrodes 305G, 306G, 307G are used for mounting the gate driver 205G. Also, the third and sixth surface electrodes 303, 306G are used for mounting the capacitor 208G.

[0203] Similarly, the second to fifth surface electrodes 302H, 303, 304H, 305H are used for mounting the drive circuit 40H, and the third surface electrode 303 and the fifth to seventh surface electrodes 305H, 306H, 307H are used for mounting the gate driver 205H. Also, the third and sixth surface electrodes 303, 306H are used for mounting the capacitor 208H.

[0204] The eighth surface electrode 308D is provided for electrical connection with the pulse generator 206G (see FIG. 22), and the ninth surface electrode 309D is provided for electrical connection with the pulse generator 206H (see FIG. 22). The tenth surface electrode 310D is provided for electrical connection with the control power supplies 207G, 207H.

[0205] Therefore, the third surface electrode 303 is shared for mounting the drive circuits 40G and 40H, the gate drivers 205G and 205H, and the capacitors 208G and 208H. The fourth placement area AP4 of the substrate 20 is assigned for mounting four semiconductor light-emitting elements 30, two drive circuits 40G and 40H, two gate drivers 205G and 205H, and two capacitors 208G and 208H.

[0206] The first surface electrode 301G is disposed closer to the virtual center line VC within the fourth placement area AP4. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301G are each connected to the second surface electrode 302G by a wire W4. The second surface electrode 302G is provided at a position adjacent or close to the first surface electrode 301G in the Y-axis direction.

[0207] The first surface electrode 301H is disposed adjacent to the first surface electrode 301G in the X-axis direction within the fourth placement area AP4. The surface electrodes 34 (anode electrodes) of the two semiconductor light-emitting elements 30 mounted on the first surface electrode 301H are each connected to the second surface electrode 302H by a wire W4. The second surface electrode 302H is provided at a position adjacent or close to the first surface electrode 301H in both the X-axis direction and the Y-axis direction.

[0208] The layout of some surface electrodes (and the elements mounted thereon) located within the fourth placement area AP4 corresponds to the layout of some corresponding surface electrodes (and the elements mounted thereon) located within the second placement area AP2 rotated 90° clockwise in plan view. In other words, the layout of some surface electrodes (and the elements mounted thereon) located within the fourth placement area AP4 corresponds to the layout of some corresponding surface electrodes (and the elements mounted thereon) located within the third placement area AP3 rotated 90° counterclockwise.

[0209] For example, the layout of the fourth to seventh surface electrodes 304G, 305G, 306G, 307G in the fourth arrangement region AP4 corresponds to the layout of the fourth to seventh surface electrodes 304D, 305D, 306D, 307D in the second arrangement region AP2 rotated clockwise by 90°. Therefore, the layout of the drive circuit 40G (capacitor 427 and switching element 417), gate driver 205G, and capacitor 208G in the fourth arrangement region AP4 corresponds to the layout of the drive circuit 40D (capacitor 424 and switching element 414), gate driver 205D, and capacitor 208D in the second arrangement region AP2 rotated clockwise by 90°. For this reason, detailed descriptions of the arrangement of the fourth to seventh surface electrodes 304G, 305G, 306G, 307G and the arrangement of the drive circuit 40G (capacitor 427 and switching element 417), gate driver 205G, and capacitor 208G are omitted.

[0210] Similarly, the layout of the fourth to seventh surface electrodes 304H, 305H, 306H, 307H in the fourth arrangement region AP4 corresponds to the layout of the fourth to seventh surface electrodes 304C, 305C, 306C, 307C in the second arrangement region AP2 rotated clockwise by 90°. Therefore, the layout of the drive circuit 40H (capacitor 428 and switching element 418), gate driver 205H, and capacitor 208H in the fourth arrangement region AP4 corresponds to the layout of the drive circuit 40C (capacitor 423 and switching element 413), gate driver 205C, and capacitor 208C in the second arrangement region AP2 rotated clockwise by 90°. For this reason, detailed descriptions of the arrangement of the fourth to seventh surface electrodes 304H, 305H, 306H, 307H and the arrangement of the drive circuit 40H (capacitor 428 and switching element 418), gate driver 205H, and capacitor 208H are omitted.

[0211] Note that the gate driver 205G is supplied with power from the control power supply 207G (see FIG. 22) through a conduction path formed by the sixth and tenth surface electrodes 306G and 310D and the second to fourth electrode layers 28B to 28D. Further, the gate driver 205G is electrically connected to the pulse generator 206G (see FIG. 22) through a conduction path formed by the seventh and eighth surface electrodes 307G and 308D and the second to fourth electrode layers 28B to 28D.

[0212] Also, the gate driver 205H is supplied with power from the control power supply 207H (see FIG. 22) through a conduction path formed by the sixth and tenth surface electrodes 306H and 310D and the second to fourth electrode layers 28B to 28D. Further, the gate driver 205H is electrically connected to the pulse generator 206H (see FIG. 22) through a conduction path formed by the seventh and ninth surface electrodes 307H and 309D and the second to fourth electrode layers 28B to 28D.

[0213] [2-2B. Second Electrode Layer (Back Surface Electrode Layer)] As shown in FIG. 19, the second electrode layer 28B (back surface electrode layer) located on the back surface 22 of the substrate 20 includes a plurality of back surface electrodes (pattern electrodes) spaced apart from each other. In the second embodiment, the second electrode layer 28B includes first back surface electrodes 321A to 321H, second back surface electrodes 322A to 322H, third back surface electrodes 323A to 323C, fourth back surface electrodes 324A to 324H, fifth back surface electrodes 325A to 325H, sixth back surface electrodes 326A to 326D, seventh back surface electrodes 327A to 327D, eighth back surface electrodes 328A to 328D, and ninth back surface electrodes 329A to 329D.

[0214] The second back electrodes 322A to 322H, the third back electrodes 323A to 323C, the seventh back electrodes 327A to 327D, the eighth back electrodes 328A to 328D, and the ninth back electrodes 329A to 329D function as external electrode terminals that are electrically connected to a circuit board (not shown) when the semiconductor light-emitting device 10 is mounted on the circuit board. The first back electrodes 321A to 321H also function as heat-radiating electrodes for radiating heat to the outside of the semiconductor light-emitting device 10. Note that the fourth back electrodes 324A to 324H, the fifth back electrodes 325A to 325H, and the sixth back electrodes 326A to 326D are covered by a back resist layer 29B (see FIG. 7) and thus do not constitute external electrode terminals.

[0215] The first arrangement region AP1 (the lower left region in FIG. 19) is used for arranging a part of each of the first back electrodes 321A and 321B, the second back electrodes 322A and 322B, the third back electrodes 323A and 323B, the fourth back electrodes 324A and 324B, the fifth back electrodes 325A and 325B, the sixth back electrode 326A, the seventh back electrode 327A, the eighth back electrode 328A, and the ninth back electrode 329A.

[0216] The first back electrode 321A is provided for electrical connection to the first and fourth front electrodes 301A and 304A (both see FIG. 15) and includes a portion that overlaps the first and fourth front electrodes 301A and 304A in plan view. The first back electrode 321A is formed in an elongated shape extending in the Y-axis direction. The first back electrode 321B is provided for electrical connection to the first and fourth front electrodes 301B and 304B (both see FIG. 15) and includes a portion that overlaps the first and fourth front electrodes 301B and 304B in plan view. The first back electrode 321B is formed in an elongated shape extending in the X-axis direction.

[0217] The second back surface electrode 322A is provided for electrical connection with the second front surface electrode 302A (see FIG. 15), and includes a portion overlapping the second front surface electrode 302A in plan view. The second back surface electrode 322A is provided at a position adjacent to or close to the first back surface electrode 321A in the X-axis direction. The second back surface electrode 322B is provided for electrical connection with the second front surface electrode 302B (see FIG. 15), and includes a portion overlapping the second front surface electrode 302B in plan view. The second back surface electrode 322B is provided at a position adjacent to or close to the first back surface electrode 321B in the Y-axis direction.

[0218] The third back surface electrodes 323A and 323B are provided for electrical connection with the third front surface electrode 203 (see FIG. 15). The third back surface electrode 323A is formed in a substantially U shape in plan view. It includes a first portion 323A1 corresponding to half of the third back surface electrode 323A and a second portion 323A2 corresponding to the remaining half of the third back surface electrode 323A. The first portion 323A1 is arranged in the first arrangement region AP1, and the second portion 323A2 is arranged in a second arrangement region AP2 adjacent to the first arrangement region AP1. The first portion 323A1 and the second portion 323A2 have a shape that is line-symmetric with respect to the virtual center line VC.

[0219] The third back surface electrode 323B is formed in a substantially H shape in plan view. The third back surface electrode 323B is arranged over the first to fourth arrangement regions AP1 to AP4. The third back surface electrode 323B includes a first portion 323B1 located within the first arrangement region AP1. The first portion 323B1 is similar to a shape obtained by rotating the second portion 323A2 of the third back surface electrode 323A clockwise by 90°.

[0220] The fourth back surface electrode 324A is provided for electrical connection with the sixth front surface electrode 306A (see FIG. 15), and includes a portion overlapping the sixth front surface electrode 306A in plan view. The fourth back surface electrode 324B is provided for electrical connection with the sixth front surface electrode 306B (see FIG. 15), and includes a portion overlapping the sixth front surface electrode 306B in plan view. The fourth back surface electrodes 324A and 324B are formed in a circular shape, for example, and are respectively arranged within circular openings formed in the sixth back surface electrode 326A.

[0221] The fifth back surface electrode 325A is provided for electrical connection with the seventh front surface electrode 307A (see FIG. 15), and includes a portion overlapping with the seventh front surface electrode 307A in a plan view. The fifth back surface electrode 325B is provided for electrical connection with the seventh front surface electrode 307B (see FIG. 15), and includes a portion overlapping with the seventh front surface electrode 307B in a plan view. The fifth back surface electrodes 325A and 325B are formed, for example, in a circular shape, and are respectively disposed within circular openings formed in the sixth back surface electrode 326A.

[0222] The sixth back surface electrode 326A is provided for electrical connection with the third front surface electrode 303 (see FIG. 15). The sixth back surface electrode 326A has a substantially rectangular shape and is provided adjacent to both of the second back surface electrodes 322A and 322B. The seventh back surface electrode 327A is provided for electrical connection with the eighth front surface electrode 308A (see FIG. 15). The eighth back surface electrode 328A is provided for electrical connection with the ninth front surface electrode 309A (see FIG. 15). The ninth back surface electrode 329A is provided for electrical connection with the tenth front surface electrode 310A (see FIG. 15). The seventh to ninth back surface electrodes 327A, 328A, and 329A are arranged in a row in the X-axis direction.

[0223] The second arrangement region AP2 (the lower right region in FIG. 19) is used for the arrangement of a part of each of the first back surface electrodes 321C and 321D, the second back surface electrodes 322C and 322D, the third back surface electrodes 323A and 323B, the fourth back surface electrodes 324C and 324D, the fifth back surface electrodes 325C and 325D, the sixth back surface electrode 326B, the seventh back surface electrode 327B, the eighth back surface electrode 328B, and the ninth back surface electrode 329B.

[0224] The first back electrode 321C is provided for electrical connection with the first and fourth surface electrodes 301C and 304C (both see FIG. 16), and includes a portion overlapping with the first and fourth surface electrodes 301C and 304C in plan view. The first back electrode 321C is formed in an elongated shape extending in the Y-axis direction. The first back electrode 321D is provided for electrical connection with the first and fourth surface electrodes 301D and 304D (both see FIG. 16), and includes a portion overlapping with the first and fourth surface electrodes 301D and 304D in plan view. The first back electrode 321D is formed in an elongated shape extending in the X-axis direction.

[0225] The second back electrode 322C is provided for electrical connection with the second surface electrode 302C (see FIG. 16), and includes a portion overlapping with the second surface electrode 302C in plan view. The second back electrode 322C is provided at a position adjacent or close to the first back electrode 321C in the X-axis direction. The second back electrode 322D is provided for electrical connection with the second surface electrode 302D (see FIG. 16), and includes a portion overlapping with the second surface electrode 302D in plan view. The second back electrode 322D is provided at a position adjacent or close to the first back electrode 321D in the Y-axis direction.

[0226] As described above, the third back electrode 323A includes a second portion 323A2 located within the second arrangement region AP2. The third back electrode 323B includes a second portion 323B2 located within the second arrangement region AP2. This second portion 323B2 is similar to the shape obtained by rotating the first portion 323A1 of the third back electrode 323A counterclockwise by 90°.

[0227] The fourth back electrode 324C is provided for electrical connection with the sixth surface electrode 306C (see FIG. 16), and includes a portion overlapping with the sixth surface electrode 306C in plan view. The fourth back electrode 324D is provided for electrical connection with the sixth surface electrode 306D (see FIG. 16), and includes a portion overlapping with the sixth surface electrode 306D in plan view. The fourth back electrodes 324C and 324D are formed, for example, in a circular shape, and are respectively disposed within circular openings formed in the sixth back electrode 326B.

[0228] The fifth back surface electrode 325C is provided for electrical connection with the seventh front surface electrode 307C (see FIG. 16), and includes a portion overlapping the seventh front surface electrode 307C in plan view. The fifth back surface electrode 325D is provided for electrical connection with the seventh front surface electrode 307D (see FIG. 16), and includes a portion overlapping the seventh front surface electrode 307D in plan view. The fifth back surface electrodes 325C and 325D are formed, for example, in a circular shape, and are respectively disposed within circular openings formed in the sixth back surface electrode 326B.

[0229] The sixth back surface electrode 326B is provided for electrical connection with the third front surface electrode 303 (see FIG. 16). The sixth back surface electrode 326B has a substantially rectangular shape and is provided adjacent to both of the second back surface electrodes 322C and 322D. The seventh back surface electrode 327B is provided for electrical connection with the eighth front surface electrode 308B (see FIG. 16). The eighth back surface electrode 328B is provided for electrical connection with the ninth front surface electrode 309B (see FIG. 16). The ninth back surface electrode 329B is provided for electrical connection with the tenth front surface electrode 310B (see FIG. 16). The seventh to ninth back surface electrodes 327B, 328B, and 329B are arranged in a row in the X-axis direction.

[0230] The third arrangement region AP3 (the upper left region in FIG. 19) is used for the arrangement of a part of each of the first back surface electrodes 321E and 321F, the second back surface electrodes 322E and 322F, the third back surface electrodes 323B and 323C, the fourth back surface electrodes 324E and 324F, the fifth back surface electrodes 325E and 325F, the sixth back surface electrode 326C, the seventh back surface electrode 327C, the eighth back surface electrode 328C, and the ninth back surface electrode 329C.

[0231] The first back electrode 321E is provided for electrical connection with the first and fourth surface electrodes 301E and 304E (both shown in FIG. 17), and includes a portion overlapping with the first and fourth surface electrodes 301E and 304E in a plan view. The first back electrode 321E is formed in an elongated shape extending in the Y-axis direction. The first back electrode 321F is provided for electrical connection with the first and fourth surface electrodes 301F and 304F (both shown in FIG. 17), and includes a portion overlapping with the first and fourth surface electrodes 301F and 304F in a plan view. The first back electrode 321F is formed in an elongated shape extending in the X-axis direction.

[0232] The second back electrode 322E is provided for electrical connection with the second surface electrode 302E (shown in FIG. 17), and includes a portion overlapping with the second surface electrode 302E in a plan view. The second back electrode 322E is provided at a position adjacent or close to the first back electrode 321E in the X-axis direction. The second back electrode 322F is provided for electrical connection with the second surface electrode 302F (shown in FIG. 17), and includes a portion overlapping with the second surface electrode 302F in a plan view. The second back electrode 322F is provided at a position adjacent or close to the first back electrode 321F in the Y-axis direction.

[0233] The third back electrode 323C is provided for electrical connection with the third surface electrode 203 (shown in FIG. 17). The third back electrode 323C is formed in a substantially U shape in a plan view. It includes a first portion 323C1 corresponding to half of the third back electrode 323C and a second portion 323C2 corresponding to the remaining half of the third back electrode 323C. The first portion 323C1 is disposed in the third arrangement region AP3, and the second portion 323C2 is disposed in the fourth arrangement region AP4 adjacent to the third arrangement region AP3. The first portion 323C1 and the second portion 323C2 have a shape that is line-symmetric with respect to the virtual center line VC.

[0234] The third back electrode 323B includes a third portion 323B3 located within the third arrangement region AP3. This third portion 323B3 is similar to the shape obtained by rotating the second portion 323C2 of the third back electrode 323C counterclockwise by 90°.

[0235] The fourth back surface electrode 324E is provided for electrical connection with the sixth front surface electrode 306E (see FIG. 17), and includes a portion overlapping with the sixth front surface electrode 306E in plan view. The fourth back surface electrode 324F is provided for electrical connection with the sixth front surface electrode 306F (see FIG. 17), and includes a portion overlapping with the sixth front surface electrode 306F in plan view. The fourth back surface electrodes 324E and 324F are formed, for example, in a circular shape, and are respectively disposed within circular openings formed in the sixth back surface electrode 326C.

[0236] The fifth back surface electrode 325E is provided for electrical connection with the seventh front surface electrode 307E (see FIG. 17), and includes a portion overlapping with the seventh front surface electrode 307E in plan view. The fifth back surface electrode 325F is provided for electrical connection with the seventh front surface electrode 307F (see FIG. 17), and includes a portion overlapping with the seventh front surface electrode 307F in plan view. The fifth back surface electrodes 325E and 325F are formed, for example, in a circular shape, and are respectively disposed within circular openings formed in the sixth back surface electrode 326C.

[0237] The sixth back surface electrode 326C is provided for electrical connection with the third front surface electrode 303 (see FIG. 17). The sixth back surface electrode 326C has a substantially rectangular shape and is provided adjacent to both of the second back surface electrodes 322E and 322F. The seventh back surface electrode 327C is provided for electrical connection with the eighth front surface electrode 308C (see FIG. 17). The eighth back surface electrode 328C is provided for electrical connection with the ninth front surface electrode 309C (see FIG. 17). The ninth back surface electrode 329C is provided for electrical connection with the tenth front surface electrode 310C (see FIG. 17). The seventh to ninth back surface electrodes 327C, 328C, and 329C are arranged in a row in the X-axis direction.

[0238] The fourth arrangement region AP4 (the upper right region in FIG. 19) is used for the arrangement of a part of each of the first back surface electrodes 321G and 321H, the second back surface electrodes 322G and 322H, the third back surface electrodes 323B and 323C, the fourth back surface electrodes 324G and 324H, the fifth back surface electrodes 325G and 325H, the sixth back surface electrode 326D, the seventh back surface electrode 327D, the eighth back surface electrode 328D, and the ninth back surface electrode 329D.

[0239] The first back electrode 321G is provided for electrical connection with the first and fourth surface electrodes 301G and 304G (both see FIG. 18), and includes a portion overlapping the first and fourth surface electrodes 301G and 304G in a plan view. The first back electrode 321G is formed in an elongated shape extending in the Y-axis direction. The first back electrode 321H is provided for electrical connection with the first and fourth surface electrodes 301H and 304H (both see FIG. 18), and includes a portion overlapping the first and fourth surface electrodes 301H and 304H in a plan view. The first back electrode 321H is formed in an elongated shape extending in the X-axis direction.

[0240] The second back electrode 322G is provided for electrical connection with the second surface electrode 302G (see FIG. 18), and includes a portion overlapping the second surface electrode 302G in a plan view. The second back electrode 322G is provided at a position adjacent or close to the first back electrode 321G in the X-axis direction. The second back electrode 322H is provided for electrical connection with the second surface electrode 302H (see FIG. 18), and includes a portion overlapping the second surface electrode 302H in a plan view. The second back electrode 322H is provided at a position adjacent or close to the first back electrode 321H in the Y-axis direction.

[0241] As described above, the third back electrode 323C includes the second portion 323C2 located in the fourth arrangement region AP4. The third back electrode 323B includes the fourth portion 323B4 located in the fourth arrangement region AP4. This fourth portion 323B4 is similar to the shape obtained by rotating the first portion 323C1 of the third back electrode 323C clockwise by 90°.

[0242] The fourth back electrode 324G is provided for electrical connection with the sixth surface electrode 306G (see FIG. 18), and includes a portion overlapping the sixth surface electrode 306G in a plan view. The fourth back electrode 324H is provided for electrical connection with the sixth surface electrode 306H (see FIG. 18), and includes a portion overlapping the sixth surface electrode 306H in a plan view. The fourth back electrodes 324G and 324H are formed in, for example, a circular shape, and are respectively disposed in the circular openings formed in the sixth back electrode 326D.

[0243] The fifth back surface electrode 325G is provided for electrical connection with the seventh front surface electrode 307G (see FIG. 18) and includes a portion overlapping the seventh front surface electrode 307G in plan view. The fifth back surface electrode 325H is provided for electrical connection with the seventh front surface electrode 307H (see FIG. 18) and includes a portion overlapping the seventh front surface electrode 307H in plan view. The fifth back surface electrodes 325G and 325H are formed, for example, in a circular shape and are respectively disposed within circular openings formed in the sixth back surface electrode 326D.

[0244] The sixth back surface electrode 326D is provided for electrical connection with the third front surface electrode 303 (see FIG. 18). The sixth back surface electrode 326D has a substantially rectangular shape and is provided adjacent to both of the second back surface electrodes 322G and 322H. The seventh back surface electrode 327D is provided for electrical connection with the eighth front surface electrode 308D (see FIG. 18). The eighth back surface electrode 328D is provided for electrical connection with the ninth front surface electrode 309D (see FIG. 18). The ninth back surface electrode 329D is provided for electrical connection with the tenth front surface electrode 310D (see FIG. 18). The seventh to ninth back surface electrodes 327D, 328D, and 329D are arranged in a row in the X-axis direction.

[0245] [2-2C. Third Electrode Layer (Front-Side Intermediate Electrode Layer)] As shown in FIG. 20, the third electrode layer 28C (front-side intermediate electrode layer) includes a plurality of intermediate electrodes (pattern electrodes) spaced apart from each other. In the second embodiment, the third electrode layer 28C includes first intermediate electrodes 331A to 331H, second intermediate electrodes 332A to 332H, third intermediate electrode 333, fourth intermediate electrodes 334A to 334H, fifth intermediate electrodes 335A to 335D, sixth intermediate electrodes 336A to 336D, and seventh intermediate electrodes 337A to 337D.

[0246] In the example of FIG. 20, the third intermediate electrode 333 has a substantially rectangular shape in plan view and is arranged over the first to fourth arrangement regions AP1 to AP4. The third intermediate electrode 333 includes two T-shaped openings. In one of the T-shaped openings, the first intermediate electrodes 331A to 331D and the second intermediate electrodes 332A to 332D are arranged. In the other T-shaped opening, the first intermediate electrodes 331E to 331H and the second intermediate electrodes 332E to 332H are arranged. Further, the third intermediate electrode 333 includes eight circular openings, and the fourth intermediate electrodes 334A to 334H are arranged in these eight circular openings. Further, the third intermediate electrode 333 has four notches for arranging the fifth intermediate electrodes 335A to 335D, the sixth intermediate electrodes 336A to 336D, and the seventh intermediate electrodes 337A to 337D at positions corresponding to the four corners of the substrate 20 in plan view, respectively.

[0247] The first arrangement region AP1 (the lower right region in FIG. 20) is used for arranging the first intermediate electrodes 331A and 331B, the second intermediate electrodes 332A and 332B, a part of the third intermediate electrode 333 (the lower right region in FIG. 20), the fourth intermediate electrodes 334A and 334B, the fifth intermediate electrode 335A, the sixth intermediate electrode 336A, and the seventh intermediate electrode 337A.

[0248] The shapes, sizes, and arrangements of the first intermediate electrodes 331A and 331B are the same as those of the first back electrodes 321A and 321B (see FIG. 19). The first intermediate electrode 331A is provided for electrical connection between the first and fourth surface electrodes 301A and 304A (both see FIG. 15) and the first back electrode 321A. The first intermediate electrode 331B is provided for electrical connection between the first and fourth surface electrodes 301B and 304B (both see FIG. 15) and the first back electrode 321B.

[0249] The second intermediate electrode 332A is provided for electrical connection with the second front electrode 302A and the second back electrode 322A. The second intermediate electrode 332A is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331A in the X-axis direction. The second intermediate electrode 332B is provided for electrical connection with the second front electrode 302B and the second back electrode 322B. The second intermediate electrode 332B is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331B in the Y-axis direction.

[0250] The third intermediate electrode 333 is provided for electrical connection with the third front electrode 303 (see FIG. 15), the third back electrodes 323A to 323C (see FIG. 19), and the sixth back electrodes 326A to 326D (see FIG. 19).

[0251] The fourth intermediate electrodes 334A are provided for electrical connection with the seventh front electrode 307A (see FIG. 15) and the fifth back electrode 325A (see FIG. 19). The fourth intermediate electrodes 334B are provided for electrical connection with the seventh front electrode 307B (see FIG. 15) and the fifth back electrode 325B (see FIG. 19). The fourth intermediate electrodes 334A and 334B are circular in shape and are arranged in two circular openings within the first arrangement region AP1.

[0252] The fifth intermediate electrode 335A is provided for electrical connection with the eighth front electrode 308A (see FIG. 15) and the seventh back electrode 327A (see FIG. 19). The sixth intermediate electrode 336A is provided for electrical connection with the ninth front electrode 309A (see FIG. 15) and the eighth back electrode 328A (see FIG. 19). The fifth and sixth intermediate electrodes 335A and 336A are rectangular in shape and are arranged side by side in the X-axis direction.

[0253] The seventh intermediate electrode 337A is provided for electrical connection with the sixth surface electrodes 306A and 306B, the tenth surface electrode 310A (see FIG. 15 respectively), the fourth back electrodes 324A and 324B, and the ninth back electrode 329A (see FIG. 19 respectively). The seventh intermediate electrode 337A includes a rectangular base portion 337A1 provided adjacent to the sixth intermediate electrode 336A, and first and second branch wirings 337A2 and 337A3 integrally formed with the base portion 337A1. The base portion 337A1 is provided at a position overlapping the tenth surface electrode 310A and the ninth back electrode 329A in a plan view. The first branch wiring 337A2 is provided at a position overlapping the sixth surface electrode 306A and the fourth back electrode 324A in a plan view. The second branch wiring 337A3 is provided at a position overlapping the sixth surface electrode 306B and the fourth back electrode 324B in a plan view.

[0254] The second arrangement region AP2 (the lower left region in FIG. 20) is used for arranging the first intermediate electrodes 331C and 331D, the second intermediate electrodes 332C and 332D, a part of the third intermediate electrode 333 (the lower left region in FIG. 20), the fourth intermediate electrodes 334C and 334D, the fifth intermediate electrode 335B, the sixth intermediate electrode 336B, and the seventh intermediate electrode 337B.

[0255] The shapes, sizes, and arrangements of the first intermediate electrodes 331C and 331D are the same as those of the first back electrodes 321C and 321D (see FIG. 19). The first intermediate electrode 331C is provided for electrical connection between the first and fourth surface electrodes 301C and 304C (both see FIG. 16) and the first back electrode 321C. The first intermediate electrode 331D is provided for electrical connection between the first and fourth surface electrodes 301D and 304D (both see FIG. 16) and the first back electrode 321D.

[0256] The second intermediate electrode 332C is provided for electrical connection with the second front surface electrode 302C and the second back surface electrode 322C. The second intermediate electrode 332C is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331C in the X-axis direction. The second intermediate electrode 332D is provided for electrical connection with the second front surface electrode 302D and the second back surface electrode 322D. The second intermediate electrode 332D is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331D in the Y-axis direction.

[0257] The fourth intermediate electrode 334C is provided for electrical connection with the seventh front surface electrode 307C (see FIG. 16) and the fifth back surface electrode 325C (see FIG. 19). The fourth intermediate electrode 334D is provided for electrical connection with the seventh front surface electrode 307D (see FIG. 16) and the fifth back surface electrode 325D (see FIG. 19). The fourth intermediate electrodes 334C and 334D are circular in shape and are arranged in two circular openings within the second arrangement region AP2.

[0258] The fifth intermediate electrode 335B is provided for electrical connection with the eighth front surface electrode 308B (see FIG. 16) and the seventh back surface electrode 327B (see FIG. 19). The sixth intermediate electrode 336B is provided for electrical connection with the ninth front surface electrode 309B (see FIG. 16) and the eighth back surface electrode 328B (see FIG. 19). The fifth and sixth intermediate electrodes 335B and 336B are rectangular in shape and are arranged side by side in the X-axis direction.

[0259] The seventh intermediate electrode 337B is provided for electrical connection with the sixth surface electrodes 306C and 306D, the tenth surface electrode 310B (see FIG. 16 respectively), the fourth back electrodes 324C and 324D, and the ninth back electrode 329B (see FIG. 19 respectively). The seventh intermediate electrode 337B includes a rectangular base 337B1 provided adjacent to the sixth intermediate electrode 336B, and first and second branch wirings 337B2 and 337B3 integrally formed with the base 337B1. The base 337B1 is provided at a position overlapping the tenth surface electrode 310B and the ninth back electrode 329B in a plan view. The first branch wiring 337B2 is provided at a position overlapping the sixth surface electrode 306C and the fourth back electrode 324C in a plan view. The second branch wiring 337B3 is provided at a position overlapping the sixth surface electrode 306D and the fourth back electrode 324D in a plan view.

[0260] The third arrangement region AP3 (the upper right region in FIG. 20) is used for arranging the first intermediate electrodes 331E and 331F, the second intermediate electrodes 332E and 332F, a part of the third intermediate electrode 333 (the upper right region in FIG. 20), the fourth intermediate electrodes 334E and 334F, the fifth intermediate electrode 335C, the sixth intermediate electrode 336C, and the seventh intermediate electrode 337C.

[0261] The shapes, sizes, and arrangements of the first intermediate electrodes 331E and 331F are the same as those of the first back electrodes 321E and 321F (see FIG. 19). The first intermediate electrode 331E is provided for electrical connection between the first and fourth surface electrodes 301E and 304E (both see FIG. 17) and the first back electrode 321E. The first intermediate electrode 331F is provided for electrical connection between the first and fourth surface electrodes 301F and 304F (both see FIG. 17) and the first back electrode 321F.

[0262] The second intermediate electrode 332E is provided for electrical connection with the second front surface electrode 302E and the second back surface electrode 322E. The second intermediate electrode 332E is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331E in the X-axis direction. The second intermediate electrode 332F is provided for electrical connection with the second front surface electrode 302F and the second back surface electrode 322F. The second intermediate electrode 332F is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 331F in the Y-axis direction.

[0263] The fourth intermediate electrode 334E is provided for electrical connection with the seventh front surface electrode 307E (see FIG. 17) and the fifth back surface electrode 325E (see FIG. 19). The fourth intermediate electrode 334F is provided for electrical connection with the seventh front surface electrode 307F (see FIG. 17) and the fifth back surface electrode 325F (see FIG. 19). The fourth intermediate electrodes 334E and 334F are circular in shape and are arranged in two circular openings within the third arrangement region AP3.

[0264] The fifth intermediate electrode 335C is provided for electrical connection with the eighth front surface electrode 308C (see FIG. 17) and the seventh back surface electrode 327C (see FIG. 19). The sixth intermediate electrode 336C is provided for electrical connection with the ninth front surface electrode 309C (see FIG. 17) and the eighth back surface electrode 328C (see FIG. 19). The fifth and sixth intermediate electrodes 335C and 336C are rectangular in shape and are arranged side by side in the X-axis direction.

[0265] The seventh intermediate electrode 337C is provided for electrical connection with the sixth surface electrodes 306E and 306F, the tenth surface electrode 310C (see FIG. 17 respectively), the fourth back electrodes 324E and 324F, and the ninth back electrode 329C (see FIG. 19 respectively). The seventh intermediate electrode 337C includes a rectangular base 337C1 provided adjacent to the sixth intermediate electrode 336C, and first and second branch wirings 337C2 and 337C3 integrally formed with the base 337C1. The base 337C1 is provided at a position overlapping the tenth surface electrode 310C and the ninth back electrode 329C in a plan view. The first branch wiring 337C2 is provided at a position overlapping the sixth surface electrode 306E and the fourth back electrode 324E in a plan view. The second branch wiring 337C3 is provided at a position overlapping the sixth surface electrode 306F and the fourth back electrode 324F in a plan view.

[0266] The fourth arrangement region AP4 (the upper left region in FIG. 20) is used for arranging the first intermediate electrodes 331G and 331H, the second intermediate electrodes 332G and 332H, a part of the third intermediate electrode 333 (the upper left region in FIG. 20), the fourth intermediate electrodes 334G and 334H, the fifth intermediate electrode 335D, the sixth intermediate electrode 336D, and the seventh intermediate electrode 337D.

[0267] The shapes, sizes, and arrangements of the first intermediate electrodes 331G and 331H are the same as those of the first back electrodes 321G and 321H (see FIG. 19). The first intermediate electrode 331G is provided for electrical connection between the first and fourth surface electrodes 301G and 304G (both see FIG. 18) and the first back electrode 321G. The first intermediate electrode 331H is provided for electrical connection between the first and fourth surface electrodes 301H and 304H (both see FIG. 18) and the first back electrode 321H.

[0268] The second intermediate electrode 332G is provided for electrical connection with the second front surface electrode 302G and the second back surface electrode 322G. The second intermediate electrode 332G is oval-shaped and is provided at a position adjacent to or close to the first intermediate electrode 331G in the X-axis direction. The second intermediate electrode 332H is provided for electrical connection with the second front surface electrode 302H and the second back surface electrode 322H. The second intermediate electrode 332H is oval-shaped and is provided at a position adjacent to or close to the first intermediate electrode 331H in the Y-axis direction.

[0269] The fourth intermediate electrode 334G is provided for electrical connection with the seventh front surface electrode 307G (see FIG. 18) and the fifth back surface electrode 325G (see FIG. 19). The fourth intermediate electrode 334H is provided for electrical connection with the seventh front surface electrode 307H (see FIG. 18) and the fifth back surface electrode 325H (see FIG. 19). The fourth intermediate electrodes 334G and 334H are circular and are arranged in two circular openings within the fourth arrangement region AP4.

[0270] The fifth intermediate electrode 335D is provided for electrical connection with the eighth front surface electrode 308D (see FIG. 18) and the seventh back surface electrode 327D (see FIG. 19). The sixth intermediate electrode 336D is provided for electrical connection with the ninth front surface electrode 309D (see FIG. 18) and the eighth back surface electrode 328D (see FIG. 19). The fifth and sixth intermediate electrodes 335D and 336D are rectangular and are arranged side by side in the X-axis direction.

[0271] The seventh intermediate electrode 337D is provided for electrical connection with the sixth surface electrode 306G, the sixth surface electrode 306H, the tenth surface electrode 310D (see FIG. 18 respectively), the fourth back surface electrode 324G, the fourth back surface electrode 324H, and the ninth back surface electrode 329D (see FIG. 19 respectively). The seventh intermediate electrode 337D includes a rectangular base portion 337D1 provided adjacent to the sixth intermediate electrode 336D, and first and second branch wirings 337D2 and 337D3 integrally formed with the base portion 337D1. The base portion 337D1 is provided at a position overlapping the tenth surface electrode 310D and the ninth back surface electrode 329D in a plan view. The first branch wiring 337D2 is provided at a position overlapping the sixth surface electrode 306G and the fourth back surface electrode 324G in a plan view. The second branch wiring 337D3 is provided at a position overlapping the sixth surface electrode 306H and the fourth back surface electrode 324H in a plan view.

[0272] [2-2D. Fourth Electrode Layer (Back Surface Side Intermediate Electrode Layer)] As shown in FIG. 21, the fourth electrode layer 28D (back surface side intermediate electrode layer) includes a plurality of intermediate electrodes (pattern electrodes) spaced apart from each other. In the second embodiment, the fourth electrode layer 28D includes first intermediate electrodes 341A to 341H, second intermediate electrodes 342A to 342H, a third intermediate electrode 343, fourth intermediate electrodes 344A to 344H, fifth intermediate electrodes 345A to 345D, sixth intermediate electrodes 346A to 346D, and seventh intermediate electrodes 347A to 347D.

[0273] In the example of FIG. 21, the third intermediate electrode 343 has a substantially rectangular shape in plan view and is arranged over the first to fourth arrangement regions AP1 to AP4. The third intermediate electrode 343 includes two T-shaped openings. In one of the T-shaped openings, the first intermediate electrodes 341A to 341D and the second intermediate electrodes 342A to 342D are arranged. In the other T-shaped opening, the first intermediate electrodes 341E to 341H and the second intermediate electrodes 342E to 342H are arranged. Further, the third intermediate electrode 343 includes eight circular openings, and the fourth intermediate electrodes 344A to 344H are arranged in these eight circular openings. Further, the third intermediate electrode 333 has four notches for arranging the fifth intermediate electrodes 345A to 345D, the sixth intermediate electrodes 346A to 346D, and the seventh intermediate electrodes 347A to 347D at positions corresponding to the four corners of the substrate 20 in plan view, respectively.

[0274] The first arrangement region AP1 (the lower right region in FIG. 21) is used for arranging the first intermediate electrodes 341A, 341B, the second intermediate electrodes 342A, 342B, a part of the third intermediate electrode 343 (the lower right region in FIG. 20), the fourth intermediate electrodes 344A, 344B, the fifth intermediate electrode 345A, the sixth intermediate electrode 346A, and the seventh intermediate electrode 347A.

[0275] The shapes, sizes, and arrangements of the first intermediate electrodes 341A, 341B are the same as those of the first intermediate electrodes 331A, 331B (see FIG. 20). The first intermediate electrode 341A is provided for electrical connection between the first and fourth surface electrodes 301A, 304A (both see FIG. 15), the first back surface electrode 321A (see FIG. 19), and the first intermediate electrode 331A (see FIG. 20). The first intermediate electrode 341B is provided for electrical connection between the first and fourth surface electrodes 301B, 304B (both see FIG. 15), the first back surface electrode 321B (see FIG. 19), and the first intermediate electrode 331B (see FIG. 20).

[0276] The shapes, sizes, and arrangements of the second intermediate electrodes 342A and 342B are the same as those of the first intermediate electrodes 331A and 331B (see FIG. 20). The second intermediate electrode 342A is provided for electrical connection between the second surface electrode 302A (see FIG. 15), the second back surface electrode 322A (see FIG. 19), and the first intermediate electrode 331A (see FIG. 20). The second intermediate electrode 342A has an oval shape and is provided at a position adjacent to or close to the first intermediate electrode 341A in the X-axis direction. The second intermediate electrode 342B is provided for electrical connection between the second surface electrode 302B (see FIG. 15), the second back surface electrode 322B (see FIG. 19), and the first intermediate electrode 331B (see FIG. 20). The second intermediate electrode 342B has an oval shape and is provided at a position adjacent to or close to the first intermediate electrode 341B in the Y-axis direction.

[0277] The third intermediate electrode 343 is provided for electrical connection between the third surface electrode 303 (see FIG. 15), the third back surface electrodes 323A to 323C (see FIG. 19), the sixth back surface electrodes 326A to 326D (see FIG. 19), and the third intermediate electrode 333 (see FIG. 20).

[0278] The fourth intermediate electrode 344A is provided for electrical connection between the sixth surface electrode 306A (see FIG. 15), the fourth back surface electrode 324A (see FIG. 19), and the seventh intermediate electrode 337A (see FIG. 20). The fourth intermediate electrode 344B is provided for electrical connection between the sixth surface electrode 306B (see FIG. 15), the fourth back surface electrode 324B (see FIG. 19), and the seventh intermediate electrode 337B (see FIG. 20). The fourth intermediate electrodes 344A and 344B are circular in shape and are arranged within two circular openings in the first arrangement region AP1.

[0279] The fifth intermediate electrode 345A is provided for electrical connection between the seventh surface electrode 307A (see FIG. 15), the eighth surface electrode 308A (see FIG. 15), the fifth back surface electrode 325A (see FIG. 19), the seventh back surface electrode 327A (see FIG. 19), the fourth intermediate electrode 334A (see FIG. 20), and the fifth intermediate electrode 335A (see FIG. 20).

[0280] The sixth intermediate electrode 346A is provided for electrical connection between the seventh surface electrode 307B (see FIG. 15), the ninth surface electrode 309A (see FIG. 15), the fifth back surface electrode 325B (see FIG. 19), the eighth back surface electrode 328A (see FIG. 19), the fourth intermediate electrode 334B (see FIG. 20), and the sixth intermediate electrode 336A (see FIG. 20). The seventh intermediate electrode 347A is provided for electrical connection between the tenth surface electrode 310A (see FIG. 15), the ninth back surface electrode 329A (see FIG. 19), and the seventh intermediate electrode 337A (see FIG. 20).

[0281] The second arrangement region AP2 (the lower left region in FIG. 21) is used for arranging the first intermediate electrodes 341C and 341D, the second intermediate electrodes 342C and 342D, a part of the third intermediate electrode 343 (the lower left region in FIG. 20), the fourth intermediate electrodes 344C and 344D, the fifth intermediate electrode 345B, the sixth intermediate electrode 346B, and the seventh intermediate electrode 347B.

[0282] The shapes, sizes, and arrangements of the first intermediate electrodes 341C and 341D are the same as those of the first intermediate electrodes 331C and 331D (see FIG. 20). The first intermediate electrode 341C is provided for electrical connection between the first and fourth surface electrodes 301C and 304C (both see FIG. 16), the first back surface electrode 321C (see FIG. 19), and the first intermediate electrode 331C (see FIG. 20). The first intermediate electrode 341D is provided for electrical connection between the first and fourth surface electrodes 301D and 304D (both see FIG. 16), the first back surface electrode 321D (see FIG. 19), and the first intermediate electrode 331D (see FIG. 20).

[0283] The shapes, sizes, and arrangements of the second intermediate electrodes 342C and 342D are the same as those of the first intermediate electrodes 331C and 331D (see FIG. 20). The second intermediate electrode 342C is provided for electrical connection between the second surface electrode 302C (see FIG. 16), the second back surface electrode 322C (see FIG. 19), and the first intermediate electrode 331C (see FIG. 20). The second intermediate electrode 342C is oval-shaped and is provided at a position adjacent to or close to the first intermediate electrode 341C in the X-axis direction. The second intermediate electrode 342D is provided for electrical connection between the second surface electrode 302D (see FIG. 16), the second back surface electrode 322D (see FIG. 19), and the first intermediate electrode 331D (see FIG. 20). The second intermediate electrode 342D is oval-shaped and is provided at a position adjacent to or close to the first intermediate electrode 341D in the Y-axis direction.

[0284] The fourth intermediate electrode 344C is provided for electrical connection between the sixth surface electrode 306C (see FIG. 16), the fourth back surface electrode 324C (see FIG. 19), and the seventh intermediate electrode 337B (see FIG. 20). The fourth intermediate electrode 344D is provided for electrical connection between the sixth surface electrode 306D (see FIG. 16), the fourth back surface electrode 324D (see FIG. 19), and the seventh intermediate electrode 337B (see FIG. 20). The fourth intermediate electrodes 344C and 344D are circular-shaped and are arranged in two circular openings within the second arrangement region AP2.

[0285] The fifth intermediate electrode 345B is provided for electrical connection between the seventh surface electrode 307C (see FIG. 16), the eighth surface electrode 308B (see FIG. 16), the fifth back surface electrode 325C (see FIG. 19), the seventh back surface electrode 327B (see FIG. 19), the fourth intermediate electrode 334C (see FIG. 20), and the fifth intermediate electrode 335B (see FIG. 20).

[0286] The sixth intermediate electrode 346B is provided for electrical connection with the seventh surface electrode 307D (see FIG. 16), the ninth surface electrode 309B (see FIG. 16), the fifth back surface electrode 325D (see FIG. 19), the eighth back surface electrode 328B (see FIG. 19), the fourth intermediate electrode 334D (see FIG. 20), and the sixth intermediate electrode 336B (see FIG. 20). The seventh intermediate electrode 347B is provided for electrical connection with the tenth surface electrode 310B (see FIG. 16), the ninth back surface electrode 329B (see FIG. 19), and the seventh intermediate electrode 337B (see FIG. 20).

[0287] The third arrangement region AP3 (the upper right region in FIG. 21) is used for arranging the first intermediate electrodes 341E and 341F, the second intermediate electrodes 342E and 342F, a part of the third intermediate electrode 343 (the lower left region in FIG. 21), the fourth intermediate electrodes 344E and 344F, the fifth intermediate electrode 345C, the sixth intermediate electrode 346C, and the seventh intermediate electrode 347C.

[0288] The shapes, sizes, and arrangements of the first intermediate electrodes 341E and 341F are the same as those of the first intermediate electrodes 331E and 331F (see FIG. 20). The first intermediate electrode 341E is provided for electrical connection with the first and fourth surface electrodes 301E and 304E (both see FIG. 17), the first back surface electrode 321E (see FIG. 19), and the first intermediate electrode 331E (see FIG. 20). The first intermediate electrode 341F is provided for electrical connection with the first and fourth surface electrodes 301F and 304F (both see FIG. 17), the first back surface electrode 321F (see FIG. 19), and the first intermediate electrode 331F (see FIG. 20).

[0289] The shapes, sizes, and arrangements of the second intermediate electrodes 342E and 342F are the same as those of the first intermediate electrodes 331E and 331F (see FIG. 20). The second intermediate electrode 342E is provided for electrical connection between the second surface electrode 302E (see FIG. 17), the second back surface electrode 322E (see FIG. 19), and the first intermediate electrode 331E (see FIG. 20). The second intermediate electrode 342E is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 341E in the X-axis direction. The second intermediate electrode 342F is provided for electrical connection between the second surface electrode 302F (see FIG. 17), the second back surface electrode 322F (see FIG. 19), and the first intermediate electrode 331F (see FIG. 20). The second intermediate electrode 342F is oval in shape and is provided at a position adjacent to or close to the first intermediate electrode 341F in the Y-axis direction.

[0290] The fourth intermediate electrode 344E is provided for electrical connection between the sixth surface electrode 306E (see FIG. 17), the fourth back surface electrode 324E (see FIG. 19), and the seventh intermediate electrode 337C (see FIG. 20). The fourth intermediate electrode 344F is provided for electrical connection between the sixth surface electrode 306F (see FIG. 17), the fourth back surface electrode 324F (see FIG. 19), and the seventh intermediate electrode 337C (see FIG. 20). The fourth intermediate electrodes 344E and 344F are circular in shape and are arranged in two circular openings within the third arrangement region AP3.

[0291] The fifth intermediate electrode 345C is provided for electrical connection between the seventh surface electrode 307E (see FIG. 17), the eighth surface electrode 308E (see FIG. 17), the fifth back surface electrode 325E (see FIG. 19), the seventh back surface electrode 327C (see FIG. 19), the fourth intermediate electrode 334E (see FIG. 20), and the fifth intermediate electrode 335C (see FIG. 20).

[0292] The sixth intermediate electrode 346C is provided for electrical connection with the seventh surface electrode 307F (see FIG. 17), the ninth surface electrode 309F (see FIG. 17), the fifth back surface electrode 325F (see FIG. 19), the eighth back surface electrode 328C (see FIG. 19), the fourth intermediate electrode 334F (see FIG. 20), and the sixth intermediate electrode 336C (see FIG. 20). The seventh intermediate electrode 347C is provided for electrical connection with the tenth surface electrode 310C (see FIG. 17), the ninth back surface electrode 329C (see FIG. 19), and the seventh intermediate electrode 337C (see FIG. 20).

[0293] The fourth arrangement region AP4 (the upper left region in FIG. 21) is used for arranging the first intermediate electrodes 341G and 341H, the second intermediate electrodes 342G and 342H, a part of the third intermediate electrode 343 (the upper left region in FIG. 21), the fourth intermediate electrodes 344G and 344H, the fifth intermediate electrode 345D, the sixth intermediate electrode 346D, and the seventh intermediate electrode 347D.

[0294] The shapes, sizes, and arrangements of the first intermediate electrodes 341G and 341H are the same as those of the first intermediate electrodes 331G and 331H (see FIG. 20). The first intermediate electrode 341G is provided for electrical connection with the first and fourth surface electrodes 301G and 304G (both see FIG. 18), the first back surface electrode 321G (see FIG. 19), and the first intermediate electrode 331G (see FIG. 20). The first intermediate electrode 341H is provided for electrical connection with the first and fourth surface electrodes 301H and 304H (both see FIG. 18), the first back surface electrode 321H (see FIG. 19), and the first intermediate electrode 331H (see FIG. 20).

[0295] The shapes, sizes, and arrangements of the second intermediate electrodes 342G and 342H are the same as those of the first intermediate electrodes 331G and 331H (see FIG. 20). The second intermediate electrode 342G is provided for electrical connection between the second surface electrode 302G (see FIG. 18), the second back electrode 322G (see FIG. 19), and the first intermediate electrode 331G (see FIG. 20). The second intermediate electrode 342G has an oval shape and is provided at a position adjacent to or close to the first intermediate electrode 341G in the X-axis direction. The second intermediate electrode 342H is provided for electrical connection between the second surface electrode 302H (see FIG. 18), the second back electrode 322H (see FIG. 19), and the first intermediate electrode 331H (see FIG. 20). The second intermediate electrode 342H has an oval shape and is provided at a position adjacent to or close to the first intermediate electrode 341H in the Y-axis direction.

[0296] The fourth intermediate electrode 344G is provided for electrical connection between the sixth surface electrode 306G (see FIG. 18), the fourth back electrode 324G (see FIG. 19), and the seventh intermediate electrode 337D (see FIG. 20). The fourth intermediate electrode 344H is provided for electrical connection between the sixth surface electrode 306H (see FIG. 18), the fourth back electrode 324H (see FIG. 19), and the seventh intermediate electrode 337D (see FIG. 20). The fourth intermediate electrodes 344G and 344H are circular in shape and are arranged in two circular openings within the fourth arrangement region AP4.

[0297] The fifth intermediate electrode 345D is provided for electrical connection between the seventh surface electrode 307G (see FIG. 18), the eighth surface electrode 308G (see FIG. 18), the fifth back electrode 325G (see FIG. 19), the seventh back electrode 327D (see FIG. 19), the fourth intermediate electrode 334G (see FIG. 20), and the fifth intermediate electrode 335D (see FIG. 20).

[0298] The sixth intermediate electrode 346D is provided for electrical connection between the seventh surface electrode 307H (see FIG. 18), the ninth surface electrode 309H (see FIG. 18), the fifth back surface electrode 325H (see FIG. 19), the eighth back surface electrode 328D (see FIG. 19), the fourth intermediate electrode 334H (see FIG. 20), and the sixth intermediate electrode 336D (see FIG. 20). The seventh intermediate electrode 347D is provided for electrical connection between the tenth surface electrode 310D (see FIG. 18), the ninth back surface electrode 329D (see FIG. 19), and the seventh intermediate electrode 337D (see FIG. 20).

[0299] [2-3. Connection Structure between Electrode Layers] The substrate 20 includes a plurality of vias (connection conductors) that electrically connect the first electrode layer 28A (surface electrode layer), the second electrode layer 28B (back surface electrode layer), and the third and fourth electrode layers 28C and 28D (intermediate electrode layers, respectively). For example, as shown in FIGS. 15 to 21, the substrate 20 includes first vias 401A to 401H, second vias 402A to 402H, third vias 403A to 403L, fourth vias 404A to 404H, fifth vias 405A to 405H, sixth vias 406A to 406H, seventh vias 407A to 407D, eighth vias 408A to 408D, and ninth vias 409A to 409D that penetrate the first to third base materials 27A to 27C and the third and fourth electrode layers 28C and 28D in the thickness direction of the substrate 20, respectively. Note that these plurality of vias may penetrate the first and second electrode layers 28A and 28B. These plurality of vias are formed of one or more materials selected from the group including Ti, TiN, Au, Ag, Cu, Al, and W, for example.

[0300] The first via 401A electrically connects the first surface electrode 301A, the first back surface electrode 321A, the first intermediate electrode 331A, and the first intermediate electrode 341A. The number of the first vias 101A is not particularly limited. For example, there may be one or more per semiconductor light-emitting element 30, that is, two or more at positions where the first surface electrode 301A, the first back surface electrode 321A, and the two first intermediate electrodes 331A and 341A overlap.

[0301] The second via 402A electrically connects the second front electrode 302A, the second back electrode 322A, the second intermediate electrode 332A, and the second intermediate electrode 342A. The number of the second vias 402A is not particularly limited, and for example, there may be one or more at positions where the second front electrode 302A, the second back electrode 322A, and the two second intermediate electrodes 332A and 342A overlap.

[0302] The third via 403A electrically connects the third front electrode 303, the third back electrode 323A, the third intermediate electrode 333, and the third intermediate electrode 343. The number of the third vias 403A is not particularly limited, and for example, there may be one or more at positions where the third front electrode 303, the third back electrode 323A, and the two third intermediate electrodes 333 and 343 overlap. In the second embodiment, for example, a large number of the third vias 403A are arranged in a matrix (for example, 2×5).

[0303] The third via 403B electrically connects the third front electrode 303, the third back electrode 323B, the third intermediate electrode 333, and the third intermediate electrode 343. The number of the third vias 403A is not particularly limited, and for example, there may be one or more at positions where the third front electrode 303, the third back electrode 323B, and the two third intermediate electrodes 333 and 343 overlap. In the second embodiment, for example, a large number of the third vias 403B are arranged in a matrix (for example, 2×5).

[0304] The third via 403C electrically connects the third front electrode 303, the sixth back electrode 326A, the third intermediate electrode 333, and the third intermediate electrode 343. The number of the third vias 403C is not particularly limited, and for example, there may be one or more at positions where the third front electrode 303, the sixth back electrode 326A, and the two third intermediate electrodes 333 and 343 overlap.

[0305] The fourth via 404A electrically connects the fourth front electrode 304A, the first back electrode 321A, the first intermediate electrode 331A, and the first intermediate electrode 341A. The number of the fourth vias 404A is not particularly limited, and for example, there may be one or more at positions where the fourth front electrode 304A, the first back electrode 321A, and the two first intermediate electrodes 331A and 341A overlap.

[0306] The fifth via 405A electrically connects the sixth surface electrode 306A, the fourth back surface electrode 324A, the seventh intermediate electrode 337A, and the fourth intermediate electrode 344A. The number of the fifth vias 405A is not particularly limited, and for example, there may be one or more at a position where the sixth surface electrode 306A, the fourth back surface electrode 324A, the seventh intermediate electrode 337A, and the fourth intermediate electrode 344A overlap.

[0307] The sixth via 406A electrically connects the seventh surface electrode 307A, the fifth back surface electrode 325A, the fourth intermediate electrode 334A, and the fifth intermediate electrode 345A. The number of the sixth vias 406A is not particularly limited, and for example, there may be one or more at a position where the seventh surface electrode 307A, the fifth back surface electrode 325A, the fourth intermediate electrode 334A, and the fifth intermediate electrode 345A overlap.

[0308] The seventh via 407A electrically connects the eighth surface electrode 308A, the seventh back surface electrode 327A, the fifth intermediate electrode 335A, and the fifth intermediate electrode 345A. The number of the seventh vias 407A is not particularly limited, and for example, there may be one or more at a position where the eighth surface electrode 308A, the seventh back surface electrode 327A, and the two fifth intermediate electrodes 335A, 345A overlap.

[0309] The eighth via 408A electrically connects the ninth surface electrode 309A, the eighth back surface electrode 328A, the sixth intermediate electrode 336A, and the sixth intermediate electrode 346A. The number of the eighth vias 408A is not particularly limited, and for example, there may be one or more at a position where the ninth surface electrode 309A, the eighth back surface electrode 328A, and the two sixth intermediate electrodes 336A, 346A overlap.

[0310] The ninth via 409A electrically connects the tenth surface electrode 310A, the ninth back surface electrode 329A, the seventh intermediate electrode 337A, and the seventh intermediate electrode 347A. The number of the ninth vias 409A is not particularly limited, and for example, there may be one or more at a position where the tenth surface electrode 310A, the ninth back surface electrode 329A, and the two seventh intermediate electrodes 337A, 347A overlap.

[0311] In the first configuration region AP1, the first, second, fourth, fifth, and sixth vias 401B, 402B, 404B, 405B, 406B are arranged in the same manner as the above-described first, second, fourth, fifth, and sixth vias 401A, 402A, 404A, 405A, 406A. Therefore, detailed descriptions of the first, second, fourth, fifth, and sixth vias 401B, 402B, 404B, 405B, 406B are omitted.

[0312] The second configuration region AP2 includes the first vias 401C, 401D, the second vias 402C, 402D, the third vias 403D to 403F, the fourth vias 404C, 404D, the fifth vias 405C, 405D, the sixth vias 406C, 406D, the seventh via 407B, the eighth via 408B, and the ninth via 409B. The third configuration region AP3 includes the first vias 401E, 401F, the second vias 402E, 402F, the third vias 403G to 403I, the fourth vias 404E, 404F, the fifth vias 405E, 405F, the sixth vias 406E, 406F, the seventh via 407C, the eighth via 408C, and the ninth via 409C. The fourth configuration region AP4 includes the first vias 401G, 401H, the second vias 402G, 402H, the third vias 403J to 403L, the fourth vias 404G, 404H, the fifth vias 405G, 405H, the sixth vias 406G, 406H, the seventh via 407D, the eighth via 408D, and the ninth via 409D. Since the arrangements of these vias in the second to fourth configuration regions AP2, AP3, AP4 are the same as the arrangement of the vias in the above-described first configuration region AP1, detailed descriptions are omitted.

[0313] [2-4. Current Path of Semiconductor Light-Emitting Device] In the second embodiment, the current path of the current flowing through the drive circuit 40A and the semiconductor light-emitting element 30 to be driven by the drive circuit 40A is the first electrode 42A of the capacitor 421, the second surface electrode 302A, the wire W4, the surface electrode 34 (anode electrode) of the semiconductor light-emitting element 30, the back surface electrode 35 (cathode electrode) of the semiconductor light-emitting element 30, the first surface electrode 301A, the first via 401A, the first intermediate electrode 331A, the fourth via 404A, the fourth surface electrode 304A, the drain electrode 41D of the switching element 411, the source electrode 41S of the switching element 411, the third surface electrode 303, and the second electrode 42B of the capacitor 421 in this order, and is configured in a loop shape through which the current flows.

[0314] Although detailed description is omitted here, for each of the other drive circuits 40B to 40H, the same electrical connection as that of the drive circuit 40A is realized, and a loop-shaped current path similar to the above-described current path is individually configured.

[0315] [2-5. Circuit Configuration of Semiconductor Light-Emitting Device] Next, with reference to FIG. 22, a light-emitting system 200 including the semiconductor light-emitting device 10 of the second embodiment will be described. For clarity of illustration, in FIG. 22, the illustration of the drive circuits 40C to 40F, the semiconductor light-emitting elements 30 to be driven by the drive circuits 40C to 40F, the protection diodes 70C to 70F, the backflow prevention diodes 204C to 204F, the gate drivers 205C to 205F, the pulse generators 206C to 206F, the capacitors 208C to 208F, and the control power supplies 207C to 207F is omitted. Also, two semiconductor light-emitting elements 30 to be driven by each drive circuit 40 are collectively shown as one diode element symbol.

[0316] The backflow prevention diodes 204A to 204H, the gate drivers 205A to 205H, the pulse generators 206A to 206H, the capacitors 208A to 208H, and the control power supplies 207A to 207H are provided corresponding to the drive circuits 40A to 40H, respectively. Hereinafter, the description will be centered on the differences from the light-emitting system 200 (FIG. 12) according to the first embodiment.

[0317] The cathodes of the backflow prevention diodes 204A to 204H are electrically connected to the first electrodes 42A of the capacitors 421 to 428, and further to the surface electrodes 34 (anode electrodes) of the corresponding two semiconductor light-emitting elements 30 to be driven by the drive circuits 40C to 40F via the second back electrodes 322A to 322H. The back electrodes 35 (cathode electrodes) of the semiconductor light-emitting elements 30 are electrically connected to the drain electrodes 41D of the corresponding switching elements 411 to 418. The source electrodes 41S of the switching elements 411 to 418 are connected to the ground via the third back electrodes 323A to 323C respectively. The protection diodes 70A to 70H provided outside the semiconductor light-emitting device 10 are connected in anti-parallel to the corresponding semiconductor light-emitting elements 30 respectively.

[0318] The semiconductor light-emitting device 10 of the second embodiment described above can obtain the same advantages as those obtained by the semiconductor light-emitting device 10 of the first embodiment. Further, in the second embodiment, HEMT using, for example, a nitride semiconductor as a lateral transistor is adopted for the switching elements 411 to 418. In this configuration, since the switching elements 411 to 418 are miniaturized, the gate drivers 205A to 205H can be mounted together on the substrate 20 (that is, on the semiconductor light-emitting device 10). Thereby, the entire light-emitting system 200 can be miniaturized.

[0319] [Modification Example] The above embodiment can be implemented with the following modifications. Further, the above embodiment and each of the following modification examples can be implemented in combination with each other within a technically non-contradictory range.

[0320] ·In each of the above embodiments, a plurality of semiconductor light-emitting elements 30 are arranged on both sides of the light reflection element 50. However, for example, as shown in FIG. 23, a plurality of semiconductor light-emitting elements 30 may be arranged along the four sides of a rectangular light reflection element 50 in a plan view. In the example of FIG. 23, the light reflection element 50 includes first to fourth light incident surfaces 51A to 51D. The plurality of semiconductor light-emitting elements 30 include a first semiconductor light-emitting element 30 provided along the first light incident surface 51A, a second semiconductor light-emitting element 30 provided along the second light incident surface 51B, a third semiconductor light-emitting element 30 provided along the third light incident surface 51C, and a fourth semiconductor light-emitting element 30 provided along the fourth light incident surface 51D. That is, the first semiconductor light-emitting element 30 is oriented to emit light in the first direction D1, the second semiconductor light-emitting element 30 is oriented to emit light in the second direction D2, the third semiconductor light-emitting element 30 is oriented to emit light in the third direction D3, and the fourth semiconductor light-emitting element 30 is oriented to emit light in the fourth direction D4. With this configuration, more semiconductor light-emitting elements 30 can be arranged near the center of the substrate 20.

[0321] ·In each of the above embodiments, the number of capacitors provided in each drive circuit 40 may be one. Further, the capacitor is not limited to a ceramic capacitor and may be a silicon capacitor.

[0322] ·In each of the above embodiments, the number of intermediate electrode layers provided inside the substrate 20 is not limited to two layers and may be one layer or three or more layers. Further, the material of the substrate 20 is not limited to glass epoxy resin or ceramic and may be silicon.

[0323] ·Gate drivers 205A to 205H such as those in the second embodiment may be mounted on the substrate 20 of the first embodiment. ·Protection diodes 70A to 70H such as those in the first embodiment may be mounted on the substrate 20 of the second embodiment.

[0324] As used herein, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is implemented on a second element" is intended that in some embodiments the first element may be in contact with the second element and disposed directly on the second element, while in other embodiments the first element may be disposed above the second element without contacting the second element. That is, the term "on" does not exclude a structure in which other elements are formed between the first element and the second element.

[0325] The Z-axis direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to completely coincide with the vertical direction. Thus, various structures according to the present disclosure (e.g., the structure shown in FIG. 1) are not limited to the "up" and "down" in the Z-axis direction described herein being the "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0326] [Appendix] The technical ideas understood from the above embodiments and each modification example are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples for assisting understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0327] (Appendix 1) A substrate (20), A plurality of semiconductor light-emitting elements (30) each formed by an end-face light-emitting element and provided on the substrate (20), A plurality of drive circuits (40A to 40H) provided on the substrate (20) and each driving one or more of the plurality of semiconductor light-emitting elements (30), A light reflection element (50) provided on the substrate (20) and reflecting the light emitted from the plurality of semiconductor light-emitting elements (30) in a direction intersecting the substrate (20), A semiconductor light-emitting device (10) comprising.

[0328] (Appendix 2) The plurality of semiconductor light-emitting elements (30) are a first semiconductor light-emitting element (30) oriented to emit light in a first direction (D1) parallel to the substrate (20), and a second semiconductor light-emitting element (30) oriented to emit light in a second direction (D2) opposite to the first direction (50), and include The light reflecting element (50) is located between the first semiconductor light-emitting element (30) and the second semiconductor light-emitting element (30) and is configured to reflect the light emitted from each of the first and second semiconductor light-emitting elements (30). The semiconductor light-emitting device (10) according to Appendix 1.

[0329] (Appendix 3) The light reflecting element (50) includes a first light incident surface (51A) and a second light incident surface (51B) on the side opposite to the first light incident surface (51A). The first semiconductor light-emitting element (30) is one of the plurality of first semiconductor light-emitting elements (30) provided along the first light incident surface (51A). The second semiconductor light-emitting element (30) is one of the plurality of second semiconductor light-emitting elements (30) provided along the second light incident surface (51B). The semiconductor light-emitting device (10) according to Appendix 2.

[0330] (Appendix 4) The plurality of semiconductor light-emitting elements (30) are a third semiconductor light-emitting element (30) oriented to emit light in a third direction (D3) parallel to the substrate (20) and orthogonal to the first and second directions (D1, D2), and a fourth semiconductor light-emitting element (30) oriented to emit light in a fourth direction (D4) opposite to the third direction (D3), and further include The first semiconductor light-emitting element (30), the second semiconductor light-emitting element (30), the third semiconductor light-emitting element (30), and the fourth semiconductor light-emitting element (30) are located adjacent to the four sides of the light reflecting element (50). The semiconductor light-emitting device (10) according to appended claim 2, wherein the light reflecting element (50) is configured to reflect the light emitted from each of the first to fourth semiconductor light-emitting elements (30).

[0331] (Appended claim 5) The light reflecting element (50) includes a first light incident surface (51A), a second light incident surface (51B) on the side opposite to the first light incident surface (51A), a third light incident surface (51C) continuous with the first and second light incident surfaces (51A, 51B), and a fourth light incident surface (51D) continuous with the first and second light incident surfaces (51A, 51B) and on the side opposite to the third light incident surface (51C). The first semiconductor light-emitting element (30) is one of a plurality of first semiconductor light-emitting elements (30) provided along the first light incident surface (51A). The second semiconductor light-emitting element (30) is one of a plurality of second semiconductor light-emitting elements (30) provided along the second light incident surface (51B). The third semiconductor light-emitting element (30) is one of a plurality of third semiconductor light-emitting elements (30) provided along the third light incident surface (51C). The semiconductor light-emitting device (10) according to appended claim 4, wherein the fourth semiconductor light-emitting element (30) is one of a plurality of fourth semiconductor light-emitting elements (30) provided along the fourth light incident surface (51D).

[0332] (Appended claim 6) The semiconductor light-emitting device (10) according to any one of appended claims 1 to 5, wherein the light reflecting element (50) is configured to reflect the light emitted from the plurality of semiconductor light-emitting elements (30) in the same direction in a direction intersecting the substrate (20).

[0333] (Appended claim 7) The semiconductor light-emitting device (10) according to any one of appended claims 1 to 6, wherein the light reflecting element (50) is a mirror or a diffraction grating.

[0334] (Appended claim 8) Each of the plurality of drive circuits (40A to 40H) a switching element (411 to 418) that controls one or more of the plurality of semiconductor light-emitting elements (30); a capacitor (421 to 428) that supplies current to one or more of the plurality of semiconductor light-emitting elements (30), the semiconductor light-emitting device (10) according to any one of Appendices 1 to 7.

[0335] (Appendix 9) The capacitor is one of the plurality of capacitors (421 to 428) provided in each of the plurality of drive circuits (40A to 40H), the semiconductor light-emitting device (10) according to Appendix 8.

[0336] (Appendix 10) The capacitors (421 to 428) are ceramic capacitors or silicon capacitors, the semiconductor light-emitting device (10) according to Appendix 8 or 9.

[0337] (Appendix 11) The switching elements (411 to 418) are MOSFETs or nitride semiconductor transistors, the semiconductor light-emitting device (10) according to any one of Appendices 8 to 10.

[0338] (Appendix 12) The switching elements (411 to 418) are connected to each of one or more of the plurality of semiconductor light-emitting elements (30) by a plurality of wires (W1), the semiconductor light-emitting device (10) according to any one of Appendices 8 to 11.

[0339] (Appendix 13) The semiconductor light-emitting device (10) according to any one of Appendices 8 to 12, further comprising a plurality of gate drivers (205A to 205H) that drive the switching elements (411 to 418) in one of the plurality of drive circuits (40A to 40H).

[0340] (Appendix 14) The semiconductor light-emitting device (10) according to any one of Appendices 1 to 13, further comprising a plurality of protection diodes (70A to 70H) each connected in anti-parallel to one or more of the plurality of semiconductor light-emitting elements (30).

[0341] (Appendix 15) The semiconductor light-emitting device (10) according to any one of Appendices 1 to 14, further comprising a plurality of reverse current prevention diodes (204A to 204H) provided between a power input unit (201, 202, 203) that supplies current to the plurality of semiconductor light-emitting elements (30) and the plurality of drive circuits (40A to 40H) and one of the plurality of drive circuits (40A to 40H).

[0342] (Appendix 16) The semiconductor light-emitting device (10) according to any one of Appendices 1 to 15, wherein the substrate (20) is formed of any one of glass epoxy resin, ceramic, and silicon.

[0343] (Appendix 17) A surface electrode layer (28A) located on the main surface (21) of the substrate (20), A back surface electrode layer (28B) located on the back surface (22) of the substrate (20), An intermediate electrode layer (28C; 28D) located between the surface electrode layer (28A) and the back surface electrode layer (28B) in the thickness direction of the substrate (20), A plurality of vias provided in the substrate (20) for electrically connecting the surface electrode layer (28A), the back surface electrode layer (28B), and the intermediate electrode layer (28C; 28D), Comprising, The plurality of semiconductor light-emitting elements (30) and the plurality of drive circuits (40A to 40H) are mounted on the surface electrode layer (28A), The current path (CP) of the current flowing through each of the plurality of drive circuits (40A to 40H) and one or more of the plurality of semiconductor light-emitting elements (30) to be driven by each of the drive circuits (40A to 40H) is constituted by the surface electrode layer (28A), the intermediate electrode layer (28C; 28D), and some of the plurality of vias. The semiconductor light-emitting device (10) according to any one of Appendices 1 to 16.

Explanation of Signs

[0344] 10: Semiconductor light-emitting device 20: Substrate 21: Main surface 22: Back surface 23 to 26: First to fourth side surfaces 27A to 27C: First to third base materials 28A: First electrode layer (surface electrode layer) 28B: Second electrode layer (back surface electrode layer) 28C: Third electrode layer (intermediate electrode layer; surface-side intermediate electrode layer) 28D: Fourth electrode layer (intermediate electrode layer; back surface-side intermediate electrode layer) 29A: Main surface resist layer 29B: Back surface resist layer 30: Semiconductor light-emitting element 31: Element surface 32: Element back surface 34: Surface electrode 35: Back surface electrode 40, 40A to 40H: Drive circuit 411 to 418: Switching element 41A: Element surface 41B: Element back surface 41S: Source electrode 41G: Gate electrode 41D: Drain electrode 421 to 428: Capacitor 42A: First electrode 42B: Second electrode 50: Light reflection element 51A to 51D: Light incident surface 70A to 70H: Protection diode 71: Anode electrode 72: Cathode electrode 200: Light-emitting system 201: DC power supply 202: Capacitor 203: DC limiting resistor 204A~204H: Reverse current prevention diode 205A~205H: Gate driver 206A~206H: Pulse generator 207A~207H: Control power supply 208A~208H: Capacitor 101A~101H,401A~401H: First via 102A~102H,402A~402H: Second via 103A~103H,403A~403L: Third via 104A~104D,404A~404H: Fourth via 105A~105H,405A~405H: Fifth via 406A~406H: Sixth via 407A~407D: Seventh via 408A~408D: Eighth via 409A~409D: Ninth via AC: Central region AP: Peripheral region AP1: First arrangement region AP2: Second arrangement region AP3: Third arrangement region AP4: Fourth arrangement region CP: Current path D1~D4: First to fourth directions L1: Light L2: Reflected light VC,HC: Virtual center line W1~W4: Wire

Claims

1. A substrate, a plurality of semiconductor light-emitting elements provided on the substrate and each constituted by an end-face light-emitting element, a plurality of drive circuits provided on the substrate and each driving one or more of the plurality of semiconductor light-emitting elements, a light reflection element provided on the substrate and reflecting light emitted from the plurality of semiconductor light-emitting elements in a direction intersecting the substrate, a semiconductor light-emitting device comprising the above.

2. The plurality of semiconductor light-emitting elements include a first semiconductor light-emitting element oriented to emit light in a first direction parallel to the substrate, a second semiconductor light-emitting element oriented to emit light in a second direction opposite to the first direction, and the light reflection element is positioned between the first semiconductor light-emitting element and the second semiconductor light-emitting element and is configured to reflect light emitted from each of the first and second semiconductor light-emitting elements. The semiconductor light-emitting device according to Claim 1.

3. The light reflection element includes a first light incident surface and a second light incident surface on the side opposite to the first light incident surface, the first semiconductor light-emitting element is one of a plurality of first semiconductor light-emitting elements provided along the first light incident surface, the second semiconductor light-emitting element is one of a plurality of second semiconductor light-emitting elements provided along the second light incident surface. The semiconductor light-emitting device according to Claim 2.

4. The plurality of semiconductor light-emitting elements further include a third semiconductor light-emitting element oriented to emit light in a third direction parallel to the substrate and orthogonal to the first and second directions, a fourth semiconductor light-emitting element oriented to emit light in a fourth direction opposite to the third direction, and the first semiconductor light-emitting element, the second semiconductor light-emitting element, the third semiconductor light-emitting element, and the fourth semiconductor light-emitting element are positioned adjacent to four sides of the light reflection element, the light reflection element is configured to reflect light emitted from each of the first to fourth semiconductor light-emitting elements. The semiconductor light-emitting device according to Claim 2.

5. The light reflection element includes a first light incident surface, a second light incident surface on the side opposite to the first light incident surface, a third light incident surface continuous with the first and second light incident surfaces, and a fourth light incident surface continuous with the first and second light incident surfaces and on the side opposite to the third light incident surface, the first semiconductor light-emitting element is one of a plurality of first semiconductor light-emitting elements provided along the first light incident surface, The second semiconductor light-emitting element is one of a plurality of second semiconductor light-emitting elements provided along the second light incident surface, The third semiconductor light-emitting element is one of a plurality of third semiconductor light-emitting elements provided along the third light incident surface, The fourth semiconductor light-emitting element is one of a plurality of fourth semiconductor light-emitting elements provided along the fourth light incident surface. The semiconductor light-emitting device according to claim 4.

6. The semiconductor light-emitting device according to claim 1, wherein the light reflecting element is configured to reflect light emitted from the plurality of semiconductor light-emitting elements in the same direction in a direction intersecting the substrate.

7. The semiconductor light-emitting device according to claim 1, wherein the light reflecting element is a mirror or a diffraction grating.

8. Each of the plurality of drive circuits, A switching element that controls one or more of the plurality of semiconductor light-emitting elements; A capacitor that supplies current to one or more of the plurality of semiconductor light-emitting elements. The semiconductor light-emitting device according to claim 1.

9. The capacitor is one of a plurality of capacitors provided in each of the plurality of drive circuits. The semiconductor light-emitting device according to claim 8.

10. The capacitor is a ceramic capacitor or a silicon capacitor. The semiconductor light-emitting device according to claim 8.

11. The switching element is a MOSFET or a nitride semiconductor transistor. The semiconductor light-emitting device according to claim 8.

12. The switching element is connected to each of one or more of the plurality of semiconductor light-emitting elements by a plurality of wires. The semiconductor light-emitting device according to claim 8.

13. The semiconductor light-emitting device according to claim 8, further comprising a plurality of gate drivers that drive the switching elements in one of the plurality of drive circuits.

14. The semiconductor light-emitting device according to claim 1, further comprising a plurality of protection diodes each connected in anti-parallel to one or more of the plurality of semiconductor light-emitting elements.

15. The semiconductor light-emitting device according to claim 1, further comprising a plurality of backflow prevention diodes provided between a power input unit that supplies current to the plurality of semiconductor light-emitting elements and the plurality of drive circuits and one of the plurality of drive circuits.

16. The semiconductor light-emitting device according to claim 1, wherein the substrate is formed of any one of glass epoxy resin, ceramic, and silicon.

17. a surface electrode layer located on the main surface of the substrate; a back surface electrode layer located on the back surface of the substrate; an intermediate electrode layer located between the surface electrode layer and the back surface electrode layer in the thickness direction of the substrate; a plurality of vias provided in the substrate for electrically connecting the surface electrode layer, the back surface electrode layer, and the intermediate electrode layer; comprising the plurality of semiconductor light-emitting elements and the plurality of drive circuits are mounted on the surface electrode layer; the current path of the current flowing through each of the plurality of drive circuits and one or more of the plurality of semiconductor light-emitting elements to be driven by each drive circuit is constituted by the surface electrode layer, the intermediate electrode layer, and some of the plurality of vias. The semiconductor light-emitting device according to any one of claims 1 to 16.

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