Method for manufacturing semiconductor device

Abstract

To provide an etching method capable of alleviating the phenomenon in which the diameter at the bottom of a hole becomes narrower than that at the top, and a method for manufacturing a semiconductor device.SOLUTION: An etching method includes etching a structure formed by stacking sacrificial members 60, 61, and 62 and insulating layers 31, 32, 33, and 35 from within a memory hole (MH) or a slit provided in the structure using an etching solution containing an acid and a polymer.SELECTED DRAWING: Figure 19

Description

Technical Field

[0001] This embodiment relates to a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. With the miniaturization and multilayerization of the memory cell array, the aspect ratios of memory holes, contact holes, etc. are increasing. In the process of forming holes such as high-aspect-ratio memory holes and contact holes, a phenomenon (so-called loading) occurs in which the diameter of the bottom of the hole becomes narrower than that of the upper part.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided is a method for manufacturing a semiconductor device capable of alleviating the phenomenon that the diameter of the bottom of a hole becomes narrower than the diameter of the upper part.

Means for Solving the Problems

[0005] The etching method according to this embodiment includes etching the structure with an etching chemical solution containing an acid and a polymer from inside a hole or a slit provided in the structure.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments according to the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] (First Embodiment) FIG. 1 is a block diagram showing a configuration example of a semiconductor device according to the first embodiment. The semiconductor device 1 is a NAND-type flash memory capable of storing data non-volatilely and is controlled by an external memory controller 2.

[0009] The semiconductor device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0010] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is a set of a plurality of memory cells capable of storing data non-volatilely and is used, for example, as an erasure unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0011] The command register 11 holds the command CMD received by the semiconductor device 1 from the memory controller 2. The command CMD includes, for example, an instruction to cause the sequencer 13 to execute a read operation, a write operation, an erase operation, etc.

[0012] The address register 12 holds the address information ADD received by the semiconductor device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used for selecting a block BLK, a word line, and a bit line, respectively.

[0013] The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11 to execute a read operation, a write operation, an erase operation, etc.

[0014] The driver module 14 generates voltages used in a read operation, a write operation, an erase operation, etc. Then, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on, for example, the page address PAd held in the address register 12.

[0015] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd held in the address register 12. Then, the row decoder module 15 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0016] In the write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. Further, in the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as the read data DAT.

[0017] Note that the semiconductor device 1 and the memory controller 2 may constitute one semiconductor device in combination. Examples of such semiconductor devices include memory cards such as SDTM cards and SSDs (Solid State Drives).

[0018] FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array according to the first embodiment. FIG. 2 shows one block BLK among the plurality of blocks BLK included in the memory cell array 10. The block BLK includes, for example, five string units SU0 to SU4.

[0019] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer, and holds data non-volatilely. Each of the selection transistors ST1 and ST2 is used for selecting the string unit SU during various operations.

[0020] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0021] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are connected to the word lines WL0 to WL7, respectively. The gates of the plurality of selection transistors ST1 in the string unit SU0 are connected to the selection gate line SGD0. The gates of the plurality of selection transistors ST1 in the string unit SU1 are connected to the selection gate line SGD1. The gates of the plurality of selection transistors ST1 in the string unit SU2 are connected to the selection gate line SGD2. The gates of the plurality of selection transistors ST1 in the string unit SU3 are connected to the selection gate line SGD3. The gates of the plurality of selection transistors ST1 in the string unit SU4 are connected to the selection gate line SGD4. The gates of the plurality of selection transistors ST2 are connected to the selection gate line SGS.

[0022] Different column addresses are assigned to the bit lines BL0 to BLm, respectively. Each bit line BL is shared by NAND strings NS to which the same column address is assigned among a plurality of blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared among a plurality of blocks BLK, for example.

[0023] A set of a plurality of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing 1-bit data is defined as "1 page of data". The cell unit CU can have a storage capacity of 2 pages of data or more according to the number of bits of data stored in the memory cell transistor MT.

[0024] Note that the circuit configuration of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other circuit configurations. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to be arbitrary numbers respectively.

[0025] Hereinafter, an example of the structure of the memory cell array 10 included in the semiconductor device 1 according to the embodiment will be described. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate 20 used for forming the semiconductor device 1. The hatching for the plan view is added for easy viewing of the figure, and is not necessarily related to the material or characteristics of the components with the hatching added. In the cross-sectional view, for easy viewing of the figure, the illustration of the configuration is appropriately omitted. Also, the configurations shown in each drawing are appropriately simplified.

[0026] FIG. 3 is a plan view showing an example of the planar layout of the memory cell array according to the first embodiment. FIG. 3 shows regions corresponding to four blocks BLK0 to BLK3 included in the memory cell array 10. The planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory region MA, and lead-out regions HA1 and HA2. Also, the memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE. The semiconductor device 1 according to the present embodiment is a non-volatile memory having a three-dimensional structure memory cell array.

[0027] The memory region MA includes a plurality of NAND strings NS. The memory region MA is sandwiched in the X direction by lead-out regions HA1 and HA2. Each of the lead-out regions HA1 and HA2 is used for connection between the stacked wiring (word lines WL and select gate lines SGD and SGS) and the row decoder module 15. For example, each of the lead-out regions HA1 and HA2 includes a portion (terrace portion) that does not overlap with the upper wiring layer (conductor layer) of each of the select gate line SGS, word lines WL0 to WL7, and select gate line SGD. And a plurality of contacts are respectively provided on the terrace portions of each of the select gate line SGS, word lines WL0 to WL7, and select gate lines SGD0 to SGD4 within each block BLK. The contacts for the stacked wiring are provided, for example, in the lead-out region HA1 in even-numbered blocks BLK and in the lead-out region HA2 in odd-numbered blocks BLK.

[0028] The plurality of slits SLT each have a portion extending along the X direction and are arranged in the Y direction. Each slit SLT crosses the memory region MA and the lead-out regions HA1 and HA2 in the X direction. Also, each slit SLT has, for example, a structure in which an insulator or a plate-like contact is embedded. And each slit SLT divides adjacent wirings (for example, word lines WL0 to WL7 and select gate lines SGD and SGS) via the slit SLT. The aspect ratio of the slit SLT is, for example, 100 or more.

[0029] The plurality of slits SHE each have a portion extending along the X direction and are arranged in the Y direction. In this example, four slits SHE are respectively arranged between adjacent slits SLT. Each slit SHE crosses the memory region MA in the X direction, one end of each slit SHE is included in the lead-out region HA1, and the other end is included in the lead-out region HA2. Also, each slit SHE has, for example, a structure in which an insulator is embedded. And each slit SHE divides adjacent wirings (at least the select gate line SGD) via the slit SHE.

[0030] In the planar layout of the memory cell array 10 described above, each of the regions separated by the slit SLT corresponds to one block BLK. Also, each of the regions separated by the slits SLT and SHE corresponds to one string unit SU. And in the memory cell array 10, for example, the layout shown in FIG. 3 is repeatedly arranged in the Y direction.

[0031] Note that the planar layout of the memory cell array 10 may be other layouts. For example, the number of slits SHE arranged between adjacent slits SLT can be designed to be any number. The number of string units SU formed between adjacent slits SLT can be changed based on the number of slits SHE arranged between adjacent slits SLT.

[0032] FIG. 4 is a plan view showing an example of the planar layout of the memory region of the memory cell array according to the first embodiment. FIG. 4 shows a region including one block BLK (that is, string units SU0 to SU4). The memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MA. Also, each slit SLT includes a contact LI and a spacer SP.

[0033] Each of the memory pillars MP functions as, for example, one NAND string NS. The plurality of memory pillars MP are arranged in a staggered pattern of, for example, 24 columns in the region between two adjacent slits SLT. And, for example, starting from the upper side of the paper surface, one slit SHE overlaps each of the memory pillars MP in the 5th column, the 10th column, the 15th column, and the 20th column.

[0034] A plurality of bit lines BL each have a portion extending in the Y direction and are arranged side by side in the X direction. Each bit line BL is arranged to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged to overlap one memory pillar MP. Among the plurality of bit lines BL overlapping the memory pillar MP, one bit line BL and the memory pillar MP are electrically connected via a contact CV.

[0035] For example, the contact CV between the memory pillar MP in contact with the slit SHE and the bit line BL is omitted. In other words, the contact CV between the memory pillar MP and the bit line BL in contact with two different select gate lines SGD is omitted. The number and arrangement of the memory pillars MP, slits SHE, etc. between adjacent slits SLT may be other configurations and can be appropriately changed. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0036] The contact LI is a conductor having a portion extending in the X direction. The spacer SP is an insulator provided on the side surface of the contact LI. The contact LI is sandwiched by the spacer SP. The contact LI and a conductor (for example, word lines WL0 to WL7, and select gate lines SGD and SGS) adjacent to the contact LI in the Y direction are separated and insulated by the spacer SP.

[0037] FIG. 5 is a diagram showing an example of a cross-sectional structure of a memory region of a memory cell array according to the first embodiment. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 4. The memory cell array 10 further includes, for example, a semiconductor substrate 20, conductor layers 21 to 25, and insulator layers 30 to 34.

[0038] Specifically, an insulator layer 30 is provided on the semiconductor substrate 20. Although not shown, the insulator layer 30 includes circuits corresponding to, for example, a row decoder module 15 and a sense amplifier module 16.

[0039] On the insulator layer 30, a conductor layer 21 is provided. The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane and is used as a source line SL. The conductor layer 21 contains, for example, phosphorus-doped silicon.

[0040] On the conductor layer 21, an insulator layer 31 is provided. On the insulator layer 31, a conductor layer 22 is provided. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line SGS.

[0041] On the conductor layer 22, the insulator layer 32 and the conductor layer 23 are alternately laminated. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. The plurality of laminated conductor layers 23 are used as word lines WL0 to WL7 in order from the semiconductor substrate 20 side.

[0042] On the uppermost conductor layer 23, an insulator layer 33 is provided. On the insulator layer 33, a conductor layer 24 is provided. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line SGD.

[0043] On the conductor layer 24, an insulator layer 34 is provided. On the insulator layer 34, a conductor layer 25 is provided. The conductor layer 25 is formed, for example, in a line shape extending in the Y direction and is used as a bit line BL. That is, in a region not shown, a plurality of conductor layers 25 are arranged along the X direction. The conductor layer 25 contains, for example, copper.

[0044] Each of the memory pillars MP extends along the Z direction and penetrates the insulator layers 31 to 33 and the conductor layers 22 to 24. The bottom of each of the memory pillars MP is in contact with the conductor layer 21. The portion where the memory pillar MP intersects with the conductor layer 22 functions as the selection transistor ST2. The portion where the memory pillar MP intersects with one conductor layer 23 functions as one memory cell transistor MT. The portion where the memory pillar MP intersects with the conductor layer 24 functions as the selection transistor ST1.

[0045] Also, each of the memory pillars MP includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is provided to extend along the Z direction. For example, the upper end of the core member 40 is included in an upper layer than the conductor layer 24, and the lower end of the core member 40 reaches the conductor layer 21. The semiconductor layer 41 covers the periphery of the core member 40. In the lower part of the memory pillar MP, a part of the semiconductor layer 41 is in contact with the conductor layer 21. The laminated film 42 covers the side surface and the bottom surface of the semiconductor layer 41 except for the portion where the semiconductor layer 41 and the conductor layer 21 are in contact. The core member 40 is made of an insulating material such as silicon oxide. The semiconductor layer 41 contains, for example, silicon.

[0046] A columnar contact CV is provided on the semiconductor layer 41 in the memory pillar MP. In the illustrated region, two contacts CV corresponding to two of the six memory pillars MP are shown. In the memory region MA, the contacts CV are connected in a region not shown for the memory pillars MP that do not overlap with the slit SHE and to which the contacts CV are not connected.

[0047] On the contact CV, one conductor layer 25, that is, one bit line BL, is in contact. In each of the spaces separated by the slits SLT and SHE in one conductor layer 25, one contact CV is connected. That is, in each of the conductor layers 25, a memory pillar MP provided between adjacent slits SLT and SHE and a memory pillar MP provided between two adjacent slits SHE are electrically connected.

[0048] The slit SLT has a portion provided along, for example, the XZ plane and divides the conductor layers 22 to 24. The contact LI in the slit SLT is provided along the slit SLT. A part of the upper end of the contact LI is in contact with the insulator layer 34. The lower end of the contact LI is in contact with the conductor layer 21. The contact LI is used, for example, as a part of the source line SL. The spacer SP is provided at least between the contact LI and the conductor layers 22 to 24. The contact LI and the conductor layers 22 to 24 are separated and insulated by the spacer SP.

[0049] The slit SHE has a portion provided along, for example, the XZ plane and divides at least the conductor layer 24. The upper end of the slit SHE is in contact with the insulator layer 34. The lower end of the slit SHE is in contact with the insulator layer 33. The slit SHE contains an insulator such as silicon oxide, for example. The upper end of the slit SHE and the upper end of the slit SLT may or may not be aligned. Also, the upper end of the slit SHE and the upper end of the memory pillar MP may or may not be aligned.

[0050] FIG. 6 is a diagram showing an example of a cross-sectional structure of a memory region MA of the memory cell array 10 according to the first embodiment. FIG. 6 is an enlarged view of region VI in FIG. 5. Specifically, FIG. 6 shows the respective structures of the memory pillar MP and the conductor layer 23 at the portion where the conductor layer 23 and the memory pillar MP intersect. The stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a cover insulating film 45. The conductor layer 23 includes, for example, a conductor 50 and a barrier metal 51. The memory cell array 10 further includes a block insulating film 46.

[0051] The tunnel insulating film 43 is provided on the side surface of the semiconductor layer 41. The insulating film 44 is provided on the side surface of the tunnel insulating film 43. The cover insulating film 45 is provided on the side surface of the insulating film 44. The cover insulating film 45 is divided by the block insulating film 46 at the portion where the memory pillar MP and the conductor layer 23 intersect. The block insulating film 46 is provided between the conductor layer 23 and the insulator layer 32 and between the conductor layer 23 and the insulating film 44. The conductor 50 is embedded in a space surrounded by three sides by the block insulating film 46. The conductor 50 and the block insulating film 46 are separated by the barrier metal 51.

[0052] As the tunnel insulating film 43, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride film is used. The cover insulating film 45 contains, for example, silicon oxide.

[0053] The insulating film 44 contains, for example, silicon nitride. The block insulating film 46 contains, for example, aluminum oxide (Al2O3). The block insulating film 46 is also used as a seed layer for forming the conductor 50. The conductor 50 contains molybdenum (Mo). The conductor 50 may contain impurities. Examples of impurities that may be contained in the conductor 50 include oxygen (O), hydrogen (H), etc. The barrier metal 51 contains, for example, titanium nitride (TiN).

[0054] Note that the barrier metal 51 may be omitted. The block insulating film 46 may be provided on the side surface portion of the memory pillar MP instead of the cover insulating film 45. The structures of the conductor layer 22 and the memory pillar MP at the intersection of the conductor layer 22 and the memory pillar MP, and the structures of the conductor layer 24 and the memory pillar MP at the intersection of the conductor layer 24 and the memory pillar MP are the same as the structures of the conductor layer 23 and the memory pillar MP at the intersection of the conductor layer 23 and the memory pillar MP.

[0055] FIG. 7 is a diagram showing an example of a cross-sectional structure of a memory pillar according to the first embodiment. FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 5. Specifically, FIG. 7 shows the cross-sectional structure of the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23. In the cross-section including the conductor layer 23, the core member 40 is provided at the center of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 46 surrounds the side surface of the insulating film 44. The barrier metal 51 surrounds the side surface of the block insulating film 46. The conductor layer 23 surrounds the side surface of the barrier metal 51.

[0056] In a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 22, the structure of the conductor layer 22 and the memory pillar MP, and in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 24, the structure of the conductor layer 24 and the memory pillar MP are each the same as the structure of the conductor layer 23 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23. In each of the memory pillars MP described above, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 44 is used as the charge storage layer of the memory cell transistor MT. The semiconductor device 1 can cause a current to flow between the bit line BL and the contact LI through the memory pillar MP by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0057] Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described.

[0058] FIGS. 8 to 15 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0059] As shown in FIG. 8, a CMOS (Complementary Metal Oxide Semiconductor) circuit (not shown) corresponding to the row decoder module 15 or the like is formed on the semiconductor substrate 20, and an insulator layer 30 covering the CMOS circuit is further formed. Note that the CMOS circuit may be formed on another semiconductor substrate (not shown). In this case, after forming the memory region MA on the semiconductor substrate 20, the semiconductor substrate of the CMOS circuit may be bonded to the semiconductor substrate of the memory region MA.

[0060] Next, a conductor layer 21 is formed on the insulator layer 30. An insulator layer 31 and a sacrificial member 60 are sequentially formed on the conductor layer 21. A sacrificial member 61 and an insulator layer 32 are alternately laminated on the sacrificial member 60. An insulator layer 33 and a sacrificial member 62 are sequentially formed on the uppermost sacrificial member 61. An insulator layer 35 is formed on the sacrificial member 62. Note that the sacrificial member 60 is associated with the select gate line SGS. The sacrificial member 61 is associated with the word line WL. The sacrificial member 62 is associated with the select gate line SGD. Each of the sacrificial members 60, 61, and 62 is, for example, a material containing nitrogen and silicon (e.g., silicon nitride). The insulator layers 30 to 33, 35 are, for example, materials containing oxygen and silicon (e.g., silicon oxide film).

[0061] Next, as shown in FIG. 9, a memory hole MH is formed. Specifically, a mask (not shown) having openings in regions corresponding to a plurality of memory pillars MP is formed. A plurality of memory holes MH are formed by anisotropic etching processing using the mask. The memory hole MH penetrates each of the insulator layers 31, 32, 33, and 35, and the sacrificial members 60, 61, and 62. Further, the bottom of the memory hole MH reaches the conductor layer 21.

[0062] Next, as shown in FIG. 10, a memory pillar MP is formed. Specifically, a cover insulating film 45, an insulating film 44, and a tunnel insulating film 43 are sequentially formed on the side surfaces and the bottom surface of a plurality of memory holes MH. Thereby, a laminated film of the cover insulating film 45, the insulating film 44, and the tunnel insulating film 43 is formed. A part of the cover insulating film 45, the insulating film 44, and the tunnel insulating film 43 provided at the bottom of the memory hole MH is removed, and a semiconductor layer 41 and a core member 40 are formed in the memory hole MH. Then, a part of the core member 40 provided at the upper part of the memory hole is removed, and a semiconductor layer 41 is formed in the part where a part of the core member 40 is removed. Thereby, the structure of a plurality of memory pillars MP is formed. Thereafter, an insulator layer 36 is formed on the insulator layer 35 and the plurality of memory pillars MP. The insulator layer 36 protects the upper part of the memory pillar MP. The insulator layers 35 and 36 are included in the insulator layer 34 shown in FIG. 5.

[0063] Next, as shown in FIG. 11, a slit SLT is formed. Specifically, a mask having an opening in a region corresponding to the slit SLT is formed by photolithography or the like. Then, an anisotropic etching using the mask forms a slit SLT that divides each of the insulator layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62. Also, the bottom of the slit SLT reaches, for example, the conductor layer 21. Note that after the formation of the slit SLT, a process of forming a protective film for the conductor layer 21 exposed at the bottom of the slit SLT may be performed.

[0064] Next, as shown in FIG. 12, the sacrificial members 60, 61, and 62 are removed and formed. Specifically, in the process of step S14, a wet etching process using hot phosphoric acid or the like is executed. More specifically, by supplying hot phosphoric acid or the like through the slit SLT, the sacrificial members 60, 61, and 62 are selectively removed. Also, although not shown in the figure, the cover insulating film 45 provided at the portion in contact with any of the sacrificial members 60, 61, and 62 in each memory pillar MP is removed. The structure in which the sacrificial members 60, 61, and 62 are removed is supported by a plurality of memory pillars MP and the like.

[0065] Next, as shown in FIG. 13, the conductor 50 is formed. Specifically, the block insulating film 46 and the barrier metal 51 in FIG. 6 are formed in order. For the formation of the block insulating film 46, for example, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like is used. The conductor 50 is embedded in the space where the sacrificial members 60 to 62 are removed. For the formation of the conductor 50, for example, a thermal CVD method, an ALD method, or the like is used. Note that each of the block insulating film 46, the barrier metal 51, and the conductor 50 is also formed on the side surface portion of the slit SLT and the upper surface portion of the insulator layer 36. At this point, the conductors 50 formed in the space where the sacrificial members 60 to 62 are removed are continuously provided and electrically connected.

[0066] Next, as shown in FIG. 14, an etching process of the conductor 50 is executed. Specifically, using a wet etching method, the conductor 50 formed on the side surface of the slit SLT and the conductor 50 formed on the upper surface of the insulator layer 36 are removed. Note that it is sufficient that the conductors 50 formed in the wiring layers adjacent in the Z direction are at least separated. Thereby, a conductor layer 22 functioning as a select gate line SGS, a plurality of conductor layers 23 each functioning as word lines WL0 to WL7, and a conductor layer 24 functioning as a select gate line SGD are respectively formed.

[0067] Next, as shown in FIG. 15, the embedding process of the slit SLT is executed. Specifically, an insulating film (spacer SP) is formed so as to cover the side surface and the bottom surface of the slit SLT. A part of the spacer SP provided at the bottom of the slit SLT is removed, and a part of the conductor layer 21 is exposed at the bottom of the slit SLT. A conductor (contact LI) is formed in the slit SLT, and the conductor formed outside the slit SLT is removed by, for example, CMP (Chemical Mechanical Polishing). Thereafter, a plurality of grooves parallel to the slit SLT are formed between the slits SLT adjacent in the Y direction, and an insulating film is embedded in each groove, whereby the slit SHE of FIG. 5 that divides the conductor layer 24 in the Y direction is formed.

[0068] Through the manufacturing process as described above, the laminated wiring structure in the memory cell array 10 is formed. A series of processes for replacing the sacrificial members 60, 61, and 62 with the conductor layers 22, 23, and 24 may be referred to as a "replacement process". Note that the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between the respective manufacturing processes, or some processes may be omitted or integrated. For example, a process for forming a stepped structure of the laminated wiring may be inserted between the processes shown in FIGS. 8 and 9.

[0069] Here, the formation process of the memory hole MH shown in FIG. 9 will be described in more detail.

[0070] FIGS. 16 to 19 are cross-sectional views showing an example of the formation process of the memory hole according to the first embodiment.

[0071] The memory hole MH shown in FIG. 9 is formed in a structure formed by laminating the sacrificial members 60, 61, 62 and the insulator layers 31, 32, 33, 35 shown in FIG. 8 using lithography technology and dry etching technology such as RIE (Reactive Ion Etching) method. The memory hole MH is formed so as to extend and penetrate in the Z direction within this structure. The lower end of the memory hole MH reaches the conductor layer 21.

[0072] At this time, the diameter of the memory hole MH is narrow at the bottom of the memory hole MH and widens toward the top. Furthermore, the diameter of the memory hole MH is slightly narrower near the opening of the memory hole MH. The difference between the diameter of the upper part and the diameter of the lower part of the memory hole MH is more noticeable when the aspect ratio of the memory hole MH is high (for example, 100 or more). The opening diameter of the upper part of the memory hole MH is, for example, 110 nm to 120 nm, and the depth is, for example, 14 μm. In such a case, the difference between the diameter of the upper part and the diameter of the lower part of the memory hole MH becomes significantly large. A large difference between the diameter of the upper part and the diameter of the lower part of the memory hole MH can cause device failure. It is believed that such a tapered shape of the memory hole MH is caused by the loading effect in the etching process.

[0073] Therefore, in this embodiment, in order to reduce the difference between the diameters of the upper and lower parts of the memory hole MH, the following wet etching process (recess process) is performed.

[0074] As shown in FIG. 16, the structure is etched from inside the memory hole MH using an etching solution for the recess process. This etching solution contains an acid ECH that functions as an etchant and a polymer PLM that protects the structure from the acid ECH. The acid ECH is, for example, hydrofluoric acid (HF), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3COOH), phosphoric acid (H3PO4), etc. The polymer PLM is, for example, an organic polymer, and further, for example, an organic amine or an organic amine salt. The organic amine added to the etching solution is, for example, a polyalkyleneimine (polyethyleneimine, polypropyleneimine, polybutyleneimine). The organic amine salt is, for example, a hydrochloride or a nitrate. Furthermore, polyethylene glycol, polypropylene glycol, or polybutylene glycol may be added to the etching solution as an organic polymer.

[0075] More specifically, as the etching chemical solution, for example, as the acid ECH, buffered hydrofluoric acid (BHF) has polyethyleneimine (PEI) added thereto as the polymer PLM. As the etching chemical solution, for example, the above polymer PLM may be added to a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water as the acid ECH. The PEI molecular weight is, for example, 600 to 70,000, and the additive concentration is adjusted within the range of 0.05 wt% to 10 wt%. In the recess process using this etching chemical solution, while the surface of the upper part of the memory hole MH is protected by the added polymer PLM, the acid ECH quickly reaches the lower part of the memory hole MH. The molecular weight of the polymer PLM is as large as 600 to 70,000 and the diffusion is slower than that of the acid ECH. Therefore, although the polymer PLM covers the upper part of the memory hole MH with an aspect ratio of 100 or more, it takes time to reach the lower part of the memory hole MH. On the other hand, since the acid ECH as an etchant diffuses faster than the polymer PLM, it quickly reaches the lower part of the memory hole MH. Thus, the acid ECH etches more of the lower part than the upper part of the memory hole MH. Thereby, as shown in FIG. 17, while suppressing the etching of the upper part of the memory hole MH, the etching of the lower part can be promoted.

[0076] Furthermore, as shown in FIGS. 18 and 19, when the polymer PLM gradually diffuses to the lower part of the memory hole MH, the polymer PLM gradually covers and protects the inner wall of the memory hole MH from the upper part to the lower part. Thereby, the etching amount in this recess process increases as it goes from the upper part to the lower part of the memory hole MH.

[0077] That is, the recess process using the etching chemical solution according to this embodiment acts to reduce the difference between the diameter of the upper part and the diameter of the lower part of the memory hole MH (reverse loading effect), whereby the tapered shape of the memory hole MH can be relaxed. As shown in FIG. 19, the opening diameter Wb at the bottom of the memory hole MH can be made equal to or larger than the opening diameter Wt at the upper part. As a result, the yield and reliability of the device can be improved.

[0078] In addition, in FIG. 19, for the sake of convenience, the inner wall is illustrated as having steps from the upper part to the lower part of the memory hole MH, but actually, the inner wall is in a smoother state according to the molecular weight of the polymer PLM.

[0079] The smaller the molecular weight of the polymer PLM, the faster the polymer PLM diffuses to the lower part of the memory hole MH. In this case, the reverse loading effect becomes smaller, and the tapered shape of the memory hole MH cannot be sufficiently corrected. Therefore, the molecular weight of the polymer PLM is preferably large. For example, as shown in FIG. 20, in the experiment, it was found that the molecular weight of PEI as the polymer PLM is preferably 600 or more, and more preferably 10,000 or more.

[0080] In addition, experimentally, it was found that when the polymer PLM is polyethylene glycol (PEG), the effects of this embodiment can be obtained even if its molecular weight is 5,000,000. However, since a polymer PLM with a molecular weight of 5,000,000 or more is not available on the market, the upper limit is set at 5,000,000. Therefore, the molecular weight of the polymer PLM is preferably 600 to 5,000,000. When PEI is used as the polymer PLM, since PEI with a molecular weight of 70,000 or more is not available on the market, the upper limit of the molecular weight of PEI is set at 70,000.

[0081] In addition, whether polyethyleneimine is contained in the chemical solution can be determined from the analysis using infrared spectroscopy (FT-IR: Fourier Transform Infrared Spectroscopy) and nuclear magnetic resonance (NMR: Nuclear Magnetic Resonance). Further, the weight average molecular weight of the polyethyleneimine contained in the chemical solution can be determined by gel permeation chromatography (GPC: Gel Permeation Chromatography).

[0082] FIG. 20 is a graph showing the relationship between the molecular weight of PEI and the reverse loading effect. The vertical axis represents the ratio of the etching amount at the bottom of the memory hole MH to the etching amount at the top (etching amount at the top / etching amount at the bottom). The horizontal axis represents the molecular weight of PEI. The ratio of the etching amounts can be derived, for example, by implementing the manufacturing method of the first embodiment under conditions where the etching rates for the insulator layer 33 and the insulator layer 32 are different, and obtaining the ratio of the magnitudes of the steps generated by the difference in the etching rates of the insulator layer 33 and the insulator layer 32.

[0083] Referring to this graph, when the molecular weight of PEI is 600 or more, the ratio of the etching amounts decreases, and when the molecular weight of PEI is 10,000 or more, the ratio of the etching amounts becomes 1 or less. That is, the etching amount at the bottom of the memory hole MH becomes larger than the etching amount at the top due to the reverse loading effect. Therefore, the molecular weight of PEI is preferably 600 or more, and more preferably 10,000 or more.

[0084] (Modification 1) The above recess process can be applied to the formation process of the slit SLT shown in FIG. 11. That is, using lithography technology and dry etching technology such as the RIE method, the slit SLT is formed in the structure of the memory region MA so as to reach the conductor layer 21. The slit SLT is formed so as to divide the structures of the insulator layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62. At this time, in a cross-section parallel to the Y-Z plane, due to the loading effect, the difference between the upper diameter and the lower diameter of the slit SLT is large, and it has a tapered shape.

[0085] Next, in the recess process, the slit SLT is etched using the etching chemical solution containing the acid ECH and the polymer PLM. Thereby, it acts to reduce the difference between the upper diameter and the lower diameter of the slit SLT (reverse loading effect), and thereby, the tapered shape of the slit SLT can be relaxed.

[0086] Thus, the recess process according to this embodiment is also applicable to the process of forming the slit SLT.

[0087] (Modification 2) FIGS. 21 and 22 are perspective views showing an example of the configuration of the extraction regions according to Modification 2 of the first embodiment. FIGS. 21 and 22 show an overview of the extraction regions HA1 and HA2 of a certain block BLK. The stepped portions SSA of the extraction regions HA1 and HA2 are provided at both ends in the X direction of the memory region MA in FIG. 3. The stepped portion SSA is configured such that each conductor layer 23 (word line WL) is exposed from the memory region MA when viewed from the Z direction in the stacking direction. Although not shown, the stepped portion SSA is covered with an interlayer insulating film such as a silicon oxide film, for example.

[0088] In the stepped portion SSA, as shown in FIG. 22, a plurality of conductor layers 23 (word lines WL) are configured in a stepped shape. The contact plug CC extends in the Z direction within the interlayer insulating film and is connected to each of the plurality of conductor layers 23 (word lines WL). For the contact plug CC, a conductive metal material such as tungsten is used, for example.

[0089] The contact plug CC is electrically connected to a CMOS such as a row decoder provided under the memory cell array 10 via an upper layer wiring (not shown) and via another contact plug. Thereby, the row decoder can control the voltage of each conductor layer 23 (word line WL) via the contact plug CC.

[0090] Such a recess process can also be applied to the formation of the contact plug CC. That is, both ends in the X direction of the structures of the insulator layers 31, 32, 33, 35 and 36, and the sacrificial members 60, 61 and 62 are processed in a stepped manner and go through a replacement process. The structure is covered with an interlayer insulating film (not shown). After the placement process, contact holes CH are formed in the interlayer insulating film using lithography technology and dry etching technology such as the RIE method so that the contact holes CH reach each conductor layer 23. At this time, due to the loading effect, the difference between the upper diameter and the lower diameter of the contact hole CH is large, and it has a tapered shape.

[0091] Next, in the recess process, the contact hole CH is etched using an etching chemical solution containing the acid ECH and the polymer PLM. Thereby, it acts to reduce the difference between the upper diameter and the lower diameter of the contact hole CH (reverse loading effect), and thereby, the tapered shape of the contact hole CH can be relaxed.

[0092] Thus, the recess process according to the present embodiment is also applicable to the formation process of the contact plug CC.

[0093] The recess process according to the present embodiment is not limited to the above process and can be applied to the formation process of holes or slits with a high aspect ratio.

[0094] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0095] 1 Semiconductor device 10 Memory cell array SLT slit SHE slit MA memory area HA1, HA2 extraction area MP memory pillar MH memory hole slit SLT 31 - 36 insulator layer 60 - 62 sacrificial member 21 - 24 conductor layer ECH acid PLM polymer

Claims

1. An etching method comprising etching the structure from within a hole or slit provided in the structure with an etching chemical solution containing an acid and a polymer.

2. The etching method according to claim 1, wherein the polymer is an organic polymer.

3. The etching method according to claim 2, wherein the organic polymer is an organic amine or an organic amine salt.

4. The etching method according to claim 3, wherein the organic amine is a polyalkyleneimine.

5. The etching method according to claim 3, wherein the organic amine is polyethyleneimine, polypropyleneimine, or polybutyleneimine.

6. The etching method according to claim 2, wherein the organic polymer is polyethylene glycol, polypropylene glycol, or polybutylene glycol.

7. The molecular weight of the polymer is from 600 to 5,000,000, and when the polymer is polyethyleneimine, the molecular weight is from 10,000 to 70,000. The etching method according to any one of claims 1 to 6.

8. The etching method according to any one of claims 1 to 6, wherein the aspect ratio of the structure is 100 or more.

9. The etching method according to claim 1, wherein the structure is a laminate in which a sacrificial member and an insulator layer are alternately laminated in a first direction.

10. A method for manufacturing a semiconductor device, comprising etching the structure from within a hole or slit provided in the structure with an etching chemical solution containing an acid and a polymer.

11. Forming the structure by alternately laminating a sacrificial member and an insulator layer in a first direction, forming a hole extending in the first direction within the structure, etching the structure from within the hole using the etching chemical solution, forming a columnar body including a stacked film and a semiconductor layer within the hole, removing the sacrificial member, and further comprising embedding a conductor material in the space from which the sacrificial member has been removed after removing the sacrificial member to form a conductive layer between the adjacent insulators in the first direction. The manufacturing method according to claim 10, wherein the etching chemical solution is used when etching the structure from within the hole.

12. After forming the columnar body, forming a slit for dividing the structure, and further comprising etching the structure from within the slit using the etching chemical solution. ​ The sacrificial member is etched and removed through the slit, The material of the conductor is embedded in the space through the slit, The manufacturing method according to claim 11.

13. The end of the structure is processed into a stepped shape, An interlayer insulating film is formed on the structure, A contact hole that extends in the first direction and reaches each conductive layer is formed in the interlayer insulating film, The structure is etched from within the contact hole using the etching chemical solution, The manufacturing method according to claim 12, further comprising forming a conductive material in the contact hole to form a contact plug that is electrically connected to each conductive layer.

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