Semiconductor device

Abstract

To reduce the number of ropes contacted to a pad by suppressing an influence of noises to the other circuit.SOLUTION: A plurality of first standard cells (10, 10D, and 10E) that is arranged in parallel to a first direction (x) is arranged at a neighbor of a border from a P-well region (10p) or the other well region in an N-well region (10n), and includes first active regions (13, 15, and 13e) that are constructed so as to be extended to the first direction (x). The first active regions (13, 15, and 13e) are constructed by a P-diffusion layer (110) when they are formed in the P-well region (10p), and are constructed by an N-diffusion layer (110e) when they are formed in the N-well region (10n). A back gate of each of the first active regions (13, 15, and 13e) and a P-channel type MOS transistor (11) or a back gate of an N-channel type MOS transistor (12) become the same potential.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In the design of semiconductor integrated circuits, EDA (Electronic Design Automation) tools may be used. In EDA tools, based on the connection information of standard cells, the positions of the standard cells are automatically arranged and the standard cells are automatically wired (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In a semiconductor integrated circuit using standard cells as shown in Patent Document 1, latch-up may occur.

[0005] A semiconductor device according to one aspect of the present disclosure has a plurality of first standard cells arranged side by side in a first direction. The first standard cell has a P-well region having a P-well structure, an N-well region having an N-well structure arranged side by side in a second direction intersecting the P-well region and the first direction, and a first active region arranged near a boundary between the P-well region and the other well region in the P-well region or the N-well region and having a structure extending in the first direction. At least one of the first standard cells is a functional cell. A P-channel MOS transistor is arranged in the N-well region, and an N-channel MOS transistor is arranged in the P-well region. The first active region is composed of a P-diffusion layer when formed in the P-well region and is composed of an N-diffusion layer when formed in the N-well region. The first active region has a configuration in which it has the same potential as the back gate of the N-channel MOS transistor or the back gate of the P-channel MOS transistor. The first active regions of the first standard cells adjacent to each other in the first direction have a configuration in which they have the same potential.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 7

Figure 8

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Figure 10

Figure 11

Figure 12

Figure 13

[0007] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a transistor in which the gate structure is composed of at least three layers of "a layer made of a conductor or a semiconductor such as polysilicon having a small resistance value", "an insulating layer", and "a P-channel type, N-channel type, or intrinsic semiconductor layer". That is, the gate structure of the MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. In addition, the MOS field effect transistor may be simply referred to as a MOS transistor. Further, a P-channel type MOS transistor is described as a PMOS transistor, and an N-channel type MOS transistor is described as an NMOS transistor.

[0008] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings to be referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted in principle.

[0009] For "connection" between a plurality of parts forming a circuit, such as any element, line, etc., it shall include the case of being mechanically connected, and also the case of being electrically connected, in other words, the case where electricity can flow. That is, "connect" includes the case of "electrically connecting". In the semiconductor device 100 shown in FIG. 1, the left - right direction in which the first standard cells 10 are arranged is defined as the first direction x, and the up - down direction orthogonal to the first direction x is defined as the second direction y. Also, for the composite cells arranged in the semiconductor device, up, down, left, and right are defined based on the state shown in FIG. 1. Further, in the plan views such as FIG. 1 and FIG. 2, for the sake of easy understanding, a part of the wiring is hatched with grid lines.

[0010] <semiconductor device 100> FIG. 1 is a schematic plan view of a semiconductor device 100 according to an embodiment of the present disclosure. As shown in FIG. 1, in the semiconductor device 100, the first standard cells 10 and the second standard cells 20 are automatically arranged and automatically connected based on the given connection information in advance.

[0011] In the semiconductor device 100, a plurality of first standard cells 10 are arranged side by side in the first direction x. Also, second standard cells 20 are arranged at both ends of the plurality of first standard cells 10 in the first direction x. And the first standard cells 10 arranged in the first direction x and the second standard cells 20 arranged at both ends thereof are connected to form a structure. The detailed configuration of the semiconductor device 100 will be described later.

[0012] <first standard cell> FIG. 2 is a schematic plan view of the first standard cell 10. FIG. 3 is an equivalent circuit diagram of the first standard cell 10 shown in FIG. 2. FIG. 4 is a schematic plan view of a first standard cell 10A having a configuration different from that of FIG. 2. FIG. 5 is an equivalent circuit diagram of the first standard cell 10A shown in FIG. 4. FIG. 6 is a schematic cross - sectional view of the first standard cell 10A shown in FIG. 5.

[0013] An electronic element is arranged in the first standard cell 10 shown in this embodiment, and a circuit that provides a determined function is configured.

[0014] As shown in FIG. 2, the first standard cell 10 has a rectangular shape with sides extending in the first direction x and the second direction y. In the semiconductor device 100, the length Ly in the second direction y of the first standard cell 10 is a determined length. The length Ly in the second direction y of the first standard cell 10 may be referred to as a reference length Ly. Also, although the length in the second direction y of the first standard cell 10 may vary depending on the circuit configuration, in this case, the length in the second direction y of the first standard cell 10 is adjusted to be an integer multiple of the reference length Ly. Note that the length in the second direction y of the second standard cell 20 is also the reference length Ly.

[0015] As shown in FIG. 2, the first standard cell 10 has a power supply line VDD and a ground line VSS. The first standard cell 10 has a PMOS transistor 11, an NMOS transistor 12, and a first active region 13. The power supply line VDD is connected to a power supply voltage terminal, and a power supply voltage is applied. The ground line VSS is connected to a ground terminal and is maintained at a ground potential.

[0016] As shown in FIG. 2, the power supply line VDD is arranged at the upper end in the second direction y of the first standard cell 10 and extends in the first direction x. The ground line VSS is arranged at the lower end in the second direction y of the first standard cell 10 and extends in the first direction x. The first active region 13 extends in the first direction x along the boundary with the N-well region 10n (to be described later) inside the P-well region 10p (to be described later) (see FIG. 6).

[0017] In addition, the length of the first standard cell in the first direction x varies depending on the circuit configuration. For example, in the first standard cell 10A shown in FIG. 4, the number of electronic elements used is smaller than that in the standard cell 10 shown in FIG. 2. Therefore, the length Lxa of the first standard cell 10A in the first direction x is shorter than the length Lx of the first standard cell 10 in the first direction x. Note that depending on the circuit configuration, regardless of the number of electronic elements used, in other words, even if the number of electronic elements is the same, the length in the first direction x may change.

[0018] Here, the circuit configuration of the first standard cell 10 will be described. Note that the configuration of the first standard cell 10A shown in FIGS. 4 and 5 is included in the configuration of the standard cell 10 shown in FIGS. 2 and 3. Therefore, first, the configuration of the first standard cell 10A shown in FIGS. 4 and 5 will be described, and then the configuration of the standard cell 10 shown in FIGS. 2 and 3 will be described.

[0019] In the first standard cell 10A shown in FIGS. 4 and 5, a circuit is configured by a PMOS transistor 11 and an NMOS transistor 12. As shown in FIG. 6, in the first standard cell 10A, the source of the PMOS transistor 11 is connected to the power supply line VDD. Also, the drain of the PMOS transistor 11 is connected to the drain of the NMOS transistor 12. The output signal OUT is output from this connection point. Also, the source of the NMOS transistor 12 is connected to the ground line VSS.

[0020] The gate electrode 111 of the PMOS transistor 11 and the gate electrode 121 of the NMOS transistor 12 are arranged above an oxide film 10t, which will be described later, and are arranged apart from each other. And the gate electrode 111 and the gate electrode 121 are connected by a jumper wire 14. That is, the first standard cell 10A constitutes an inverter INV. The input signal IN is input to the jumper wire 14.

[0021] Also, as shown in FIG. 6, in the first standard cell 10A, a P well 102 formed of a P semiconductor is formed on the upper surface of an N substrate 101 formed of an N semiconductor. Further, as shown in FIG. 6, an N well 103 formed of an N semiconductor is formed at the upper part of one side (the left side in FIG. 6) of the P well 102.

[0022] Note that an N well 103 is disposed on one side (the left side in FIG. 6) of the upper surface of the first standard cell 10A, and this region is defined as an N well region 10n. Also, a P well 102 is disposed on the other side (the right side in FIG. 6) of the upper surface of the first standard cell 10A, and this region is defined as a P well region 10p. Note that an oxide film 10t made of SiO2 or the like is formed on the upper surface of the first standard cell 10A, and contacts for contacting a diffusion layer (described later) that constitutes the sources and drains of the PMOS transistor 11 and the NMOS transistor are formed.

[0023] P diffusion layers 104 and 105 are formed on the upper surface of the N well region 10n of the first standard cell 10A, and the P diffusion layers 104 and 105 respectively constitute the source and drain of the PMOS transistor 11. Also, the portion between the P diffusion layer 104 and the P diffusion layer 105 constitutes the gate of the PMOS transistor 11.

[0024] A gate electrode 111 formed of polysilicon or the like is connected to the gate of the PMOS transistor 11. Also, an N diffusion layer 106 is formed on one side (the left side in FIG. 6) of the P diffusion layer 104 in the N well region 10n, and the N diffusion layer 106 constitutes a power supply line VDD.

[0025] N diffusion layers 107 and 108 are formed on the upper surface of the P well region 10p of the first standard cell 10A, and the N diffusion layers 107 and 108 respectively constitute the drain and source of the NMOS transistor 12. Also, the portion between the N diffusion layer 107 and the N diffusion layer 108 constitutes the gate of the NMOS transistor 12.

[0026] A gate electrode 121 formed of polysilicon or the like is connected to the gate of the NMOS transistor 12. Also, a P diffusion layer 109 is formed on the other side (the right side in FIG. 6) of the N diffusion layer 108 of the P well region 10p, and the P diffusion layer 109 constitutes the ground line VSS.

[0027] In the vicinity of the boundary between the N well region 10n and the P well region 10p, a P diffusion layer 110 extending in the first direction x along the boundary is formed. The P diffusion layer 110 constitutes the first active region 13. Note that the vicinity of the boundary can also be defined as a portion closer to the boundary than other diffusion layers formed in the P well region 10p.

[0028] In the first standard cell 10A, the first active region 13 is connected to the ground terminal and maintained at the ground potential. And the first active region 13 serves as the back gate of the NMOS transistor 12.

[0029] In this way, by forming the first active region 13, the back gate of the NMOS transistor 12 can be surely connected to the ground potential, and the potential of the P well 102 can be kept low. Thereby, the base distance of the NMOS transistor 12 can be ensured, and the occurrence of latch-up is suppressed. The first standard cell 10 has the same semiconductor configuration as the first standard cell 10A.

[0030] As shown in FIG. 3, the first standard cell 10 has a configuration in which three PMOS transistors 11 (11a, 11b, 11c) and three NMOS transistors 12 (12a, 12b, 12c) are added to the inverter INV shown in FIG. 5. The sources of the three PMOS transistors 11 are connected to the power supply line VDD, and the drains are connected to the wiring L1 connected to the input of the inverter INV.

[0031] Also, as shown in FIG. 3, the three NMOS transistors 12 (12a, 12b, 12c) have their drains and sources connected and are connected in series. The drain of the NMOS transistor 12a is connected to the wiring L1, and the source of the NMOS transistor 12c is connected to the ground line VSS.

[0032] The gate of the PMOS transistor 11a and the gate of the NMOS transistor 12a are connected by a jumper wire 14. Similarly, the gate of the PMOS transistor 11b and the gate of the NMOS transistor 12b are connected by a jumper wire 14, and the gate of the PMOS transistor 11c and the gate of the NMOS transistor 12 are connected by a jumper wire 14. The input signal IN is input to each jumper wire 14, and the first standard cell 10 has three input signals that are AND circuits.

[0033] For example, assuming that the input signal IN is a voltage signal that takes a high level or a low level, a high-level output signal OUT is output when all three input signals IN of the first standard cell 10 are at a high level. Also, a low-level output signal OUT is output when at least one of the three input signals IN is at a low level.

[0034] The first standard cells 10, 10A are not limited to the above-described configuration. For example, necessary functions can be obtained by combining PMOS transistors and NMOS transistors.

[0035] <The second standard cell 20> Figs. 7 to 9 are all schematic plan views of the second standard cell 20. The second standard cell 20 shown in Figs. 7 to 9 is all rectangular in shape, and the length in the second direction is the same as the length Ly in the second direction of the first standard cell 10. Different from the first standard cell 10, the second standard cell 20 shown in Figs. 7 to 9 does not have a power supply line VDD and a ground line VSS. Further, the second standard cell 20 has a second active region 22 formed so as to connect two different sides of the substrate 21 constituting a rectangle. The second active region 22 has conductivity.

[0036] Note that the second standard cells 20 shown in Figs. 7 to 9 are respectively referred to as the second standard cell 20A to the second standard cell 20C. Further, each of the second standard cells 20A to 20C will be described as having second active regions 22a to 22c.

[0037] The second standard cell 20A shown in Fig. 7 has a second active region 22a formed in a broken line shape. Both ends of the second active region 22a of the second standard cell 20A are formed so as to be connected to each of the adjacent sides of the substrate 21.

[0038] Note that the second standard cell 20A shown in Fig. 7 has a configuration in which the second active region 22a extends in the second direction y and the lower end portion is bent to the right, but is not limited thereto. For example, a configuration having a second active region 22a in which the lower end portion is bent to the left, or the upper end portion is bent to the right or left is also the second standard cell 20A. Further, those having different lengths of the second active region 22a in the second direction y are also regarded as the second standard cell 20A.

[0039] The second standard cell 20B shown in Fig. 8 has a second active region 22b configured in a crank shape. Both ends of the second active region 22b are formed so as to be connected to the sides at both ends in the first direction x of the substrate 21.

[0040] Note that the second standard cell 20B shown in FIG. 8 has a configuration in which the second active region 22b extends in the second direction y and has a shape in which the upper end is folded to the right and the lower end is folded to the left, but is not limited thereto. For example, a configuration having a second active region 22b with a shape in which the upper end is folded to the left and the lower end is folded to the right is also the second standard cell 20B. Further, in the second standard cell 20C shown in FIG. 9, both ends of the second active region 22c are formed so as to be connected to each side at both ends of the substrate 21 in the first direction x.

[0041] <Arrangement of the First Standard Cell 10 and the Second Standard Cell 20> As shown in FIG. 1, in the semiconductor device 100, a plurality of, here, three first standard cells 10 are arranged and connected in the first direction x. The first standard cells 10 have the same length Ly in the second direction y. In the first standard cells 10 arranged in the first direction x, the power supply lines VDD are in contact with each other, and the ground lines VSS are in contact with each other. In this state, the power supply lines VDD of the first standard cells 10 adjacent to each other in the first direction x are connected, and the ground lines VSS are connected.

[0042] Further, as shown in FIG. 1, in the semiconductor device 100, the first active regions 13 of the first standard cells 10 arranged in the first direction x are in contact with each other. In this state, the first active regions 13 of the first standard cells 10 adjacent to each other in the first direction x are connected. Note that a configuration in which the first standard cells 10 are arranged and connected in the first direction x is defined as a composite cell 30.

[0043] In the semiconductor device 100 shown in FIG. 1, composite cells 30 in which three first standard cells 10 are arranged and connected in the first direction x are arranged in two rows in the second direction y. In FIG. 1, the upper side is defined as a composite cell 301, and the lower side is defined as a composite cell 302.

[0044] In the upper composite cell 301, each first standard cell 10 is configured such that the P-well region 10p is disposed below the N-well region 10n in the second direction y. On the other hand, in the lower composite cell 302, each first standard cell 10 is configured such that the P-well region 10p is disposed above the N-well region 10n in the second direction y. By configuring in this way, the power supply line VDD of each first standard cell 10 in the upper composite cell 301 and the power supply line VDD of each first standard cell 10 in the lower composite cell 302 are adjacent in the second direction y. Note that in the semiconductor device 100, the power supply lines VDD adjacent to each other in the second direction y may be connected.

[0045] Note that the composite cells 30 may be arranged such that the ground lines VSS are adjacent in the second direction y. Also in this case, the ground lines VSS adjacent to each other in the second direction y may be connected.

[0046] At both ends of the upper composite cell 301 in the first direction x, second standard cells 20A are disposed. The ends connected to the sides aligned in the first direction x of the second active region 22a of the second standard cell 20A are adjacent to and connected to the first active regions 13 of the first standard cells 10 disposed at both ends of the upper composite cell 301 in the first direction x.

[0047] At both ends of the lower composite cell 302 in the first direction x, second standard cells 20A are disposed. The ends connected to the sides aligned in the first direction x of the second active region 22a of the second standard cell 20A are adjacent to and connected to the first active regions 13 of the first standard cells 10 disposed at both ends of the lower composite cell 302 in the first direction x.

[0048] Then, the second active region 22a of the second standard cell 20A adjacent to the upper composite cell 301 in the first direction x is configured to be connected to the lower side in the second direction y. Also, the second active region 22a of the second standard cell 20A adjacent to the lower composite cell 302 in the first direction x is configured to be connected to the upper side in the second direction y.

[0049] The second standard cells 20A arranged at both ends of the composite cells 301 and 302 in the first direction x are arranged adjacent to each other in the second direction y. Then, the second active regions 22a of the second standard cells 20A adjacent in the second direction y are adjacent to and connected to each other.

[0050] In the semiconductor device 100, the first active regions 13 of the first standard cells 10 arranged side by side in the first direction x are connected to each other, the first active region 13 and the second active region 22a are connected, and the second active regions 22a of the second standard cells 20 arranged side by side in the second direction y are connected to each other.

[0051] As shown in FIG. 1, an annular guard ring Gd is formed by the first active region 13 and the second active region 22a so as to surround each P-well region 10p of the upper composite cell 301 and each N-well region 10n of the lower composite cell 302, that is, so as to surround the PMOS transistor 11, and the breakdown voltage of the semiconductor device 100 can be increased.

[0052] The first active region 13 is connected to the ground terminal and operates as the back gate of the NMOS transistor 12 of the first standard cell 10. Therefore, the potential of the P-well 102 can be kept low. Thereby, the parasitic NPN operation in the first direction x and the second direction y can be suppressed, and the occurrence of an unexpected operation of the semiconductor device 100 can be suppressed.

[0053] <First Modified Example> FIG. 10 is a schematic plan view of a semiconductor device 100A according to the first modified example. In the semiconductor device 100A shown in FIG. 10, the shapes of the upper composite cell 301A and the guard ring Gd1 are different from those of the semiconductor device 100. Other parts of the semiconductor device 100A are the same as those of the semiconductor device 100. Therefore, the same reference numerals are given to substantially the same parts as those of the semiconductor device 100 of the semiconductor device 100A, and the detailed description of the same parts is omitted.

[0054] As shown in FIG. 10, in the semiconductor device 100A, in the upper composite cell 301A, two first standard cells 10 are arranged side by side in the first direction x and connected. Then, the upper composite cell 301A and the lower composite cell 302 are arranged such that the positions in the first direction x at the right ends coincide with each other.

[0055] At the right end in the first direction x of the upper composite cell 301A and the right end in the first direction x of the lower composite cell 302, a second standard cell 20A is arranged. Then, the second active region 22a of the second standard cell 20A is connected to the first active region 13 of the first standard cell 10. Also, the second active regions 22a of the second standard cell 20A are connected to each other.

[0056] Also, a second standard cell 20B is connected to the left end in the first direction x of the upper composite cell 301A. The second active region 22b of the second standard cell 20B is connected to the first active region 13 of the first standard cell 10 at the left end in the first direction x of the upper composite cell 301A. Also, a second standard cell 20C is arranged on the left side in the first direction x of the second standard cell 20B. The second active region 22c of the second standard cell 20C is connected to the second active region 22b of the second standard cell 20B.

[0057] Furthermore, a second standard cell 20A is arranged on the left side in the first direction x of the second standard cell 20B. One end of the second active region 22a of the second standard cell 20A is connected to the second active region 22c of the second standard cell 20C, and the other end is connected to the second active region 22a of the second standard cell 20A arranged on the left side in the first direction x of the lower composite cell 302.

[0058] In the semiconductor device 100A formed as described above, a guard ring Gd1 surrounding each P-well region 10p of the upper composite cell 301A and each N-well region 10n of the lower composite cell 302 can be formed, and the breakdown voltage of the semiconductor device 100A can be increased.

[0059] Then, the first active region 13 is connected to the ground terminal and operates as the back gate of the NMOS transistor 12 of the first standard cell 10. Therefore, the potential of the P-well 102 can be kept low. As a result, parasitic NPN operation in the first direction x and the second direction y can be suppressed, and the occurrence of unexpected operation of the semiconductor device 100A can be suppressed.

[0060] In the semiconductor device 100A configured in this way, elements can be arranged beyond the self-frame on the left side of the upper composite cell 301A. Thereby, the semiconductor device 100A can be miniaturized.

[0061] <Second Modification> FIG. 11 is a schematic plan view of a semiconductor device 100B according to the second modification. The semiconductor device 100B shown in FIG. 11 has a configuration in which the P-well region 10p, that is, the NMOS transistor 12, is surrounded by a guard ring Gd. Other configurations of the semiconductor device 100B are the same as those of the semiconductor device 100. Therefore, the semiconductor device 100B is given the same reference numerals as the semiconductor device 100, and detailed descriptions of each part are omitted.

[0062] As shown in FIG. 11, a guard ring Gd formed in the first active region 13 of the first standard cell 10 and the second active region 22 of the second standard cell 20 may be formed so as to surround the P-well region 10p. In this way, even with a configuration in which the P-well region 10p is surrounded by the guard ring Gd, it is possible to increase the breakdown voltage of the semiconductor device 100B. Also, since the potential of the P-well 102 can be lowered, latch-up can be suppressed.

[0063] <Third Modification> FIG. 12 is a schematic plan view of an example of the first standard cell 10D of the third modification. The first standard cell 10D shown in FIG. 12 has the same configuration as the first standard cell 10 shown in FIG. 2, except that the first active region is different from the first active region 13. Therefore, the same reference numerals are given to substantially the same parts as those of the first standard cell 10 of the first standard cell 10D, and detailed descriptions thereof are omitted.

[0064] The first standard cell 10D shown in FIG. 12 has a first active region 15 extending in the first direction x at the center in the second direction y. The first active region 15 is connected to the same power supply voltage terminal as the power supply line VDD and operates as the back gate of the PMOS transistor 11.

[0065] In this way, by forming the first active region 15, the back gate of the PMOS transistor 11 can be surely set to the power supply voltage. Thereby, since the base distance of the PMOS transistor 11 can be secured, the occurrence of latch-up is suppressed.

[0066] Other features are the same as those of the above-described embodiments and each modification.

[0067] <Fourth Modification> FIG. 13 is a schematic cross-sectional view of an example of the first standard cell 10E of the fourth modification. As shown in FIG. 13, in the first standard cell 10E, an N well 102e formed of an N semiconductor is formed on the upper surface of a P substrate 101e formed of a P semiconductor. Further, a P well 103e formed of a P semiconductor is formed in the N well 102e. One side (the left side in FIG. 13) of the upper surface of the first standard cell 10E is an N well region 10n. Also, the other side (the right side in FIG. 13) of the upper surface of the first standard cell 10E is a P well region 10p.

[0068] On the upper surface of the P-well region 10p of the first standard cell 10E, N-diffusion layers 104e and 105e are formed, and the N-diffusion layers 104e and 105e respectively constitute the source and drain of the NMOS transistor 12e. Also, the portion between the N-diffusion layer 104e and the N-diffusion layer 105e constitutes the gate of the NMOS transistor 12e.

[0069] To the gate of the NMOS transistor 12e, a gate electrode 121e formed of polysilicon or the like is connected. Also, on the side of the P-well region 10p opposite to the N-diffusion layer 104e and the N-diffusion layer 105e of the N-diffusion layer 104e, a P-diffusion layer 106e is formed, and the P-diffusion layer 106e constitutes the ground line VSS.

[0070] On the upper surface of the N-well region 10n of the first standard cell 10E, P-diffusion layers 107e and 108e are formed, and the P-diffusion layers 107e and 108e respectively constitute the drain and source of the PMOS transistor 11e. Also, the portion between the P-diffusion layer 107e and the P-diffusion layer 108e constitutes the gate of the PMOS transistor 11e.

[0071] To the gate of the PMOS transistor 11e, a gate electrode 111e formed of polysilicon or the like is connected. Also, on the side of the P-well region 10p opposite to the N-diffusion layer 108e and the N-diffusion layer 107e of the N-diffusion layer 108e, an N-diffusion layer 109e is formed, and the N-diffusion layer 109e constitutes the power supply line VDD.

[0072] Furthermore, in the vicinity of the boundary between the N-well region 10n and the P-well region 10p, an N-diffusion layer 110e extending in the first direction x along the boundary is formed. The N-diffusion layer 110e constitutes the first active region 13e.

[0073] In the first standard cell 10, the first active region 13e is connected to the ground terminal and is maintained at the ground potential. And the first active region 13e serves as the back gate of the NMOS transistor 12.

[0074] In this way, by forming the first active region 13e, the back gate of the NMOS transistor 12 is surely maintained at the ground potential, and the occurrence of latch-up is suppressed.

[0075] Other features are the same as those of the above-described embodiments and each example.

[0076] <Others> The above-described embodiments should be considered as illustrative in all respects and not restrictive. The technical scope of the present invention is shown not by the description of the above embodiments but by the claims, and it should be understood that all modifications belonging to the meaning and scope equivalent to the claims are included.

[0077] <Supplementary Note> The semiconductor devices (100, 100A, 100B) described above have a plurality of first standard cells (10, 10A, 10D, 10E) arranged side by side in the first direction (x). The first standard cells (10, 10D, 10E) have a P-well region (10p) having a P-well (102, 103e), and an N-well region (10n) having an N-well (103, 102e), which is arranged side by side in the second direction (y) intersecting the first direction (x) with respect to the P-well region (10p), and a first active region (13, 15, 13e) having a configuration extending in the first direction (x), which is arranged in the vicinity of the boundary with the other well region in the P-well region (10p) or the N-well region (10n). At least one of the first standard cells (10, 10A, 10D, 10E) is a functional cell. A P-channel MOS transistor (11) is arranged in the N-well region (10n). An N-channel MOS transistor (12) is arranged in the P-well region (10p). When the first active regions (13, 15) are formed in the P-well region (10p), they are composed of P-diffusion layers (110). When the first active region (13e) is formed in the N-well region (10n), it is composed of an N-diffusion layer (110e). The first active regions (13, 15, 13e) and the back gate of the P-channel MOS transistor (11) or the back gate of the N-channel MOS transistor (12) have a configuration in which they are at the same potential. The first active regions (13, 15, 13e) of the first standard cells (10, 10A, 10D, 10E) adjacent to each other in the first direction (x) have a configuration (first configuration) in which they are at the same potential.

[0078] In the semiconductor device (100, 100A, 100B) having the above first configuration, it further has a second standard cell (20, 20A, 20B) having a configuration arranged adjacent to at least one of both ends in the first direction (x) of the first standard cells (10, 10A, 10D, 10E) arranged in the first direction (x). The second standard cell (20, 20A, 20B) has a second active region (22, 22a, 22b) having a portion extending in the second direction (y). The second active regions (22, 22a, 22b) of the second standard cell (20, 20A, 20B) have a configuration (second configuration) in which they are at the same potential as the first active regions (13, 15, 13e) of the first standard cells (10, 10A, 10D, 10E) adjacent to each other in the first direction (x).

[0079] In the semiconductor device (100, 100A, 100B) having the above first or second configuration, the first active regions (13, 15) and the second active regions (22, 22a, 22b, 22c) are connected so as to surround at least one of the P-well region (10p) and the N-well region (10n) (third configuration).

[0080] In the semiconductor device (100, 100A, 100B) having any one of the first to third configurations, the first standard cell (10, 10A, 10D, 10E) is CMOS, and an electrode (111) connected to the gate of the P-channel MOS transistor (11) and an electrode (121) connected to the gate of the N-channel MOS transistor (12) are separated and electrically connected by a jumper wire (14) (a fourth configuration).

Explanation of Reference Numerals

[0081] 100, 100A, 100B Semiconductor device 101 N substrate 101e P substrate 102, 103e P well 102e, 103 N well 104, 105 P diffusion layer 106 N diffusion layer 107, 108 N diffusion layer 109 P diffusion layer 110 P diffusion layer 110e N diffusion layer 111, 121 Gate electrode 10, 10A, 10D, 10E First standard cell 10n N well region 10p P well region 11 PMOS transistor 12 NMOS transistor 13, 13e, 15 First active region 14 Jumper wire 20, 20A, 20B, 20C Second standard cell 21 Substrate 22, 22a, 22b, 22c Second active region 30 Composite cell 301, 301A Upper composite cell 302 Lower composite cell Gd Guard ring Gd1 Guard ring

Claims

1. Having a plurality of first standard cells arranged side by side in a first direction, The first standard cell is, A P-well region having a P-well configuration, An N-well region having an N-well configuration, arranged side by side in a second direction intersecting the P-well region and the first direction, Arranged near the boundary with the other well region in the P-well region or the N-well region, and having a first active region configured to extend in the first direction, At least one of the first standard cells is a functional cell, A P-channel MOS transistor is arranged in the N-well region, An N-channel MOS transistor is arranged in the P-well region, The first active region is composed of a P-diffusion layer when formed in the P-well region and an N-diffusion layer when formed in the N-well region, The first active region and the back gate of the N-channel MOS transistor or the back gate of the P-channel MOS transistor have a configuration of being at the same potential, A semiconductor device in which the first active regions of the first standard cells adjacent to each other in the first direction have a configuration of being at the same potential.

2. Further having a second standard cell having a configuration arranged adjacent to at least one of both ends of the first standard cells arranged in the first direction in the first direction, The second standard cell has a second active region having a portion extending in the second direction, The semiconductor device according to claim 1, wherein the second active region of the second standard cell has a configuration of being at the same potential as the first active region of the first standard cell adjacent to it in the first direction.

3. The semiconductor device according to claim 2, wherein the first active region and the second active region are connected so as to surround at least one of the P-well region and the N-well region.

4. The first standard cell is CMOS, The semiconductor device according to claim 1, wherein an electrode connected to the gate of the P-channel MOS transistor and an electrode connected to the gate of the N-channel MOS transistor are separated from each other and electrically connected by a jumper wire.

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