Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device in which parasitic capacitance between wiring lines or parasitic capacitance between the wiring line and a via contact can be suppressed.SOLUTION: A semiconductor device comprises a first wiring line that is provided in a first direction of a first insulation film. The first wiring lines are arranged in a second direction, and extend in a third direction. A second insulation film is provided on the first wiring lines corresponding to each of the first wiring lines. The second insulation film has a width in the second direction in a surface contacting with each of the first wiring lines, the width narrower than a width of the corresponding first wiring line. A third insulation film is provided on the first wiring lines corresponding to each of the first wiring lines, and covers both side surfaces of the second insulation film respectively. A fourth insulation film is provided on the third insulation film, and a fifth insulation film is provided on the fourth insulation film. A first contact is connected to the first wiring line by penetrating through the second through fifth insulation films. A second wiring line is provided on the first contact. The first contact is provided in the first direction of the first wiring line or the second and fourth insulation films are provided in the first direction of the first wiring line.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present embodiment relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. As the memory cell array is miniaturized, the interval between a plurality of adjacent wirings becomes narrow. Thereby, there is a risk that the parasitic capacitance between the wirings and the parasitic capacitance between the wiring and the via contact increase.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device and a method for manufacturing the same that can suppress the parasitic capacitance between wirings or the parasitic capacitance between a wiring and a via contact to a low level.

Means for Solving the Problems

[0005] The semiconductor device according to this embodiment includes a plurality of first wirings provided in a first direction with respect to a first insulating film. The plurality of first wirings are arranged in a second direction intersecting the first direction, and extend in a third direction intersecting the first and second directions. A plurality of second insulating films are respectively provided corresponding to the plurality of first wirings. The plurality of second insulating films have a width in the second direction on the surface in contact with the respective first wirings that is narrower than the width in the second direction of the plurality of first wirings corresponding thereto. A plurality of third insulating films are respectively provided corresponding to the plurality of first wirings, are arranged in the second direction, extend in the third direction, and at least cover both side surfaces of the plurality of second insulating films. A fourth insulating film is provided on the plurality of third insulating films. A fifth insulating film is provided on the fourth insulating film. The first contact penetrates through the second to fifth insulating films and is connected to any one of the plurality of first wirings. The second wiring is provided on the first contact. In the first direction of the first wiring, a first contact is provided, or at least the second and fourth insulating films are provided.

Brief Description of the Drawings

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same elements are denoted by the same reference numerals.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. One direction intersecting, for example, orthogonal to the Z direction is defined as the Y direction. One direction intersecting, for example, orthogonal to each of the Z direction and the Y direction is defined as the X direction. In this specification, the ±Z direction is an example of the first direction. The ±X direction is an example of the third direction, and the ±Y direction is an example of the second direction.

[0009] The semiconductor memory device 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded at a bonding surface B1 and are electrically connected to each other via wirings bonded at the bonding surface. FIG. 1 shows a state where the array chip 2 is provided on the CMOS chip 3.

[0010] The CMOS chip 3 includes a substrate 30, a transistor 31, a via 32, wirings 33 and 34, and an interlayer insulating film 35.

[0011] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS or PMOS transistor provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS circuit that controls the memory cell array of the array chip 2. A plurality of transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, and a column decoder. Semiconductor elements such as resistance elements and capacitance elements other than the transistor 31 may be formed on the substrate 30.

[0012] Via 32 electrically connects between transistor 31 and wiring 33, or between wiring 33 and wiring 34. Wirings 33 and 34 form a multilayer wiring structure within interlayer insulating film 35. Wiring 34 is embedded within interlayer insulating film 35 and is substantially flush with the surface of interlayer insulating film 35. Wirings 33 and 34 are electrically connected to transistor 31 and the like. For vias 32, wirings 33, and 34, metals such as copper and tungsten are used, for example. Interlayer insulating film 35 covers and protects transistor 31, via 32, wirings 33, and 34. For interlayer insulating film 35, an insulating film such as a silicon oxide film is used, for example.

[0013] Array chip 2 includes laminate 20, columnar body CL, slit ST(LI), source layer BSL, metal layer 40, contact plug CCw, contact plug 29, bonding pad 50, and interlayer insulating film 25.

[0014] Laminate 20 is provided above transistor 31 and is positioned in the Z direction with respect to substrate 30. Laminate 20 is configured by alternately laminating a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. Laminate 20 constitutes a memory cell array. For electrode film 21, a conductive metal such as tungsten is used, for example. For insulating film 22, an insulating film such as a silicon oxide film is used, for example. Insulating film 22 insulates between electrode films 21. That is, the plurality of electrode films 21 are laminated in an insulated state from each other. The number of laminations of each of electrode film 21 and insulating film 22 is arbitrary. Insulating film 22 may be, for example, a porous insulating film or an air gap.

[0015] One or more electrode films 21 at the upper and lower ends of the laminate 20 in the Z direction function as a source-side select gate SGS and a drain-side select gate SGD, respectively. The electrode film 21 between the source-side select gate SGS and the drain-side select gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The source-side select gate SGS is the gate electrode of the source-side select transistor. The drain-side select gate SGD is the gate electrode of the drain-side select transistor. The source-side select gate SGS is provided in the upper region of the laminate 20. The drain-side select gate SGD is provided in the lower region of the laminate 20. The upper region refers to the region of the laminate 20 on the side far from the CMOS chip 3 (the side close to the metal layer 40), and the lower region refers to the region of the laminate 20 on the side close to the CMOS chip 3.

[0016] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source-side select transistor and a drain-side select transistor. The structure in which the source-side select transistor, the memory cell MC, and the drain-side select transistor are connected in series is called a "memory string" or a "NAND string". The memory string is connected to the bit line BL via, for example, the via 28. The bit line BL is a wiring 23 provided below the laminate 20 and extending in the X direction (the direction of the paper surface in FIG. 1). Therefore, hereinafter, the bit line BL will also be referred to as the bit line 23.

[0017] A plurality of columnar bodies CL are provided in the laminate 20. The columnar body CL extends through the laminate 20 in the stacking direction (Z direction) of the laminate in the laminate 20, and is provided from the via 28 connected to the bit line 23 to the source layer BSL. The internal structure of the columnar body CL will be described later. In the present embodiment, it is formed in two stages in the Z direction. However, there is no problem even if the columnar body CL is in one stage. Alternatively, the columnar body CL may be formed in three or more stages.

[0018] Although not shown in FIG. 1, a plurality of slits ST (see FIG. 2) are provided in the laminate 20. The slits ST extend in the Y direction and penetrate the laminate 20 in the stacking direction (Z direction) of the laminate 20. The slits ST are filled with an insulating film such as a silicon oxide film, and the insulating film is configured in a plate shape. The slits ST electrically separate the electrode films 21 of the laminate 20. Alternatively, the inner walls of the slits ST may be coated with an insulating film such as a silicon oxide film, and a conductive material may be embedded inside the insulating film. In this case, the conductive material can also function as a source wiring reaching the source layer BSL.

[0019] A source layer BSL is provided on the laminate 20. The source layer BSL is an example of a first semiconductor layer. The source layer BSL is provided corresponding to the laminate 20. The source layer BSL has a first surface F1 and a second surface F2 opposite to the first surface F1. On the first surface F1 side of the source layer BSL, a laminate 20 (memory cell array) is provided, and on the second surface F2 side, a metal layer 40 is provided. The metal layer 40 includes a source line 41 and a power line 42. The source layer BSL is commonly connected to one ends of a plurality of columnar bodies CL, and gives a common source potential to the plurality of columnar bodies CL in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode of the memory cell array 2m. A conductive material such as doped polysilicon is used for the source layer BSL. For the metal layer 40, a metal material having a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten, is used. Note that 2s is a stepped portion of the electrode film 21 provided to connect the contact plug CCw to each electrode film 21. The stepped portion 2s will be described later with reference to FIG. 2.

[0020] On one side, above the laminate 20 and in the region where the source layer BSL is not provided, bonding pads 50 are provided. The bonding pads 50 are connected to a metal wire or the like (not shown) and receive power supply or signals from outside the semiconductor memory device 1. The bonding pads 50 are provided so as to be connected to one end in the Z direction of the contact plug 29. The bonding pads 50 are connected to the transistors 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supply supplied from the bonding pads 50 is supplied to the transistors 31. Alternatively, signals are supplied to the transistors 31 or the memory cell array 2m via the bonding pads 50.

[0021] The contact plug CCw is provided at the peripheral portion of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug CCw is electrically connected between the electrode film 21 (word line WL) and the wiring 24. The contact plug CCw is provided at the stepped portion 2s formed stepwise at the end of the laminate 20 and is electrically connected to each electrode film 21. The contact plug CCw is provided to transmit the word line voltage from the CMOS chip 3 to each electrode film 21. For the contact plug CCw, a metal such as copper or tungsten is used, for example.

[0022] The contact plug 29 is provided at the peripheral portion of the laminate 20 and extends in the Z direction through the interlayer insulating film 25. The contact plug 29 is a contact plug provided from the wiring 24 to the bonding pad 50. The contact plug 29 is formed simultaneously in the same process as the contact plug CCw connected to the word line WL.

[0023] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply the power supply voltage or signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. Metals such as copper and tungsten are used for the contact plug 29, for example. The power supply voltage is, for example, the power supply voltage VDD or a reference voltage (e.g., ground voltage) VSS lower than the power supply voltage VDD. The signal may be an external control signal or write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and bonded at the bonding surface B1. Therefore, the transistor 31 is not provided in the array chip 2. Also, the laminate 20 (memory cell array) is not provided in the CMOS chip 3. Both the transistor 31 and the laminate 20 are on the first surface F1 side of the source layer BSL. The transistor 31 is on the side opposite to the second surface F2 where the metal layer 40 is located.

[0025] Below the laminate 20, vias 28, wirings 23, and wiring 24 are provided. The wirings 23 and 24 are embedded in the interlayer insulating film 25. The wiring 24 is substantially flush with the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL or the like. Metals such as copper and tungsten are used for the vias 28, wirings 23, and wiring 24, for example. The interlayer insulating film 25 covers and protects the laminate 20, vias 28, wirings 23, and wiring 24. An insulating film such as a silicon oxide film is used for the interlayer insulating film 25, for example.

[0026] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded at the bonding surface B1, and accordingly, the wiring 24 and the wiring 34 are joined substantially flush at the bonding surface B1. Thereby, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

[0027] FIG. 2 is a schematic plan view showing the laminate 20. The laminate 20 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is provided, for example, at an end of the laminate 20. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. The slit ST(LI) is provided from the stepped portion 2s at one end of the laminate 20, through the memory cell array 2m, to the stepped portion 2s at the other end of the laminate 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST(LI) in the Z direction and extends substantially parallel to the slit ST(LI). The slit SHE electrically separates the electrode film 21 for each drain-side select gate SGD. Note that the slit ST may be a source wiring LI that is electrically connected to the source layer BSL while being electrically separated from the electrode film 21 of the laminate 20. That is, the slit ST may be a source wiring LI that is electrically separated from the electrode film 21 of the laminate 20 constituting the memory cell array and is electrically connected to the source layer BSL.

[0028] The portion of the laminate 20 sandwiched by the two slits ST shown in FIG. 2 is called a block (BLOCK). The block constitutes, for example, the minimum unit of data erasure. The slit SHE is provided within the block. The laminate 20 between the slit ST and the slit SHE is called a finger. The drain-side select gate SGD is separated for each finger. Therefore, at the time of data writing and reading, one finger within the block can be set in a selected state by the drain-side select gate SGD.

[0029] Each of FIGS. 3 and 4 is a schematic cross-sectional view illustrating a three-dimensional structure memory cell. Each of a plurality of columnar bodies CL is provided in a memory hole MH provided in a laminate 20. Each columnar body CL penetrates the laminate 20 from one end portion of the laminate 20 along the Z direction and is provided across the laminate 20 and in a source layer BSL. The plurality of columnar bodies CL each include a semiconductor body 210, a memory film 220, and a core layer 230. The columnar body CL includes a core layer 230 provided at its central portion, a semiconductor body (semiconductor member) 210 provided around the core layer 230, and a memory film 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) within the laminate 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21 and has a charge trapping portion. A plurality of columnar bodies CL each selected one by one from each finger are commonly connected to one bit line 23 via the via 28 of FIG. 1. Each of the columnar bodies CL is provided, for example, in a region of the memory cell array 2m.

[0030] As shown in FIG. 4, the shape of the memory hole MH in the X-Y plane is, for example, a circle or an ellipse. A block insulating film 221a that constitutes a part of the memory film 220 may be provided between the electrode film 21 and the insulating film 22. The block insulating film 221a is, for example, silicon oxide or metal oxide. One example of the metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22 and between the electrode film 21 and the memory film 220. The barrier film 21b is, for example, a laminated film of titanium nitride and titanium when the electrode film 21 is tungsten. The block insulating film 221a suppresses charge back tunneling from the electrode film 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the electrode film 21 and the block insulating film 221a.

[0031] The shape of the semiconductor body 210 is, for example, cylindrical with a bottom. For example, polysilicon is used for the semiconductor body 210. The semiconductor body 210 is, for example, undoped silicon. Also, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as the channel for each of the drain-side selection transistor, the memory cell MC, and the source-side selection transistor. That is, a plurality of memory cells MC have a storage region between the semiconductor body 210 and the electrode film 21 that serves as the word line WL and are stacked in the Z direction. One ends of the plurality of semiconductor bodies 210 within the same memory cell array 2m are electrically commonly connected to the source layer BSL.

[0032] The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a block insulating film 221a. For the memory film 220, portions other than the block insulating film 221a are provided between the inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is, for example, cylindrical. Each of the charge trapping film 222 and the tunnel insulating film 223 extends in the Z direction.

[0033] The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the block insulating film 221a and the charge trapping film 222. The cover insulating film 221 includes, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when replacing a sacrificial film (not shown) with the electrode film 21 (replacement process). Note that when the replacement process is not used for forming the electrode film 21, the cover insulating film 221 may be omitted.

[0034] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride and has trap sites for trapping charges in the film. Among the charge trapping film 222, the portion sandwiched between the electrode film 21 that becomes the word line WL and the semiconductor body 210 constitutes the storage region of the memory cell MC as the charge trapping portion. The threshold voltage of the memory cell MC changes according to the presence or absence of charges in the charge trapping portion, or the amount of charges trapped in the charge trapping portion. Thereby, the memory cell MC holds information.

[0035] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 contains, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when injecting electrons from the semiconductor body 210 into the charge trapping film 222 (write operation), and when injecting holes from the semiconductor body 210 into the charge trapping film 222 (erase operation), the electrons and holes respectively pass through (tunnel through) the potential barrier of the tunnel insulating film 223.

[0036] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and is insulating.

[0037] FIG. 5 is a cross-sectional view showing a configuration example of a bit line of the array chip according to the first embodiment and its periphery. Note that FIG. 5 shows a configuration that is upside down with respect to FIG. 1. Therefore, hereinafter, the -Z direction will be described as the upward direction. Further, FIG. 5 shows the structure above (-Z direction) the columnar body CL, and the illustration of the configuration below the columnar body CL is omitted.

[0038] The array chip 2 includes insulating films 25a to 25d, via contact 28a, bit line 23 (BL), insulating films 60 and 70, via contact 28b, and wiring 24.

[0039] The insulating film 25a is provided above the laminate 20 and the columnar body CL. An insulating material such as a silicon oxide film is used for the insulating film 25a, for example.

[0040] The via contact 28a is embedded in the insulating film 25a. The via contact 28a is provided so as to penetrate the insulating film 25a from the upper surface to the lower surface of the insulating film 25a in the Z direction. The via contact 28a electrically connects the semiconductor body 210 of the columnar body CL and the bit line 23. The via contact 28a includes a barrier metal 28a1 and a contact body 28a2 embedded inside the barrier metal. For the barrier metal, a conductive metal material such as a titanium film or a titanium nitride film is used, for example. For the contact body, a conductive metal material such as tungsten is used, for example.

[0041] The insulating film 25b is provided on the insulating film 25a. The insulating film 25b is provided between a plurality of adjacent bit lines 23 and between a plurality of adjacent insulating films 70. An insulating material such as a silicon oxide film is used for the insulating film 25b, for example.

[0042] The plurality of bit lines 23 are provided in the -Z direction with respect to the insulating film 25a and are embedded in the insulating film 25b. The plurality of bit lines 23 extend in the X direction on the upper surface of the insulating film 25a and are arranged in the Y direction. For the bit line 23, a conductive metal material such as tungsten or copper is used, for example.

[0043] The plurality of insulating films 60 are provided in regions on the upper surfaces of the plurality of bit lines 23 where the via contact 28b does not contact. The plurality of insulating films 60 are in contact with the upper surface F23a of the corresponding bit line 23. At the contact surface between the insulating film 60 and the bit line 23, the width W60 of the insulating film 60 in the Y direction is narrower than the width Wbl of the corresponding bit line 23 in the Y direction. A material film containing silicon and oxygen is used for the insulating film 60, and an insulating material such as a silicon nitride film is used, for example.

[0044] The plurality of insulating films 70 are provided corresponding to the regions of the plurality of bit lines 23 respectively. The insulating film 70 is provided so as to cover the upper surface and the side surface of the insulating film 60 on the bit line 23 where the via contact 28b is not provided. That is, the insulating film 70 has an inverted U shape and covers the insulating film 60. Also, the insulating film 70 is provided on the side surface of the via contact 28b between adjacent insulating films 60. The insulating film 70 is provided between the insulating film 60 and the insulating film 25c. Also, at the contact surface between the insulating film 70 and the bit line 23, the width W70 of the insulating film 70 in the Y direction is substantially the same as the width Wbl of the corresponding bit line 23 in the Y direction. A material film containing silicon and nitrogen is used for the insulating film 70, and for example, an insulating material such as a silicon oxynitride film is used. The insulating films 60 and 70 are different materials having different etching selectivities from each other. Thereby, either one of the insulating films 60 and 70 can be selectively etched. Also, the insulating film 70 is a material having a lower relative permittivity (Low-k) than the insulating film 60.

[0045] The insulating film 25d is provided on the insulating film 25c. The insulating films 25c and 25d are different materials having different etching selectivities from each other. Therefore, the insulating film 25c functions as an etching stopper when forming a contact hole in the insulating film 25d. For example, an insulating material such as a silicon nitride film is used for the insulating film 25c. For example, an insulating material such as a silicon oxide film is used for the insulating film 25d.

[0046] The via contact 28b is embedded in the insulating films 25c and 25d. Further, the via contact 28b penetrates through a part of the insulating films 60 and 70 and is connected to the bit line 23. The via contact 28b is provided so as to penetrate through the insulating films 25d, 25c, and 60 from the upper surface of the insulating film 25d to the lower surface of the insulating film 60. The via contact 28b electrically connects the wiring 24 and the bit line 23. Thereby, the wiring 24 can be electrically connected to any bit line 23 via the via contact 28b. The via contact 28b may be substantially circular, substantially elliptical, or substantially polygonal in plan view when viewed from the Z direction. Therefore, insulating films 60 and 70 are provided on the bit line 23 outside the formation region of the via contact 28b. That is, in the Z direction of the bit line 23, either a via contact 28b is provided or at least insulating films 60 and 70 are provided. The via contact 28b includes a barrier metal 28b1 and a contact body 28b2 embedded inside the barrier metal. For the barrier metal, a conductive metal material such as a titanium film or a titanium nitride film is used, for example. For the contact body, a conductive metal material such as tungsten is used, for example.

[0047] The via contact 28b is formed self-alignedly from the insulating film 25c across the insulating films 70 and 60. Therefore, the via contact 28b has a step STP at the same height as the lower surface of the insulating film 25c. Also, the width W28b1 of the via contact 28b in the X or Y direction at the same height as the lower surface of the insulating film 25c is wider than the width W28b2 of the via contact 28b in the X or Y direction at the connection surface with the bit line 23. Further, the width W28b2 is narrower than the width Wbl of the bit line 23 in the Y direction. The width W28b1 of the via contact 28b in the X or Y direction gradually decreases from the wiring 24 toward the bit line 23, and further narrows to the width W28b2 with the step STP at the lower surface of the insulating film 25c and becomes thinner. The via contact 28b with the width W28b2 has its both side surfaces sandwiched by the insulating film 70. And, in the bit line 23, the width spreads to Wbl. Thus, the via contact 28b is configured in a bottleneck shape between the insulating films 70.

[0048] The wiring 24 is provided on the via contact 28b and the insulating film 25d. The wiring 24 applies power to the semiconductor body 210 of the columnar body CL via the bit line BL. Also, the wiring 24 is electrically connected to a sense amplifier module (see FIG. 33) and transmits a signal voltage based on the data read from the memory cell MC to the sense amplifier module. For the wiring 24, a conductive metal material such as tungsten or copper is used, for example.

[0049] In the array chip 2 according to the present embodiment, insulating films 60 and 70 are provided on the bit line 23 in a region where the via contact 28b is not provided. As described above, the insulating film 70 is, for example, a silicon oxynitride film or the like and has a lower relative dielectric constant than the insulating film 60 (for example, a silicon nitride film or the like). The insulating film 60 is covered with the insulating film 70 having a low relative dielectric constant. Therefore, the parasitic capacitance PC1 between adjacent bit lines 23, the parasitic capacitance PC2 between the via contact 28b and the bit line 23, and the parasitic capacitance PC3 between the wiring 24 and the bit line 23 are reduced as compared with the case where the insulating film 70 is not provided. The parasitic capacitance PC1 between adjacent bit lines 23 is considered to be reduced by the insulating film 70 when considering the capacitance of the wrap-around from one bit line 23 to the upper surface of the other bit line 23.

[0050] By reducing the parasitic capacitance PC1 between adjacent bit lines 23, the parasitic capacitance PC2 between the via contact 28b and the bit line 23, and the parasitic capacitance PC3 between the wiring 24 and the bit line 23, the interval between the Y-direction arrays of the plurality of bit lines 23 can be narrowed. Also, the interval between the bit line 23 and the via contact 28b and the interval between the bit line 23 and the wiring 24 can be narrowed. As a result, this leads to miniaturization of the array chip 2.

[0051] Next, a method for manufacturing the array chip 2 according to the present embodiment will be described.

[0052] Figs. 6 to 13 are cross-sectional views showing an example of a method for manufacturing an array chip according to the first embodiment.

[0053] First, a structure below the insulating film 25a such as the laminate 20 and the columnar body CL is formed.

[0054] Next, as shown in Fig. 6, an insulating film (e.g., silicon oxide film) 25a is deposited on the laminate 20 and the columnar body CL. Next, a contact hole CH1 to the columnar body CL is formed using lithography technology and etching technology. Next, a barrier metal (e.g., a laminated film of titanium and titanium nitride) 28a1 is formed on the inner wall of the contact hole CH1, and a material (e.g., tungsten) of the contact body 28a2 is embedded inside the barrier metal. Thereby, the via contact 28a shown in Fig. 6 is formed so as to penetrate the insulating film 25a. The via contact 28a electrically connects to the semiconductor body 210 of any columnar body CL through the insulating film 25a.

[0055] Next, as shown in Fig. 7, a material (e.g., tungsten) of the bit line 23 is deposited on the insulating film 25a (-Z direction). A material (e.g., silicon nitride film) of the insulating film 60 is deposited on the surface F23a of the material of the bit line 23.

[0056] Next, the material of the insulating film 60 is processed using lithography technology and etching technology. Next, the material of the bit line 23 is processed using the insulating film 60 as a mask. Thereby, as shown in Fig. 8, a plurality of bit lines 23 arranged in the Y direction and extending in the X direction and a plurality of insulating films 60 are formed. The plurality of insulating films 60 are provided on the upper surface F23a of the plurality of bit lines 23, respectively. At the contact surface between the insulating film 60 and the bit line 23, the width W60a of the insulating film 60 in the Y direction is substantially equal to the width Wbl of the bit line 23 in the Y direction.

[0057] Next, as shown in FIG. 9, by oxidizing the surfaces of the plurality of insulating films 60, insulating films 70 are formed on the upper surfaces and both side surfaces of the plurality of insulating films 60, respectively. That is, the exposed surfaces (upper surface and both side surfaces) of the insulating film 60 are oxidized to become the insulating film 70. For example, when the insulating film 60 is a silicon nitride film, the insulating film 70 is a silicon oxynitride film, or a mixed film of a silicon oxide film and a silicon oxynitride film. The silicon oxide film is a material having a lower relative dielectric constant than the silicon nitride film. At this time, the width W70 of the insulating film 70 in the Y direction is substantially equal to the width Wbl of the bit line 23 in the Y direction. However, the width W60 of the insulating film 60 in the Y direction is narrower than the width Wbl of the bit line 23 in the Y direction.

[0058] Next, a material of an insulating film (for example, a silicon oxide film) 25b is deposited between the adjacent plurality of bit lines 23 and between the adjacent plurality of insulating films 70. Next, the insulating film 25b is polished using a CMP (Chemical Mechanical Polishing) method until the surface of the insulating film 70 is exposed. As a result, as shown in FIG. 10, the insulating film 25b is embedded between the adjacent plurality of bit lines 23 and between the adjacent plurality of insulating films 70.

[0059] Next, as shown in FIG. 11, an insulating film (for example, a silicon nitride film) 25c is deposited on the insulating films 25b and 70. Further, an insulating film (for example, a silicon oxide film) 25d is deposited on the insulating film 25c.

[0060] Next, the insulating film 25d is processed using lithography technology and etching technology. At this time, the insulating film 25c functions as an etching stopper. Next, the insulating film 25c is etched using the insulating film 25d as a mask. Further, due to the difference in etching selectivity between the insulating film 70 and the insulating film 25b, the insulating film 70 is self-alignedly etched with respect to the insulating film 25b. As a result, a step STP is generated. After etching the insulating film 70, the insulating film 60 is self-alignedly and selectively etched with respect to the insulating film 70. As a result, as shown in FIG. 12, a contact hole CH2 is formed in the formation region of the via contact 28b. The contact hole CH2 penetrates the insulating films 25d, 25c, 70, and 60 and reaches the upper surface F23a of the bit line 23.

[0061] Next, a barrier metal (for example, a laminated film of titanium and titanium nitride) 28b1 is formed on the inner wall of the contact hole CH2, and a material (for example, tungsten) of the contact body 28b2 is embedded inside the barrier metal 28b1. As a result, the via contact 28b shown in FIG. 13 is formed so as to penetrate the insulating films 25d, 25c, 70, and 60 and be connected to the upper surface F23a of the bit line 23. The via contact 28b is electrically connected to the semiconductor body 210 of any one of the columnar bodies CL via the bit line 23. On the other hand, in the region where the contact hole CH2 is not provided, the insulating films 25d, 25c, 60, and 70 remain on the bit line 23.

[0062] Here, in the process of forming the contact hole CH2, the insulating film 60 is self-alignedly and selectively etched. Therefore, the via contact 28b has a step STP at the same height (height in the Z direction) as the lower surface of the insulating film 25c or the upper surfaces of the insulating films 25c and 70. An insulating film 70 is provided in a cylindrical shape around the via contact 28b between the step STP and the bit line 23.

[0063] Next, as shown in FIG. 5, a wiring 24 is formed on the via contact 28b and the insulating film 25d. As a result, the configuration of the array chip 2 shown in FIG. 5 is obtained.

[0064] (Second Embodiment) FIG. 14 is a cross-sectional view showing a configuration example of bit lines of the array chip according to the second embodiment and its periphery. In the second embodiment, an insulating film 70 (for example, a silicon oxynitride film, or a mixed film of a silicon oxide film and a silicon oxynitride film) is not provided on the insulating film 60 (for example, a silicon nitride film). Therefore, in a region where the via contact 28b is not provided, the insulating film 25c covers the upper surfaces of the respective insulating films 60 and is in contact with the insulating film 70. Further, the insulating film 70 is provided on both side surfaces of the insulating film 60. Other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0065] FIG. 15 is a cross-sectional view showing an example of a method for manufacturing an array chip according to the second embodiment. The array chip 2 according to the second embodiment, after going through the steps described with reference to FIGS. 6 to 9, in the step shown in FIG. 10, when polishing the insulating film 25b by the CMP method, the insulating film 70 is over-polished until the upper surface of the insulating film 60 is exposed. Thereby, the structure shown in FIG. 15 is obtained. Thereafter, by going through the steps described with reference to FIGS. 11 to 13, the configuration of the array chip 2 shown in FIG. 14 is obtained.

[0066] (Third Embodiment) FIG. 16 is a cross-sectional view showing a configuration example of bit lines of the array chip according to the third embodiment and its periphery. In the third embodiment, an air gap AG is provided between a plurality of adjacent bit lines 23. The upper end Etop of the air gap AG is below (+Z direction) the upper surface F23a of the bit line 23. Further, the lower end Ebtm of the air gap AG is below the lower surface F23b of the bit line 23.

[0067] The air gap AG has a lower relative permittivity than the insulating film 25b. Therefore, the parasitic capacitance PC1 between adjacent bit lines 23 can be further reduced. Since the lower end Ebtm of the air gap AG is lower than the lower surface F23b of the bit line 23, the parasitic capacitance PC1 between adjacent bit lines 23 can be further reduced. Further, the upper end Etop of the air gap AG is lower than the upper surface F23a of the bit line 23. This is to prevent the material of the via contact 28b from entering the air gap AG in the process of forming the via contact 28b, as will be described later.

[0068] Other configurations of the third embodiment may be the same as those of the first embodiment. Therefore, the third embodiment can obtain the same effects as the first embodiment. Also, the third embodiment may be combined with the second embodiment.

[0069] Next, a method for manufacturing the array chip 2 according to the third embodiment will be described.

[0070] FIGS. 17 to 22 are cross-sectional views showing an example of a method for manufacturing an array chip according to the third embodiment.

[0071] After the steps described with reference to FIGS. 6 to 9, as shown in FIG. 17, a sacrificial film 101 (e.g., polysilicon) is deposited between adjacent bit lines 23 and between adjacent insulating films 70. Note that in the step described with reference to FIG. 8, when the bit line 23 is processed, the insulating film 25a between adjacent bit lines 23 is damaged by overetching. Therefore, the lower end Ebtm of the sacrificial film 101 is below the lower surface F23b of the bit line 23 (in the +Z direction).

[0072] Next, as shown in FIG. 18, the sacrificial film 101 is etched back so that the upper surface F101a of the sacrificial film 101 is below the upper surface F23a of the bit line 23 (in the +Z direction).

[0073] Next, as shown in FIG. 19, a cap film (e.g., silicon oxide film) 102 is formed so as to cover the insulating film 70 and the sacrificial film 101.

[0074] Next, as shown in FIG. 20, the sacrificial film 101 is selectively etched to form an air gap AG between the cap film 102 and the bit line 23. At this time, the upper end Etop of the air gap AG is located below the upper surface F23a of the bit line 23, and the lower end Ebtm is located below the lower surface F23b of the bit line 23.

[0075] Next, as shown in FIG. 21, the material of the insulating film 25b is deposited on the cap film 102. At this time, the cap film 102 suppresses the material of the insulating film 25b from entering the air gap AG and maintains the air gap AG.

[0076] Next, as shown in FIG. 22, the insulating film 25b is polished using the CMP method until the insulating film 70 is exposed.

[0077] Thereafter, through the steps described with reference to FIGS. 11 to 13, the configuration of the array chip 2 shown in FIG. 16 is obtained.

[0078] In addition, when the upper end Etop of the air gap AG is higher (in the -Z direction) than the upper surface F23a of the bit line 23, when the contact hole CH2 in FIG. 12 is formed, the contact hole CH2 may penetrate the insulating film 70 and communicate with the air gap AG. In this case, in the process of forming the via contact 28b, the material of the via contact 28b may enter the air gap AG.

[0079] Therefore, in order to suppress the material of via contact 28b from entering the air gap AG, in the third embodiment, the upper end Etop of the air gap AG is positioned at a position lower than the upper surface F23a of the bit line 23 in the +Z direction. The position of the upper end Etop of the air gap AG is adjusted at the height position of the upper surface F101a of the sacrificial film 101 shown in FIG. 18. By making the upper surface F101a of the sacrificial film 101 lower than the upper surface F23a of the bit line 23, the position of the upper end Etop of the air gap AG is made lower than the upper surface F23a of the bit line 23. Thereby, the material of the via contact 28b can be suppressed from entering the air gap AG.

[0080] (Fourth Embodiment) FIG. 23 is a cross-sectional view showing a configuration example of a bit line of an array chip according to the fourth embodiment and its surroundings. In the fourth embodiment, in the region where the via contact 28b contacts the bit line 23, the insulating film 70 is not provided on the side surface in the Y direction of the via contact 28b. The via contact 28b is provided over the entire Y direction on the bit line 23.

[0081] Other configurations of the fourth embodiment may be the same as those of the first embodiment. Therefore, the fourth embodiment can obtain the same effects as the first embodiment. Also, the fourth embodiment may be combined with the second or third embodiment. In this case, the fourth embodiment can obtain the same effects as the second or third embodiment.

[0082] In the method for manufacturing a semiconductor device according to the fourth embodiment, in the step of forming the contact hole CH2 shown in FIG. 12, the insulating film 70 below the contact hole CH2 may be removed together with the insulating film 60. Other steps of the fourth embodiment may be the same as the manufacturing steps of the first embodiment.

[0083] (Fifth Embodiment) Figs. 24A to 31B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the fifth embodiment. Figs. 24A, 25A, 26A, 27A, and 31A show the step of forming via contact 28b in the peripheral region PD of Fig. 1. Figs. 24B, 25B, 26B, 27B, Figs. 28 to 30, and 31B show the step of forming via contact 28b in the laminate 20 of Fig. 1.

[0084] Through the steps described with reference to Fig. 6, via contact 28a is formed in insulating film 25a. Next, as shown in Figs. 24A and 24B, a material (e.g., tungsten) of bit line 23 is deposited on insulating film 25a (-Z direction). A material (e.g., silicon nitride film) of insulating film 60 is deposited on the surface F23a of the material of bit line 23.

[0085] Next, using lithography technology and etching technology, the material of insulating film 60 is processed. Next, using insulating film 60 as a mask, the material of bit line 23 is processed. As a result, as shown in Figs. 25A and 25B, a plurality of bit lines 23 and a plurality of insulating films 60 are formed. At this time, in the region of laminate 20 in Fig. 25B, the width between bit lines 23 is narrower and the bit lines 23 are in a dense state compared to the peripheral region PD in Fig. 25A. Therefore, in the region of laminate 20, more of insulating film 60 as a hard mask is etched compared to peripheral region PD. As a result, the height of the upper surface of insulating film 60 in the region of laminate 20 becomes lower compared to peripheral region PD. Also, the grooves between bit lines 23 are formed to a position lower than the bottom surface of bit lines 23.

[0086] Next, as shown in Figs. 26A and 26B, by oxidizing the surfaces of the plurality of insulating films 60, insulating films 70 are formed on the upper surfaces and both side surfaces of the plurality of insulating films 60, respectively. That is, the exposed surfaces (upper surface and both side surfaces) of insulating film 60 are oxidized to become insulating films 70. For example, when insulating film 60 is a silicon nitride film, insulating film 70 becomes a silicon oxynitride film or a mixed film of a silicon oxide film and a silicon oxynitride film.

[0087] Next, a material of the insulating film 25b (e.g., silicon oxide film) is deposited in the grooves between the bit lines 23 and on the insulating film 70. Next, as shown in FIGS. 26A and 26B, the material of the insulating film 25b is etched back until the upper surface of the insulating film 25b is lower than the upper surface of the insulating film 70 and higher than the bottom surface of the insulating film 60 or the insulating film 70. As a result, the upper surface of the insulating film 25b between the bit lines 23 is at a position lower than the upper surface of the insulating film 70, and the upper surfaces of the insulating films 25b and 70 are uneven as shown in FIG. 26B.

[0088] Next, as shown in FIGS. 27A and 27B, an insulating film 25c (e.g., silicon nitride film) and an insulating film 25d (e.g., silicon oxide film) are deposited on the insulating film 70 and the insulating film 25b. Here, the upper surfaces of the insulating films 25c and 25d are formed in an uneven shape following the unevenness of the upper surfaces of the insulating film 70 and the insulating film 25b. That is, the upper surfaces of the insulating film 70 and the insulating film 25b are not planarized.

[0089] Next, as shown in FIG. 28, the upper surface of the insulating film 25d is planarized using a CMP method or the like. Next, a photoresist PR is formed on the insulating film 25d using lithography technology. The photoresist PR is processed so as to expose the insulating film 25d in the formation region of the via contact 28b.

[0090] Next, as shown in FIG. 29, the insulating film 25d (e.g., silicon oxide film) is anisotropically etched using the photoresist PR as a mask. At this time, the insulating film 25c (e.g., silicon nitride film) functions as an etch stopper.

[0091] Here, the unevenness of the upper surfaces of the insulating films 25b and 70 is also transferred to the upper surface of the insulating film 25c thereon. The insulating film 25c on the bit line 23 protrudes more than other upper surface regions of the insulating film 25c. Therefore, as shown in FIG. 29, when etching the insulating film 25d, if the etching is stopped when the insulating film 25c is exposed, the insulating film 25c on the bit line 23 can be selectively exposed.

[0092] Next, as shown in FIG. 30, using the photoresist PR and the insulating film 25d as masks, the insulating films 25c, 70, and 60 are anisotropically etched. As a result, the contact hole CH2 penetrates the insulating films 25d, 25c, 70, and 60 and reaches the bit line 23. At this time, the insulating film 25c above the bit line 23 is selectively exposed. Therefore, the contact hole CH2 selectively etches the insulating film 25c above the bit line 23, and further selectively etches the insulating films 60 and 70 on the bit line 23. The insulating film 25c in the recess above the insulating film 25b between the bit lines 23 is covered with the insulating film 25d, so it remains almost unetched. As a result, even if the position of the photoresist PR is slightly deviated, the contact hole CH2 can be formed from the convex portion of the insulating film 25c on the bit line 23 to the upper part of the bit line 23. This leads to a reduction in the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23.

[0093] Next, through the process described with reference to FIG. 13, as shown in FIGS. 31A and 31B, a via contact 28b is formed in the contact hole CH2 so as to penetrate the insulating films 25d, 25c, 70, and 60 and be connected to the upper surface F23a of the bit line 23. The via contact 28b is electrically connected to the semiconductor body 210 of any one of the columnar bodies CL via the bit line 23. On the other hand, in the region where the contact hole CH2 is not provided, the insulating films 25d, 25c, 60, and 70 remain on the bit line 23.

[0094] FIG. 32 is a cross-sectional view showing a comparative example in the case where the upper surface of the insulating film 25c is flat. In this comparative example, the upper surfaces of the insulating film 25b and the insulating film 60 are substantially flush with each other, and accordingly, the upper surface of the insulating film 25c is flat. In this case, when the position of the photoresist PR is displaced, the contact hole CH2 is formed in the insulating films 25d and 25c according to the pattern of the photoresist PR, and is selectively formed on the bit line 23 in the insulating film 60. Since the insulating film 25c is etched according to the pattern of the photoresist PR, as shown in FIG. 32, the distance between the via contact 28b and the adjacent bit line 23 is short. Therefore, the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23 is relatively large.

[0095] On the other hand, in the semiconductor device according to the fifth embodiment, the unevenness on the upper surfaces of the insulating films 25b and 60 is also transferred to the upper surface of the insulating film 25c thereabove. The insulating film 25c on the bit line 23 protrudes more than the other upper surface regions of the insulating film 25c, and the upper surface of the insulating film 25c has an uneven shape. Thereby, as shown in FIG. 29, when etching the insulating film 25d, if the etching is stopped when the insulating film 25c is exposed, the insulating film 25c on the bit line 23 can be selectively exposed. As a result, the distance between the via contact 28b and the adjacent bit line 23 can be made longer than that in the comparative example. Therefore, the parasitic capacitance PC2 between the via contact 28b and the adjacent bit line 23 according to the fifth embodiment can be reduced as compared with that in the comparative example.

[0096] In addition, in the fifth embodiment, since the allowable range of the displacement of the photoresist PR is widened, alignment in the lithography process becomes easy.

[0097] The other configurations and processes of the fifth embodiment may be the same as those of any of the other embodiments. Thereby, the fifth embodiment can also obtain the same effects as those of any of the other embodiments.

[0098] The above embodiments are applied to the bit lines of the memory, but can also be applied to wirings other than the bit lines.

[0099] Also, the array chip 2 according to the above embodiment can be applied to the following semiconductor memory device.

[0100] FIG. 33 is a block diagram showing a configuration example of a semiconductor memory device to which any one of the array chips of the above embodiment is applied. The semiconductor memory device 1 is, for example, a memory 100a such as a NAND-type flash memory capable of storing data non-volatilely, and is controlled by an external memory controller 1002. Communication between the memory 100a and the memory controller 1002 conforms to, for example, the NAND interface standard.

[0101] As shown in FIG. 33, the memory 100a includes, for example, a memory cell array MCA, a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

[0102] The memory cell array MCA includes a plurality of blocks BLK(0) to BLK(n) (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cells capable of storing data non-volatilely, and is used, for example, as a data erasure unit. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array MCA. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array MCA will be described later.

[0103] The command register 1011 holds a command CMD received by the memory 100a from the memory controller 1002. The command CMD includes, for example, an instruction to cause the sequencer 1013 to execute a read operation, a write operation, an erase operation, etc.

[0104] The address register 1012 holds the address information ADD received by the memory 100a from the memory controller 1002. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used for selecting a block BLK, a word line, and a bit line, respectively.

[0105] The sequencer 1013 controls the operation of the entire memory 100a. For example, based on the command CMD held in the command register 1011, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, etc., to execute read operations, write operations, erase operations, etc.

[0106] The driver module 1014 generates the voltages used in read operations, write operations, erase operations, etc. Then, based on the page address PA held in the address register 1012, for example, the driver module 1014 applies the generated voltage to the signal line corresponding to the selected word line.

[0107] The row decoder module 1015 includes a plurality of row decoders. The row decoder selects one block BLK in the corresponding memory cell array MCA based on the block address BA held in the address register 1012. Then, the row decoder transfers the voltage applied to the signal line corresponding to the selected word line, for example, to the selected word line in the selected block BLK.

[0108] In a write operation, the sense amplifier module 1016 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 1002. Also, in a read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 1002 as the read data DAT.

[0109] The memory 100a and the memory controller 1002 described above may constitute one semiconductor memory device by their combination. Examples of such a semiconductor memory device include a memory card such as an SDTM card and an SSD (solid state drive).

[0110] FIG. 34 is a circuit diagram showing an example of the circuit configuration of the memory cell array MCA. One block BLK out of a plurality of blocks BLK included in the memory cell array MCA is extracted. As shown in FIG. 34, the block BLK includes a plurality of string units SU(0) to SU(k) (k is an integer of 1 or more).

[0111] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL(1) to BL(m) (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cells MC(0) to MC(15), and selection transistors ST(1) and ST(2). The memory cell MC includes a control gate and a charge trapping layer, and holds data non-volatilely. Each of the selection transistors ST(1) and ST(2) is used for selection of the string unit SU during various operations.

[0112] In each NAND string NS, the memory cells MC(0) to MC(15) are connected in series. The drain of the selection transistor ST(1) is connected to the associated bit line BL, and the source of the selection transistor ST(1) is connected to one end of the memory cells MC(0) to MC(15) connected in series. The drain of the selection transistor ST(2) is connected to the other end of the memory cells MC(0) to MC(15) connected in series. The source of the selection transistor ST(2) is connected to the source line SL.

[0113] In the same block BLK, the control gates of memory cells MC(0) to MC(15) are commonly connected to word lines WL(0) to WL(7), respectively. The gates of respective selection transistors ST(1) in string units SU(0) to SU(k) are commonly connected to selection gate lines SGD(0) to SGD(k), respectively. The gate of selection transistor ST(2) is commonly connected to selection gate line SGS.

[0114] In the circuit configuration of the memory cell array MCA described above, bit line BL is shared by NAND strings NS to which the same column address is assigned in each string unit SU. Source line SL is shared, for example, among a plurality of blocks BLK.

[0115] A set of a plurality of memory cells MC connected to a common word line WL within one string unit SU is referred to as, for example, a cell unit CU. For example, the storage capacity of cell unit CU including memory cells MC each storing 1-bit data is defined as "1-page data". Cell unit CU can have a storage capacity of 2-page data or more according to the number of bits of data stored in memory cell MC.

[0116] Note that the memory cell array MCA included in memory 100a according to this embodiment is not limited to the circuit configuration described above. For example, the number of memory cells MC, selection transistors ST(1) and ST(2) included in each NAND string NS can be designed to be arbitrary numbers respectively. The number of string units SU included in each block BLK can be designed to be an arbitrary number.

[0117] The above embodiment is applicable not only to the array chip of the memory but also to the wiring and via contacts of logic circuits such as CMOS chips.

[0118] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, as well as in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0119] 2 Array chip 3 CMOS chip 25a~25d Insulating film 28a, 28b Via contact 23 Bit line 60, 70 Insulating film 24 Wiring AG Air gap

Claims

1. A plurality of first wirings provided in a first direction with respect to a first insulating film, arranged in a second direction intersecting the first direction, and extending in a third direction intersecting the first and second directions; A plurality of second insulating films respectively provided corresponding to the plurality of first wirings, wherein the width in the second direction on the surface in contact with each of the first wirings is narrower than the width in the second direction of the corresponding plurality of first wirings; A plurality of third insulating films respectively provided corresponding to the plurality of first wirings, arranged in the second direction, extending in the third direction, and at least covering both side surfaces of the plurality of second insulating films; A fourth insulating film provided on the plurality of third insulating films; A fifth insulating film provided on the fourth insulating film; A first contact penetrating the second to fifth insulating films and connected to any one of the plurality of first wirings; A second wiring provided on the first contact, and A semiconductor device in which the first contact is provided in the first direction of the first wiring, or at least the second and fourth insulating films are provided.

2. The first, third, and fifth insulating films contain silicon and oxygen, The semiconductor device according to claim 1, wherein the second and fourth insulating films contain silicon and nitrogen.

3. The semiconductor device according to claim 1 or claim 2, wherein the plurality of third insulating films cover the upper surfaces of the plurality of second insulating films and are provided between the second insulating film and the fourth insulating film.

4. The semiconductor device according to claim 1 or claim 2, wherein the fourth insulating film covers the upper surfaces of the plurality of second insulating films and is in contact with the plurality of second insulating films.

5. The semiconductor device according to claim 1 or claim 2, further comprising a sixth insulating film provided between the plurality of first wirings.

6. The semiconductor device according to claim 1 or claim 2, wherein an air gap is provided between the plurality of first wirings.

7. The semiconductor device according to claim 6, wherein the upper end of the air gap is below the upper surface of the first wiring.

8. The semiconductor device according to claim 6 or claim 7, wherein the air gap is below the lower surface of the first wiring.

9. The semiconductor device according to claim 1 or claim 2, wherein the first contact has a step at the same height as the lower surface of the fourth insulating film.

10. The semiconductor device according to claim 1, wherein the upper surface of the fourth insulating film has an uneven shape so as to protrude above the first wiring.

11. The semiconductor device according to claim 5, wherein the upper surface of the second insulating film protrudes more than the upper surface of the sixth insulating film.

12. Deposit the material of the first wiring and the material of the second insulating film in a first direction on the first insulating film, Process the material of the first wiring and the material of the second insulating film to form a plurality of first wirings and a plurality of second insulating films arranged in a second direction intersecting the first direction and extending in a third direction intersecting the first and second directions, By oxidizing the surfaces of the plurality of second insulating films, a plurality of third insulating films are formed on at least both side surfaces of the plurality of second insulating films, respectively, Form a fourth insulating film on the plurality of third insulating films, Form a fifth insulating film on the fourth insulating film, Form a first contact that penetrates the second to fifth insulating films and is connected to any one of the plurality of first wirings. In a region where the first contact is not provided in the first direction of the first wiring, at least the second and third insulating films remain, A method for manufacturing a semiconductor device, comprising forming a second wiring on the first contact.

13. After forming the plurality of first wirings and the plurality of third insulating films, form a sixth insulating film between adjacent ones of the plurality of first wirings to a position lower than the second or third insulating film, and make the second or third insulating film protrude more than the sixth insulating film, Deposit the fourth insulating film on the third and sixth insulating films, and the upper surface of the fourth insulating film is uneven following the unevenness of the third and sixth insulating films, The manufacturing method according to claim 12, wherein the fifth insulating film and the first contact are formed without flattening the upper surface of the fourth insulating film.

Images