Semiconductor device

Abstract

To provide a high-performance semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate 10 having a plurality of trenches 20 provided along a first direction; FP electrodes 21 including recessed portions 21a and thinned portions 21b alternately arranged in the first direction and provided in the trenches 20; an oxide film 23 provided on the FP electrodes 21; and gate electrodes 22 formed on the oxide film 23 and arranged in the respective recessed portions 21a. In adjacent trenches 20, the gate electrodes 22 are arranged with an offset in the first direction.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device such as a MOS transistor provided with a field plate electrode.

Background Art

[0002] Patent Document 1 discloses a trench gate type MOSFET (Metal-oxide-semiconductor field-effect transistor). This MOSFET includes a source electrode provided on a semiconductor substrate and a drain electrode provided on the back side of the substrate. Further, the MOSFET includes a gate electrode extending in the trench longitudinal direction. In the embodiment, the MOSFET has a trench field plate structure in which an embedded electrode is formed below the gate electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such semiconductor devices as MOS transistors, further high performance is desired.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, recesses and spaced portions alternately arranged in the first direction, a field plate electrode provided in the trenches, an oxide film provided on the field plate electrode, and gate electrodes formed on the oxide film and disposed in respective ones of the recesses. In adjacent ones of the trenches, the gate electrodes are arranged with a shift in the first direction.

Effect of the Invention

[0007] The present disclosure can provide a high-performance semiconductor device.

Brief Description of the Drawings

[0008]

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Mode for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description of these drawings. Also, the same elements are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0010] Embodiment 1 The MOS transistor according to this embodiment is a trench gate MOSFET having a trench formed in a semiconductor substrate. For example, the MOS transistor becomes a vertical power device. The configuration of the MOS transistor will be described with reference to FIGS. 1 to 3. FIG. 1 is an XY plan view schematically showing the configuration of the MOS transistor 100. FIG. 2 is an XZ cross-sectional view schematically showing the II-II cross-section of FIG. 1. FIG. 3 is a YZ cross-sectional view schematically showing the III-III cross-section of FIG. 1.

[0011] In the following figures, for clarity of explanation, an XYZ three-dimensional orthogonal coordinate system is shown. Specifically, the thickness direction (depth direction) of the semiconductor substrate 10 is taken as the Z direction, and the plane orthogonal to the Z direction is taken as the XY plane. In the XY plane, the X direction is the longitudinal direction (depth direction) of the trench 20, and the Y direction is the short-side direction (width direction) of the trench 20. The X direction and the Y direction are orthogonal. Note that the +Z side surface of the semiconductor substrate 10 is taken as the front surface, and the -Z side surface is taken as the back surface.

[0012] The MOS transistor 100 is a power device having, for example, a vertical MOSFET structure. The MOS transistor 100 includes a semiconductor substrate 10, trenches 20, FP electrodes 21, gate electrodes 22, sources 34, gate contacts 42, source contacts 35, FP contacts 41, drains 37, insulating films 43, etc. Although not shown in the figure, a pattern of upper-layer wiring connected to each contact is formed on the insulating film 43. The upper-layer wiring is formed, for example, by a pattern of a metal film such as Al.

[0013] For example, the semiconductor substrate 10 is a silicon substrate, and a drain 37 is provided on the back side. On the drain 37, an N + layer 12 and an N - drift layer 14 and a p-type channel layer 16 are provided.

[0014] As shown in FIG. 1, a plurality of trenches 20 are formed in the semiconductor substrate 10. In FIG. 1, only two trenches 20 are shown, but the number of trenches 20 is not particularly limited. Actually, a plurality of trenches 20 are arranged side by side in the Y direction. Specifically, the two trenches 20 shown in FIG. 1 are repeatedly arranged side by side. By changing the depth direction length of the trench 20 and the number of trenches (chip area), the on-resistance Ron of the MOS transistor 100 can be changed.

[0015] As described above, each trench 20 is formed along the X direction. Also, a plurality of trenches 20 are arranged side by side in the Y direction with a gap therebetween. As shown in FIG. 3, a source 34 and a back gate 32 are arranged between two adjacent trenches 20. The source 34 is arranged on the p-type channel layer 16.

[0016] Inside the trench 20, a gate electrode 22, a field plate electrode (hereinafter referred to as FP electrode) 21, and an oxide film 23 are provided. The FP electrode 21 and the gate electrode 22 are formed of, for example, a polysilicon film. The oxide film 23 is a silicon oxide film (SiO2 film) or the like. The oxide film 23 becomes a gate insulating film 26 around the gate electrode 22.

[0017] The FP electrode 21 is disposed below the gate electrode 22. An oxide film 23 is interposed between the FP electrode 21 and the gate electrode 22. In the Z direction, the FP electrode 21 is disposed between the drain 37 and the gate electrode 22. An insulating film 43 is formed on the upper surfaces of the gate electrode 22 and the FP electrode 21. The insulating film 43 is an oxide film formed on the later-described raised portion 21c. For example, the insulating film 43 is a silicon oxide film formed so as to cover the gate electrode 22, the FP electrode 21, the source 34, and the like. The insulating film 43 is formed on the surface of the semiconductor substrate 10.

[0018] The FP electrode 21 includes a recess 21a, a scribing portion 21b, and a raised portion 21c. At the end portion in the X direction, the FP electrode 21 has a structure that rises to the surface side. At the end portion in the X direction, the raised portion of the FP electrode 21 that rises is the raised portion 21c. The recess 21a is a portion that is recessed below the FP electrode 21. A plurality of recesses 21a are provided side by side in the X direction in one FP electrode 21. The gate electrode 22 is formed in each recess 21a.

[0019] The portion between two adjacent recesses 21a is the scribing portion 21b. The scribing portion 21b is a region where the gate electrode 22 is not formed. A plurality of scribing portions 21b are arranged side by side along the X direction in one trench 20. In one trench 20, the recesses 21a and the scribing portions 21b are alternately arranged in the X direction. In one trench 20, a plurality of gate electrodes 22 are provided spaced apart from each other in the X direction.

[0020] The lifting portion 21c and the thinning portion 21b are approximately at the same height. As shown in FIGS. 1 and 2, let the size of the recess 21a in the X direction be Wg. Also, in the X direction, let the size of the thinning portion 21b be Wfp. The thinning portion 21b is the portion where the FP electrode 21 rises.

[0021] An FP contact 41 is provided on the FP electrode 21. The FP contact 41 is disposed on the lifting portion 21c. The FP contact 41 is formed of a metal film or the like and penetrates the insulating film 43. Thereby, the FP contact 41 is connected to the FP electrode 21 and can supply a potential to the FP electrode 21.

[0022] A gate contact 42 is provided on the recess 21a. That is, the gate contact 42 is formed on the gate electrode 22. The gate contact 42 is formed of a metal film or the like and penetrates the insulating film 43. The gate contact 42 is connected to the gate electrode 22 and supplies a gate potential to the gate electrode 22.

[0023] A plurality of recesses 21a and a plurality of gate electrodes 22 are provided in one trench 20. The gate electrodes 22 are formed in the respective recesses 21a. Therefore, the plurality of gate electrodes 22 are arranged in a row along the X direction. In the X direction, the plurality of gate electrodes 22 are arranged at intervals from each other.

[0024] Furthermore, as shown in FIG. 1, in two adjacent trenches 20, the gate electrodes 22 are arranged shifted in the X direction. For clarity of explanation, in FIG. 1, the gate electrode 22 of one of the two trenches 20 is also denoted as the gate electrode 22a, and the gate electrode 22 of the other trench 20 is also denoted as the gate electrode 22b. The X-direction position of the gate electrode 22a of one trench 20 is different from the X-direction position of the gate electrode 22b of the other trench 20.

[0025] In the X direction, a region where the gate electrode 22b is provided is arranged in a region where the gate electrode 22a is not provided. Similarly, in the X direction, a region where the gate electrode 22a is provided is arranged in a region where the gate electrode 22b is not provided. Further, the ends of the gate electrode 22a and the ends of the gate electrode 22b in the X direction are arranged so as to overlap.

[0026] Sources 34 are provided on both sides of the trench 20 in the Y direction. That is, in the Y direction, a source 34 is formed between two trenches 20. The source 34 is arranged on the channel layer 16. Also, a back gate 32 is formed under the source 34. As shown in FIG. 1, source contacts 35 are provided on both sides of the trench 20 in the Y direction. That is, a source contact 35 is arranged between two adjacent trenches 20. The source contact 35 penetrates the insulating film 43. The source contact 35 is connected to the source 34 to supply a source potential.

[0027] Thus, the FP electrode 21 of the MOS transistor 100 includes recesses 21a and spaced portions 21b alternately arranged in the X direction. And a gate electrode 22 is formed in the recess 21a. The FP electrode 21 is provided with a spaced portion 21b for spacing the gate electrodes 22. That is, no gate electrode 22 is formed in the spaced portion 21b. By doing so, a high-performance MOS transistor 100 can be realized. For example, since the area of the gate electrode 22 can be reduced, the capacitance Cgd between the gate and the drain can be reduced. Therefore, the switching loss can be reduced.

[0028] The performance metrics of the MOS transistor 100 will be described below. As performance metrics of a power device, not only the specific on-resistance Rsp but also Ron*Qgd considering switching losses is important. Here, Ron is the on-resistance between the drain and source, and Qgd is the amount of charge accumulated between the gate and drain. Since Qgd requires switching measurement, it is substituted with Ron*Cgd as a simpler metric. Also, by changing the chip area, the values of Ron and Cgd can be changed, but Ron*Cgd per unit area of the device becomes almost a constant value. Note that the chip area changes by changing the number of trenches 20 and the size of the trenches 20 in the X direction.

[0029] In Embodiment 1, by providing the thinning portion 21b in the trench 20, the gate electrode 22 is thinned. Since the area of the gate electrode 22 can be reduced, the capacitances Cgd and Cgs can be reduced. Here, Cgs is the capacitance between the gate and source. For example, since the capacitances Cgd and Cgs are proportional to Wg, the capacitances Cgd and Cgs can be reduced by reducing Wg. That is, by increasing Wfp, the capacitances Cgd and Cgs can be reduced.

[0030] On the other hand, as the gate area is reduced, the specific on-resistance Rsp also increases. The specific on-resistance Rsp is a value corresponding to the channel resistance Rch, the drift resistance Rdr, and the substrate resistance Rsub. For example, the specific on-resistance is approximately equal to the sum (Rch + Rdr + Rsub) of the channel resistance Rch, the drift resistance Rdr, and the substrate resistance Rsub. Here, the channel resistance Rch changes according to Wg, but the drift resistance Rdr and the substrate resistance Rsub do not depend on Wg. Therefore, by optimizing the repetition period (Wg + Wfp), the total switching loss represented by Rsp*Cgd*Cgs can be reduced. The optimal pitch can be adjusted according to the operating frequency of the device. And by shifting the repetition period between adjacent trenches, it is also possible to suppress an increase in the specific on-resistance Rsp.

[0031] It is preferable to reduce the size of Wfp. For example, in the X direction, the sizes of the concave portion 21a and the thinning portion 21b can be set to sizes that do not cause problems due to process processing constraints. For example, it can be in the range from sub-microns to about several micrometers. When it is desired to reduce the capacitance, it is preferable to reduce Wg. When it is not desired to increase the on-resistance, it is preferable to increase Wg.

[0032] Embodiment 2 The configuration of the MOS transistor 100 according to Embodiment 2 will be described with reference to FIGS. 4 to 6. FIG. 4 is an XY plan view schematically showing the configuration of the MOS transistor 100. FIG. 5 is an XZ cross-sectional view schematically showing the V-V cross section of FIG. 4. FIG. 6 is a YZ cross-sectional view schematically showing the VI-VI cross section of FIG. 4.

[0033] In Embodiment 2, a gate connection electrode 27 for connecting a plurality of gate electrodes 22 is added. Since the basic configuration other than the gate connection electrode 27 is the same as that in Embodiment 1, the description will be appropriately omitted.

[0034] The gate connection electrode 27 is formed on the gate electrode 22. The gate connection electrode 27 is formed along the Y direction. The gate connection electrode 27 is formed above the trench 20. In a plan view in the XY plane, the gate connection electrode 27 is formed across a plurality of concave portions 21a and a plurality of thinning portions 21b. The gate connection electrode 27 is disposed above the lifting portion 21c. The gate connection electrode 27 is a polysilicon film integrally formed with a plurality of gate electrodes 22.

[0035] The gate connection electrode 27 is formed at a position higher than the surface of the semiconductor substrate 10. The gate connection electrode 27 is covered with an insulating film 43. In the thinning portion 21b, the gate connection electrode 27 is disposed on the FP electrode 21. In the thinning portion 21b, an oxide film 23 is interposed between the gate connection electrode 27 and the FP electrode 21.

[0036] Thus, since the gate connection electrode 27 connects a plurality of gate electrodes 22, the number of gate contacts 42 can be reduced. For example, in Embodiment 1, a gate contact 42 is provided for each gate electrode 22, whereas in Embodiment 2, one gate contact 42 may be provided in one trench 20. That is, it is not necessary to route the upper layer wiring around the gate contact 42 of each gate electrode 22.

[0037] By doing so, the pattern of the upper layer wiring connected to the contact can be simplified. For example, the wiring resistance Rs of the upper layer wiring of the source Al can be suppressed from increasing. Furthermore, the parasitic capacitance Cgs between the gate and the source in the upper layer wiring Al can be suppressed from increasing. Therefore, a higher-performance MOS transistor 100 can be realized.

[0038] To form the gate connection electrode 27 shown in Embodiment 2, one additional photomask may be added to Embodiment 1. That is, the etching process of the gate polysilicon film may be changed from a full-surface etch-back to a photoresist etch.

[0039] Embodiment 3 The configuration of the MOS transistor 100 according to Embodiment 3 will be described with reference to FIGS. 7 to 9. FIG. 7 is an XY plan view schematically showing the configuration of the MOS transistor 100. FIG. 8 is an XZ cross-sectional view schematically showing the VIII-VIII cross-section of FIG. 7. FIG. 9 is a YZ cross-sectional view schematically showing the IX-IX cross-section of FIG. 7.

[0040] In Embodiment 3, the configuration of the gate connection electrode 27 is different from that in Embodiment 2. Since the basic configurations other than the gate connection electrode 27 overlap with those in Embodiments 1 and 2, the description will be omitted as appropriate.

[0041] In Embodiment 3, the gate connection electrode 27 is formed at a height lower than the surface of the semiconductor substrate 10. Specifically, the gate connection electrode 27 is formed at the same height as the lifting portion 21c. As shown in FIG. 8, the FP electrodes 21 are formed in three stages. The thinned portion 21b is lower than the lifting portion 21c and higher than the recessed portion 21a. That is, the thinned portion 21b is at a height between the recessed portion 21a and the lifting portion 21c. And the gate connection electrode 27 is formed in the thinned portion 21b. The gate connection electrode 27 is a polysilicon film integrally formed with the gate electrode 22. The gate connection electrode 27 is disposed in the trench 20.

[0042] And the gate connection electrode 27 connects the gate electrode 22 provided in the adjacent recessed portion 21a. Further, the gate connection electrode 27 is formed in a region shallower than the channel depth (CH depth). Therefore, the gate connection electrode 27 does not operate in MOS mode. That is, in the thinned portion 21b, the longitudinal current along the channel does not flow. Compared with Embodiment 1, the Cgs reduction effect is small, but for Cgd, a reduction effect of the same degree can be obtained.

[0043] With this configuration, it is possible to prevent a short circuit between the gate and the source. Specifically, misalignment may occur in the mask in the photolithography process. When misalignment occurs in the Y direction, in the Y direction, the distance between the gate connection electrode 27 and the source contact 35 (see the broken line in FIG. 6) becomes short. For this reason, there is a risk that the gate and the source may be short-circuited.

[0044] In this embodiment, the gate connection electrode 27 is formed at a height lower than the surface of the semiconductor substrate 10. Therefore, it is possible to prevent a short circuit between the gate and the source caused by misalignment. That is, it is possible to prevent contact between the source contact and the gate electrode caused by misalignment of the mask.

[0045] In order to adopt the configuration of Embodiment 3, one additional mask may be used in the etching process for the polysilicon film that becomes the FP electrode 21. That is, by using two masks, namely, the mask for forming the thinning portion 21b and the mask for forming the concave portion, the FP electrode 21 can be configured in three layers as shown in FIG. 8.

[0046] Modification Example 1 The configuration of Modification Example 1 of Embodiment 3 will be described with reference to FIG. 10. FIG. 10 is a YZ cross-sectional view schematically showing the configuration of the MOS transistor. In Modification Example 1, the height of the thinning portion 21b is formed to be the same as the height of the pulling-up portion 21c. Therefore, the XZ cross-section has the same configuration as FIG. 2. And in the thinning portion 21b, as shown in FIG. 10, gate connection electrodes 27 are formed on both sides of the FP electrode 21 in the Y direction.

[0047] The gate connection electrodes 27 are formed at a height lower than the surface of the semiconductor substrate 10. The gate connection electrodes 27 are formed in a region shallower than the channel depth.

[0048] Even in such a configuration, the same effects as described above can be obtained. It is possible to prevent a short circuit between the gate and the source caused by misalignment. Also, a reduction effect of the capacitance Cgd comparable to that of Embodiment 1 can be obtained.

[0049] The manufacturing process of the MOS transistor 100 of Modification Example 1 of Embodiment 3 will be described with reference to FIG. 11. FIG. 11 is a perspective view showing the configuration of the trench 20 and shows the cross-section of the trench 20 in each process.

[0050] First, in the FP deposition process, a polysilicon film 102 that becomes the FP electrode is formed in the trench 20. Specifically, in the trench 20, a silicon oxide film 101 is formed on the surface of the semiconductor substrate 10. The polysilicon film 102 is formed on the silicon oxide film 101. The polysilicon film 102 is formed so as to protrude from the trench 20.

[0051] Next, in the etching process, the silicon oxide film 101 and the polysilicon film 102 are etched. As a result, the FP electrode 21 and the oxide film 23 are formed. In this process, the surface of the semiconductor substrate 10 is also etched. Here, a mask may be added to provide a step on the polysilicon film 102. Further, by making the etching of the silicon oxide film 101 an isotropic etching, the boundary portion of the step can be made smooth. After oxidizing the surface of the FP electrode 21, the gate electrode 22 is formed (gate deposition process). That is, the gate electrode 22 is formed by depositing a polysilicon film on the oxide film 23. Thereafter, by forming an oxide film on the surface, the trench 20 is completed.

[0052] FIG. 12 is a graph showing the characteristics of the MOS transistor 100. FIG. 12 is a graph showing the verification results in TCAD (Technology Computer Aided Design) considering only the cell portion of the MOS transistor 100 of Embodiment 3. The horizontal axis of FIG. 12 represents the on-resistance Ron, and the vertical axis represents the capacitance Cgd between the gate and the drain.

[0053] In a configuration where the thinning portion 21b is not provided, the on-resistance Ron and the capacitance Cgd between the gate and the drain are in a trade-off relationship. Therefore, since Ron*Cg shown in FIG. 12 is constant, the verification results fall on the straight line of the broken line. On the other hand, in the present embodiment, by adjusting Wg and Wfp to change the cell area, it is possible to reduce Cdg while suppressing an increase in Ron compared to the Ron, Cdg trade-off.

[0054] Note that in the MOS transistor according to the above embodiment, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region), etc. may be inverted. Therefore, when one conductivity type of n-type and p-type is defined as the first conductivity type and the other conductivity type is defined as the second conductivity type, the first conductivity type can be p-type and the second conductivity type can be n-type, or conversely, the first conductivity type can be n-type and the second conductivity type can be p-type.

[0055] The invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Signs

[0056] 100 MOS transistor 10 semiconductor substrate 12 N + layer 14 N - drift layer 16 channel layer 20 trench 21 FP electrode 21a recess 21b thinning portion 21c lifting portion 22 gate electrode 23 oxide film 32 back gate 34 source 35 source contact 37 drain 41 FP contact 42 gate contact 101 silicon oxide film 102 polysilicon film

Claims

1. A semiconductor substrate having a plurality of trenches provided along a first direction, a recess and a spaced portion alternately arranged in the first direction, a field plate electrode provided in the trench, an oxide film provided on the field plate electrode, a gate electrode formed on the oxide film and disposed in each of the recesses, and a semiconductor device in which the gate electrodes are displaced in the first direction in adjacent trenches.

2. The semiconductor device according to claim 1, wherein the field plate electrode has a raised portion that rises to the surface side of the semiconductor substrate at a terminal end in the first direction.

3. The semiconductor device according to claim 2, further comprising a gate connection electrode provided to connect the gate electrodes disposed in a plurality of the recesses in one trench.

4. The spaced portion is formed lower than the raised portion, the gate connection electrode is formed in a region shallower than a channel depth in the trench, and the semiconductor device according to claim 3, wherein the gate connection electrode is formed in the spaced portion so as to connect the gate electrodes provided in adjacent recesses.

5. The semiconductor device according to claim 4, wherein the gate electrodes of adjacent trenches are formed such that ends thereof overlap in the first direction.

6. The spaced portion is formed at the same height as the raised portion, the gate connection electrode is formed in a region shallower than a channel depth in the trench, and the semiconductor device according to claim 3, wherein the gate connection electrode is disposed on both sides of the field plate electrode in a second direction orthogonal to the first direction in a plan view.

7. The semiconductor device according to claim 6, wherein the gate electrodes of adjacent trenches are formed such that ends thereof overlap in the first direction.

8. The gate connection electrode is formed at a position higher than the surface of the semiconductor substrate, and in a plan view, the gate connection electrode is provided along the first direction so as to be formed across a plurality of the recesses.

9. The semiconductor device according to claim 8, wherein the gate electrodes of adjacent trenches are formed such that ends thereof overlap in the first direction.

10. The semiconductor device according to claim 1, wherein in the trench, a plurality of the gate electrodes are provided to be spaced apart from each other in a first direction.

11. The semiconductor device according to claim 10, wherein the gate electrodes of adjacent trenches are formed such that ends thereof overlap in the first direction.

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