Silicon carbide epitaxial substrate

Abstract

To provide a high-quality silicon carbide epitaxial substrate equipped with a silicon carbide epitaxial layer having less defects.SOLUTION: A silicon carbide epitaxial substrate 10 comprises a silicon carbide substrate 20 having a first surface 20a, and a silicon carbide epitaxial layer 30 positioned on the first surface, where the first surface is a (000-1) C surface; lamination defect density confirmed by a photoluminescence image on an upper face 30a of the silicon carbide epitaxial layer is less than 1.2 cm-2; a proportion of the lamination defect density to the basal surface dislocation density on the first surface of the silicon carbide substrate is less than 0.05%; and the basal surface dislocation density on the first surface of the silicon carbide substrate is less than 3000 cm-2.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This application relates to a silicon carbide epitaxial substrate.

Background Art

[0002] Silicon carbide (SiC) semiconductors have a breakdown electric field strength, an electron saturation drift velocity, and a thermal conductivity that are greater than those of silicon semiconductors. For this reason, silicon carbide semiconductors can realize power devices that can operate at higher temperatures, higher speeds, and with larger currents than conventional silicon devices, and are attracting attention as semiconductors that realize switching elements for driving motors used in electric vehicles, hybrid cars, etc. with high efficiency.

[0003] Even for silicon carbide semiconductors with the same chemical composition, there are a plurality of polytypes in which the arrangement of carbon atoms and silicon atoms in the stacking direction (<0001> direction) is different. Furthermore, since the internal energy difference between these polytypes is small, different polytypes are likely to be generated in a single crystal, and the generated different polytypes become dislocations and stacking faults (SF, Stacking Fault). Generally, silicon carbide substrates contain more such dislocations and stacking faults than silicon substrates, etc. For this reason, when manufacturing semiconductor devices such as switching elements using silicon carbide semiconductors, a silicon carbide epitaxial layer with few such defects is formed on the silicon carbide substrate, and the main structure of the semiconductor device is formed in the silicon carbide epitaxial layer.

[0004] However, dislocations and stacking faults are extended defects, and dislocations and stacking faults generated near the surface of the silicon carbide substrate propagate to the silicon carbide epitaxial layer during epitaxial growth, easily degrading the crystal quality of the silicon carbide epitaxial layer. For this reason, the development of technologies for improving the crystal quality of the silicon carbide substrate itself and for forming a high-quality silicon carbide epitaxial layer is important for the widespread use of silicon carbide semiconductor devices.

[0005] Stacking faults are planar defects and are typical defects formed in silicon carbide epitaxial layers. Also, when a bipolar device using a silicon carbide semiconductor contains basal plane dislocations (abbreviated as BPDs), when the bipolar device is biased in the forward direction, the basal plane dislocations expand and stacking faults are formed. Since stacking faults have a high resistance, as the stacking faults increase, the internal resistance of the device also increases, and as a result, heat generation due to power loss in the device increases, which may cause the device to break down. Such a change in the characteristics of the device is known as the bipolar degradation phenomenon (Non-Patent Document 1). Therefore, from the viewpoint of the long-term reliability of electronic devices, it is necessary to suppress the generation of basal plane dislocations in the silicon carbide epitaxial growth film and also suppress the generation of stacking faults that become high-resistance layers.

[0006] Linear surface defects appear on the surface of the silicon carbide epitaxial layer. The surface linear defects may be accompanied by stacking faults, and it is also preferable to suppress the generation of linear surface defects in the epitaxial growth film.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] This application provides a silicon carbide epitaxial substrate having a silicon carbide epitaxial layer with few defects.

Means for Solving the Problems

[0010] A silicon carbide epitaxial substrate according to an embodiment of the present disclosure includes a silicon carbide substrate having a first surface and a silicon carbide epitaxial layer located on the first surface. The first surface is a (000-1)C plane, and on the upper surface of the silicon carbide epitaxial layer, the linear surface defect density is less than 1.0 cm -2 and the stacking defect density is less than 1.2 cm -2 less than.

[0011] The linear surface defect density may be less than 0.5 cm -2 less than.

[0012] The linear surface defect density may be less than 0.35 cm -2 less than.

[0013] The stacking defect density may be less than 1.0 cm -2 less than.

[0014] The stacking defect density may be less than 0.35 cm -2 less than.

[0015] The basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 3000 cm -2 less than.

[0016] The basal plane dislocation density on the first surface of the silicon carbide substrate may be 2000 cm-2 It may be less than that.

[0017] The ratio of the linear surface defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 0.04%.

[0018] The ratio of the stacking defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate may be less than 0.05%.

[0019] The first surface may have an off-angle of 4° or less.

[0020] The surface roughness Ra of the first surface may be 1 nm or less.

[0021] A method for manufacturing a silicon carbide epitaxial substrate according to an embodiment of the present disclosure includes a step of preparing a silicon carbide substrate having a first surface that is a (000-1)C plane, holding the silicon carbide substrate in a growth chamber, introducing a gas containing carbon and silicon into the growth chamber at a ratio of a C / Si ratio of 1 or more and 1.6 or less, and growing a silicon carbide epitaxial layer on the first surface.

[0022] The basal plane dislocation density on the first surface of the silicon carbide substrate is 3000 cm -2 It may be less than that.

[0023] The basal plane dislocation density on the first surface of the silicon carbide substrate is 2000 cm -2 It may be less than that.

[0024] The first surface may have an off-angle of 4° or less.

[0025] The surface roughness Ra of the first surface may be 1 nm or less.

Advantages of the Invention

[0026] According to the embodiment of the present disclosure, a silicon carbide epitaxial substrate including a silicon carbide epitaxial layer with few defects can be provided.

Brief Description of the Drawings

[0027]

Figure 1

Figure 2

Figure 3

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Figure 9

Embodiments for Carrying Out the Invention

[0028] (Structure of Silicon Carbide Epitaxial Substrate 10) FIG. 1 is a schematic cross-sectional view of a silicon carbide epitaxial substrate 10 according to the present embodiment. The silicon carbide epitaxial substrate 10 includes a silicon carbide substrate 20 and a silicon carbide epitaxial layer 30.

[0029] The silicon carbide substrate 20 has a first surface 20a and a second surface 20b located on the side opposite to the first surface 20a, and a silicon carbide epitaxial layer 30 is located on the first surface 20a. The silicon carbide substrate 20 is composed of a single crystal of silicon carbide. The polytype is preferably 4H. There is no particular limitation on the size of the silicon carbide substrate 20. However, from the viewpoint of mass productivity of semiconductor devices manufactured using the silicon carbide epitaxial substrate 10, the silicon carbide substrate 20 preferably has a diameter of 100 mm or more, and more preferably has a diameter of 150 mm. The silicon carbide substrate 20 has a thickness determined according to the diameter according to the standard. For example, when the diameter is 100 mm or 150 mm, the thickness of the silicon carbide substrate 20 is 350 μm ± 25 μm or 500 μm ± 25 μm.

[0030] FIG. 2 is a schematic diagram showing the crystal orientation of the silicon carbide substrate used in the silicon carbide epitaxial substrate of the present embodiment. The first surface 20a has the following surface orientation.

[0031]

Number

[0032] Here, C means carbon, indicating that the outermost surface of the first surface 20a is a carbon surface where carbon is exposed.

[0033] Hereinafter, for the sake of simplicity of description in the specification, it is denoted as (000-1)C plane. On the other hand, the second surface 20b is a (0001)Si plane, and the outermost surface of the second surface 20b is a silicon plane where silicon is exposed.

[0034] It is known that a silicon carbide substrate has a carbon surface and a silicon surface. Conventionally, a silicon carbide epitaxial layer is formed on the silicon surface of a silicon carbide substrate. This is because it is easier to control the growth and doping when growing a silicon carbide epitaxial layer on the silicon surface. Therefore, when there is no mention in patent documents and non-patent documents as to whether the upper surface of a silicon carbide substrate is a carbon surface or a silicon surface, it is considered that the silicon surface of the silicon carbide substrate is being used.

[0035] The inventor of the present application has studied in detail a technique for suppressing linear surface defects and stacking defects, which are major defects in silicon carbide semiconductors. As a result, it has been found that by epitaxially growing a silicon carbide epitaxial layer on the carbon surface, it is possible to suppress linear surface defects and stacking defects, as described below.

[0036] The silicon carbide substrate 20 is preferably an off-substrate. FIG. 2 is a diagram schematically showing a cross section of the silicon carbide substrate 20. The silicon carbide substrate 20 is preferably an off-substrate having an off-angle θ. Specifically, it is preferable that the first surface 20a, or the normal line 20n of the first surface 20a, is inclined by θ from the [000-1] direction to the <1120> direction. The off-angle θ is preferably 0.5° or more and 8° or less, and more preferably 0.5° or more and 5° or less.

[0037] The characteristics of the first surface 20a of the silicon carbide substrate 20 will be described in detail. The first surface 20a is preferably subjected to CMP (chemical mechanical polishing). Specifically, it is preferable that the first surface 20a is polished by CMP until the surface roughness Ra of the first surface 20a becomes 1 nm or less. More preferably, Ra of the first surface 20a is 0.2 nm or less. Ra can be measured, for example, by a white light interference microscope. For example, it is a value obtained by measuring three locations on the first surface 20a over a length of 100 μm and obtaining the average. Ideally, Ra can also be 0 nm, but in reality, Ra does not become 0 nm. Therefore, the lower limit value of the preferable range of Ra is greater than 0.

[0038] Further, the BPD density on the first surface 20a is 3000 pieces / cm 2 or less (3000 cm -2 or less), preferably 2000 cm -2 or less, more preferably 1000 cm -2 or less. The BPD density can be measured, for example, by etching the first surface 20a with molten KOH and counting the number of BPDs that appear as etch pits using an optical microscope. Similar to Ra, the lower limit of the preferred range of the BPD density is greater than 0 pieces / cm -2 greater.

[0039] The silicon carbide epitaxial layer 30 is formed by epitaxial growth on the first surface 20a of the silicon carbide substrate 20. The thickness of the silicon carbide epitaxial layer 30 can be arbitrarily set according to the performance required for the semiconductor device fabricated using the silicon carbide epitaxial substrate 10. For example, the thickness of the silicon carbide epitaxial layer 30 is about 1 μm or more and 100 μm or less.

[0040] On the upper surface 30a of the silicon carbide epitaxial layer 30, the linear surface defect density is preferably less than 1.0 cm -2 less. The linear surface defect density is more preferably less than 0.5 cm -2 less, even more preferably less than 0.35 cm -2 less, and even more preferably less than 0.1 cm -2 less. Also, on the upper surface 30a of the silicon carbide epitaxial layer 30, the stacking defect density is preferably less than 1.2 cm -2 less. The stacking defect density is more preferably less than 1.0 cm -2 less, even more preferably less than 0.35 cm -2 less, and even more preferably less than 0.1 cm -2 less. Similar to Ra, the lower limit of the preferred range of the linear surface defect density and the stacking defect density is greater than 0 cm 2 greater.

[0041] In this embodiment, when the upper surface 30a of the silicon carbide epitaxial layer 30 is viewed from the perpendicular direction, the linear surface defect has irregularities with respect to the upper surface 30a and has an elongated linear shape. The longitudinal direction (the extending direction) of the linear surface defect includes those that coincide with the step flow growth direction (the direction of the off-angle), those that are inclined by about ±5° to 60° with respect to the step flow growth direction, and those that extend in two directions in a V shape with respect to the step flow growth direction. In this embodiment, the linear surface defect starts from a defect or a scratch on the first surface 20a of the silicon carbide substrate 20. For this reason, the length L in the longitudinal direction of the linear surface defect depends on the thickness d of the silicon carbide epitaxial layer 30 and the off-angle θ of the silicon carbide substrate 20, and there is a relationship of L = d / tanθ. The linear surface defect is also called a carrot defect.

[0042] The linear surface defect density can be measured, for example, by a wafer inspection device / review device capable of acquiring a differential interference optical microscope image. Such a wafer inspection device / review device can acquire the position and number of regions of luminance change that appear linearly in the acquired differential interference optical microscope image, and calculate the density of the linear surface defects.

[0043] The stacking defect is a planar defect. It starts from a defect or a scratch on the first surface 20a of the silicon carbide substrate 20 or from a defect inside the silicon carbide epitaxial layer 30, and spreads and extends in a triangular shape toward the upper surface 30a of the silicon carbide epitaxial layer 30 and reaches the upper surface 30a. Most of the stacking defects are located within the silicon carbide epitaxial layer 30. The stacking defect density can be measured, for example, by a wafer inspection device / review device equipped with an excitation light source of 355 nm and a near-ultraviolet filter and capable of acquiring a photoluminescence image. Such a wafer inspection device / review device can acquire the position and number of regions of triangular luminance change in the acquired photoluminescence image, and calculate the density of the stacking defects.

[0044] (Method for manufacturing a silicon carbide epitaxial substrate 10) Hereinafter, a method for manufacturing the silicon carbide epitaxial substrate 10 of the present embodiment will be described. First, a silicon carbide substrate 20 is prepared. The silicon carbide substrate 20 has the first surface 20a with the above-described plane orientation and off-angle. Further, the first surface 20a is prepared to have a surface roughness Ra of 1 nm or less by CMP. It is preferable that the value of the surface roughness Ra is smaller. For this reason, for example, a commercially available silicon carbide substrate 20 may be obtained, and further CMP may be performed on the first surface 20a. For example, CMP may be performed on the first surface 20a using the method described in Japanese Patent No. 6295969. Further, in addition to the step of performing CMP, a step of wet etching the first surface 20a and a step of oxidizing the first surface 20a with a gas may be performed, and these three steps may be appropriately combined and performed two or more times.

[0045] Next, a silicon carbide epitaxial layer 30 is formed. The forming method is not limited as long as it is a device capable of epitaxially growing the silicon carbide epitaxial layer 30. From the viewpoint of forming a silicon carbide epitaxial layer 30 having uniform characteristics on a large-diameter silicon carbide substrate 20, it is preferable to form the silicon carbide epitaxial layer 30 using a CVD apparatus using a chemical vapor deposition method.

[0046] For example, the silicon carbide substrate 20 is introduced into the growth chamber of the CVD apparatus and placed on a holder with the first surface 20a which is the (000-1)C plane facing upward. The silicon carbide substrate 20 is heated to a temperature of 1500 ° C or higher and 1800 ° C or lower, and a carrier gas, a gas serving as a carbon source, a gas serving as a silicon source, and a gas serving as a dopant are introduced into the growth chamber to grow the silicon carbide epitaxial layer 30. For example, hydrogen (H2) or the like can be used as the carrier gas. For the gas serving as the carbon source in the source gas, propane (C3H8) or the like can be used. Further, for the gas serving as the silicon source in the source gas, silane (SiH4) or the like can be used. For the gas serving as the dopant, nitrogen (N2) or the like can be used. Before growing the silicon carbide epitaxial layer 30, only the carrier gas may be introduced into the growth chamber to clean the first surface 20a of the silicon carbide substrate 20.

[0047] The ratio C / Si of carbon in the gas serving as the carbon source to be introduced to silicon in the gas serving as the silicon source is preferably 1 or more. Specifically, C / Si is preferably 1 or more and 1.6 or less. As will be described later, when C / Si exceeds 1.6, the linear surface defect density on the first surface 20a of the growing silicon carbide epitaxial layer 30 increases. Further, as described in the non-patent document "Current Status of SiC High-Speed Epitaxial Growth Technology by Chemical Vapor Deposition (J. Vac. Soc. Jpn., Vol. 54, No. 6, 2011)", when C / Si is less than 1 and silane (SiH4) is supplied in an excessive state, Si droplets in which Si agglomerates on the surface of the epitaxial layer are generated during the epitaxial growth process. Since defects caused by Si droplets occur, it is not preferable.

[0048] The pressure in the growth chamber during the growth of the silicon carbide epitaxial layer 30 is preferably 10 kPa or more and 50 kPa or less.

[0049] As will be described in detail in the following examples, according to the method for manufacturing the silicon carbide epitaxial substrate 10 of the present embodiment, by growing the silicon carbide epitaxial layer 30 on the (000-1)C plane of the silicon carbide substrate 20, starting from linear surface defects, stacking defects or scratches on the first surface 20a of the silicon carbide substrate 20, generation of linear surface defects and stacking defects in the silicon carbide epitaxial layer 30 can be suppressed. In particular, the stacking defect density can be reduced. Further, when growing the silicon carbide epitaxial layer 30, by setting C / Si in the source gas to 1 or more and 1.6 or less, the linear surface defect density in the silicon carbide epitaxial layer 30 can be particularly reduced. C / Si is more preferably 1.5 or less, further preferably 1.4 or less, and still further preferably 1.3 or less. Furthermore, by performing CMP on the first surface 20a which is the (000-1)C plane and making the surface roughness Ra of the first surface 20a 1 nm or less, propagation of linear surface defects and stacking defects from the silicon carbide substrate 20 to the silicon carbide epitaxial layer 30 can be suppressed.

[0050] (Example) <Preparation of Sample> Hereinafter, a silicon carbide epitaxial substrate 10 was fabricated using the manufacturing method of the silicon carbide epitaxial substrate of the present embodiment, and the results of measuring the linear surface defect density and the stacking defect density will be described.

[0051] (Examples 1 to 6) A 150-mm-diameter silicon carbide substrate 20 with the first surface 20a being the (000-1)C plane and the off-angle θ being 4° was prepared. The first surface 20a of the silicon carbide substrate 20 was subjected to CMP until the surface roughness Ra became 1 nm or less. The CMP was performed using a slurry containing colloidal silica as a main component and an oxidizing agent added thereto and a polishing pad. Thereafter, a silicon carbide epitaxial layer 30 was grown on the first surface 20a of the silicon carbide substrate 20. The growth temperature was set at 1600°C, the growth rate was 40 μm / h, and the pressure in the growth chamber during growth was set at 30 kPa. As shown in Table 1, C / Si in the source gas was set to 1.25 or 1.4. Hydrogen was used as the carrier gas, propane and silane were used as the source gases, and nitrogen was used as the dopant source. Each of Examples 1 to 6 was fabricated using one silicon carbide substrate 20.

[0052] (Comparative Examples 1 to 3) The C / Si in the source gas was set to 1.7, and other conditions were the same as those in Examples 1 to 6 to fabricate a silicon carbide epitaxial substrate of Comparative Example 1.

[0053] A silicon carbide substrate having a surface roughness Ra of about 10 nm without CMP on the first surface was prepared, and other conditions were the same as those in Examples 3 to 5 to fabricate a silicon carbide epitaxial substrate of Comparative Example 2.

[0054] A silicon carbide substrate having the first surface being the (0001)Si plane was prepared, and other conditions were the same as those in Examples 3 to 5 to fabricate a silicon carbide epitaxial substrate of Comparative Example 3.

[0055] Reference Example 1 and 2 were each fabricated using one silicon carbide substrate, and Reference Example 3 was fabricated using 33 silicon carbide substrates of various grades.

[0056] <Measurement> For the basal plane dislocation density on the first surface of the silicon carbide substrate, the value disclosed by the substrate manufacturer was referred to. The linear surface defect density on the upper surface of the silicon carbide epitaxial layer of the fabricated silicon carbide epitaxial substrate was measured. The apparatus and measurement conditions used for the measurement are as follows. The measurement was performed excluding the region within 3 mm from the outer periphery of the substrate. Name of measurement apparatus: SICA88 manufactured by Lasertec Corporation Measurement conditions: Optical inspection using a light source wavelength of 532 nm

[0057] The obtained differential interference contrast optical microscope images were analyzed using the image analysis software attached to the apparatus. Since the linear surface defects have unevenness with respect to the surface, they appear with different brightness on the image compared to the normal crystal part which is flat. An example of the differential interference contrast optical microscope image of the linear surface defects is shown in Fig. 7. The total number of linear surface defects parallel to the step flow growth direction, linear surface defects extending obliquely with respect to the step flow growth direction, and V-shaped linear surface defects extending so as to open with respect to the step flow growth direction was defined as the number of occurrences of the linear surface defects.

[0058] The stacking defect density on the upper surface of the silicon carbide epitaxial layer of the fabricated silicon carbide epitaxial substrate was measured. The apparatus and measurement conditions used for the measurement are as follows. The measurement was performed excluding the region within 3 mm from the outer periphery of the substrate. Name of measurement apparatus: Candela CS920 manufactured by KLA TENCOR Measurement conditions: Photoluminescence (PL) inspection using an excitation light wavelength of 355 nm. Near-ultraviolet and visible light filters were used for the filter.

[0059] Fig. 8 shows the PL image of the stacking defects using a near-ultraviolet filter. Fig. 9 shows the PL image of the stacking defects using a visible light filter.

[0060] <Results and Discussion> Here, as an index of the crystal quality grade of the silicon carbide substrate, the basal plane dislocation density on the first surface of the silicon carbide substrate was used. Table 1 shows the basal plane dislocation density on the first surface of the silicon carbide substrates of Examples 1 to 6 and Comparative Examples 1 to 3, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer. Further, FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking defect density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking defect density to the basal plane dislocation density.

[0061]

Table 1

[0062] From the comparison between Examples 1 to 6 and Comparative Examples 1 and 3, it can be seen that the stacking defect density and the linear surface defect density on the upper surface of the silicon carbide epitaxial layer formed on the (000-1)C plane are significantly smaller than the stacking defect density and the linear surface defect density on the upper surface of the silicon carbide epitaxial layer formed on the (0001)Si plane. In particular, it can be seen that the stacking defect density is suppressed to less than 1.2 cm in Examples 1 to 6, and the propagation of the basal plane dislocations on the first surface of the silicon carbide substrate to the silicon carbide epitaxial layer to form stacking defects is effectively suppressed. In Examples 1, 4, and 6, the linear defect density is suppressed to 0.16 cm or less. Further, in Examples 1, 3, 4, and 6, the stacking defect density is suppressed to 0.24 cm or less. According to the study by the inventor, by performing CMP described in Japanese Patent No. 6295969 and a polishing method combined with oxidation and etching, and using a silicon carbide substrate having a basal plane dislocation density of 500 cm or less, the linear defect density can be reduced to 0.1 cm or less. -2 Here, as an index of the crystal quality grade of the silicon carbide substrate, the basal plane dislocation density on the first surface of the silicon carbide substrate was used. Table 1 shows the basal plane dislocation density on the first surface of the silicon carbide substrates of Examples 1 to 6 and Comparative Examples 1 to 3, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer. Further, FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking defect density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking defect density to the basal plane dislocation density. -2 Here, as an index of the crystal quality grade of the silicon carbide substrate, the basal plane dislocation density on the first surface of the silicon carbide substrate was used. Table 1 shows the basal plane dislocation density on the first surface of the silicon carbide substrates of Examples 1 to 6 and Comparative Examples 1 to 3, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer. Further, FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking defect density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking defect density to the basal plane dislocation density. -2 Here, as an index of the crystal quality grade of the silicon carbide substrate, the basal plane dislocation density on the first surface of the silicon carbide substrate was used. Table 1 shows the basal plane dislocation density on the first surface of the silicon carbide substrates of Examples 1 to 6 and Comparative Examples 1 to 3, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer. Further, FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking defect density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking defect density to the basal plane dislocation density. -2 Here, as an index of the crystal quality grade of the silicon carbide substrate, the basal plane dislocation density on the first surface of the silicon carbide substrate was used. Table 1 shows the basal plane dislocation density on the first surface of the silicon carbide substrates of Examples 1 to 6 and Comparative Examples 1 to 3, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer. Further, FIG. 3 shows the relationship between the basal plane dislocation density and the linear surface defect density of these samples. FIG. 4 shows the relationship between the basal plane dislocation density and the stacking defect density of these samples. FIG. 5 shows the relationship between the basal plane dislocation density of these samples and the ratio of the linear surface defect density to the basal plane dislocation density. FIG. 6 shows the relationship between the basal plane dislocation density of these samples and the ratio of the stacking defect density to the basal plane dislocation density. -2It has been found that it is possible to make it less than. Further, performing CMP described in Patent No. 6295969 and a polishing method with oxidation and etching, and the basal plane dislocation density of the substrate base surface is 500 cm -2 By using the following silicon carbide substrate, it has been found that the stacking defect density can be made less than 0.1 cm -2 It has been found that it is possible to make it less than. From FIG. 6, it can be seen that this defect suppression effect is generally constant regardless of the basal plane dislocation density of the first surface of the silicon carbide substrate. Specifically, at least when the basal plane dislocation density of the first surface of the silicon carbide substrate is 3000 cm -2 In the following range, the ratio of the stacking defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%.

[0063] Also, from the comparison between Examples 1 to 6 and Comparative Example 1, by setting C / Si in the raw material gas in the range of 1 or more and 1.6 or less, the linear surface defect density can be suppressed to less than 1.0 cm -2 It can be seen that conversely, when C / Si in the raw material gas is greater than 1.6, the linear surface defect density on the upper surface of the formed silicon carbide epitaxial layer becomes significantly larger. Since the linear surface defect density of the sample of Comparative Example 1 exceeds 12, it is not shown in FIG. 3.

[0064] From FIG. 5, when the basal plane dislocation density of the first surface of the silicon carbide substrate is 3000 cm -2 In the following range, the ratio of the linear surface defect density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.04%.

[0065] That is, from these results, it can be seen that by forming a silicon carbide epitaxial layer on the (000-1)C plane and setting C / Si in the raw material gas to 1 or more and 1.6 or less, the influence of the basal plane dislocations of the silicon carbide substrate can be effectively suppressed, and the linear surface defects and stacking defects on the upper surface of the silicon carbide epitaxial layer can be reduced.

[0066] Furthermore, from the comparison between Examples 1 to 6 and Reference Example 2, it can be seen that in order to reduce linear surface defects and stacking defects on the upper surface of the silicon carbide epitaxial layer, it is important to planarize the first surface of the silicon carbide substrate by CMP or to remove the processed altered layer by mechanical polishing or the like by CMP.

[0067] Patent No. 4539140 discloses that by using the (000-1)C plane of a silicon carbide substrate for the growth of a silicon carbide epitaxial layer, a silicon carbide semiconductor layer can be epitaxially grown on a silicon carbide substrate with a low off-angle of less than 1°, and that the occurrence of step bunching can be reduced by using a substrate with a low off-angle. However, according to this patent document, the surface defect density of the obtained silicon carbide epitaxial layer is 100 cm -2 which is a considerably large value even when compared with the linear surface defect density and stacking defect density in the samples of Examples 1 to 6 and Reference Examples 1 to 3 described above.

[0068] Also, for example, in the non-patent document "Homoepitaxial Growth on the Vicinal Plane of 4H-SiC{0001}" ("Materials" (J.Soc.Mat.Sci., Japan), Vol. 53, No. 12, pp. 1323-1327, Dec. 2004), there is a description of surface defects in a homoepitaxial growth film on the vicinal (000-1)C plane. This non-patent document reports that the surface defect density was reduced by forming a thermal oxide film before epitaxial growth, but no specific numerical value is shown for the density. Estimating the surface defect density from Fig. 4 "Surface Observation Image of Homoepitaxial Growth Film on the Vicinal (000-1)C Plane" gives about 100 cm -2 (6 surface defects in 6 mm 2 ).

[0069] From these facts, it can be seen that in the silicon carbide epitaxial substrate 10 manufactured by the method for manufacturing a silicon carbide epitaxial substrate of the present embodiment, the linear surface defect density and the stacking defect density on the upper surface of the silicon carbide epitaxial layer are considerably smaller than those of the prior art, and a silicon carbide epitaxial substrate having a high-quality silicon carbide epitaxial layer can be realized.

Industrial Applicability

[0070] The silicon carbide epitaxial substrate of the present disclosure is a high-quality silicon carbide epitaxial substrate that can be used for various applications, and is particularly suitably used for manufacturing semiconductor devices such as power devices.

Explanation of Reference Numerals

[0071] 10 Silicon carbide epitaxial substrate 20 Silicon carbide substrate 20a First surface 20b Second surface 20n Normal line 30 Silicon carbide epitaxial layer 30a Upper surface

Claims

1. A silicon carbide substrate having a first surface, A silicon carbide epitaxial layer located on the first surface, Comprising, The first surface is a (000-1)C plane, On the upper surface of the silicon carbide epitaxial layer, the stacking defect density confirmed by a photoluminescence image is less than 1.2 cm －２ −2 The ratio of the stacking fault density to the basal plane dislocation density on the first surface of the silicon carbide substrate is less than 0.05%, The basal plane dislocation density on the first surface of the silicon carbide substrate is less than 3000 cm －２ −2 A silicon carbide epitaxial substrate.

2. The stacking defect density is less than 1.0 cm －２ The silicon carbide epitaxial substrate according to claim 1, wherein the stacking defect density is less than 1.0 cm.

3. The stacking defect density is less than 0.35 cm －２ The silicon carbide epitaxial substrate according to claim 1, wherein the stacking defect density is less than 0.35 cm.

4. The silicon carbide epitaxial substrate according to claim 1, wherein the diameter of the silicon carbide substrate is 100 mm or more.

5. The basal plane dislocation density on the first surface of the silicon carbide substrate is less than 2000 cm －２ The silicon carbide epitaxial substrate according to claim 1, wherein the density is less than 2000 cm.

6. The silicon carbide epitaxial substrate according to claim 1, wherein the first surface has an off-angle of 4° or less.

7. The silicon carbide epitaxial substrate according to claim 1, wherein the surface roughness Ra of the first surface is 1 nm or less.

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