Oscillator circuit

Abstract

To provide an oscillator circuit that can generate a pulse signal with a duty cycle of 50% with a smaller circuit area.SOLUTION: A first current source CS1 and a second current source CS2 generate a first current Ir and a second current Ic, respectively. A first transistor M1 has its drain connected to the first current source CS1, and a reference voltage Vr is applied to its source. A second transistor M2 is connected between a first end A of a capacitor C1 and a first node N1. A third transistor M3 is connected between a second end B of a capacitor C2 and a second node N2. A first switch SW1 is connected between the first node N1 and the second current source CS2. A second switch SW2 is connected between the second node N2 and the second current source CS2. A charging-discharging circuit 120 includes a third switch SW3 connected between the first end A of the capacitor C1 and the ground, and a fourth switch SW4 connected between the second end B of the capacitor C1 and the ground.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an oscillator circuit.

Background Art

[0002] Digital circuits and frequency synthesizers require a reference clock for their operation. An oscillator is used to generate the reference clock. Oscillators include those using crystals, ceramics, MEMS (Micro Electro Mechanical Systems) oscillators, LC oscillators, CR oscillators, ring oscillators, multivibrators, relaxation oscillators, and the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The present disclosure has been made in such circumstances, and an exemplary object of one aspect thereof is to provide an oscillator circuit capable of generating a pulse signal with a duty cycle of 50% with a small circuit area.

[0005] An oscillator circuit according to an aspect of the present disclosure includes a first current source that generates a first current, a second current source that generates a second current, a first node and a second node, a first transistor having a drain connected to the first current source, a reference voltage circuit that generates a reference voltage at a source of the first transistor, a capacitor, a second transistor having a source connected to a first end of the capacitor, a drain connected to the first node, and a gate connected to a gate of the first transistor, a third transistor having a source connected to a second end of the capacitor, a drain connected to the second node, and a gate connected to the gate of the first transistor, a first switch connected between the first node and the second current source, a second switch connected between the second node and the second current source, a charge / discharge circuit including a third switch connected between the first end of the capacitor and ground and a fourth switch connected between the second end of the capacitor and ground, a first voltage generated at the first node, and a second voltage generated at the second node. Based on these, (i) a first state in which the second switch and the third switch are on and the first switch and the fourth switch are off, and (ii) a second state in which the second switch and the third switch are off and the first switch and the fourth switch are on are switched, and a control circuit that controls the charge / discharge circuit so that the capacitor discharges during a discharge period at the start of the first state and a discharge period at the start of the second state is provided.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] (Overview of Embodiment) The overview of some exemplary embodiments of the present disclosure will be described. This overview is provided as a prelude to the detailed description that follows and is intended to provide a basic understanding of the embodiments by briefly describing some concepts of one or more embodiments. It is not intended to limit the scope of the invention or disclosure. This overview is not an exhaustive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed in this specification.

[0008] An oscillator circuit according to an embodiment includes a first current source that generates a first current, a second current source that generates a second current, a first node and a second node, a first transistor whose drain is connected to the first current source, a reference voltage circuit that generates a reference voltage connected to the source of the first transistor, a capacitor, a second transistor whose source is connected to the first end of the capacitor, whose drain is connected to the first node, and whose gate is connected to the gate of the first transistor, a third transistor whose source is connected to the second end of the capacitor, whose drain is connected to the second node, and whose gate is connected to the gate of the first transistor, a first switch connected between the first node and the second current source, a second switch connected between the second node and the second current source, a charge and discharge circuit including a third switch connected between the first end of the capacitor and ground and a fourth switch connected between the second end of the capacitor and ground, a first voltage generated at the first node, and a second voltage generated at the second node. Based on these, (i) a first state in which the second switch and the third switch are on and the first switch and the fourth switch are off, and (ii) a second state in which the second switch and the third switch are off and the first switch and the fourth switch are on are switched, and a control circuit that controls the charge and discharge circuit so that the capacitor discharges during the discharge period at the start of the first state and the discharge period at the start of the second state is provided.

[0009] According to this configuration, a pulse signal with a duty cycle of 50% can be generated using one capacitor, and the circuit area can be reduced compared to the case where two capacitors are used.

[0010] In one embodiment, the charge and discharge circuit may further include a fifth switch connected in parallel with the capacitor and turned on during the discharge period.

[0011] In one embodiment, during the discharge period, the control circuit may turn on the third switch and the fourth switch.

[0012] In one embodiment, the charge and discharge circuit may further include a sixth switch connected between the first node and the ground, and a seventh switch connected between the second node and the ground. The control circuit may turn off the sixth switch and turn on the seventh switch in the first state, and turn on the sixth switch and turn off the seventh switch in the second state.

[0013] In one embodiment, the oscillator circuit may further include a reference current source that generates a reference current. The first current source may generate a first current corresponding to the reference current, and the second current source may generate a second current corresponding to the reference current.

[0014] In one embodiment, the reference current source may include a β - multiplication type self - bias circuit.

[0015] In one embodiment, the first transistor, the reference voltage circuit, and the first current source may also serve as part of a β - multiplication type self - bias circuit. Thereby, the circuit area can be further reduced.

[0016] In one embodiment, the reference voltage circuit may include a resistor.

[0017] In one embodiment, the reference voltage circuit may include a reference voltage source.

[0018] In one embodiment, the reference voltage circuit may include an NMOS transistor whose gate is supplied with a bias voltage.

[0019] In one embodiment, the control circuit may include a flip - flop that is set according to a first voltage and reset according to a second voltage, and a pulse generator that generates a discharge control signal that is asserted for a predetermined period in response to the state transition of the flip - flop.

[0020] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Also, the embodiments are illustrative and not restrictive of the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the invention.

[0021] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0022] Similarly, the phrase "member C is in a state of being provided between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members without substantially affecting their electrical connection states or impairing the functions and effects achieved by their connection.

[0023] FIG. 1 is a circuit diagram of an oscillator circuit 100 according to an embodiment. The oscillator circuit 100 includes a first current source CS1, a second current source CS2, first to third transistors M1 to M3 which are NMOS transistors, a first node N1, a second node N2, a reference voltage circuit 110, a charge and discharge circuit 120, a control circuit 130, a reference current source 140, a capacitor C1, a first switch SW1, and a second switch SW2, and is integrated on a single semiconductor substrate.

[0024] The first current source CS1 generates a first current Ir. The second current source CS2 generates a second current Ic. The first current Ir and the second current Ic respectively depend on a reference current I ref generated by the reference current source 140.

[0025] The drain of the first transistor M1 is connected to the first current source CS1. The reference voltage circuit 110 generates a reference voltage Vr at the source of the first transistor M1.

[0026] The source of the second transistor M2 is connected to the first end A of the capacitor C1, the drain is connected to the first node N1, and the gate is connected to the gate of the first transistor M1. The source of the third transistor M3 is connected to the second end B of the capacitor C1, the drain is connected to the second node N2, and the gate is connected to the gate of the first transistor M1. A bias voltage Vbn generated at the gate of the first transistor M1 is supplied to the gates of the second transistor M2 and the third transistor M3.

[0027] The first switch SW1 is connected between the first node N1 and the second current source CS2, and the second switch SW2 is connected between the second node N2 and the second current source CS2.

[0028] The charge and discharge circuit 120 includes a third switch SW3 connected between the first end A of the capacitor C1 and ground, and a fourth switch SW4 connected between the second end B of the capacitor C1 and ground. The charge and discharge circuit 120 further includes a fifth switch SW5 connected in parallel with the capacitor C1.

[0029] The control circuit 130 controls the first switch SW1 to the fifth switch SW5 based on the first voltage V A generated at the first node N1 and the second voltage V B generated at the second node N2.

[0030] The control circuit 130 switches between (i) a first state φ A in which the first switch SW1 and the fourth switch SW4 are off and the second switch SW2 and the third switch SW3 are on, and (ii) a second state φ B in which the first switch SW1 and the fourth switch SW4 are on and the second switch SW2 and the third switch SW3 are off. Also, the control circuit 130, at the beginning of the discharge period φ A of the first state φdischg and the second state φ B At the beginning of the discharge period φ dischg in, the charge-discharge circuit 120 is controlled so that the capacitor C1 discharges. In this embodiment, the discharge period φ dischg in, the fifth switch SW5 is turned on, and the charge of the capacitor C1 is reset. In FIG. 1, the symbol φ A , φ B , φ dischg each indicates a state and represents a control signal for the switch to be turned on in each state.

[0031] The above is the configuration of the oscillator circuit 100. Next, its operation will be described.

[0032] FIG. 2 is a circuit diagram of the oscillator circuit 100 in the first state φ A . In the first state φ A , the second switch SW2 and the third switch SW3 are on, and the first switch SW1 and the fourth switch SW4 are off. Since the third switch SW3 is on, the potential of the first terminal A of the capacitor C1 decreases toward 0V. Also, since the second switch SW2 is on, the second current Ic generated by the second current source CS2 is supplied to the second terminal B of the capacitor C1 via the second switch SW2 and the third transistor M3.

[0033] In the first state φ A , during the initial discharge period φ dischg , since the fifth switch SW5 is on, the voltage V cB of the second terminal B of the capacitor C1 cA becomes equal to the voltage V

[0034] When the discharge period φ dischg ends, the fifth switch SW5 turns off. Then, the capacitor C1 is charged by the second current Ic, and the voltage V cB of the second terminal B increases with time, and accordingly, the second voltage V B of the second node N2 also increases.

[0035] The oscillator circuit 100 operates as a comparator that compares the voltage V at the second terminal B of the capacitor C1 with the reference voltage Vr in the first state φ. A In the first state φ, the oscillator circuit 100 operates as a comparator that compares the voltage V at the second terminal B of the capacitor C1 with the reference voltage Vr. When the second voltage V exceeds a certain threshold value Vt, the control circuit 130 transitions to the second state φ. cB In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. B When the second voltage V exceeds a certain threshold value Vt, the control circuit 130 transitions to the second state φ. B

[0036] In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. B In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. A In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. A In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. A In the second state φ, the oscillator circuit 100 performs an operation symmetric to the first state φ, the first voltage V rises with time, and when the first voltage V exceeds the threshold value Vt, the control circuit 130 transitions to the first state φ. A

[0037] Figure 3 is a waveform diagram showing the operation of the oscillator circuit 100 in Figure 1.

[0038] · In the first state φ A At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. A At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. cA At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. A At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. dischg At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. cB At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A. cA At time t0, it becomes the first state φ. Since the third switch SW3 is on, the voltage V at the first terminal A of the capacitor C1 decreases. Also, the beginning of the first state φ is the discharge period φ, and since the fifth switch SW5 is on, the voltage V at the second terminal B approaches the voltage V at the first terminal A.

[0039] At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. dischg At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. cB At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. CR At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. cB At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. B At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. cB At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ. comp At time t1, when the discharge period φ ends and the fifth switch SW5 turns off, the voltage V rises at a constant slope determined by the second current Ic. At time t2, after the time constant τ determined by the circuit constant has elapsed from time t1, the voltage V exceeds the reference voltage Vr. Here, the voltage V rises with the voltage V and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, at time t3, after the delay time τ for comparison has elapsed, the control circuit 130 transitions to the second state φ.B Transitions to

[0040] ·Second state φ B At time t3, the second state φ B is reached, the fourth switch SW4 turns on, and the voltage V cB at the second terminal B of the capacitor C1 decreases. Also, at the start of the second state φ B is the discharge period φ dischg and since the fifth switch SW5 is on, the voltage V cA at the first terminal A approaches the voltage V cB at the second terminal B.

[0041] At time t4, when the discharge period φ dischg ends and the fifth switch SW5 turns off, the voltage V cA rises at a constant slope determined by the second current Ic. At time t5, the voltage V cA exceeds the reference voltage Vr. Here, the voltage V A rises together with the voltage V cA and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, the control circuit 130 transitions to the first state φ comp at time t6 after the elapse of the delay time τ A for comparison.

[0042] The above is the operation of the oscillator circuit 100. The oscillation period T OSC of this oscillator circuit 100 is expressed by the following equation. T OSC = τ dischg + τ CR + τ comp τ dischg is the length of the discharge period φ dischg .

[0043] The advantages of the oscillator circuit 100 become clear by comparison with the oscillator circuit 100R according to the comparative technique. Therefore, the comparative technique will be described.

[0044] FIG. 4 is a circuit diagram of an oscillator circuit 100R according to a comparative technique. The oscillator circuit 100R includes two capacitors C1 and C2. The first end of the first capacitor C1 is grounded, and the second end is connected to the source of the second transistor M2. The third switch SW3 is connected in parallel with the capacitor C1. The first end of the second capacitor C2 is grounded, and the second end is connected to the source of the third transistor M3. The fourth switch SW4 is connected in parallel with the capacitor C2.

[0045] In the comparative technique, there is no discharge period φdischg, and the control circuit 130R alternates between the first state φ A and the second state φ2 based on the first voltage V of the first node N1 B and the second voltage V of the second node N2. A

[0046] FIG. 5 is a waveform diagram showing the operation of the oscillator circuit 100R of FIG. 4.

[0047] · In the second state φ A before time t0, since the fourth switch SW4 is on, the voltage V of the second capacitor C2 B is 0V. cB

[0048] At time t0, the first state φ A is entered. Since the third switch SW3 is on, the voltage V of the first capacitor C1 cA decreases.

[0049] In the first state φ A , the voltage V of the second capacitor C2 cB increases at a constant slope determined by the second current Ic. At time t2, the voltage V cB exceeds the reference voltage Vr. Here, the voltage V B increases together with the voltage V cB and exceeds the determination threshold voltage Vt of the control circuit 130. Therefore, the control circuit 130 transitions to the second state φ comp at time t3 after the elapse of the delay time τ for comparison B .

[0050] · The second state φ B At time t3, the second state φ B is reached, and the voltage V of the first capacitor C1 cA increases at a constant slope determined by the second current Ic. At time t5, the voltage V cA exceeds the reference voltage Vr. Here, the voltage V A is the voltage V cA and increases to exceed the determination threshold voltage Vt of the control circuit 130. Therefore, the control circuit 130 transitions to the first state φ comp at time t6 after the elapse of the delay time τ A for comparison.

[0051] The above is the operation of the oscillator circuit 100R. By using two capacitors C1 and C2, the following advantages can be obtained with this comparative technique.

[0052] · The first advantage It is possible to generate a pulse signal with a duty cycle of 50%.

[0053] · The second advantage While one capacitor C1 (C2) is being charged, the other capacitor C2 (C1) is being discharged. As a result, the discharge period τ delay of the capacitor C2 (C1) does not affect the oscillation period T OSC , and the oscillation period T OSC is determined only by the comparison time τ comp and the time constant τ CR . T OSC = τ comp + τ CR

[0054] · The third advantage Since it is possible to design the discharge time τ delay to be short, the oscillation period T OSC can be shortened. In other words, it is easy to increase the oscillation frequency f OSC (= 1 / T OSC ).

[0055] On the other hand, in the oscillator circuit 100 according to the comparative technique, two capacitors C1 and C2 are required. Since the capacitors C1 and C2 occupy a relatively large area on the semiconductor substrate, it is difficult to miniaturize the oscillator circuit 100R.

[0056] Returning to the embodiment. In the oscillator circuit 100 according to the embodiment, three advantages obtained by the comparative technique can be obtained. Furthermore, since the number of capacitors can be reduced to one, the circuit area can be reduced.

[0057] The present disclosure is understood as the block diagram and circuit diagram of FIG. 1, or extends to various devices and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and embodiments will be described not to narrow the scope of the present disclosure, but to assist in understanding the essence and operation of the present disclosure and the present invention, and to clarify them.

[0058] (Example 1) FIG. 6 is a circuit diagram of the oscillator circuit 100A according to Example 1. The control circuit 130 includes a flip-flop 132 and a pulse generator 134. The flip-flop 132 is an SR latch (SR flip-flop), and receives the first voltage V of the first node N1 at the set terminal (S), and receives the voltage V of the second node N2 at the reset terminal (R). The non-inverted output Q of the flip-flop 132 is used as a control signal for an element that turns on when in the first state φ, and the inverted output / Q of the flip-flop 132 is used as a control signal for an element that turns on when in the second state φ. A at the set terminal (S), and receives the voltage V of the second node N2 B at the reset terminal (R). The non-inverted output Q of the flip-flop 132 is used as a control signal for an element that turns on when in the first state φ A , and the inverted output / Q of the flip-flop 132 is used as a control signal for an element that turns on when in the second state φ B .

[0059] The pulse generator 134 generates a discharge control signal φ based on at least one of the outputs Q and / Q (where / represents inverted logic) of the flip-flop 132. The pulse generator 134 generates a discharge time τ in response to the state transition of the flip-flop 132 dischg . dischgDuring that time, a pulse signal (discharge control signal φ dischg ) that reaches a predetermined level (for example, high) is generated.

[0060] The reference current source 140 includes a so-called β - multiplication type self - bias circuit. Specifically, the reference current source 140 includes NMOS transistors M11, M12, PMOS transistors M12, M13, and a resistor R11. The first current source CS1 includes the fourth transistor M4, and the second current source CS2 includes the fifth transistor M5. The fourth transistor M4 and the fifth transistor M5, together with the transistor M12 of the reference current source 140, form a current mirror circuit. A first current Ir proportional to the reference current I ref generated by the reference current source 140 flows through the fourth transistor M4, and a second current Ic proportional to the reference current I ref flows through the fifth transistor M5.

[0061] Also in this embodiment, the reference voltage circuit 110 includes a first resistor R1. The reference voltage Vr is Ir×R1.

[0062] FIG. 7 is a circuit diagram showing a configuration example of the pulse generator 134. The pulse generator 134 includes inverters INV1 to INV4, AND gates AND1, AND2, and an OR gate OR1. The inverters INV1, INV2 delay the output Q of the previous SR flip - flop. The delay time of the two - stage inverters INV1, INV2 corresponds to the discharge time τ dischg . The AND gate AND1 generates the logical product of the delayed output Qd and the non - delayed output Q. The output of the AND gate AND1 becomes a pulse signal that is at a high level during the delay time τ dischg from the positive edge of the output Q.

[0063] Similarly, the inverters INV3, INV4 delay the inverted output / Q of the previous SR flip - flop. The AND gate AND2 generates the logical product of the delayed inverted output / Qd and the non - delayed inverted output / Q. The output of the AND gate AND2 becomes a pulse signal that is at a high level during the delay time τ dischgDuring that time, it becomes a high-level pulse signal.

[0064] The OR gate OR1 takes the logical sum of the outputs of the AND gates AND1 and AND2, and outputs it as the discharge control signal φ dischg as an output.

[0065] (Example 2) FIG. 8 is a circuit diagram of the oscillator circuit 100B according to Example 2. In this example, the first transistor M1, the fourth transistor M4 (the first current source CS1), and the resistor R1 (the reference voltage circuit 110) in FIG. 6 are incorporated in the reference current source 140B. In other words, the transistor M12 of the β multiplication type self-bias circuit also serves as the first current source CS1 (the transistor M4 in FIG. 6), the transistor M11 also serves as the first transistor M1, and the resistor R11 also serves as the reference voltage circuit 110.

[0066] According to Example 2, the circuit area and the current consumption can be further reduced compared to Example 1.

[0067] FIG. 9 is a more specific circuit diagram of the oscillator circuit 100B in FIG. 8. The third switch SW3 and the fourth switch SW4 are composed of NMOS transistors. The first control signal φ that becomes high level in the first state φ is input to the gate of the third switch SW3. A at high level in the first state φ A is input, and the second control signal φ that becomes high level in the second state φ is input to the gate of the fourth switch SW4. B at high level in the second state φ B is input.

[0068] The fifth switch SW5 is composed of an NMOS transistor, and a control signal that becomes high level during the discharge period φ is input to its gate. dischg is input.

[0069] The first switch SW1 and the second switch SW2 are composed of PMOS transistors. A PMOS transistor turns on when a low level is input to its gate. Therefore, the gate of the first switch SW1 is in the second state φ BThe first control signal φ that goes low A is input, and the gate of the second switch SW2 is in the second state φ B The second control signal φ that goes low A is input.

[0070] (Embodiment 3) FIG. 10 is a circuit diagram of the oscillator circuit 100C according to Embodiment 3. The charge / discharge circuit 120C of this oscillator circuit 100C further includes a sixth switch SW6 and a seventh switch SW7. The sixth switch SW6 is connected between the first node N1 and the ground and is turned on in the first state φ A . The seventh switch SW7 is connected between the second node N1 and the ground and is turned on in the second state φ B .

[0071] FIG. 11 is a more specific circuit diagram of the oscillator circuit 100C in FIG. 10. The sixth switch SW6 and the seventh switch SW7 are composed of NMOS transistors. A first control signal φ that becomes high in the first state φ A is input to the gate of the sixth switch SW6, and a second control signal φ that becomes high in the second state φ A is input to the gate of the seventh switch SW7, and a second control signal φ that becomes high in the second state φ B is input. B is input.

[0072] The above is the configuration of the oscillator circuit 100C. Before explaining the operation of the oscillator circuit 100C, the problems of the configuration without the sixth switch SW6 and the seventh switch SW7 (FIG. 1, etc.) will be described with reference to FIG. 3.

[0073] In the waveform diagram of FIG. 3, the voltages V A , V B of the first node N1 and the second node N2 are respectively in the discharge period φ dischgDuring this period, it drops to a voltage range slightly higher than 0V. At this time, since the second transistor M2 and the third transistor M3 operate in the linear region, they are susceptible to PVT (process, voltage, temperature) variations. As a result, frequency drift of the oscillator circuit 100 may occur due to temperature fluctuations or power supply voltage fluctuations.

[0074] FIG. 12 is a waveform diagram showing the operation of the oscillator circuit 100C of FIG. 10. In the third embodiment, by adding the sixth switch SW6 and the seventh switch SW7, the voltages V A , V B of the first node N1 and the second node N2 respectively drop to near 0V during the discharge period φ dischg . This can mitigate the influence of frequency drift.

[0075] (Embodiment 4) FIG. 13 is a circuit diagram of an oscillator circuit 100D according to the fourth embodiment. In the fourth embodiment, similar to the second embodiment (FIG. 8), a first current source CS1, a first transistor M1, and a reference voltage circuit 110D are incorporated in the reference current source 140D. The reference voltage circuit 110D includes an NMOS transistor M15 provided between the source of the NMOS transistor M11 and the ground, and a bias circuit 112 that supplies a bias voltage Vbn to the gate of the NMOS transistor M15. The bias circuit 112 includes a PMOS transistor M17 and an NMOS transistor M16. The gate of the PMOS transistor M17 is connected to the gates of the PMOS transistors M12 and M13. The NMOS transistor M16 is connected between the drain of the PMOS transistor M17 and the ground.

[0076] The preferred operating point of the reference current source 140D will be described. The PMOS transistors M5, M12, M14, M17 and the NMOS transistors M2, M3, M11, M13 operate in the weak inversion region (subthreshold region Vgs < Vth). The NMOS transistor M16 operates in the strong inversion region (Vgs > Vth). The NMOS transistor M15 operates in the strong inversion region (Vgs > Vth) and the linear region (Vds < Vgs - Vth).

[0077] In this way, when the operating point is determined, each current can be suppressed to the nanoampere order, and the circuit area can be reduced by reducing the element size.

[0078] As shown in FIG. 8, in the configuration using the resistor R11, in order to make the current in the nanoampere order, a very large resistance value is required, and the circuit area becomes large. On the other hand, in this embodiment, since the NMOS transistor M15 operating in the strong inversion region and the linear region is used instead of the resistor R11, the circuit area can be further reduced. In addition, by adopting a configuration without using a resistor, the number of mask layers can be reduced, and the manufacturing process can be made less costly.

[0079] Furthermore, the resistance characteristic of the linear region of the MOS transistor has a positive temperature coefficient. On the other hand, the threshold value Vth of the NMOS transistor has a negative temperature coefficient. Therefore, by adjusting the size of the transistor M15, the temperature dependence of the current of the β - multiplication type self - bias circuit can be adjusted, and the comp and delay frequency drift caused by the temperature characteristics of can be adjusted.

[0080] (Embodiment 5) FIG. 14 is a circuit diagram of the oscillator circuit 100E according to Embodiment 5. In Embodiment 5, as the reference voltage circuit 110E, a reference voltage source such as a band - gap reference (BGR) circuit is used.

[0081] Many ICs (Integrated Circuits) and LSIs (Large Scale Integrations) are equipped with a reference voltage source such as a band - gap reference circuit. Therefore, by using the reference voltage generated by the reference voltage source instead of the resistor R11, it is possible to suppress the temperature drift of the frequency while reducing the circuit area.

[0082] (Embodiment 6) FIG. 15 is a circuit diagram of the pulse generator 134F according to Example 6. In this example, two fifth switches SW5A and SW5B are connected in parallel to the capacitor C1.

[0083] The pulse generator 134F includes inverters INV1 to INV4 and NOR gates NOR1 and NOR2. The output of the NOR gate NOR1 is the discharge control signal φ for the fifth switch SW5B. dischgB That is, the output of the NOR gate NOR2 is the discharge control signal φ for the fifth switch SW5A. dischgA That's it.

[0084] Also, the output of the inverter INV3 is the control signal asserted in the first state φ. A That is, the output of the inverter INV4 is the control signal asserted in the second state φ. B That's the control signal.

[0085] The pulse generator 134F in FIG. 15 is composed only of NOR gates which are basic logic operation elements, eliminating the need for composite gates (OR1, AND1, AND2) as shown in FIG. 7, and effects such as reduction of circuit area and improvement of delay time can be obtained.

[0086] (Example 7) FIG. 16 is a circuit diagram of the oscillator circuit 100G according to Example 7. The charge and discharge circuit 120G includes a third switch SW3, a fourth switch SW4, and OR gates OR3 and OR4, and the fifth switch SW5 is omitted. The OR gate OR3 supplies the logical sum of the control signals φ A and φ dischg to the third switch SW3, and the OR gate OR4 supplies the logical sum of the control signals φ B and φ dischg to the fourth switch SW4. During the discharge period φ dischg , both the third switch SW3 and the fourth switch SW4 are turned on, so that the voltages V cA , V cB across both ends of the capacitor C1 become 0V, and the capacitor C1 is discharged.

[0087] (Modification example) The configurations of the above-described Examples 1 to 7 can be arbitrarily combined, and such combinations are also included in the scope of the present disclosure.

[0088] (Use) The use of the oscillator circuit 100 is not particularly limited, and for example, it can be suitably used for a timer circuit.

[0089] The embodiments described using specific terms only show the principles and applications of the present invention. In the embodiments, many modification examples and arrangement changes are recognized within the scope not departing from the idea of the present invention defined in the claims.

[0090] (Supplementary note) The technology disclosed in this specification is expressed as follows in one aspect.

[0091] (Item 1) A first current source that generates a first current, A second current source that generates a second current, A first node and a second node, A first transistor whose drain is connected to the first current source, A reference voltage circuit that generates a reference voltage at the source of the first transistor, A capacitor, A second transistor whose source is connected to the first end of the capacitor, whose drain is connected to the first node, and whose gate is connected to the gate of the first transistor, A third transistor whose source is connected to the second end of the capacitor, whose drain is connected to the second node, and whose gate is connected to the gate of the first transistor, A first switch connected between the first node and the second current source, A second switch connected between the second node and the second current source, A charge and discharge circuit including a third switch connected between the first end of the capacitor and ground and a fourth switch connected between the second end of the capacitor and ground, a control circuit that switches between (i) a first state in which the second switch and the third switch are on and the first switch and the fourth switch are off, and (ii) a second state in which the second switch and the third switch are off and the first switch and the fourth switch are on, based on a first voltage generated at the drain of the second transistor and a second voltage generated at the drain of the third transistor, and controls the charge / discharge circuit so that the capacitor is discharged during a leading discharge period of the first state and a leading discharge period of the second state; 1. An oscillator circuit comprising:

[0092] (Item 2) 2. The oscillator circuit of item 1, wherein the charge / discharge circuit further includes a fifth switch connected in parallel with the capacitor and turned on during the discharge period.

[0093] (Item 3) 2. The oscillator circuit of claim 1, wherein the control circuit turns on the third switch and the fourth switch during the discharge period.

[0094] (Item 4) The charge / discharge circuit includes: a sixth switch connected between the first node and ground; a seventh switch connected between the second node and ground; Further comprising: 4. The oscillator circuit of any one of items 1 to 3, wherein the control circuit, in the first state, turns on the sixth switch and turns off the seventh switch, and, in the second state, turns off the sixth switch and turns on the seventh switch.

[0095] (Item 5) A reference current source for generating a reference current is further provided. the first current source generates the first current in response to the reference current; 5. The oscillator circuit of any one of items 1 to 4, wherein the second current source generates the second current in response to the reference current.

[0096] (Item 6) The reference current source is the oscillator circuit according to Item 5, including a β - multiplication type self - bias circuit.

[0097] (Item 7) The first transistor, the reference voltage circuit, and the first current source are the oscillator circuit according to Item 6, which also serve as part of the β - multiplication type self - bias circuit.

[0098] (Item 8) The reference voltage circuit is the oscillator circuit according to any one of Items 1 to 7, including a resistor.

[0099] (Item 9) The reference voltage circuit is the oscillator circuit according to any one of Items 1 to 7, including a reference voltage source.

[0100] (Item 10) The reference voltage circuit is the oscillator circuit according to any one of Items 1 to 7, including an NMOS transistor with a bias voltage supplied to its gate.

[0101] (Item 11) The control circuit a flip - flop set according to the first voltage and reset according to the second voltage, and a pulse generator that generates a discharge control signal asserted for a predetermined period in response to the state transition of the flip - flop is included in the oscillator circuit according to any one of Items 1 to 10.

Description of Reference Signs

[0102] 100 Oscillator circuit CS1 First current source CS2 Second current source N1 First node N2 Second node V A First voltage V B Second voltage C1 Capacitor 110 Reference Voltage Circuit 120 Charge and Discharge Circuit 130 Control Circuit 132 Flip-Flop 134 Pulse Generator 140 Reference Current Source SW1 First Switch SW2 Second Switch SW3 Third Switch SW4 Fourth Switch SW5 Fifth Switch SW6 Sixth Switch SW7 Seventh Switch M1 First Transistor M2 Second Transistor M3 Third Transistor M4 Fourth Transistor M5 Fifth Transistor

Claims

1. A first current source that generates a first current, A second current source that generates a second current, A first node and a second node, A first transistor having a drain connected to the first current source, A reference voltage circuit that generates a reference voltage at the source of the first transistor, A capacitor, A second transistor having a source connected to the first end of the capacitor, a drain connected to the first node, and a gate connected to the gate of the first transistor, A third transistor having a source connected to the second end of the capacitor, a drain connected to the second node, and a gate connected to the gate of the first transistor, A first switch connected between the first node and the second current source, A second switch connected between the second node and the second current source, A charge and discharge circuit including a third switch connected between the first end of the capacitor and ground and a fourth switch connected between the second end of the capacitor and ground, Based on a first voltage generated at the drain of the second transistor and a second voltage generated at the drain of the third transistor, (i) a first state in which the second switch and the third switch are on and the first switch and the fourth switch are off, and (ii) a second state in which the second switch and the third switch are off and the first switch and the fourth switch are on, and controlling the charge and discharge circuit so that the capacitor discharges during a discharge period at the start of the first state and a discharge period at the start of the second state. A control circuit, An oscillator circuit comprising:

2. The charge and discharge circuit further includes a fifth switch connected in parallel with the capacitor and turned on during the discharge period, and the oscillator circuit according to claim 1.

3. The control circuit turns on the third switch and the fourth switch during the discharge period, and the oscillator circuit according to claim 1.

4. The charge and discharge circuit A sixth switch connected between the first node and ground, A seventh switch connected between the second node and ground, Further includes The control circuit turns on the sixth switch and turns off the seventh switch in the first state, and turns off the sixth switch and turns on the seventh switch in the second state, and the oscillator circuit according to any one of claims 1 to 3.

5. further comprising a reference current source for generating a reference current, the first current source generates the first current according to the reference current, the second current source generates the second current according to the reference current, the oscillator circuit according to any one of claims 1 to 3.

6. the reference current source includes a beta multiplication type self-bias circuit, the oscillator circuit according to claim 5.

7. the first transistor, the reference voltage circuit, the first current source also serve as a part of the beta multiplication type self-bias circuit, the oscillator circuit according to claim 6.

8. the reference voltage circuit includes a resistor, the oscillator circuit according to any one of claims 1 to 3.

9. the reference voltage circuit includes a reference voltage source, the oscillator circuit according to any one of claims 1 to 3.

10. the reference voltage circuit includes an NMOS transistor with a bias voltage supplied to the gate, the oscillator circuit according to any one of claims 1 to 3.

11. the control circuit, a flip-flop set according to the first voltage and reset according to the second voltage, a pulse generator that generates a discharge control signal asserted for a predetermined period in response to a state transition of the flip-flop, including the oscillator circuit according to any one of claims 1 to 3.

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